arch/powerpc/kernel/traps.c

   1 /*
   2  *  Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  *
   9  *  Modified by Cort Dougan (cort@cs.nmt.edu)
  10  *  and Paul Mackerras (paulus@samba.org)
  11  */
  12
  13 /*
  14  * This file handles the architecture-dependent parts of hardware exceptions
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/errno.h>
  19 #include <linux/sched.h>
  20 #include <linux/kernel.h>
  21 #include <linux/mm.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/a.out.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/init.h>
  30 #include <linux/module.h>
  31 #include <linux/prctl.h>
  32 #include <linux/delay.h>
  33 #include <linux/kprobes.h>
  34
  35 #include <asm/kdebug.h>
  36 #include <asm/pgtable.h>
  37 #include <asm/uaccess.h>
  38 #include <asm/system.h>
  39 #include <asm/io.h>
  40 #include <asm/machdep.h>
  41 #include <asm/rtas.h>
  42 #include <asm/pmc.h>
  43 #ifdef CONFIG_PPC32
  44 #include <asm/reg.h>
  45 #endif
  46 #ifdef CONFIG_PMAC_BACKLIGHT
  47 #include <asm/backlight.h>
  48 #endif
  49 #ifdef CONFIG_PPC64
  50 #include <asm/firmware.h>
  51 #include <asm/processor.h>
  52 #endif
  53
  54 #ifdef CONFIG_PPC64     /* XXX */
  55 #define _IO_BASE        pci_io_base
  56 #endif
  57
  58 #ifdef CONFIG_DEBUGGER
  59 int (*__debugger)(struct pt_regs *regs);
  60 int (*__debugger_ipi)(struct pt_regs *regs);
  61 int (*__debugger_bpt)(struct pt_regs *regs);
  62 int (*__debugger_sstep)(struct pt_regs *regs);
  63 int (*__debugger_iabr_match)(struct pt_regs *regs);
  64 int (*__debugger_dabr_match)(struct pt_regs *regs);
  65 int (*__debugger_fault_handler)(struct pt_regs *regs);
  66
  67 EXPORT_SYMBOL(__debugger);
  68 EXPORT_SYMBOL(__debugger_ipi);
  69 EXPORT_SYMBOL(__debugger_bpt);
  70 EXPORT_SYMBOL(__debugger_sstep);
  71 EXPORT_SYMBOL(__debugger_iabr_match);
  72 EXPORT_SYMBOL(__debugger_dabr_match);
  73 EXPORT_SYMBOL(__debugger_fault_handler);
  74 #endif
  75
  76 struct notifier_block *powerpc_die_chain;
  77 static DEFINE_SPINLOCK(die_notifier_lock);
  78
  79 int register_die_notifier(struct notifier_block *nb)
  80 {
  81         int err = 0;
  82         unsigned long flags;
  83
  84         spin_lock_irqsave(&die_notifier_lock, flags);
  85         err = notifier_chain_register(&powerpc_die_chain, nb);
  86         spin_unlock_irqrestore(&die_notifier_lock, flags);
  87         return err;
  88 }
  89
  90 /*
  91  * Trap & Exception support
  92  */
  93
  94 static DEFINE_SPINLOCK(die_lock);
  95
  96 int die(const char *str, struct pt_regs *regs, long err)
  97 {
  98         static int die_counter;
  99         int nl = 0;
 100
 101         if (debugger(regs))
 102                 return 1;
 103
 104         console_verbose();
 105         spin_lock_irq(&die_lock);
 106         bust_spinlocks(1);
 107 #ifdef CONFIG_PMAC_BACKLIGHT
 108         if (_machine == _MACH_Pmac) {
 109                 set_backlight_enable(1);
 110                 set_backlight_level(BACKLIGHT_MAX);
 111         }
 112 #endif
 113         printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
 114 #ifdef CONFIG_PREEMPT
 115         printk("PREEMPT ");
 116         nl = 1;
 117 #endif
 118 #ifdef CONFIG_SMP
 119         printk("SMP NR_CPUS=%d ", NR_CPUS);
 120         nl = 1;
 121 #endif
 122 #ifdef CONFIG_DEBUG_PAGEALLOC
 123         printk("DEBUG_PAGEALLOC ");
 124         nl = 1;
 125 #endif
 126 #ifdef CONFIG_NUMA
 127         printk("NUMA ");
 128         nl = 1;
 129 #endif
 130 #ifdef CONFIG_PPC64
 131         switch (_machine) {
 132         case PLATFORM_PSERIES:
 133                 printk("PSERIES ");
 134                 nl = 1;
 135                 break;
 136         case PLATFORM_PSERIES_LPAR:
 137                 printk("PSERIES LPAR ");
 138                 nl = 1;
 139                 break;
 140         case PLATFORM_ISERIES_LPAR:
 141                 printk("ISERIES LPAR ");
 142                 nl = 1;
 143                 break;
 144         case PLATFORM_POWERMAC:
 145                 printk("POWERMAC ");
 146                 nl = 1;
 147                 break;
 148         case PLATFORM_CELL:
 149                 printk("CELL ");
 150                 nl = 1;
 151                 break;
 152         }
 153 #endif
 154         if (nl)
 155                 printk("\n");
 156         print_modules();
 157         show_regs(regs);
 158         bust_spinlocks(0);
 159         spin_unlock_irq(&die_lock);
 160
 161         if (in_interrupt())
 162                 panic("Fatal exception in interrupt");
 163
 164         if (panic_on_oops) {
 165 #ifdef CONFIG_PPC64
 166                 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
 167                 ssleep(5);
 168 #endif
 169                 panic("Fatal exception");
 170         }
 171         do_exit(err);
 172
 173         return 0;
 174 }
 175
 176 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
 177 {
 178         siginfo_t info;
 179
 180         if (!user_mode(regs)) {
 181                 if (die("Exception in kernel mode", regs, signr))
 182                         return;
 183         }
 184
 185         memset(&info, 0, sizeof(info));
 186         info.si_signo = signr;
 187         info.si_code = code;
 188         info.si_addr = (void __user *) addr;
 189         force_sig_info(signr, &info, current);
 190
 191         /*
 192          * Init gets no signals that it doesn't have a handler for.
 193          * That's all very well, but if it has caused a synchronous
 194          * exception and we ignore the resulting signal, it will just
 195          * generate the same exception over and over again and we get
 196          * nowhere.  Better to kill it and let the kernel panic.
 197          */
 198         if (current->pid == 1) {
 199                 __sighandler_t handler;
 200
 201                 spin_lock_irq(&current->sighand->siglock);
 202                 handler = current->sighand->action[signr-1].sa.sa_handler;
 203                 spin_unlock_irq(&current->sighand->siglock);
 204                 if (handler == SIG_DFL) {
 205                         /* init has generated a synchronous exception
 206                            and it doesn't have a handler for the signal */
 207                         printk(KERN_CRIT "init has generated signal %d "
 208                                "but has no handler for it\n", signr);
 209                         do_exit(signr);
 210                 }
 211         }
 212 }
 213
 214 #ifdef CONFIG_PPC64
 215 void system_reset_exception(struct pt_regs *regs)
 216 {
 217         /* See if any machine dependent calls */
 218         if (ppc_md.system_reset_exception)
 219                 ppc_md.system_reset_exception(regs);
 220
 221         die("System Reset", regs, SIGABRT);
 222
 223         /* Must die if the interrupt is not recoverable */
 224         if (!(regs->msr & MSR_RI))
 225                 panic("Unrecoverable System Reset");
 226
 227         /* What should we do here? We could issue a shutdown or hard reset. */
 228 }
 229 #endif
 230
 231 /*
 232  * I/O accesses can cause machine checks on powermacs.
 233  * Check if the NIP corresponds to the address of a sync
 234  * instruction for which there is an entry in the exception
 235  * table.
 236  * Note that the 601 only takes a machine check on TEA
 237  * (transfer error ack) signal assertion, and does not
 238  * set any of the top 16 bits of SRR1.
 239  *  -- paulus.
 240  */
 241 static inline int check_io_access(struct pt_regs *regs)
 242 {
 243 #ifdef CONFIG_PPC_PMAC
 244         unsigned long msr = regs->msr;
 245         const struct exception_table_entry *entry;
 246         unsigned int *nip = (unsigned int *)regs->nip;
 247
 248         if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
 249             && (entry = search_exception_tables(regs->nip)) != NULL) {
 250                 /*
 251                  * Check that it's a sync instruction, or somewhere
 252                  * in the twi; isync; nop sequence that inb/inw/inl uses.
 253                  * As the address is in the exception table
 254                  * we should be able to read the instr there.
 255                  * For the debug message, we look at the preceding
 256                  * load or store.
 257                  */
 258                 if (*nip == 0x60000000)         /* nop */
 259                         nip -= 2;
 260                 else if (*nip == 0x4c00012c)    /* isync */
 261                         --nip;
 262                 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
 263                         /* sync or twi */
 264                         unsigned int rb;
 265
 266                         --nip;
 267                         rb = (*nip >> 11) & 0x1f;
 268                         printk(KERN_DEBUG "%s bad port %lx at %p\n",
 269                                (*nip & 0x100)? "OUT to": "IN from",
 270                                regs->gpr[rb] - _IO_BASE, nip);
 271                         regs->msr |= MSR_RI;
 272                         regs->nip = entry->fixup;
 273                         return 1;
 274                 }
 275         }
 276 #endif /* CONFIG_PPC_PMAC */
 277         return 0;
 278 }
 279
 280 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
 281 /* On 4xx, the reason for the machine check or program exception
 282    is in the ESR. */
 283 #define get_reason(regs)        ((regs)->dsisr)
 284 #ifndef CONFIG_FSL_BOOKE
 285 #define get_mc_reason(regs)     ((regs)->dsisr)
 286 #else
 287 #define get_mc_reason(regs)     (mfspr(SPRN_MCSR))
 288 #endif
 289 #define REASON_FP               ESR_FP
 290 #define REASON_ILLEGAL          (ESR_PIL | ESR_PUO)
 291 #define REASON_PRIVILEGED       ESR_PPR
 292 #define REASON_TRAP             ESR_PTR
 293
 294 /* single-step stuff */
 295 #define single_stepping(regs)   (current->thread.dbcr0 & DBCR0_IC)
 296 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
 297
 298 #else
 299 /* On non-4xx, the reason for the machine check or program
 300    exception is in the MSR. */
 301 #define get_reason(regs)        ((regs)->msr)
 302 #define get_mc_reason(regs)     ((regs)->msr)
 303 #define REASON_FP               0x100000
 304 #define REASON_ILLEGAL          0x80000
 305 #define REASON_PRIVILEGED       0x40000
 306 #define REASON_TRAP             0x20000
 307
 308 #define single_stepping(regs)   ((regs)->msr & MSR_SE)
 309 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
 310 #endif
 311
 312 /*
 313  * This is "fall-back" implementation for configurations
 314  * which don't provide platform-specific machine check info
 315  */
 316 void __attribute__ ((weak))
 317 platform_machine_check(struct pt_regs *regs)
 318 {
 319 }
 320
 321 void machine_check_exception(struct pt_regs *regs)
 322 {
 323 #ifdef CONFIG_PPC64
 324         int recover = 0;
 325
 326         /* See if any machine dependent calls */
 327         if (ppc_md.machine_check_exception)
 328                 recover = ppc_md.machine_check_exception(regs);
 329
 330         if (recover)
 331                 return;
 332 #else
 333         unsigned long reason = get_mc_reason(regs);
 334
 335         if (user_mode(regs)) {
 336                 regs->msr |= MSR_RI;
 337                 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
 338                 return;
 339         }
 340
 341 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
 342         /* the qspan pci read routines can cause machine checks -- Cort */
 343         bad_page_fault(regs, regs->dar, SIGBUS);
 344         return;
 345 #endif
 346
 347         if (debugger_fault_handler(regs)) {
 348                 regs->msr |= MSR_RI;
 349                 return;
 350         }
 351
 352         if (check_io_access(regs))
 353                 return;
 354
 355 #if defined(CONFIG_4xx) && !defined(CONFIG_440A)
 356         if (reason & ESR_IMCP) {
 357                 printk("Instruction");
 358                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 359         } else
 360                 printk("Data");
 361         printk(" machine check in kernel mode.\n");
 362 #elif defined(CONFIG_440A)
 363         printk("Machine check in kernel mode.\n");
 364         if (reason & ESR_IMCP){
 365                 printk("Instruction Synchronous Machine Check exception\n");
 366                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 367         }
 368         else {
 369                 u32 mcsr = mfspr(SPRN_MCSR);
 370                 if (mcsr & MCSR_IB)
 371                         printk("Instruction Read PLB Error\n");
 372                 if (mcsr & MCSR_DRB)
 373                         printk("Data Read PLB Error\n");
 374                 if (mcsr & MCSR_DWB)
 375                         printk("Data Write PLB Error\n");
 376                 if (mcsr & MCSR_TLBP)
 377                         printk("TLB Parity Error\n");
 378                 if (mcsr & MCSR_ICP){
 379                         flush_instruction_cache();
 380                         printk("I-Cache Parity Error\n");
 381                 }
 382                 if (mcsr & MCSR_DCSP)
 383                         printk("D-Cache Search Parity Error\n");
 384                 if (mcsr & MCSR_DCFP)
 385                         printk("D-Cache Flush Parity Error\n");
 386                 if (mcsr & MCSR_IMPE)
 387                         printk("Machine Check exception is imprecise\n");
 388
 389                 /* Clear MCSR */
 390                 mtspr(SPRN_MCSR, mcsr);
 391         }
 392 #elif defined (CONFIG_E500)
 393         printk("Machine check in kernel mode.\n");
 394         printk("Caused by (from MCSR=%lx): ", reason);
 395
 396         if (reason & MCSR_MCP)
 397                 printk("Machine Check Signal\n");
 398         if (reason & MCSR_ICPERR)
 399                 printk("Instruction Cache Parity Error\n");
 400         if (reason & MCSR_DCP_PERR)
 401                 printk("Data Cache Push Parity Error\n");
 402         if (reason & MCSR_DCPERR)
 403                 printk("Data Cache Parity Error\n");
 404         if (reason & MCSR_GL_CI)
 405                 printk("Guarded Load or Cache-Inhibited stwcx.\n");
 406         if (reason & MCSR_BUS_IAERR)
 407                 printk("Bus - Instruction Address Error\n");
 408         if (reason & MCSR_BUS_RAERR)
 409                 printk("Bus - Read Address Error\n");
 410         if (reason & MCSR_BUS_WAERR)
 411                 printk("Bus - Write Address Error\n");
 412         if (reason & MCSR_BUS_IBERR)
 413                 printk("Bus - Instruction Data Error\n");
 414         if (reason & MCSR_BUS_RBERR)
 415                 printk("Bus - Read Data Bus Error\n");
 416         if (reason & MCSR_BUS_WBERR)
 417                 printk("Bus - Read Data Bus Error\n");
 418         if (reason & MCSR_BUS_IPERR)
 419                 printk("Bus - Instruction Parity Error\n");
 420         if (reason & MCSR_BUS_RPERR)
 421                 printk("Bus - Read Parity Error\n");
 422 #elif defined (CONFIG_E200)
 423         printk("Machine check in kernel mode.\n");
 424         printk("Caused by (from MCSR=%lx): ", reason);
 425
 426         if (reason & MCSR_MCP)
 427                 printk("Machine Check Signal\n");
 428         if (reason & MCSR_CP_PERR)
 429                 printk("Cache Push Parity Error\n");
 430         if (reason & MCSR_CPERR)
 431                 printk("Cache Parity Error\n");
 432         if (reason & MCSR_EXCP_ERR)
 433                 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
 434         if (reason & MCSR_BUS_IRERR)
 435                 printk("Bus - Read Bus Error on instruction fetch\n");
 436         if (reason & MCSR_BUS_DRERR)
 437                 printk("Bus - Read Bus Error on data load\n");
 438         if (reason & MCSR_BUS_WRERR)
 439                 printk("Bus - Write Bus Error on buffered store or cache line push\n");
 440 #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
 441         printk("Machine check in kernel mode.\n");
 442         printk("Caused by (from SRR1=%lx): ", reason);
 443         switch (reason & 0x601F0000) {
 444         case 0x80000:
 445                 printk("Machine check signal\n");
 446                 break;
 447         case 0:         /* for 601 */
 448         case 0x40000:
 449         case 0x140000:  /* 7450 MSS error and TEA */
 450                 printk("Transfer error ack signal\n");
 451                 break;
 452         case 0x20000:
 453                 printk("Data parity error signal\n");
 454                 break;
 455         case 0x10000:
 456                 printk("Address parity error signal\n");
 457                 break;
 458         case 0x20000000:
 459                 printk("L1 Data Cache error\n");
 460                 break;
 461         case 0x40000000:
 462                 printk("L1 Instruction Cache error\n");
 463                 break;
 464         case 0x00100000:
 465                 printk("L2 data cache parity error\n");
 466                 break;
 467         default:
 468                 printk("Unknown values in msr\n");
 469         }
 470 #endif /* CONFIG_4xx */
 471
 472         /*
 473          * Optional platform-provided routine to print out
 474          * additional info, e.g. bus error registers.
 475          */
 476         platform_machine_check(regs);
 477 #endif /* CONFIG_PPC64 */
 478
 479         if (debugger_fault_handler(regs))
 480                 return;
 481         die("Machine check", regs, SIGBUS);
 482
 483         /* Must die if the interrupt is not recoverable */
 484         if (!(regs->msr & MSR_RI))
 485                 panic("Unrecoverable Machine check");
 486 }
 487
 488 void SMIException(struct pt_regs *regs)
 489 {
 490         die("System Management Interrupt", regs, SIGABRT);
 491 }
 492
 493 void unknown_exception(struct pt_regs *regs)
 494 {
 495         printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
 496                regs->nip, regs->msr, regs->trap);
 497
 498         _exception(SIGTRAP, regs, 0, 0);
 499 }
 500
 501 void instruction_breakpoint_exception(struct pt_regs *regs)
 502 {
 503         if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
 504                                         5, SIGTRAP) == NOTIFY_STOP)
 505                 return;
 506         if (debugger_iabr_match(regs))
 507                 return;
 508         _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
 509 }
 510
 511 void RunModeException(struct pt_regs *regs)
 512 {
 513         _exception(SIGTRAP, regs, 0, 0);
 514 }
 515
 516 void __kprobes single_step_exception(struct pt_regs *regs)
 517 {
 518         regs->msr &= ~(MSR_SE | MSR_BE);  /* Turn off 'trace' bits */
 519
 520         if (notify_die(DIE_SSTEP, "single_step", regs, 5,
 521                                         5, SIGTRAP) == NOTIFY_STOP)
 522                 return;
 523         if (debugger_sstep(regs))
 524                 return;
 525
 526         _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
 527 }
 528
 529 /*
 530  * After we have successfully emulated an instruction, we have to
 531  * check if the instruction was being single-stepped, and if so,
 532  * pretend we got a single-step exception.  This was pointed out
 533  * by Kumar Gala.  -- paulus
 534  */
 535 static void emulate_single_step(struct pt_regs *regs)
 536 {
 537         if (single_stepping(regs)) {
 538                 clear_single_step(regs);
 539                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 540         }
 541 }
 542
 543 static void parse_fpe(struct pt_regs *regs)
 544 {
 545         int code = 0;
 546         unsigned long fpscr;
 547
 548         flush_fp_to_thread(current);
 549
 550         fpscr = current->thread.fpscr.val;
 551
 552         /* Invalid operation */
 553         if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
 554                 code = FPE_FLTINV;
 555
 556         /* Overflow */
 557         else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
 558                 code = FPE_FLTOVF;
 559
 560         /* Underflow */
 561         else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
 562                 code = FPE_FLTUND;
 563
 564         /* Divide by zero */
 565         else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
 566                 code = FPE_FLTDIV;
 567
 568         /* Inexact result */
 569         else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
 570                 code = FPE_FLTRES;
 571
 572         _exception(SIGFPE, regs, code, regs->nip);
 573 }
 574
 575 /*
 576  * Illegal instruction emulation support.  Originally written to
 577  * provide the PVR to user applications using the mfspr rd, PVR.
 578  * Return non-zero if we can't emulate, or -EFAULT if the associated
 579  * memory access caused an access fault.  Return zero on success.
 580  *
 581  * There are a couple of ways to do this, either "decode" the instruction
 582  * or directly match lots of bits.  In this case, matching lots of
 583  * bits is faster and easier.
 584  *
 585  */
 586 #define INST_MFSPR_PVR          0x7c1f42a6
 587 #define INST_MFSPR_PVR_MASK     0xfc1fffff
 588
 589 #define INST_DCBA               0x7c0005ec
 590 #define INST_DCBA_MASK          0x7c0007fe
 591
 592 #define INST_MCRXR              0x7c000400
 593 #define INST_MCRXR_MASK         0x7c0007fe
 594
 595 #define INST_STRING             0x7c00042a
 596 #define INST_STRING_MASK        0x7c0007fe
 597 #define INST_STRING_GEN_MASK    0x7c00067e
 598 #define INST_LSWI               0x7c0004aa
 599 #define INST_LSWX               0x7c00042a
 600 #define INST_STSWI              0x7c0005aa
 601 #define INST_STSWX              0x7c00052a
 602
 603 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
 604 {
 605         u8 rT = (instword >> 21) & 0x1f;
 606         u8 rA = (instword >> 16) & 0x1f;
 607         u8 NB_RB = (instword >> 11) & 0x1f;
 608         u32 num_bytes;
 609         unsigned long EA;
 610         int pos = 0;
 611
 612         /* Early out if we are an invalid form of lswx */
 613         if ((instword & INST_STRING_MASK) == INST_LSWX)
 614                 if ((rT == rA) || (rT == NB_RB))
 615                         return -EINVAL;
 616
 617         EA = (rA == 0) ? 0 : regs->gpr[rA];
 618
 619         switch (instword & INST_STRING_MASK) {
 620                 case INST_LSWX:
 621                 case INST_STSWX:
 622                         EA += NB_RB;
 623                         num_bytes = regs->xer & 0x7f;
 624                         break;
 625                 case INST_LSWI:
 626                 case INST_STSWI:
 627                         num_bytes = (NB_RB == 0) ? 32 : NB_RB;
 628                         break;
 629                 default:
 630                         return -EINVAL;
 631         }
 632
 633         while (num_bytes != 0)
 634         {
 635                 u8 val;
 636                 u32 shift = 8 * (3 - (pos & 0x3));
 637
 638                 switch ((instword & INST_STRING_MASK)) {
 639                         case INST_LSWX:
 640                         case INST_LSWI:
 641                                 if (get_user(val, (u8 __user *)EA))
 642                                         return -EFAULT;
 643                                 /* first time updating this reg,
 644                                  * zero it out */
 645                                 if (pos == 0)
 646                                         regs->gpr[rT] = 0;
 647                                 regs->gpr[rT] |= val << shift;
 648                                 break;
 649                         case INST_STSWI:
 650                         case INST_STSWX:
 651                                 val = regs->gpr[rT] >> shift;
 652                                 if (put_user(val, (u8 __user *)EA))
 653                                         return -EFAULT;
 654                                 break;
 655                 }
 656                 /* move EA to next address */
 657                 EA += 1;
 658                 num_bytes--;
 659
 660                 /* manage our position within the register */
 661                 if (++pos == 4) {
 662                         pos = 0;
 663                         if (++rT == 32)
 664                                 rT = 0;
 665                 }
 666         }
 667
 668         return 0;
 669 }
 670
 671 static int emulate_instruction(struct pt_regs *regs)
 672 {
 673         u32 instword;
 674         u32 rd;
 675
 676         if (!user_mode(regs))
 677                 return -EINVAL;
 678         CHECK_FULL_REGS(regs);
 679
 680         if (get_user(instword, (u32 __user *)(regs->nip)))
 681                 return -EFAULT;
 682
 683         /* Emulate the mfspr rD, PVR. */
 684         if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
 685                 rd = (instword >> 21) & 0x1f;
 686                 regs->gpr[rd] = mfspr(SPRN_PVR);
 687                 return 0;
 688         }
 689
 690         /* Emulating the dcba insn is just a no-op.  */
 691         if ((instword & INST_DCBA_MASK) == INST_DCBA)
 692                 return 0;
 693
 694         /* Emulate the mcrxr insn.  */
 695         if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
 696                 int shift = (instword >> 21) & 0x1c;
 697                 unsigned long msk = 0xf0000000UL >> shift;
 698
 699                 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
 700                 regs->xer &= ~0xf0000000UL;
 701                 return 0;
 702         }
 703
 704         /* Emulate load/store string insn. */
 705         if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
 706                 return emulate_string_inst(regs, instword);
 707
 708         return -EINVAL;
 709 }
 710
 711 /*
 712  * Look through the list of trap instructions that are used for BUG(),
 713  * BUG_ON() and WARN_ON() and see if we hit one.  At this point we know
 714  * that the exception was caused by a trap instruction of some kind.
 715  * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
 716  * otherwise.
 717  */
 718 extern struct bug_entry __start___bug_table[], __stop___bug_table[];
 719
 720 #ifndef CONFIG_MODULES
 721 #define module_find_bug(x)      NULL
 722 #endif
 723
 724 struct bug_entry *find_bug(unsigned long bugaddr)
 725 {
 726         struct bug_entry *bug;
 727
 728         for (bug = __start___bug_table; bug < __stop___bug_table; ++bug)
 729                 if (bugaddr == bug->bug_addr)
 730                         return bug;
 731         return module_find_bug(bugaddr);
 732 }
 733
 734 static int check_bug_trap(struct pt_regs *regs)
 735 {
 736         struct bug_entry *bug;
 737         unsigned long addr;
 738
 739         if (regs->msr & MSR_PR)
 740                 return 0;       /* not in kernel */
 741         addr = regs->nip;       /* address of trap instruction */
 742         if (addr < PAGE_OFFSET)
 743                 return 0;
 744         bug = find_bug(regs->nip);
 745         if (bug == NULL)
 746                 return 0;
 747         if (bug->line & BUG_WARNING_TRAP) {
 748                 /* this is a WARN_ON rather than BUG/BUG_ON */
 749                 printk(KERN_ERR "Badness in %s at %s:%ld\n",
 750                        bug->function, bug->file,
 751                        bug->line & ~BUG_WARNING_TRAP);
 752                 dump_stack();
 753                 return 1;
 754         }
 755         printk(KERN_CRIT "kernel BUG in %s at %s:%ld!\n",
 756                bug->function, bug->file, bug->line);
 757
 758         return 0;
 759 }
 760
 761 void __kprobes program_check_exception(struct pt_regs *regs)
 762 {
 763         unsigned int reason = get_reason(regs);
 764         extern int do_mathemu(struct pt_regs *regs);
 765
 766 #ifdef CONFIG_MATH_EMULATION
 767         /* (reason & REASON_ILLEGAL) would be the obvious thing here,
 768          * but there seems to be a hardware bug on the 405GP (RevD)
 769          * that means ESR is sometimes set incorrectly - either to
 770          * ESR_DST (!?) or 0.  In the process of chasing this with the
 771          * hardware people - not sure if it can happen on any illegal
 772          * instruction or only on FP instructions, whether there is a
 773          * pattern to occurences etc. -dgibson 31/Mar/2003 */
 774         if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
 775                 emulate_single_step(regs);
 776                 return;
 777         }
 778 #endif /* CONFIG_MATH_EMULATION */
 779
 780         if (reason & REASON_FP) {
 781                 /* IEEE FP exception */
 782                 parse_fpe(regs);
 783                 return;
 784         }
 785         if (reason & REASON_TRAP) {
 786                 /* trap exception */
 787                 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
 788                                 == NOTIFY_STOP)
 789                         return;
 790                 if (debugger_bpt(regs))
 791                         return;
 792                 if (check_bug_trap(regs)) {
 793                         regs->nip += 4;
 794                         return;
 795                 }
 796                 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
 797                 return;
 798         }
 799
 800         /* Try to emulate it if we should. */
 801         if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
 802                 switch (emulate_instruction(regs)) {
 803                 case 0:
 804                         regs->nip += 4;
 805                         emulate_single_step(regs);
 806                         return;
 807                 case -EFAULT:
 808                         _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
 809                         return;
 810                 }
 811         }
 812
 813         if (reason & REASON_PRIVILEGED)
 814                 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
 815         else
 816                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 817 }
 818
 819 void alignment_exception(struct pt_regs *regs)
 820 {
 821         int fixed;
 822
 823         fixed = fix_alignment(regs);
 824
 825         if (fixed == 1) {
 826                 regs->nip += 4; /* skip over emulated instruction */
 827                 emulate_single_step(regs);
 828                 return;
 829         }
 830
 831         /* Operand address was bad */
 832         if (fixed == -EFAULT) {
 833                 if (user_mode(regs))
 834                         _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar);
 835                 else
 836                         /* Search exception table */
 837                         bad_page_fault(regs, regs->dar, SIGSEGV);
 838                 return;
 839         }
 840         _exception(SIGBUS, regs, BUS_ADRALN, regs->dar);
 841 }
 842
 843 void StackOverflow(struct pt_regs *regs)
 844 {
 845         printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
 846                current, regs->gpr[1]);
 847         debugger(regs);
 848         show_regs(regs);
 849         panic("kernel stack overflow");
 850 }
 851
 852 void nonrecoverable_exception(struct pt_regs *regs)
 853 {
 854         printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
 855                regs->nip, regs->msr);
 856         debugger(regs);
 857         die("nonrecoverable exception", regs, SIGKILL);
 858 }
 859
 860 void trace_syscall(struct pt_regs *regs)
 861 {
 862         printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld    %s\n",
 863                current, current->pid, regs->nip, regs->link, regs->gpr[0],
 864                regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
 865 }
 866
 867 void kernel_fp_unavailable_exception(struct pt_regs *regs)
 868 {
 869         printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
 870                           "%lx at %lx\n", regs->trap, regs->nip);
 871         die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
 872 }
 873
 874 void altivec_unavailable_exception(struct pt_regs *regs)
 875 {
 876 #if !defined(CONFIG_ALTIVEC)
 877         if (user_mode(regs)) {
 878                 /* A user program has executed an altivec instruction,
 879                    but this kernel doesn't support altivec. */
 880                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 881                 return;
 882         }
 883 #endif
 884         printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
 885                         "%lx at %lx\n", regs->trap, regs->nip);
 886         die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
 887 }
 888
 889 #if defined(CONFIG_PPC64) || defined(CONFIG_E500)
 890 void performance_monitor_exception(struct pt_regs *regs)
 891 {
 892         perf_irq(regs);
 893 }
 894 #endif
 895
 896 #ifdef CONFIG_8xx
 897 void SoftwareEmulation(struct pt_regs *regs)
 898 {
 899         extern int do_mathemu(struct pt_regs *);
 900         extern int Soft_emulate_8xx(struct pt_regs *);
 901         int errcode;
 902
 903         CHECK_FULL_REGS(regs);
 904
 905         if (!user_mode(regs)) {
 906                 debugger(regs);
 907                 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
 908         }
 909
 910 #ifdef CONFIG_MATH_EMULATION
 911         errcode = do_mathemu(regs);
 912 #else
 913         errcode = Soft_emulate_8xx(regs);
 914 #endif
 915         if (errcode) {
 916                 if (errcode > 0)
 917                         _exception(SIGFPE, regs, 0, 0);
 918                 else if (errcode == -EFAULT)
 919                         _exception(SIGSEGV, regs, 0, 0);
 920                 else
 921                         _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 922         } else
 923                 emulate_single_step(regs);
 924 }
 925 #endif /* CONFIG_8xx */
 926
 927 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
 928
 929 void DebugException(struct pt_regs *regs, unsigned long debug_status)
 930 {
 931         if (debug_status & DBSR_IC) {   /* instruction completion */
 932                 regs->msr &= ~MSR_DE;
 933                 if (user_mode(regs)) {
 934                         current->thread.dbcr0 &= ~DBCR0_IC;
 935                 } else {
 936                         /* Disable instruction completion */
 937                         mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
 938                         /* Clear the instruction completion event */
 939                         mtspr(SPRN_DBSR, DBSR_IC);
 940                         if (debugger_sstep(regs))
 941                                 return;
 942                 }
 943                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 944         }
 945 }
 946 #endif /* CONFIG_4xx || CONFIG_BOOKE */
 947
 948 #if !defined(CONFIG_TAU_INT)
 949 void TAUException(struct pt_regs *regs)
 950 {
 951         printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
 952                regs->nip, regs->msr, regs->trap, print_tainted());
 953 }
 954 #endif /* CONFIG_INT_TAU */
 955
 956 #ifdef CONFIG_ALTIVEC
 957 void altivec_assist_exception(struct pt_regs *regs)
 958 {
 959         int err;
 960
 961         if (!user_mode(regs)) {
 962                 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
 963                        " at %lx\n", regs->nip);
 964                 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
 965         }
 966
 967         flush_altivec_to_thread(current);
 968
 969         err = emulate_altivec(regs);
 970         if (err == 0) {
 971                 regs->nip += 4;         /* skip emulated instruction */
 972                 emulate_single_step(regs);
 973                 return;
 974         }
 975
 976         if (err == -EFAULT) {
 977                 /* got an error reading the instruction */
 978                 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
 979         } else {
 980                 /* didn't recognize the instruction */
 981                 /* XXX quick hack for now: set the non-Java bit in the VSCR */
 982                 if (printk_ratelimit())
 983                         printk(KERN_ERR "Unrecognized altivec instruction "
 984                                "in %s at %lx\n", current->comm, regs->nip);
 985                 current->thread.vscr.u[3] |= 0x10000;
 986         }
 987 }
 988 #endif /* CONFIG_ALTIVEC */
 989
 990 #ifdef CONFIG_FSL_BOOKE
 991 void CacheLockingException(struct pt_regs *regs, unsigned long address,
 992                            unsigned long error_code)
 993 {
 994         /* We treat cache locking instructions from the user
 995          * as priv ops, in the future we could try to do
 996          * something smarter
 997          */
 998         if (error_code & (ESR_DLK|ESR_ILK))
 999                 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1000         return;
1001 }
1002 #endif /* CONFIG_FSL_BOOKE */
1003
1004 #ifdef CONFIG_SPE
1005 void SPEFloatingPointException(struct pt_regs *regs)
1006 {
1007         unsigned long spefscr;
1008         int fpexc_mode;
1009         int code = 0;
1010
1011         spefscr = current->thread.spefscr;
1012         fpexc_mode = current->thread.fpexc_mode;
1013
1014         /* Hardware does not neccessarily set sticky
1015          * underflow/overflow/invalid flags */
1016         if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1017                 code = FPE_FLTOVF;
1018                 spefscr |= SPEFSCR_FOVFS;
1019         }
1020         else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1021                 code = FPE_FLTUND;
1022                 spefscr |= SPEFSCR_FUNFS;
1023         }
1024         else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1025                 code = FPE_FLTDIV;
1026         else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1027                 code = FPE_FLTINV;
1028                 spefscr |= SPEFSCR_FINVS;
1029         }
1030         else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1031                 code = FPE_FLTRES;
1032
1033         current->thread.spefscr = spefscr;
1034
1035         _exception(SIGFPE, regs, code, regs->nip);
1036         return;
1037 }
1038 #endif
1039
1040 /*
1041  * We enter here if we get an unrecoverable exception, that is, one
1042  * that happened at a point where the RI (recoverable interrupt) bit
1043  * in the MSR is 0.  This indicates that SRR0/1 are live, and that
1044  * we therefore lost state by taking this exception.
1045  */
1046 void unrecoverable_exception(struct pt_regs *regs)
1047 {
1048         printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1049                regs->trap, regs->nip);
1050         die("Unrecoverable exception", regs, SIGABRT);
1051 }
1052
1053 #ifdef CONFIG_BOOKE_WDT
1054 /*
1055  * Default handler for a Watchdog exception,
1056  * spins until a reboot occurs
1057  */
1058 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1059 {
1060         /* Generic WatchdogHandler, implement your own */
1061         mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1062         return;
1063 }
1064
1065 void WatchdogException(struct pt_regs *regs)
1066 {
1067         printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1068         WatchdogHandler(regs);
1069 }
1070 #endif
1071
1072 /*
1073  * We enter here if we discover during exception entry that we are
1074  * running in supervisor mode with a userspace value in the stack pointer.
1075  */
1076 void kernel_bad_stack(struct pt_regs *regs)
1077 {
1078         printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1079                regs->gpr[1], regs->nip);
1080         die("Bad kernel stack pointer", regs, SIGABRT);
1081 }
1082
1083 void __init trap_init(void)
1084 {
1085 }