arch/ppc/syslib/ppc4xx_setup.c

   1 /*
   2  *
   3  *    Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
   4  *
   5  *    Copyright 2000-2001 MontaVista Software Inc.
   6  *      Completed implementation.
   7  *      Author: MontaVista Software, Inc.  <source@mvista.com>
   8  *              Frank Rowand <frank_rowand@mvista.com>
   9  *              Debbie Chu   <debbie_chu@mvista.com>
  10  *      Further modifications by Armin Kuster
  11  *
  12  *    Module name: ppc4xx_setup.c
  13  *
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/init.h>
  18 #include <linux/smp.h>
  19 #include <linux/threads.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/reboot.h>
  22 #include <linux/param.h>
  23 #include <linux/string.h>
  24 #include <linux/initrd.h>
  25 #include <linux/pci.h>
  26 #include <linux/rtc.h>
  27 #include <linux/console.h>
  28 #include <linux/ide.h>
  29 #include <linux/serial_reg.h>
  30 #include <linux/seq_file.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/processor.h>
  34 #include <asm/machdep.h>
  35 #include <asm/page.h>
  36 #include <asm/kgdb.h>
  37 #include <asm/ibm4xx.h>
  38 #include <asm/time.h>
  39 #include <asm/todc.h>
  40 #include <asm/ppc4xx_pic.h>
  41 #include <asm/pci-bridge.h>
  42 #include <asm/bootinfo.h>
  43
  44 #include <syslib/gen550.h>
  45
  46 /* Function Prototypes */
  47 extern void abort(void);
  48 extern void ppc4xx_find_bridges(void);
  49
  50 /* Global Variables */
  51 bd_t __res;
  52
  53 void __init
  54 ppc4xx_setup_arch(void)
  55 {
  56 #if !defined(CONFIG_BDI_SWITCH)
  57         /*
  58          * The Abatron BDI JTAG debugger does not tolerate others
  59          * mucking with the debug registers.
  60          */
  61         mtspr(SPRN_DBCR0, (DBCR0_IDM));
  62         mtspr(SPRN_DBSR, 0xffffffff);
  63 #endif
  64
  65         /* Setup PCI host bridges */
  66 #ifdef CONFIG_PCI
  67         ppc4xx_find_bridges();
  68 #endif
  69 }
  70
  71 /*
  72  *   This routine pretty-prints the platform's internal CPU clock
  73  *   frequencies into the buffer for usage in /proc/cpuinfo.
  74  */
  75
  76 static int
  77 ppc4xx_show_percpuinfo(struct seq_file *m, int i)
  78 {
  79         seq_printf(m, "clock\t\t: %ldMHz\n", (long)__res.bi_intfreq / 1000000);
  80
  81         return 0;
  82 }
  83
  84 /*
  85  *   This routine pretty-prints the platform's internal bus clock
  86  *   frequencies into the buffer for usage in /proc/cpuinfo.
  87  */
  88 static int
  89 ppc4xx_show_cpuinfo(struct seq_file *m)
  90 {
  91         bd_t *bip = &__res;
  92
  93         seq_printf(m, "machine\t\t: %s\n", PPC4xx_MACHINE_NAME);
  94         seq_printf(m, "plb bus clock\t: %ldMHz\n",
  95                    (long) bip->bi_busfreq / 1000000);
  96 #ifdef CONFIG_PCI
  97         seq_printf(m, "pci bus clock\t: %dMHz\n",
  98                    bip->bi_pci_busfreq / 1000000);
  99 #endif
 100
 101         return 0;
 102 }
 103
 104 /*
 105  * Return the virtual address representing the top of physical RAM.
 106  */
 107 static unsigned long __init
 108 ppc4xx_find_end_of_memory(void)
 109 {
 110         return ((unsigned long) __res.bi_memsize);
 111 }
 112
 113 void __init
 114 ppc4xx_map_io(void)
 115 {
 116         io_block_mapping(PPC4xx_ONB_IO_VADDR,
 117                          PPC4xx_ONB_IO_PADDR, PPC4xx_ONB_IO_SIZE, _PAGE_IO);
 118 #ifdef CONFIG_PCI
 119         io_block_mapping(PPC4xx_PCI_IO_VADDR,
 120                          PPC4xx_PCI_IO_PADDR, PPC4xx_PCI_IO_SIZE, _PAGE_IO);
 121         io_block_mapping(PPC4xx_PCI_CFG_VADDR,
 122                          PPC4xx_PCI_CFG_PADDR, PPC4xx_PCI_CFG_SIZE, _PAGE_IO);
 123         io_block_mapping(PPC4xx_PCI_LCFG_VADDR,
 124                          PPC4xx_PCI_LCFG_PADDR, PPC4xx_PCI_LCFG_SIZE, _PAGE_IO);
 125 #endif
 126 }
 127
 128 void __init
 129 ppc4xx_init_IRQ(void)
 130 {
 131         ppc4xx_pic_init();
 132 }
 133
 134 static void
 135 ppc4xx_restart(char *cmd)
 136 {
 137         printk("%s\n", cmd);
 138         abort();
 139 }
 140
 141 static void
 142 ppc4xx_power_off(void)
 143 {
 144         printk("System Halted\n");
 145         local_irq_disable();
 146         while (1) ;
 147 }
 148
 149 static void
 150 ppc4xx_halt(void)
 151 {
 152         printk("System Halted\n");
 153         local_irq_disable();
 154         while (1) ;
 155 }
 156
 157 /*
 158  * This routine retrieves the internal processor frequency from the board
 159  * information structure, sets up the kernel timer decrementer based on
 160  * that value, enables the 4xx programmable interval timer (PIT) and sets
 161  * it up for auto-reload.
 162  */
 163 static void __init
 164 ppc4xx_calibrate_decr(void)
 165 {
 166         unsigned int freq;
 167         bd_t *bip = &__res;
 168
 169 #if defined(CONFIG_WALNUT) || defined(CONFIG_SYCAMORE)
 170         /* Walnut boot rom sets DCR CHCR1 (aka CPC0_CR1) bit CETE to 1 */
 171         mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE);
 172 #endif
 173         freq = bip->bi_tbfreq;
 174         tb_ticks_per_jiffy = freq / HZ;
 175         tb_to_us = mulhwu_scale_factor(freq, 1000000);
 176
 177         /* Set the time base to zero.
 178            ** At 200 Mhz, time base will rollover in ~2925 years.
 179          */
 180
 181         mtspr(SPRN_TBWL, 0);
 182         mtspr(SPRN_TBWU, 0);
 183
 184         /* Clear any pending timer interrupts */
 185
 186         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_PIS | TSR_FIS);
 187         mtspr(SPRN_TCR, TCR_PIE | TCR_ARE);
 188
 189         /* Set the PIT reload value and just let it run. */
 190         mtspr(SPRN_PIT, tb_ticks_per_jiffy);
 191 }
 192
 193 /*
 194  * IDE stuff.
 195  * should be generic for every IDE PCI chipset
 196  */
 197 #if defined(CONFIG_PCI) && defined(CONFIG_IDE)
 198 static void
 199 ppc4xx_ide_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
 200                            unsigned long ctrl_port, int *irq)
 201 {
 202         int i;
 203
 204         for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
 205                 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
 206
 207         hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
 208 }
 209 #endif /* defined(CONFIG_PCI) && defined(CONFIG_IDE) */
 210
 211 TODC_ALLOC();
 212
 213 /*
 214  * Input(s):
 215  *   r3 - Optional pointer to a board information structure.
 216  *   r4 - Optional pointer to the physical starting address of the init RAM
 217  *        disk.
 218  *   r5 - Optional pointer to the physical ending address of the init RAM
 219  *        disk.
 220  *   r6 - Optional pointer to the physical starting address of any kernel
 221  *        command-line parameters.
 222  *   r7 - Optional pointer to the physical ending address of any kernel
 223  *        command-line parameters.
 224  */
 225 void __init
 226 ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
 227             unsigned long r6, unsigned long r7)
 228 {
 229         parse_bootinfo(find_bootinfo());
 230
 231         /*
 232          * If we were passed in a board information, copy it into the
 233          * residual data area.
 234          */
 235         if (r3)
 236                 __res = *(bd_t *)(r3 + KERNELBASE);
 237
 238 #if defined(CONFIG_BLK_DEV_INITRD)
 239         /*
 240          * If the init RAM disk has been configured in, and there's a valid
 241          * starting address for it, set it up.
 242          */
 243         if (r4) {
 244                 initrd_start = r4 + KERNELBASE;
 245                 initrd_end = r5 + KERNELBASE;
 246         }
 247 #endif                          /* CONFIG_BLK_DEV_INITRD */
 248
 249         /* Copy the kernel command line arguments to a safe place. */
 250
 251         if (r6) {
 252                 *(char *) (r7 + KERNELBASE) = 0;
 253                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 254         }
 255
 256         /* Initialize machine-dependent vectors */
 257
 258         ppc_md.setup_arch = ppc4xx_setup_arch;
 259         ppc_md.show_percpuinfo = ppc4xx_show_percpuinfo;
 260         ppc_md.show_cpuinfo = ppc4xx_show_cpuinfo;
 261         ppc_md.init_IRQ = ppc4xx_init_IRQ;
 262
 263         ppc_md.restart = ppc4xx_restart;
 264         ppc_md.power_off = ppc4xx_power_off;
 265         ppc_md.halt = ppc4xx_halt;
 266
 267         ppc_md.calibrate_decr = ppc4xx_calibrate_decr;
 268
 269         ppc_md.find_end_of_memory = ppc4xx_find_end_of_memory;
 270         ppc_md.setup_io_mappings = ppc4xx_map_io;
 271
 272 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 273         ppc_md.progress = gen550_progress;
 274 #endif
 275
 276 #if defined(CONFIG_PCI) && defined(CONFIG_IDE)
 277         ppc_ide_md.ide_init_hwif = ppc4xx_ide_init_hwif_ports;
 278 #endif /* defined(CONFIG_PCI) && defined(CONFIG_IDE) */
 279 }
 280
 281 /* Called from machine_check_exception */
 282 void platform_machine_check(struct pt_regs *regs)
 283 {
 284 #if defined(DCRN_PLB0_BEAR)
 285         printk("PLB0: BEAR= 0x%08x ACR=   0x%08x BESR=  0x%08x\n",
 286             mfdcr(DCRN_PLB0_BEAR), mfdcr(DCRN_PLB0_ACR),
 287             mfdcr(DCRN_PLB0_BESR));
 288 #endif
 289 #if defined(DCRN_POB0_BEAR)
 290         printk("PLB0 to OPB: BEAR= 0x%08x BESR0= 0x%08x BESR1= 0x%08x\n",
 291             mfdcr(DCRN_POB0_BEAR), mfdcr(DCRN_POB0_BESR0),
 292             mfdcr(DCRN_POB0_BESR1));
 293 #endif
 294
 295 }