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ath9k_hw: Fix and complete force bias for AR5416
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / hw.c
blob111ff049f75dcfa152589f6f43fb8081e913d8b0
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "hw.h"
21 #include "rc.h"
22 #include "initvals.h"
23
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31 struct ar5416_eeprom_def *pEepData,
32 u32 reg, u32 value);
33
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
38
39 static int __init ath9k_init(void)
40 {
41 return 0;
42 }
43 module_init(ath9k_init);
44
45 static void __exit ath9k_exit(void)
46 {
47 return;
48 }
49 module_exit(ath9k_exit);
50
51 /********************/
52 /* Helper Functions */
53 /********************/
54
55 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
56 {
57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
58
59 if (!ah->curchan) /* should really check for CCK instead */
60 return clks / ATH9K_CLOCK_RATE_CCK;
61 if (conf->channel->band == IEEE80211_BAND_2GHZ)
62 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
63
64 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
65 }
66
67 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
68 {
69 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
70
71 if (conf_is_ht40(conf))
72 return ath9k_hw_mac_usec(ah, clks) / 2;
73 else
74 return ath9k_hw_mac_usec(ah, clks);
75 }
76
77 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
78 {
79 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
80
81 if (!ah->curchan) /* should really check for CCK instead */
82 return usecs *ATH9K_CLOCK_RATE_CCK;
83 if (conf->channel->band == IEEE80211_BAND_2GHZ)
84 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
85 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
86 }
87
88 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
89 {
90 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
91
92 if (conf_is_ht40(conf))
93 return ath9k_hw_mac_clks(ah, usecs) * 2;
94 else
95 return ath9k_hw_mac_clks(ah, usecs);
96 }
97
98 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
99 {
100 int i;
101
102 BUG_ON(timeout < AH_TIME_QUANTUM);
103
104 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
105 if ((REG_READ(ah, reg) & mask) == val)
106 return true;
107
108 udelay(AH_TIME_QUANTUM);
109 }
110
111 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
112 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
113 timeout, reg, REG_READ(ah, reg), mask, val);
114
115 return false;
116 }
117 EXPORT_SYMBOL(ath9k_hw_wait);
118
119 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
120 {
121 u32 retval;
122 int i;
123
124 for (i = 0, retval = 0; i < n; i++) {
125 retval = (retval << 1) | (val & 1);
126 val >>= 1;
127 }
128 return retval;
129 }
130
131 bool ath9k_get_channel_edges(struct ath_hw *ah,
132 u16 flags, u16 *low,
133 u16 *high)
134 {
135 struct ath9k_hw_capabilities *pCap = &ah->caps;
136
137 if (flags & CHANNEL_5GHZ) {
138 *low = pCap->low_5ghz_chan;
139 *high = pCap->high_5ghz_chan;
140 return true;
141 }
142 if ((flags & CHANNEL_2GHZ)) {
143 *low = pCap->low_2ghz_chan;
144 *high = pCap->high_2ghz_chan;
145 return true;
146 }
147 return false;
148 }
149
150 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
151 const struct ath_rate_table *rates,
152 u32 frameLen, u16 rateix,
153 bool shortPreamble)
154 {
155 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
156 u32 kbps;
157
158 kbps = rates->info[rateix].ratekbps;
159
160 if (kbps == 0)
161 return 0;
162
163 switch (rates->info[rateix].phy) {
164 case WLAN_RC_PHY_CCK:
165 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
166 if (shortPreamble && rates->info[rateix].short_preamble)
167 phyTime >>= 1;
168 numBits = frameLen << 3;
169 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
170 break;
171 case WLAN_RC_PHY_OFDM:
172 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
173 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
174 numBits = OFDM_PLCP_BITS + (frameLen << 3);
175 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
176 txTime = OFDM_SIFS_TIME_QUARTER
177 + OFDM_PREAMBLE_TIME_QUARTER
178 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
179 } else if (ah->curchan &&
180 IS_CHAN_HALF_RATE(ah->curchan)) {
181 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
182 numBits = OFDM_PLCP_BITS + (frameLen << 3);
183 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
184 txTime = OFDM_SIFS_TIME_HALF +
185 OFDM_PREAMBLE_TIME_HALF
186 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
187 } else {
188 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
189 numBits = OFDM_PLCP_BITS + (frameLen << 3);
190 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
191 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
192 + (numSymbols * OFDM_SYMBOL_TIME);
193 }
194 break;
195 default:
196 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
197 "Unknown phy %u (rate ix %u)\n",
198 rates->info[rateix].phy, rateix);
199 txTime = 0;
200 break;
201 }
202
203 return txTime;
204 }
205 EXPORT_SYMBOL(ath9k_hw_computetxtime);
206
207 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
208 struct ath9k_channel *chan,
209 struct chan_centers *centers)
210 {
211 int8_t extoff;
212
213 if (!IS_CHAN_HT40(chan)) {
214 centers->ctl_center = centers->ext_center =
215 centers->synth_center = chan->channel;
216 return;
217 }
218
219 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
220 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
221 centers->synth_center =
222 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
223 extoff = 1;
224 } else {
225 centers->synth_center =
226 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
227 extoff = -1;
228 }
229
230 centers->ctl_center =
231 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
232 /* 25 MHz spacing is supported by hw but not on upper layers */
233 centers->ext_center =
234 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
235 }
236
237 /******************/
238 /* Chip Revisions */
239 /******************/
240
241 static void ath9k_hw_read_revisions(struct ath_hw *ah)
242 {
243 u32 val;
244
245 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
246
247 if (val == 0xFF) {
248 val = REG_READ(ah, AR_SREV);
249 ah->hw_version.macVersion =
250 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
251 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
252 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
253 } else {
254 if (!AR_SREV_9100(ah))
255 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
256
257 ah->hw_version.macRev = val & AR_SREV_REVISION;
258
259 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
260 ah->is_pciexpress = true;
261 }
262 }
263
264 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
265 {
266 u32 val;
267 int i;
268
269 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
270
271 for (i = 0; i < 8; i++)
272 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
273 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
274 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
275
276 return ath9k_hw_reverse_bits(val, 8);
277 }
278
279 /************************************/
280 /* HW Attach, Detach, Init Routines */
281 /************************************/
282
283 static void ath9k_hw_disablepcie(struct ath_hw *ah)
284 {
285 if (AR_SREV_9100(ah))
286 return;
287
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
297
298 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
299 }
300
301 static bool ath9k_hw_chip_test(struct ath_hw *ah)
302 {
303 struct ath_common *common = ath9k_hw_common(ah);
304 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
305 u32 regHold[2];
306 u32 patternData[4] = { 0x55555555,
307 0xaaaaaaaa,
308 0x66666666,
309 0x99999999 };
310 int i, j;
311
312 for (i = 0; i < 2; i++) {
313 u32 addr = regAddr[i];
314 u32 wrData, rdData;
315
316 regHold[i] = REG_READ(ah, addr);
317 for (j = 0; j < 0x100; j++) {
318 wrData = (j << 16) | j;
319 REG_WRITE(ah, addr, wrData);
320 rdData = REG_READ(ah, addr);
321 if (rdData != wrData) {
322 ath_print(common, ATH_DBG_FATAL,
323 "address test failed "
324 "addr: 0x%08x - wr:0x%08x != "
325 "rd:0x%08x\n",
326 addr, wrData, rdData);
327 return false;
328 }
329 }
330 for (j = 0; j < 4; j++) {
331 wrData = patternData[j];
332 REG_WRITE(ah, addr, wrData);
333 rdData = REG_READ(ah, addr);
334 if (wrData != rdData) {
335 ath_print(common, ATH_DBG_FATAL,
336 "address test failed "
337 "addr: 0x%08x - wr:0x%08x != "
338 "rd:0x%08x\n",
339 addr, wrData, rdData);
340 return false;
341 }
342 }
343 REG_WRITE(ah, regAddr[i], regHold[i]);
344 }
345 udelay(100);
346
347 return true;
348 }
349
350 static const char *ath9k_hw_devname(u16 devid)
351 {
352 switch (devid) {
353 case AR5416_DEVID_PCI:
354 return "Atheros 5416";
355 case AR5416_DEVID_PCIE:
356 return "Atheros 5418";
357 case AR9160_DEVID_PCI:
358 return "Atheros 9160";
359 case AR5416_AR9100_DEVID:
360 return "Atheros 9100";
361 case AR9280_DEVID_PCI:
362 case AR9280_DEVID_PCIE:
363 return "Atheros 9280";
364 case AR9285_DEVID_PCIE:
365 return "Atheros 9285";
366 case AR5416_DEVID_AR9287_PCI:
367 case AR5416_DEVID_AR9287_PCIE:
368 return "Atheros 9287";
369 }
370
371 return NULL;
372 }
373
374 static void ath9k_hw_init_config(struct ath_hw *ah)
375 {
376 int i;
377
378 ah->config.dma_beacon_response_time = 2;
379 ah->config.sw_beacon_response_time = 10;
380 ah->config.additional_swba_backoff = 0;
381 ah->config.ack_6mb = 0x0;
382 ah->config.cwm_ignore_extcca = 0;
383 ah->config.pcie_powersave_enable = 0;
384 ah->config.pcie_clock_req = 0;
385 ah->config.pcie_waen = 0;
386 ah->config.analog_shiftreg = 1;
387 ah->config.ht_enable = 1;
388 ah->config.ofdm_trig_low = 200;
389 ah->config.ofdm_trig_high = 500;
390 ah->config.cck_trig_high = 200;
391 ah->config.cck_trig_low = 100;
392 ah->config.enable_ani = 1;
393 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
394 ah->config.antenna_switch_swap = 0;
395
396 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
397 ah->config.spurchans[i][0] = AR_NO_SPUR;
398 ah->config.spurchans[i][1] = AR_NO_SPUR;
399 }
400
401 ah->config.intr_mitigation = true;
402
403 /*
404 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
405 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
406 * This means we use it for all AR5416 devices, and the few
407 * minor PCI AR9280 devices out there.
408 *
409 * Serialization is required because these devices do not handle
410 * well the case of two concurrent reads/writes due to the latency
411 * involved. During one read/write another read/write can be issued
412 * on another CPU while the previous read/write may still be working
413 * on our hardware, if we hit this case the hardware poops in a loop.
414 * We prevent this by serializing reads and writes.
415 *
416 * This issue is not present on PCI-Express devices or pre-AR5416
417 * devices (legacy, 802.11abg).
418 */
419 if (num_possible_cpus() > 1)
420 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
421 }
422 EXPORT_SYMBOL(ath9k_hw_init);
423
424 static void ath9k_hw_init_defaults(struct ath_hw *ah)
425 {
426 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
427
428 regulatory->country_code = CTRY_DEFAULT;
429 regulatory->power_limit = MAX_RATE_POWER;
430 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
431
432 ah->hw_version.magic = AR5416_MAGIC;
433 ah->hw_version.subvendorid = 0;
434
435 ah->ah_flags = 0;
436 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
437 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
438 if (!AR_SREV_9100(ah))
439 ah->ah_flags = AH_USE_EEPROM;
440
441 ah->atim_window = 0;
442 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
443 ah->beacon_interval = 100;
444 ah->enable_32kHz_clock = DONT_USE_32KHZ;
445 ah->slottime = (u32) -1;
446 ah->acktimeout = (u32) -1;
447 ah->ctstimeout = (u32) -1;
448 ah->globaltxtimeout = (u32) -1;
449
450 ah->gbeacon_rate = 0;
451
452 ah->power_mode = ATH9K_PM_UNDEFINED;
453 }
454
455 static int ath9k_hw_rf_claim(struct ath_hw *ah)
456 {
457 u32 val;
458
459 REG_WRITE(ah, AR_PHY(0), 0x00000007);
460
461 val = ath9k_hw_get_radiorev(ah);
462 switch (val & AR_RADIO_SREV_MAJOR) {
463 case 0:
464 val = AR_RAD5133_SREV_MAJOR;
465 break;
466 case AR_RAD5133_SREV_MAJOR:
467 case AR_RAD5122_SREV_MAJOR:
468 case AR_RAD2133_SREV_MAJOR:
469 case AR_RAD2122_SREV_MAJOR:
470 break;
471 default:
472 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
473 "Radio Chip Rev 0x%02X not supported\n",
474 val & AR_RADIO_SREV_MAJOR);
475 return -EOPNOTSUPP;
476 }
477
478 ah->hw_version.analog5GhzRev = val;
479
480 return 0;
481 }
482
483 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
484 {
485 struct ath_common *common = ath9k_hw_common(ah);
486 u32 sum;
487 int i;
488 u16 eeval;
489
490 sum = 0;
491 for (i = 0; i < 3; i++) {
492 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
493 sum += eeval;
494 common->macaddr[2 * i] = eeval >> 8;
495 common->macaddr[2 * i + 1] = eeval & 0xff;
496 }
497 if (sum == 0 || sum == 0xffff * 3)
498 return -EADDRNOTAVAIL;
499
500 return 0;
501 }
502
503 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
504 {
505 u32 rxgain_type;
506
507 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
508 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
509
510 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
511 INIT_INI_ARRAY(&ah->iniModesRxGain,
512 ar9280Modes_backoff_13db_rxgain_9280_2,
513 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
514 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
515 INIT_INI_ARRAY(&ah->iniModesRxGain,
516 ar9280Modes_backoff_23db_rxgain_9280_2,
517 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
518 else
519 INIT_INI_ARRAY(&ah->iniModesRxGain,
520 ar9280Modes_original_rxgain_9280_2,
521 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
522 } else {
523 INIT_INI_ARRAY(&ah->iniModesRxGain,
524 ar9280Modes_original_rxgain_9280_2,
525 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
526 }
527 }
528
529 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
530 {
531 u32 txgain_type;
532
533 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
534 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
535
536 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
537 INIT_INI_ARRAY(&ah->iniModesTxGain,
538 ar9280Modes_high_power_tx_gain_9280_2,
539 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
540 else
541 INIT_INI_ARRAY(&ah->iniModesTxGain,
542 ar9280Modes_original_tx_gain_9280_2,
543 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
544 } else {
545 INIT_INI_ARRAY(&ah->iniModesTxGain,
546 ar9280Modes_original_tx_gain_9280_2,
547 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
548 }
549 }
550
551 static int ath9k_hw_post_init(struct ath_hw *ah)
552 {
553 int ecode;
554
555 if (!ath9k_hw_chip_test(ah))
556 return -ENODEV;
557
558 ecode = ath9k_hw_rf_claim(ah);
559 if (ecode != 0)
560 return ecode;
561
562 ecode = ath9k_hw_eeprom_init(ah);
563 if (ecode != 0)
564 return ecode;
565
566 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
567 "Eeprom VER: %d, REV: %d\n",
568 ah->eep_ops->get_eeprom_ver(ah),
569 ah->eep_ops->get_eeprom_rev(ah));
570
571 if (!AR_SREV_9280_10_OR_LATER(ah)) {
572 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
573 if (ecode) {
574 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
575 "Failed allocating banks for "
576 "external radio\n");
577 return ecode;
578 }
579 }
580
581 if (!AR_SREV_9100(ah)) {
582 ath9k_hw_ani_setup(ah);
583 ath9k_hw_ani_init(ah);
584 }
585
586 return 0;
587 }
588
589 static bool ath9k_hw_devid_supported(u16 devid)
590 {
591 switch (devid) {
592 case AR5416_DEVID_PCI:
593 case AR5416_DEVID_PCIE:
594 case AR5416_AR9100_DEVID:
595 case AR9160_DEVID_PCI:
596 case AR9280_DEVID_PCI:
597 case AR9280_DEVID_PCIE:
598 case AR9285_DEVID_PCIE:
599 case AR5416_DEVID_AR9287_PCI:
600 case AR5416_DEVID_AR9287_PCIE:
601 case AR9271_USB:
602 return true;
603 default:
604 break;
605 }
606 return false;
607 }
608
609 static bool ath9k_hw_macversion_supported(u32 macversion)
610 {
611 switch (macversion) {
612 case AR_SREV_VERSION_5416_PCI:
613 case AR_SREV_VERSION_5416_PCIE:
614 case AR_SREV_VERSION_9160:
615 case AR_SREV_VERSION_9100:
616 case AR_SREV_VERSION_9280:
617 case AR_SREV_VERSION_9285:
618 case AR_SREV_VERSION_9287:
619 case AR_SREV_VERSION_9271:
620 return true;
621 default:
622 break;
623 }
624 return false;
625 }
626
627 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
628 {
629 if (AR_SREV_9160_10_OR_LATER(ah)) {
630 if (AR_SREV_9280_10_OR_LATER(ah)) {
631 ah->iq_caldata.calData = &iq_cal_single_sample;
632 ah->adcgain_caldata.calData =
633 &adc_gain_cal_single_sample;
634 ah->adcdc_caldata.calData =
635 &adc_dc_cal_single_sample;
636 ah->adcdc_calinitdata.calData =
637 &adc_init_dc_cal;
638 } else {
639 ah->iq_caldata.calData = &iq_cal_multi_sample;
640 ah->adcgain_caldata.calData =
641 &adc_gain_cal_multi_sample;
642 ah->adcdc_caldata.calData =
643 &adc_dc_cal_multi_sample;
644 ah->adcdc_calinitdata.calData =
645 &adc_init_dc_cal;
646 }
647 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
648 }
649 }
650
651 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
652 {
653 if (AR_SREV_9271(ah)) {
654 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
655 ARRAY_SIZE(ar9271Modes_9271), 6);
656 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
657 ARRAY_SIZE(ar9271Common_9271), 2);
658 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
659 ar9271Modes_9271_1_0_only,
660 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
661 return;
662 }
663
664 if (AR_SREV_9287_11_OR_LATER(ah)) {
665 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
666 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
667 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
668 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
669 if (ah->config.pcie_clock_req)
670 INIT_INI_ARRAY(&ah->iniPcieSerdes,
671 ar9287PciePhy_clkreq_off_L1_9287_1_1,
672 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
673 else
674 INIT_INI_ARRAY(&ah->iniPcieSerdes,
675 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
676 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
677 2);
678 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
679 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
680 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
681 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
682 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
683
684 if (ah->config.pcie_clock_req)
685 INIT_INI_ARRAY(&ah->iniPcieSerdes,
686 ar9287PciePhy_clkreq_off_L1_9287_1_0,
687 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
688 else
689 INIT_INI_ARRAY(&ah->iniPcieSerdes,
690 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
691 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
692 2);
693 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
694
695
696 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
697 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
698 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
699 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
700
701 if (ah->config.pcie_clock_req) {
702 INIT_INI_ARRAY(&ah->iniPcieSerdes,
703 ar9285PciePhy_clkreq_off_L1_9285_1_2,
704 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
705 } else {
706 INIT_INI_ARRAY(&ah->iniPcieSerdes,
707 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
708 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
709 2);
710 }
711 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
712 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
713 ARRAY_SIZE(ar9285Modes_9285), 6);
714 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
715 ARRAY_SIZE(ar9285Common_9285), 2);
716
717 if (ah->config.pcie_clock_req) {
718 INIT_INI_ARRAY(&ah->iniPcieSerdes,
719 ar9285PciePhy_clkreq_off_L1_9285,
720 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
721 } else {
722 INIT_INI_ARRAY(&ah->iniPcieSerdes,
723 ar9285PciePhy_clkreq_always_on_L1_9285,
724 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
725 }
726 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
727 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
728 ARRAY_SIZE(ar9280Modes_9280_2), 6);
729 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
730 ARRAY_SIZE(ar9280Common_9280_2), 2);
731
732 if (ah->config.pcie_clock_req) {
733 INIT_INI_ARRAY(&ah->iniPcieSerdes,
734 ar9280PciePhy_clkreq_off_L1_9280,
735 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
736 } else {
737 INIT_INI_ARRAY(&ah->iniPcieSerdes,
738 ar9280PciePhy_clkreq_always_on_L1_9280,
739 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
740 }
741 INIT_INI_ARRAY(&ah->iniModesAdditional,
742 ar9280Modes_fast_clock_9280_2,
743 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
744 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
745 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
746 ARRAY_SIZE(ar9280Modes_9280), 6);
747 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
748 ARRAY_SIZE(ar9280Common_9280), 2);
749 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
750 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
751 ARRAY_SIZE(ar5416Modes_9160), 6);
752 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
753 ARRAY_SIZE(ar5416Common_9160), 2);
754 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
755 ARRAY_SIZE(ar5416Bank0_9160), 2);
756 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
757 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
758 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
759 ARRAY_SIZE(ar5416Bank1_9160), 2);
760 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
761 ARRAY_SIZE(ar5416Bank2_9160), 2);
762 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
763 ARRAY_SIZE(ar5416Bank3_9160), 3);
764 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
765 ARRAY_SIZE(ar5416Bank6_9160), 3);
766 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
767 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
768 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
769 ARRAY_SIZE(ar5416Bank7_9160), 2);
770 if (AR_SREV_9160_11(ah)) {
771 INIT_INI_ARRAY(&ah->iniAddac,
772 ar5416Addac_91601_1,
773 ARRAY_SIZE(ar5416Addac_91601_1), 2);
774 } else {
775 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
776 ARRAY_SIZE(ar5416Addac_9160), 2);
777 }
778 } else if (AR_SREV_9100_OR_LATER(ah)) {
779 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
780 ARRAY_SIZE(ar5416Modes_9100), 6);
781 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
782 ARRAY_SIZE(ar5416Common_9100), 2);
783 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
784 ARRAY_SIZE(ar5416Bank0_9100), 2);
785 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
786 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
787 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
788 ARRAY_SIZE(ar5416Bank1_9100), 2);
789 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
790 ARRAY_SIZE(ar5416Bank2_9100), 2);
791 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
792 ARRAY_SIZE(ar5416Bank3_9100), 3);
793 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
794 ARRAY_SIZE(ar5416Bank6_9100), 3);
795 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
796 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
797 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
798 ARRAY_SIZE(ar5416Bank7_9100), 2);
799 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
800 ARRAY_SIZE(ar5416Addac_9100), 2);
801 } else {
802 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
803 ARRAY_SIZE(ar5416Modes), 6);
804 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
805 ARRAY_SIZE(ar5416Common), 2);
806 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
807 ARRAY_SIZE(ar5416Bank0), 2);
808 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
809 ARRAY_SIZE(ar5416BB_RfGain), 3);
810 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
811 ARRAY_SIZE(ar5416Bank1), 2);
812 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
813 ARRAY_SIZE(ar5416Bank2), 2);
814 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
815 ARRAY_SIZE(ar5416Bank3), 3);
816 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
817 ARRAY_SIZE(ar5416Bank6), 3);
818 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
819 ARRAY_SIZE(ar5416Bank6TPC), 3);
820 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
821 ARRAY_SIZE(ar5416Bank7), 2);
822 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
823 ARRAY_SIZE(ar5416Addac), 2);
824 }
825 }
826
827 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
828 {
829 if (AR_SREV_9287_11_OR_LATER(ah))
830 INIT_INI_ARRAY(&ah->iniModesRxGain,
831 ar9287Modes_rx_gain_9287_1_1,
832 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
833 else if (AR_SREV_9287_10(ah))
834 INIT_INI_ARRAY(&ah->iniModesRxGain,
835 ar9287Modes_rx_gain_9287_1_0,
836 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
837 else if (AR_SREV_9280_20(ah))
838 ath9k_hw_init_rxgain_ini(ah);
839
840 if (AR_SREV_9287_11_OR_LATER(ah)) {
841 INIT_INI_ARRAY(&ah->iniModesTxGain,
842 ar9287Modes_tx_gain_9287_1_1,
843 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
844 } else if (AR_SREV_9287_10(ah)) {
845 INIT_INI_ARRAY(&ah->iniModesTxGain,
846 ar9287Modes_tx_gain_9287_1_0,
847 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
848 } else if (AR_SREV_9280_20(ah)) {
849 ath9k_hw_init_txgain_ini(ah);
850 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
851 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
852
853 /* txgain table */
854 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
855 INIT_INI_ARRAY(&ah->iniModesTxGain,
856 ar9285Modes_high_power_tx_gain_9285_1_2,
857 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
858 } else {
859 INIT_INI_ARRAY(&ah->iniModesTxGain,
860 ar9285Modes_original_tx_gain_9285_1_2,
861 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
862 }
863
864 }
865 }
866
867 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
868 {
869 u32 i, j;
870
871 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
872 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
873
874 /* EEPROM Fixup */
875 for (i = 0; i < ah->iniModes.ia_rows; i++) {
876 u32 reg = INI_RA(&ah->iniModes, i, 0);
877
878 for (j = 1; j < ah->iniModes.ia_columns; j++) {
879 u32 val = INI_RA(&ah->iniModes, i, j);
880
881 INI_RA(&ah->iniModes, i, j) =
882 ath9k_hw_ini_fixup(ah,
883 &ah->eeprom.def,
884 reg, val);
885 }
886 }
887 }
888 }
889
890 int ath9k_hw_init(struct ath_hw *ah)
891 {
892 struct ath_common *common = ath9k_hw_common(ah);
893 int r = 0;
894
895 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
896 ath_print(common, ATH_DBG_FATAL,
897 "Unsupported device ID: 0x%0x\n",
898 ah->hw_version.devid);
899 return -EOPNOTSUPP;
900 }
901
902 ath9k_hw_init_defaults(ah);
903 ath9k_hw_init_config(ah);
904
905 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
906 ath_print(common, ATH_DBG_FATAL,
907 "Couldn't reset chip\n");
908 return -EIO;
909 }
910
911 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
912 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
913 return -EIO;
914 }
915
916 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
917 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
918 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
919 ah->config.serialize_regmode =
920 SER_REG_MODE_ON;
921 } else {
922 ah->config.serialize_regmode =
923 SER_REG_MODE_OFF;
924 }
925 }
926
927 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
928 ah->config.serialize_regmode);
929
930 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
931 ath_print(common, ATH_DBG_FATAL,
932 "Mac Chip Rev 0x%02x.%x is not supported by "
933 "this driver\n", ah->hw_version.macVersion,
934 ah->hw_version.macRev);
935 return -EOPNOTSUPP;
936 }
937
938 if (AR_SREV_9100(ah)) {
939 ah->iq_caldata.calData = &iq_cal_multi_sample;
940 ah->supp_cals = IQ_MISMATCH_CAL;
941 ah->is_pciexpress = false;
942 }
943
944 if (AR_SREV_9271(ah))
945 ah->is_pciexpress = false;
946
947 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
948
949 ath9k_hw_init_cal_settings(ah);
950
951 ah->ani_function = ATH9K_ANI_ALL;
952 if (AR_SREV_9280_10_OR_LATER(ah)) {
953 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
954 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
955 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
956 } else {
957 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
958 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
959 }
960
961 ath9k_hw_init_mode_regs(ah);
962
963 if (ah->is_pciexpress)
964 ath9k_hw_configpcipowersave(ah, 0, 0);
965 else
966 ath9k_hw_disablepcie(ah);
967
968 /* Support for Japan ch.14 (2484) spread */
969 if (AR_SREV_9287_11_OR_LATER(ah)) {
970 INIT_INI_ARRAY(&ah->iniCckfirNormal,
971 ar9287Common_normal_cck_fir_coeff_92871_1,
972 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
973 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
974 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
975 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
976 }
977
978 r = ath9k_hw_post_init(ah);
979 if (r)
980 return r;
981
982 ath9k_hw_init_mode_gain_regs(ah);
983 ath9k_hw_fill_cap_info(ah);
984 ath9k_hw_init_11a_eeprom_fix(ah);
985
986 r = ath9k_hw_init_macaddr(ah);
987 if (r) {
988 ath_print(common, ATH_DBG_FATAL,
989 "Failed to initialize MAC address\n");
990 return r;
991 }
992
993 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
994 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
995 else
996 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
997
998 ath9k_init_nfcal_hist_buffer(ah);
999
1000 common->state = ATH_HW_INITIALIZED;
1001
1002 return 0;
1003 }
1004
1005 static void ath9k_hw_init_bb(struct ath_hw *ah,
1006 struct ath9k_channel *chan)
1007 {
1008 u32 synthDelay;
1009
1010 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1011 if (IS_CHAN_B(chan))
1012 synthDelay = (4 * synthDelay) / 22;
1013 else
1014 synthDelay /= 10;
1015
1016 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1017
1018 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1019 }
1020
1021 static void ath9k_hw_init_qos(struct ath_hw *ah)
1022 {
1023 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1024 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1025
1026 REG_WRITE(ah, AR_QOS_NO_ACK,
1027 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1028 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1029 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1030
1031 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1032 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1033 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1034 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1035 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1036 }
1037
1038 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
1039 {
1040 u32 lcr;
1041 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
1042
1043 lcr = REG_READ(ah , 0x5100c);
1044 lcr |= 0x80;
1045
1046 REG_WRITE(ah, 0x5100c, lcr);
1047 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1048 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1049
1050 lcr &= ~0x80;
1051 REG_WRITE(ah, 0x5100c, lcr);
1052 }
1053
1054 static void ath9k_hw_init_pll(struct ath_hw *ah,
1055 struct ath9k_channel *chan)
1056 {
1057 u32 pll;
1058
1059 if (AR_SREV_9100(ah)) {
1060 if (chan && IS_CHAN_5GHZ(chan))
1061 pll = 0x1450;
1062 else
1063 pll = 0x1458;
1064 } else {
1065 if (AR_SREV_9280_10_OR_LATER(ah)) {
1066 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1067
1068 if (chan && IS_CHAN_HALF_RATE(chan))
1069 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1070 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1071 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1072
1073 if (chan && IS_CHAN_5GHZ(chan)) {
1074 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1075
1076
1077 if (AR_SREV_9280_20(ah)) {
1078 if (((chan->channel % 20) == 0)
1079 || ((chan->channel % 10) == 0))
1080 pll = 0x2850;
1081 else
1082 pll = 0x142c;
1083 }
1084 } else {
1085 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1086 }
1087
1088 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1089
1090 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1091
1092 if (chan && IS_CHAN_HALF_RATE(chan))
1093 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1094 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1095 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1096
1097 if (chan && IS_CHAN_5GHZ(chan))
1098 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1099 else
1100 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1101 } else {
1102 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1103
1104 if (chan && IS_CHAN_HALF_RATE(chan))
1105 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1106 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1107 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1108
1109 if (chan && IS_CHAN_5GHZ(chan))
1110 pll |= SM(0xa, AR_RTC_PLL_DIV);
1111 else
1112 pll |= SM(0xb, AR_RTC_PLL_DIV);
1113 }
1114 }
1115 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1116
1117 /* Switch the core clock for ar9271 to 117Mhz */
1118 if (AR_SREV_9271(ah)) {
1119 if ((pll == 0x142c) || (pll == 0x2850) ) {
1120 udelay(500);
1121 /* set CLKOBS to output AHB clock */
1122 REG_WRITE(ah, 0x7020, 0xe);
1123 /*
1124 * 0x304: 117Mhz, ahb_ratio: 1x1
1125 * 0x306: 40Mhz, ahb_ratio: 1x1
1126 */
1127 REG_WRITE(ah, 0x50040, 0x304);
1128 /*
1129 * makes adjustments for the baud dividor to keep the
1130 * targetted baud rate based on the used core clock.
1131 */
1132 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1133 AR9271_TARGET_BAUD_RATE);
1134 }
1135 }
1136
1137 udelay(RTC_PLL_SETTLE_DELAY);
1138
1139 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1140 }
1141
1142 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1143 {
1144 int rx_chainmask, tx_chainmask;
1145
1146 rx_chainmask = ah->rxchainmask;
1147 tx_chainmask = ah->txchainmask;
1148
1149 switch (rx_chainmask) {
1150 case 0x5:
1151 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1152 AR_PHY_SWAP_ALT_CHAIN);
1153 case 0x3:
1154 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1155 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1156 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1157 break;
1158 }
1159 case 0x1:
1160 case 0x2:
1161 case 0x7:
1162 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1163 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1164 break;
1165 default:
1166 break;
1167 }
1168
1169 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1170 if (tx_chainmask == 0x5) {
1171 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1172 AR_PHY_SWAP_ALT_CHAIN);
1173 }
1174 if (AR_SREV_9100(ah))
1175 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1176 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1177 }
1178
1179 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1180 enum nl80211_iftype opmode)
1181 {
1182 ah->mask_reg = AR_IMR_TXERR |
1183 AR_IMR_TXURN |
1184 AR_IMR_RXERR |
1185 AR_IMR_RXORN |
1186 AR_IMR_BCNMISC;
1187
1188 if (ah->config.intr_mitigation)
1189 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1190 else
1191 ah->mask_reg |= AR_IMR_RXOK;
1192
1193 ah->mask_reg |= AR_IMR_TXOK;
1194
1195 if (opmode == NL80211_IFTYPE_AP)
1196 ah->mask_reg |= AR_IMR_MIB;
1197
1198 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1199 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1200
1201 if (!AR_SREV_9100(ah)) {
1202 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1203 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1204 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1205 }
1206 }
1207
1208 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1209 {
1210 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1211 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1212 "bad ack timeout %u\n", us);
1213 ah->acktimeout = (u32) -1;
1214 return false;
1215 } else {
1216 REG_RMW_FIELD(ah, AR_TIME_OUT,
1217 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1218 ah->acktimeout = us;
1219 return true;
1220 }
1221 }
1222
1223 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1224 {
1225 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1226 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1227 "bad cts timeout %u\n", us);
1228 ah->ctstimeout = (u32) -1;
1229 return false;
1230 } else {
1231 REG_RMW_FIELD(ah, AR_TIME_OUT,
1232 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1233 ah->ctstimeout = us;
1234 return true;
1235 }
1236 }
1237
1238 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1239 {
1240 if (tu > 0xFFFF) {
1241 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1242 "bad global tx timeout %u\n", tu);
1243 ah->globaltxtimeout = (u32) -1;
1244 return false;
1245 } else {
1246 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1247 ah->globaltxtimeout = tu;
1248 return true;
1249 }
1250 }
1251
1252 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1253 {
1254 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1255 ah->misc_mode);
1256
1257 if (ah->misc_mode != 0)
1258 REG_WRITE(ah, AR_PCU_MISC,
1259 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1260 if (ah->slottime != (u32) -1)
1261 ath9k_hw_setslottime(ah, ah->slottime);
1262 if (ah->acktimeout != (u32) -1)
1263 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1264 if (ah->ctstimeout != (u32) -1)
1265 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1266 if (ah->globaltxtimeout != (u32) -1)
1267 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1268 }
1269
1270 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1271 {
1272 return vendorid == ATHEROS_VENDOR_ID ?
1273 ath9k_hw_devname(devid) : NULL;
1274 }
1275
1276 void ath9k_hw_detach(struct ath_hw *ah)
1277 {
1278 struct ath_common *common = ath9k_hw_common(ah);
1279
1280 if (common->state <= ATH_HW_INITIALIZED)
1281 goto free_hw;
1282
1283 if (!AR_SREV_9100(ah))
1284 ath9k_hw_ani_disable(ah);
1285
1286 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1287
1288 free_hw:
1289 if (!AR_SREV_9280_10_OR_LATER(ah))
1290 ath9k_hw_rf_free_ext_banks(ah);
1291 kfree(ah);
1292 ah = NULL;
1293 }
1294 EXPORT_SYMBOL(ath9k_hw_detach);
1295
1296 /*******/
1297 /* INI */
1298 /*******/
1299
1300 static void ath9k_hw_override_ini(struct ath_hw *ah,
1301 struct ath9k_channel *chan)
1302 {
1303 u32 val;
1304
1305 if (AR_SREV_9271(ah)) {
1306 /*
1307 * Enable spectral scan to solution for issues with stuck
1308 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1309 * AR9271 1.1
1310 */
1311 if (AR_SREV_9271_10(ah)) {
1312 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1313 AR_PHY_SPECTRAL_SCAN_ENABLE;
1314 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1315 }
1316 else if (AR_SREV_9271_11(ah))
1317 /*
1318 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1319 * present on AR9271 1.1
1320 */
1321 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1322 return;
1323 }
1324
1325 /*
1326 * Set the RX_ABORT and RX_DIS and clear if off only after
1327 * RXE is set for MAC. This prevents frames with corrupted
1328 * descriptor status.
1329 */
1330 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1331
1332 if (AR_SREV_9280_10_OR_LATER(ah)) {
1333 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1334 (~AR_PCU_MISC_MODE2_HWWAR1);
1335
1336 if (AR_SREV_9287_10_OR_LATER(ah))
1337 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1338
1339 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1340 }
1341
1342 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1343 AR_SREV_9280_10_OR_LATER(ah))
1344 return;
1345 /*
1346 * Disable BB clock gating
1347 * Necessary to avoid issues on AR5416 2.0
1348 */
1349 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1350 }
1351
1352 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1353 struct ar5416_eeprom_def *pEepData,
1354 u32 reg, u32 value)
1355 {
1356 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1357 struct ath_common *common = ath9k_hw_common(ah);
1358
1359 switch (ah->hw_version.devid) {
1360 case AR9280_DEVID_PCI:
1361 if (reg == 0x7894) {
1362 ath_print(common, ATH_DBG_EEPROM,
1363 "ini VAL: %x EEPROM: %x\n", value,
1364 (pBase->version & 0xff));
1365
1366 if ((pBase->version & 0xff) > 0x0a) {
1367 ath_print(common, ATH_DBG_EEPROM,
1368 "PWDCLKIND: %d\n",
1369 pBase->pwdclkind);
1370 value &= ~AR_AN_TOP2_PWDCLKIND;
1371 value |= AR_AN_TOP2_PWDCLKIND &
1372 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1373 } else {
1374 ath_print(common, ATH_DBG_EEPROM,
1375 "PWDCLKIND Earlier Rev\n");
1376 }
1377
1378 ath_print(common, ATH_DBG_EEPROM,
1379 "final ini VAL: %x\n", value);
1380 }
1381 break;
1382 }
1383
1384 return value;
1385 }
1386
1387 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1388 struct ar5416_eeprom_def *pEepData,
1389 u32 reg, u32 value)
1390 {
1391 if (ah->eep_map == EEP_MAP_4KBITS)
1392 return value;
1393 else
1394 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1395 }
1396
1397 static void ath9k_olc_init(struct ath_hw *ah)
1398 {
1399 u32 i;
1400
1401 if (OLC_FOR_AR9287_10_LATER) {
1402 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1403 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1404 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1405 AR9287_AN_TXPC0_TXPCMODE,
1406 AR9287_AN_TXPC0_TXPCMODE_S,
1407 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1408 udelay(100);
1409 } else {
1410 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1411 ah->originalGain[i] =
1412 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1413 AR_PHY_TX_GAIN);
1414 ah->PDADCdelta = 0;
1415 }
1416 }
1417
1418 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1419 struct ath9k_channel *chan)
1420 {
1421 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1422
1423 if (IS_CHAN_B(chan))
1424 ctl |= CTL_11B;
1425 else if (IS_CHAN_G(chan))
1426 ctl |= CTL_11G;
1427 else
1428 ctl |= CTL_11A;
1429
1430 return ctl;
1431 }
1432
1433 static int ath9k_hw_process_ini(struct ath_hw *ah,
1434 struct ath9k_channel *chan)
1435 {
1436 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1437 int i, regWrites = 0;
1438 struct ieee80211_channel *channel = chan->chan;
1439 u32 modesIndex, freqIndex;
1440
1441 switch (chan->chanmode) {
1442 case CHANNEL_A:
1443 case CHANNEL_A_HT20:
1444 modesIndex = 1;
1445 freqIndex = 1;
1446 break;
1447 case CHANNEL_A_HT40PLUS:
1448 case CHANNEL_A_HT40MINUS:
1449 modesIndex = 2;
1450 freqIndex = 1;
1451 break;
1452 case CHANNEL_G:
1453 case CHANNEL_G_HT20:
1454 case CHANNEL_B:
1455 modesIndex = 4;
1456 freqIndex = 2;
1457 break;
1458 case CHANNEL_G_HT40PLUS:
1459 case CHANNEL_G_HT40MINUS:
1460 modesIndex = 3;
1461 freqIndex = 2;
1462 break;
1463
1464 default:
1465 return -EINVAL;
1466 }
1467
1468 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1469 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1470 ah->eep_ops->set_addac(ah, chan);
1471
1472 if (AR_SREV_5416_22_OR_LATER(ah)) {
1473 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1474 } else {
1475 struct ar5416IniArray temp;
1476 u32 addacSize =
1477 sizeof(u32) * ah->iniAddac.ia_rows *
1478 ah->iniAddac.ia_columns;
1479
1480 memcpy(ah->addac5416_21,
1481 ah->iniAddac.ia_array, addacSize);
1482
1483 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1484
1485 temp.ia_array = ah->addac5416_21;
1486 temp.ia_columns = ah->iniAddac.ia_columns;
1487 temp.ia_rows = ah->iniAddac.ia_rows;
1488 REG_WRITE_ARRAY(&temp, 1, regWrites);
1489 }
1490
1491 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1492
1493 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1494 u32 reg = INI_RA(&ah->iniModes, i, 0);
1495 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1496
1497 REG_WRITE(ah, reg, val);
1498
1499 if (reg >= 0x7800 && reg < 0x78a0
1500 && ah->config.analog_shiftreg) {
1501 udelay(100);
1502 }
1503
1504 DO_DELAY(regWrites);
1505 }
1506
1507 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1508 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1509
1510 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1511 AR_SREV_9287_10_OR_LATER(ah))
1512 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1513
1514 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1515 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1516 u32 val = INI_RA(&ah->iniCommon, i, 1);
1517
1518 REG_WRITE(ah, reg, val);
1519
1520 if (reg >= 0x7800 && reg < 0x78a0
1521 && ah->config.analog_shiftreg) {
1522 udelay(100);
1523 }
1524
1525 DO_DELAY(regWrites);
1526 }
1527
1528 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1529
1530 if (AR_SREV_9271_10(ah))
1531 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1532 modesIndex, regWrites);
1533
1534 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1535 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1536 regWrites);
1537 }
1538
1539 ath9k_hw_override_ini(ah, chan);
1540 ath9k_hw_set_regs(ah, chan);
1541 ath9k_hw_init_chain_masks(ah);
1542
1543 if (OLC_FOR_AR9280_20_LATER)
1544 ath9k_olc_init(ah);
1545
1546 ah->eep_ops->set_txpower(ah, chan,
1547 ath9k_regd_get_ctl(regulatory, chan),
1548 channel->max_antenna_gain * 2,
1549 channel->max_power * 2,
1550 min((u32) MAX_RATE_POWER,
1551 (u32) regulatory->power_limit));
1552
1553 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1554 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1555 "ar5416SetRfRegs failed\n");
1556 return -EIO;
1557 }
1558
1559 return 0;
1560 }
1561
1562 /****************************************/
1563 /* Reset and Channel Switching Routines */
1564 /****************************************/
1565
1566 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1567 {
1568 u32 rfMode = 0;
1569
1570 if (chan == NULL)
1571 return;
1572
1573 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1574 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1575
1576 if (!AR_SREV_9280_10_OR_LATER(ah))
1577 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1578 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1579
1580 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1581 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1582
1583 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1584 }
1585
1586 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1587 {
1588 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1589 }
1590
1591 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1592 {
1593 u32 regval;
1594
1595 /*
1596 * set AHB_MODE not to do cacheline prefetches
1597 */
1598 regval = REG_READ(ah, AR_AHB_MODE);
1599 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1600
1601 /*
1602 * let mac dma reads be in 128 byte chunks
1603 */
1604 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1605 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1606
1607 /*
1608 * Restore TX Trigger Level to its pre-reset value.
1609 * The initial value depends on whether aggregation is enabled, and is
1610 * adjusted whenever underruns are detected.
1611 */
1612 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1613
1614 /*
1615 * let mac dma writes be in 128 byte chunks
1616 */
1617 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1618 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1619
1620 /*
1621 * Setup receive FIFO threshold to hold off TX activities
1622 */
1623 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1624
1625 /*
1626 * reduce the number of usable entries in PCU TXBUF to avoid
1627 * wrap around issues.
1628 */
1629 if (AR_SREV_9285(ah)) {
1630 /* For AR9285 the number of Fifos are reduced to half.
1631 * So set the usable tx buf size also to half to
1632 * avoid data/delimiter underruns
1633 */
1634 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1635 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1636 } else if (!AR_SREV_9271(ah)) {
1637 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1638 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1639 }
1640 }
1641
1642 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1643 {
1644 u32 val;
1645
1646 val = REG_READ(ah, AR_STA_ID1);
1647 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1648 switch (opmode) {
1649 case NL80211_IFTYPE_AP:
1650 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1651 | AR_STA_ID1_KSRCH_MODE);
1652 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1653 break;
1654 case NL80211_IFTYPE_ADHOC:
1655 case NL80211_IFTYPE_MESH_POINT:
1656 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1657 | AR_STA_ID1_KSRCH_MODE);
1658 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1659 break;
1660 case NL80211_IFTYPE_STATION:
1661 case NL80211_IFTYPE_MONITOR:
1662 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1663 break;
1664 }
1665 }
1666
1667 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1668 u32 coef_scaled,
1669 u32 *coef_mantissa,
1670 u32 *coef_exponent)
1671 {
1672 u32 coef_exp, coef_man;
1673
1674 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1675 if ((coef_scaled >> coef_exp) & 0x1)
1676 break;
1677
1678 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1679
1680 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1681
1682 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1683 *coef_exponent = coef_exp - 16;
1684 }
1685
1686 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1687 struct ath9k_channel *chan)
1688 {
1689 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1690 u32 clockMhzScaled = 0x64000000;
1691 struct chan_centers centers;
1692
1693 if (IS_CHAN_HALF_RATE(chan))
1694 clockMhzScaled = clockMhzScaled >> 1;
1695 else if (IS_CHAN_QUARTER_RATE(chan))
1696 clockMhzScaled = clockMhzScaled >> 2;
1697
1698 ath9k_hw_get_channel_centers(ah, chan, &centers);
1699 coef_scaled = clockMhzScaled / centers.synth_center;
1700
1701 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1702 &ds_coef_exp);
1703
1704 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1705 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1706 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1707 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1708
1709 coef_scaled = (9 * coef_scaled) / 10;
1710
1711 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1712 &ds_coef_exp);
1713
1714 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1715 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1716 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1717 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1718 }
1719
1720 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1721 {
1722 u32 rst_flags;
1723 u32 tmpReg;
1724
1725 if (AR_SREV_9100(ah)) {
1726 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1727 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1728 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1729 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1730 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1731 }
1732
1733 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1734 AR_RTC_FORCE_WAKE_ON_INT);
1735
1736 if (AR_SREV_9100(ah)) {
1737 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1738 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1739 } else {
1740 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1741 if (tmpReg &
1742 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1743 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1744 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1745 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1746 } else {
1747 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1748 }
1749
1750 rst_flags = AR_RTC_RC_MAC_WARM;
1751 if (type == ATH9K_RESET_COLD)
1752 rst_flags |= AR_RTC_RC_MAC_COLD;
1753 }
1754
1755 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1756 udelay(50);
1757
1758 REG_WRITE(ah, AR_RTC_RC, 0);
1759 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1760 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1761 "RTC stuck in MAC reset\n");
1762 return false;
1763 }
1764
1765 if (!AR_SREV_9100(ah))
1766 REG_WRITE(ah, AR_RC, 0);
1767
1768 if (AR_SREV_9100(ah))
1769 udelay(50);
1770
1771 return true;
1772 }
1773
1774 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1775 {
1776 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1777 AR_RTC_FORCE_WAKE_ON_INT);
1778
1779 if (!AR_SREV_9100(ah))
1780 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1781
1782 REG_WRITE(ah, AR_RTC_RESET, 0);
1783 udelay(2);
1784
1785 if (!AR_SREV_9100(ah))
1786 REG_WRITE(ah, AR_RC, 0);
1787
1788 REG_WRITE(ah, AR_RTC_RESET, 1);
1789
1790 if (!ath9k_hw_wait(ah,
1791 AR_RTC_STATUS,
1792 AR_RTC_STATUS_M,
1793 AR_RTC_STATUS_ON,
1794 AH_WAIT_TIMEOUT)) {
1795 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1796 "RTC not waking up\n");
1797 return false;
1798 }
1799
1800 ath9k_hw_read_revisions(ah);
1801
1802 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1803 }
1804
1805 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1806 {
1807 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1808 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1809
1810 switch (type) {
1811 case ATH9K_RESET_POWER_ON:
1812 return ath9k_hw_set_reset_power_on(ah);
1813 case ATH9K_RESET_WARM:
1814 case ATH9K_RESET_COLD:
1815 return ath9k_hw_set_reset(ah, type);
1816 default:
1817 return false;
1818 }
1819 }
1820
1821 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1822 {
1823 u32 phymode;
1824 u32 enableDacFifo = 0;
1825
1826 if (AR_SREV_9285_10_OR_LATER(ah))
1827 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1828 AR_PHY_FC_ENABLE_DAC_FIFO);
1829
1830 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1831 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1832
1833 if (IS_CHAN_HT40(chan)) {
1834 phymode |= AR_PHY_FC_DYN2040_EN;
1835
1836 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1837 (chan->chanmode == CHANNEL_G_HT40PLUS))
1838 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1839
1840 }
1841 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1842
1843 ath9k_hw_set11nmac2040(ah);
1844
1845 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1846 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1847 }
1848
1849 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1850 struct ath9k_channel *chan)
1851 {
1852 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1853 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1854 return false;
1855 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1856 return false;
1857
1858 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1859 return false;
1860
1861 ah->chip_fullsleep = false;
1862 ath9k_hw_init_pll(ah, chan);
1863 ath9k_hw_set_rfmode(ah, chan);
1864
1865 return true;
1866 }
1867
1868 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1869 struct ath9k_channel *chan)
1870 {
1871 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1872 struct ath_common *common = ath9k_hw_common(ah);
1873 struct ieee80211_channel *channel = chan->chan;
1874 u32 synthDelay, qnum;
1875 int r;
1876
1877 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1878 if (ath9k_hw_numtxpending(ah, qnum)) {
1879 ath_print(common, ATH_DBG_QUEUE,
1880 "Transmit frames pending on "
1881 "queue %d\n", qnum);
1882 return false;
1883 }
1884 }
1885
1886 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1887 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1888 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1889 ath_print(common, ATH_DBG_FATAL,
1890 "Could not kill baseband RX\n");
1891 return false;
1892 }
1893
1894 ath9k_hw_set_regs(ah, chan);
1895
1896 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1897 if (r) {
1898 ath_print(common, ATH_DBG_FATAL,
1899 "Failed to set channel\n");
1900 return false;
1901 }
1902
1903 ah->eep_ops->set_txpower(ah, chan,
1904 ath9k_regd_get_ctl(regulatory, chan),
1905 channel->max_antenna_gain * 2,
1906 channel->max_power * 2,
1907 min((u32) MAX_RATE_POWER,
1908 (u32) regulatory->power_limit));
1909
1910 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1911 if (IS_CHAN_B(chan))
1912 synthDelay = (4 * synthDelay) / 22;
1913 else
1914 synthDelay /= 10;
1915
1916 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1917
1918 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1919
1920 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1921 ath9k_hw_set_delta_slope(ah, chan);
1922
1923 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1924
1925 if (!chan->oneTimeCalsDone)
1926 chan->oneTimeCalsDone = true;
1927
1928 return true;
1929 }
1930
1931 static void ath9k_enable_rfkill(struct ath_hw *ah)
1932 {
1933 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1934 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1935
1936 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1937 AR_GPIO_INPUT_MUX2_RFSILENT);
1938
1939 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1940 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1941 }
1942
1943 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1944 bool bChannelChange)
1945 {
1946 struct ath_common *common = ath9k_hw_common(ah);
1947 u32 saveLedState;
1948 struct ath9k_channel *curchan = ah->curchan;
1949 u32 saveDefAntenna;
1950 u32 macStaId1;
1951 u64 tsf = 0;
1952 int i, rx_chainmask, r;
1953
1954 ah->txchainmask = common->tx_chainmask;
1955 ah->rxchainmask = common->rx_chainmask;
1956
1957 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1958 return -EIO;
1959
1960 if (curchan && !ah->chip_fullsleep)
1961 ath9k_hw_getnf(ah, curchan);
1962
1963 if (bChannelChange &&
1964 (ah->chip_fullsleep != true) &&
1965 (ah->curchan != NULL) &&
1966 (chan->channel != ah->curchan->channel) &&
1967 ((chan->channelFlags & CHANNEL_ALL) ==
1968 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1969 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1970 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1971
1972 if (ath9k_hw_channel_change(ah, chan)) {
1973 ath9k_hw_loadnf(ah, ah->curchan);
1974 ath9k_hw_start_nfcal(ah);
1975 return 0;
1976 }
1977 }
1978
1979 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1980 if (saveDefAntenna == 0)
1981 saveDefAntenna = 1;
1982
1983 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1984
1985 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1986 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1987 tsf = ath9k_hw_gettsf64(ah);
1988
1989 saveLedState = REG_READ(ah, AR_CFG_LED) &
1990 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1991 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1992
1993 ath9k_hw_mark_phy_inactive(ah);
1994
1995 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1996 REG_WRITE(ah,
1997 AR9271_RESET_POWER_DOWN_CONTROL,
1998 AR9271_RADIO_RF_RST);
1999 udelay(50);
2000 }
2001
2002 if (!ath9k_hw_chip_reset(ah, chan)) {
2003 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
2004 return -EINVAL;
2005 }
2006
2007 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2008 ah->htc_reset_init = false;
2009 REG_WRITE(ah,
2010 AR9271_RESET_POWER_DOWN_CONTROL,
2011 AR9271_GATE_MAC_CTL);
2012 udelay(50);
2013 }
2014
2015 /* Restore TSF */
2016 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2017 ath9k_hw_settsf64(ah, tsf);
2018
2019 if (AR_SREV_9280_10_OR_LATER(ah))
2020 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2021
2022 if (AR_SREV_9287_12_OR_LATER(ah)) {
2023 /* Enable ASYNC FIFO */
2024 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2025 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2026 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2027 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2028 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2029 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2030 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2031 }
2032 r = ath9k_hw_process_ini(ah, chan);
2033 if (r)
2034 return r;
2035
2036 /* Setup MFP options for CCMP */
2037 if (AR_SREV_9280_20_OR_LATER(ah)) {
2038 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2039 * frames when constructing CCMP AAD. */
2040 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2041 0xc7ff);
2042 ah->sw_mgmt_crypto = false;
2043 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2044 /* Disable hardware crypto for management frames */
2045 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2046 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2047 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2048 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2049 ah->sw_mgmt_crypto = true;
2050 } else
2051 ah->sw_mgmt_crypto = true;
2052
2053 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2054 ath9k_hw_set_delta_slope(ah, chan);
2055
2056 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2057 ah->eep_ops->set_board_values(ah, chan);
2058
2059 if (AR_SREV_5416(ah))
2060 ath9k_hw_decrease_chain_power(ah, chan);
2061
2062 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2063 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2064 | macStaId1
2065 | AR_STA_ID1_RTS_USE_DEF
2066 | (ah->config.
2067 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2068 | ah->sta_id1_defaults);
2069 ath9k_hw_set_operating_mode(ah, ah->opmode);
2070
2071 ath_hw_setbssidmask(common);
2072
2073 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2074
2075 ath9k_hw_write_associd(ah);
2076
2077 REG_WRITE(ah, AR_ISR, ~0);
2078
2079 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2080
2081 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2082 if (r)
2083 return r;
2084
2085 for (i = 0; i < AR_NUM_DCU; i++)
2086 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2087
2088 ah->intr_txqs = 0;
2089 for (i = 0; i < ah->caps.total_queues; i++)
2090 ath9k_hw_resettxqueue(ah, i);
2091
2092 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2093 ath9k_hw_init_qos(ah);
2094
2095 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2096 ath9k_enable_rfkill(ah);
2097
2098 ath9k_hw_init_user_settings(ah);
2099
2100 if (AR_SREV_9287_12_OR_LATER(ah)) {
2101 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2102 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2103 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2104 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2105 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2106 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2107
2108 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2109 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2110
2111 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2112 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2113 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2114 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2115 }
2116 if (AR_SREV_9287_12_OR_LATER(ah)) {
2117 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2118 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2119 }
2120
2121 REG_WRITE(ah, AR_STA_ID1,
2122 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2123
2124 ath9k_hw_set_dma(ah);
2125
2126 REG_WRITE(ah, AR_OBS, 8);
2127
2128 if (ah->config.intr_mitigation) {
2129 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2130 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2131 }
2132
2133 ath9k_hw_init_bb(ah, chan);
2134
2135 if (!ath9k_hw_init_cal(ah, chan))
2136 return -EIO;
2137
2138 rx_chainmask = ah->rxchainmask;
2139 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2140 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2141 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2142 }
2143
2144 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2145
2146 /*
2147 * For big endian systems turn on swapping for descriptors
2148 */
2149 if (AR_SREV_9100(ah)) {
2150 u32 mask;
2151 mask = REG_READ(ah, AR_CFG);
2152 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2153 ath_print(common, ATH_DBG_RESET,
2154 "CFG Byte Swap Set 0x%x\n", mask);
2155 } else {
2156 mask =
2157 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2158 REG_WRITE(ah, AR_CFG, mask);
2159 ath_print(common, ATH_DBG_RESET,
2160 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2161 }
2162 } else {
2163 /* Configure AR9271 target WLAN */
2164 if (AR_SREV_9271(ah))
2165 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2166 #ifdef __BIG_ENDIAN
2167 else
2168 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2169 #endif
2170 }
2171
2172 if (ah->btcoex_hw.enabled)
2173 ath9k_hw_btcoex_enable(ah);
2174
2175 return 0;
2176 }
2177 EXPORT_SYMBOL(ath9k_hw_reset);
2178
2179 /************************/
2180 /* Key Cache Management */
2181 /************************/
2182
2183 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2184 {
2185 u32 keyType;
2186
2187 if (entry >= ah->caps.keycache_size) {
2188 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2189 "keychache entry %u out of range\n", entry);
2190 return false;
2191 }
2192
2193 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2194
2195 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2196 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2197 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2198 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2199 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2200 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2201 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2202 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2203
2204 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2205 u16 micentry = entry + 64;
2206
2207 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2208 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2209 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2210 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2211
2212 }
2213
2214 return true;
2215 }
2216 EXPORT_SYMBOL(ath9k_hw_keyreset);
2217
2218 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2219 {
2220 u32 macHi, macLo;
2221
2222 if (entry >= ah->caps.keycache_size) {
2223 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2224 "keychache entry %u out of range\n", entry);
2225 return false;
2226 }
2227
2228 if (mac != NULL) {
2229 macHi = (mac[5] << 8) | mac[4];
2230 macLo = (mac[3] << 24) |
2231 (mac[2] << 16) |
2232 (mac[1] << 8) |
2233 mac[0];
2234 macLo >>= 1;
2235 macLo |= (macHi & 1) << 31;
2236 macHi >>= 1;
2237 } else {
2238 macLo = macHi = 0;
2239 }
2240 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2241 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2242
2243 return true;
2244 }
2245 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2246
2247 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2248 const struct ath9k_keyval *k,
2249 const u8 *mac)
2250 {
2251 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2252 struct ath_common *common = ath9k_hw_common(ah);
2253 u32 key0, key1, key2, key3, key4;
2254 u32 keyType;
2255
2256 if (entry >= pCap->keycache_size) {
2257 ath_print(common, ATH_DBG_FATAL,
2258 "keycache entry %u out of range\n", entry);
2259 return false;
2260 }
2261
2262 switch (k->kv_type) {
2263 case ATH9K_CIPHER_AES_OCB:
2264 keyType = AR_KEYTABLE_TYPE_AES;
2265 break;
2266 case ATH9K_CIPHER_AES_CCM:
2267 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2268 ath_print(common, ATH_DBG_ANY,
2269 "AES-CCM not supported by mac rev 0x%x\n",
2270 ah->hw_version.macRev);
2271 return false;
2272 }
2273 keyType = AR_KEYTABLE_TYPE_CCM;
2274 break;
2275 case ATH9K_CIPHER_TKIP:
2276 keyType = AR_KEYTABLE_TYPE_TKIP;
2277 if (ATH9K_IS_MIC_ENABLED(ah)
2278 && entry + 64 >= pCap->keycache_size) {
2279 ath_print(common, ATH_DBG_ANY,
2280 "entry %u inappropriate for TKIP\n", entry);
2281 return false;
2282 }
2283 break;
2284 case ATH9K_CIPHER_WEP:
2285 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2286 ath_print(common, ATH_DBG_ANY,
2287 "WEP key length %u too small\n", k->kv_len);
2288 return false;
2289 }
2290 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2291 keyType = AR_KEYTABLE_TYPE_40;
2292 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2293 keyType = AR_KEYTABLE_TYPE_104;
2294 else
2295 keyType = AR_KEYTABLE_TYPE_128;
2296 break;
2297 case ATH9K_CIPHER_CLR:
2298 keyType = AR_KEYTABLE_TYPE_CLR;
2299 break;
2300 default:
2301 ath_print(common, ATH_DBG_FATAL,
2302 "cipher %u not supported\n", k->kv_type);
2303 return false;
2304 }
2305
2306 key0 = get_unaligned_le32(k->kv_val + 0);
2307 key1 = get_unaligned_le16(k->kv_val + 4);
2308 key2 = get_unaligned_le32(k->kv_val + 6);
2309 key3 = get_unaligned_le16(k->kv_val + 10);
2310 key4 = get_unaligned_le32(k->kv_val + 12);
2311 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2312 key4 &= 0xff;
2313
2314 /*
2315 * Note: Key cache registers access special memory area that requires
2316 * two 32-bit writes to actually update the values in the internal
2317 * memory. Consequently, the exact order and pairs used here must be
2318 * maintained.
2319 */
2320
2321 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2322 u16 micentry = entry + 64;
2323
2324 /*
2325 * Write inverted key[47:0] first to avoid Michael MIC errors
2326 * on frames that could be sent or received at the same time.
2327 * The correct key will be written in the end once everything
2328 * else is ready.
2329 */
2330 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2331 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2332
2333 /* Write key[95:48] */
2334 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2335 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2336
2337 /* Write key[127:96] and key type */
2338 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2339 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2340
2341 /* Write MAC address for the entry */
2342 (void) ath9k_hw_keysetmac(ah, entry, mac);
2343
2344 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2345 /*
2346 * TKIP uses two key cache entries:
2347 * Michael MIC TX/RX keys in the same key cache entry
2348 * (idx = main index + 64):
2349 * key0 [31:0] = RX key [31:0]
2350 * key1 [15:0] = TX key [31:16]
2351 * key1 [31:16] = reserved
2352 * key2 [31:0] = RX key [63:32]
2353 * key3 [15:0] = TX key [15:0]
2354 * key3 [31:16] = reserved
2355 * key4 [31:0] = TX key [63:32]
2356 */
2357 u32 mic0, mic1, mic2, mic3, mic4;
2358
2359 mic0 = get_unaligned_le32(k->kv_mic + 0);
2360 mic2 = get_unaligned_le32(k->kv_mic + 4);
2361 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2362 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2363 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2364
2365 /* Write RX[31:0] and TX[31:16] */
2366 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2367 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2368
2369 /* Write RX[63:32] and TX[15:0] */
2370 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2371 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2372
2373 /* Write TX[63:32] and keyType(reserved) */
2374 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2375 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2376 AR_KEYTABLE_TYPE_CLR);
2377
2378 } else {
2379 /*
2380 * TKIP uses four key cache entries (two for group
2381 * keys):
2382 * Michael MIC TX/RX keys are in different key cache
2383 * entries (idx = main index + 64 for TX and
2384 * main index + 32 + 96 for RX):
2385 * key0 [31:0] = TX/RX MIC key [31:0]
2386 * key1 [31:0] = reserved
2387 * key2 [31:0] = TX/RX MIC key [63:32]
2388 * key3 [31:0] = reserved
2389 * key4 [31:0] = reserved
2390 *
2391 * Upper layer code will call this function separately
2392 * for TX and RX keys when these registers offsets are
2393 * used.
2394 */
2395 u32 mic0, mic2;
2396
2397 mic0 = get_unaligned_le32(k->kv_mic + 0);
2398 mic2 = get_unaligned_le32(k->kv_mic + 4);
2399
2400 /* Write MIC key[31:0] */
2401 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2402 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2403
2404 /* Write MIC key[63:32] */
2405 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2406 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2407
2408 /* Write TX[63:32] and keyType(reserved) */
2409 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2410 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2411 AR_KEYTABLE_TYPE_CLR);
2412 }
2413
2414 /* MAC address registers are reserved for the MIC entry */
2415 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2416 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2417
2418 /*
2419 * Write the correct (un-inverted) key[47:0] last to enable
2420 * TKIP now that all other registers are set with correct
2421 * values.
2422 */
2423 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2424 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2425 } else {
2426 /* Write key[47:0] */
2427 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2428 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2429
2430 /* Write key[95:48] */
2431 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2432 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2433
2434 /* Write key[127:96] and key type */
2435 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2436 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2437
2438 /* Write MAC address for the entry */
2439 (void) ath9k_hw_keysetmac(ah, entry, mac);
2440 }
2441
2442 return true;
2443 }
2444 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2445
2446 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2447 {
2448 if (entry < ah->caps.keycache_size) {
2449 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2450 if (val & AR_KEYTABLE_VALID)
2451 return true;
2452 }
2453 return false;
2454 }
2455 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2456
2457 /******************************/
2458 /* Power Management (Chipset) */
2459 /******************************/
2460
2461 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2462 {
2463 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2464 if (setChip) {
2465 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2466 AR_RTC_FORCE_WAKE_EN);
2467 if (!AR_SREV_9100(ah))
2468 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2469
2470 if(!AR_SREV_5416(ah))
2471 REG_CLR_BIT(ah, (AR_RTC_RESET),
2472 AR_RTC_RESET_EN);
2473 }
2474 }
2475
2476 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2477 {
2478 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2479 if (setChip) {
2480 struct ath9k_hw_capabilities *pCap = &ah->caps;
2481
2482 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2483 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2484 AR_RTC_FORCE_WAKE_ON_INT);
2485 } else {
2486 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2487 AR_RTC_FORCE_WAKE_EN);
2488 }
2489 }
2490 }
2491
2492 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2493 {
2494 u32 val;
2495 int i;
2496
2497 if (setChip) {
2498 if ((REG_READ(ah, AR_RTC_STATUS) &
2499 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2500 if (ath9k_hw_set_reset_reg(ah,
2501 ATH9K_RESET_POWER_ON) != true) {
2502 return false;
2503 }
2504 ath9k_hw_init_pll(ah, NULL);
2505 }
2506 if (AR_SREV_9100(ah))
2507 REG_SET_BIT(ah, AR_RTC_RESET,
2508 AR_RTC_RESET_EN);
2509
2510 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2511 AR_RTC_FORCE_WAKE_EN);
2512 udelay(50);
2513
2514 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2515 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2516 if (val == AR_RTC_STATUS_ON)
2517 break;
2518 udelay(50);
2519 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2520 AR_RTC_FORCE_WAKE_EN);
2521 }
2522 if (i == 0) {
2523 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2524 "Failed to wakeup in %uus\n",
2525 POWER_UP_TIME / 20);
2526 return false;
2527 }
2528 }
2529
2530 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2531
2532 return true;
2533 }
2534
2535 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2536 {
2537 struct ath_common *common = ath9k_hw_common(ah);
2538 int status = true, setChip = true;
2539 static const char *modes[] = {
2540 "AWAKE",
2541 "FULL-SLEEP",
2542 "NETWORK SLEEP",
2543 "UNDEFINED"
2544 };
2545
2546 if (ah->power_mode == mode)
2547 return status;
2548
2549 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2550 modes[ah->power_mode], modes[mode]);
2551
2552 switch (mode) {
2553 case ATH9K_PM_AWAKE:
2554 status = ath9k_hw_set_power_awake(ah, setChip);
2555 break;
2556 case ATH9K_PM_FULL_SLEEP:
2557 ath9k_set_power_sleep(ah, setChip);
2558 ah->chip_fullsleep = true;
2559 break;
2560 case ATH9K_PM_NETWORK_SLEEP:
2561 ath9k_set_power_network_sleep(ah, setChip);
2562 break;
2563 default:
2564 ath_print(common, ATH_DBG_FATAL,
2565 "Unknown power mode %u\n", mode);
2566 return false;
2567 }
2568 ah->power_mode = mode;
2569
2570 return status;
2571 }
2572 EXPORT_SYMBOL(ath9k_hw_setpower);
2573
2574 /*
2575 * Helper for ASPM support.
2576 *
2577 * Disable PLL when in L0s as well as receiver clock when in L1.
2578 * This power saving option must be enabled through the SerDes.
2579 *
2580 * Programming the SerDes must go through the same 288 bit serial shift
2581 * register as the other analog registers. Hence the 9 writes.
2582 */
2583 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2584 {
2585 u8 i;
2586 u32 val;
2587
2588 if (ah->is_pciexpress != true)
2589 return;
2590
2591 /* Do not touch SerDes registers */
2592 if (ah->config.pcie_powersave_enable == 2)
2593 return;
2594
2595 /* Nothing to do on restore for 11N */
2596 if (!restore) {
2597 if (AR_SREV_9280_20_OR_LATER(ah)) {
2598 /*
2599 * AR9280 2.0 or later chips use SerDes values from the
2600 * initvals.h initialized depending on chipset during
2601 * ath9k_hw_init()
2602 */
2603 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2604 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2605 INI_RA(&ah->iniPcieSerdes, i, 1));
2606 }
2607 } else if (AR_SREV_9280(ah) &&
2608 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2609 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2610 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2611
2612 /* RX shut off when elecidle is asserted */
2613 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2614 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2615 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2616
2617 /* Shut off CLKREQ active in L1 */
2618 if (ah->config.pcie_clock_req)
2619 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2620 else
2621 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2622
2623 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2624 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2625 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2626
2627 /* Load the new settings */
2628 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2629
2630 } else {
2631 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2632 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2633
2634 /* RX shut off when elecidle is asserted */
2635 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2636 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2637 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2638
2639 /*
2640 * Ignore ah->ah_config.pcie_clock_req setting for
2641 * pre-AR9280 11n
2642 */
2643 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2644
2645 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2646 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2647 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2648
2649 /* Load the new settings */
2650 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2651 }
2652
2653 udelay(1000);
2654
2655 /* set bit 19 to allow forcing of pcie core into L1 state */
2656 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2657
2658 /* Several PCIe massages to ensure proper behaviour */
2659 if (ah->config.pcie_waen) {
2660 val = ah->config.pcie_waen;
2661 if (!power_off)
2662 val &= (~AR_WA_D3_L1_DISABLE);
2663 } else {
2664 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2665 AR_SREV_9287(ah)) {
2666 val = AR9285_WA_DEFAULT;
2667 if (!power_off)
2668 val &= (~AR_WA_D3_L1_DISABLE);
2669 } else if (AR_SREV_9280(ah)) {
2670 /*
2671 * On AR9280 chips bit 22 of 0x4004 needs to be
2672 * set otherwise card may disappear.
2673 */
2674 val = AR9280_WA_DEFAULT;
2675 if (!power_off)
2676 val &= (~AR_WA_D3_L1_DISABLE);
2677 } else
2678 val = AR_WA_DEFAULT;
2679 }
2680
2681 REG_WRITE(ah, AR_WA, val);
2682 }
2683
2684 if (power_off) {
2685 /*
2686 * Set PCIe workaround bits
2687 * bit 14 in WA register (disable L1) should only
2688 * be set when device enters D3 and be cleared
2689 * when device comes back to D0.
2690 */
2691 if (ah->config.pcie_waen) {
2692 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2693 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2694 } else {
2695 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2696 AR_SREV_9287(ah)) &&
2697 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2698 (AR_SREV_9280(ah) &&
2699 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2700 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2701 }
2702 }
2703 }
2704 }
2705 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2706
2707 /**********************/
2708 /* Interrupt Handling */
2709 /**********************/
2710
2711 bool ath9k_hw_intrpend(struct ath_hw *ah)
2712 {
2713 u32 host_isr;
2714
2715 if (AR_SREV_9100(ah))
2716 return true;
2717
2718 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2719 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2720 return true;
2721
2722 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2723 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2724 && (host_isr != AR_INTR_SPURIOUS))
2725 return true;
2726
2727 return false;
2728 }
2729 EXPORT_SYMBOL(ath9k_hw_intrpend);
2730
2731 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2732 {
2733 u32 isr = 0;
2734 u32 mask2 = 0;
2735 struct ath9k_hw_capabilities *pCap = &ah->caps;
2736 u32 sync_cause = 0;
2737 bool fatal_int = false;
2738 struct ath_common *common = ath9k_hw_common(ah);
2739
2740 if (!AR_SREV_9100(ah)) {
2741 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2742 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2743 == AR_RTC_STATUS_ON) {
2744 isr = REG_READ(ah, AR_ISR);
2745 }
2746 }
2747
2748 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2749 AR_INTR_SYNC_DEFAULT;
2750
2751 *masked = 0;
2752
2753 if (!isr && !sync_cause)
2754 return false;
2755 } else {
2756 *masked = 0;
2757 isr = REG_READ(ah, AR_ISR);
2758 }
2759
2760 if (isr) {
2761 if (isr & AR_ISR_BCNMISC) {
2762 u32 isr2;
2763 isr2 = REG_READ(ah, AR_ISR_S2);
2764 if (isr2 & AR_ISR_S2_TIM)
2765 mask2 |= ATH9K_INT_TIM;
2766 if (isr2 & AR_ISR_S2_DTIM)
2767 mask2 |= ATH9K_INT_DTIM;
2768 if (isr2 & AR_ISR_S2_DTIMSYNC)
2769 mask2 |= ATH9K_INT_DTIMSYNC;
2770 if (isr2 & (AR_ISR_S2_CABEND))
2771 mask2 |= ATH9K_INT_CABEND;
2772 if (isr2 & AR_ISR_S2_GTT)
2773 mask2 |= ATH9K_INT_GTT;
2774 if (isr2 & AR_ISR_S2_CST)
2775 mask2 |= ATH9K_INT_CST;
2776 if (isr2 & AR_ISR_S2_TSFOOR)
2777 mask2 |= ATH9K_INT_TSFOOR;
2778 }
2779
2780 isr = REG_READ(ah, AR_ISR_RAC);
2781 if (isr == 0xffffffff) {
2782 *masked = 0;
2783 return false;
2784 }
2785
2786 *masked = isr & ATH9K_INT_COMMON;
2787
2788 if (ah->config.intr_mitigation) {
2789 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2790 *masked |= ATH9K_INT_RX;
2791 }
2792
2793 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2794 *masked |= ATH9K_INT_RX;
2795 if (isr &
2796 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2797 AR_ISR_TXEOL)) {
2798 u32 s0_s, s1_s;
2799
2800 *masked |= ATH9K_INT_TX;
2801
2802 s0_s = REG_READ(ah, AR_ISR_S0_S);
2803 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2804 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2805
2806 s1_s = REG_READ(ah, AR_ISR_S1_S);
2807 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2808 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2809 }
2810
2811 if (isr & AR_ISR_RXORN) {
2812 ath_print(common, ATH_DBG_INTERRUPT,
2813 "receive FIFO overrun interrupt\n");
2814 }
2815
2816 if (!AR_SREV_9100(ah)) {
2817 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2818 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2819 if (isr5 & AR_ISR_S5_TIM_TIMER)
2820 *masked |= ATH9K_INT_TIM_TIMER;
2821 }
2822 }
2823
2824 *masked |= mask2;
2825 }
2826
2827 if (AR_SREV_9100(ah))
2828 return true;
2829
2830 if (isr & AR_ISR_GENTMR) {
2831 u32 s5_s;
2832
2833 s5_s = REG_READ(ah, AR_ISR_S5_S);
2834 if (isr & AR_ISR_GENTMR) {
2835 ah->intr_gen_timer_trigger =
2836 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2837
2838 ah->intr_gen_timer_thresh =
2839 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2840
2841 if (ah->intr_gen_timer_trigger)
2842 *masked |= ATH9K_INT_GENTIMER;
2843
2844 }
2845 }
2846
2847 if (sync_cause) {
2848 fatal_int =
2849 (sync_cause &
2850 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2851 ? true : false;
2852
2853 if (fatal_int) {
2854 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2855 ath_print(common, ATH_DBG_ANY,
2856 "received PCI FATAL interrupt\n");
2857 }
2858 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2859 ath_print(common, ATH_DBG_ANY,
2860 "received PCI PERR interrupt\n");
2861 }
2862 *masked |= ATH9K_INT_FATAL;
2863 }
2864 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2865 ath_print(common, ATH_DBG_INTERRUPT,
2866 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2867 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2868 REG_WRITE(ah, AR_RC, 0);
2869 *masked |= ATH9K_INT_FATAL;
2870 }
2871 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2872 ath_print(common, ATH_DBG_INTERRUPT,
2873 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2874 }
2875
2876 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2877 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2878 }
2879
2880 return true;
2881 }
2882 EXPORT_SYMBOL(ath9k_hw_getisr);
2883
2884 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2885 {
2886 u32 omask = ah->mask_reg;
2887 u32 mask, mask2;
2888 struct ath9k_hw_capabilities *pCap = &ah->caps;
2889 struct ath_common *common = ath9k_hw_common(ah);
2890
2891 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2892
2893 if (omask & ATH9K_INT_GLOBAL) {
2894 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2895 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2896 (void) REG_READ(ah, AR_IER);
2897 if (!AR_SREV_9100(ah)) {
2898 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2899 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2900
2901 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2902 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2903 }
2904 }
2905
2906 mask = ints & ATH9K_INT_COMMON;
2907 mask2 = 0;
2908
2909 if (ints & ATH9K_INT_TX) {
2910 if (ah->txok_interrupt_mask)
2911 mask |= AR_IMR_TXOK;
2912 if (ah->txdesc_interrupt_mask)
2913 mask |= AR_IMR_TXDESC;
2914 if (ah->txerr_interrupt_mask)
2915 mask |= AR_IMR_TXERR;
2916 if (ah->txeol_interrupt_mask)
2917 mask |= AR_IMR_TXEOL;
2918 }
2919 if (ints & ATH9K_INT_RX) {
2920 mask |= AR_IMR_RXERR;
2921 if (ah->config.intr_mitigation)
2922 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2923 else
2924 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2925 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2926 mask |= AR_IMR_GENTMR;
2927 }
2928
2929 if (ints & (ATH9K_INT_BMISC)) {
2930 mask |= AR_IMR_BCNMISC;
2931 if (ints & ATH9K_INT_TIM)
2932 mask2 |= AR_IMR_S2_TIM;
2933 if (ints & ATH9K_INT_DTIM)
2934 mask2 |= AR_IMR_S2_DTIM;
2935 if (ints & ATH9K_INT_DTIMSYNC)
2936 mask2 |= AR_IMR_S2_DTIMSYNC;
2937 if (ints & ATH9K_INT_CABEND)
2938 mask2 |= AR_IMR_S2_CABEND;
2939 if (ints & ATH9K_INT_TSFOOR)
2940 mask2 |= AR_IMR_S2_TSFOOR;
2941 }
2942
2943 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2944 mask |= AR_IMR_BCNMISC;
2945 if (ints & ATH9K_INT_GTT)
2946 mask2 |= AR_IMR_S2_GTT;
2947 if (ints & ATH9K_INT_CST)
2948 mask2 |= AR_IMR_S2_CST;
2949 }
2950
2951 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2952 REG_WRITE(ah, AR_IMR, mask);
2953 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2954 AR_IMR_S2_DTIM |
2955 AR_IMR_S2_DTIMSYNC |
2956 AR_IMR_S2_CABEND |
2957 AR_IMR_S2_CABTO |
2958 AR_IMR_S2_TSFOOR |
2959 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2960 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2961 ah->mask_reg = ints;
2962
2963 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2964 if (ints & ATH9K_INT_TIM_TIMER)
2965 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2966 else
2967 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2968 }
2969
2970 if (ints & ATH9K_INT_GLOBAL) {
2971 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2972 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2973 if (!AR_SREV_9100(ah)) {
2974 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2975 AR_INTR_MAC_IRQ);
2976 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2977
2978
2979 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2980 AR_INTR_SYNC_DEFAULT);
2981 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2982 AR_INTR_SYNC_DEFAULT);
2983 }
2984 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2985 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2986 }
2987
2988 return omask;
2989 }
2990 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2991
2992 /*******************/
2993 /* Beacon Handling */
2994 /*******************/
2995
2996 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2997 {
2998 int flags = 0;
2999
3000 ah->beacon_interval = beacon_period;
3001
3002 switch (ah->opmode) {
3003 case NL80211_IFTYPE_STATION:
3004 case NL80211_IFTYPE_MONITOR:
3005 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3006 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3007 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3008 flags |= AR_TBTT_TIMER_EN;
3009 break;
3010 case NL80211_IFTYPE_ADHOC:
3011 case NL80211_IFTYPE_MESH_POINT:
3012 REG_SET_BIT(ah, AR_TXCFG,
3013 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3014 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3015 TU_TO_USEC(next_beacon +
3016 (ah->atim_window ? ah->
3017 atim_window : 1)));
3018 flags |= AR_NDP_TIMER_EN;
3019 case NL80211_IFTYPE_AP:
3020 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3021 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3022 TU_TO_USEC(next_beacon -
3023 ah->config.
3024 dma_beacon_response_time));
3025 REG_WRITE(ah, AR_NEXT_SWBA,
3026 TU_TO_USEC(next_beacon -
3027 ah->config.
3028 sw_beacon_response_time));
3029 flags |=
3030 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3031 break;
3032 default:
3033 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3034 "%s: unsupported opmode: %d\n",
3035 __func__, ah->opmode);
3036 return;
3037 break;
3038 }
3039
3040 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3041 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3042 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3043 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3044
3045 beacon_period &= ~ATH9K_BEACON_ENA;
3046 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3047 ath9k_hw_reset_tsf(ah);
3048 }
3049
3050 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3051 }
3052 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3053
3054 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3055 const struct ath9k_beacon_state *bs)
3056 {
3057 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3058 struct ath9k_hw_capabilities *pCap = &ah->caps;
3059 struct ath_common *common = ath9k_hw_common(ah);
3060
3061 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3062
3063 REG_WRITE(ah, AR_BEACON_PERIOD,
3064 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3065 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3066 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3067
3068 REG_RMW_FIELD(ah, AR_RSSI_THR,
3069 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3070
3071 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3072
3073 if (bs->bs_sleepduration > beaconintval)
3074 beaconintval = bs->bs_sleepduration;
3075
3076 dtimperiod = bs->bs_dtimperiod;
3077 if (bs->bs_sleepduration > dtimperiod)
3078 dtimperiod = bs->bs_sleepduration;
3079
3080 if (beaconintval == dtimperiod)
3081 nextTbtt = bs->bs_nextdtim;
3082 else
3083 nextTbtt = bs->bs_nexttbtt;
3084
3085 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3086 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3087 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3088 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3089
3090 REG_WRITE(ah, AR_NEXT_DTIM,
3091 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3092 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3093
3094 REG_WRITE(ah, AR_SLEEP1,
3095 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3096 | AR_SLEEP1_ASSUME_DTIM);
3097
3098 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3099 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3100 else
3101 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3102
3103 REG_WRITE(ah, AR_SLEEP2,
3104 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3105
3106 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3107 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3108
3109 REG_SET_BIT(ah, AR_TIMER_MODE,
3110 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3111 AR_DTIM_TIMER_EN);
3112
3113 /* TSF Out of Range Threshold */
3114 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3115 }
3116 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3117
3118 /*******************/
3119 /* HW Capabilities */
3120 /*******************/
3121
3122 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3123 {
3124 struct ath9k_hw_capabilities *pCap = &ah->caps;
3125 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3126 struct ath_common *common = ath9k_hw_common(ah);
3127 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3128
3129 u16 capField = 0, eeval;
3130
3131 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3132 regulatory->current_rd = eeval;
3133
3134 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3135 if (AR_SREV_9285_10_OR_LATER(ah))
3136 eeval |= AR9285_RDEXT_DEFAULT;
3137 regulatory->current_rd_ext = eeval;
3138
3139 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3140
3141 if (ah->opmode != NL80211_IFTYPE_AP &&
3142 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3143 if (regulatory->current_rd == 0x64 ||
3144 regulatory->current_rd == 0x65)
3145 regulatory->current_rd += 5;
3146 else if (regulatory->current_rd == 0x41)
3147 regulatory->current_rd = 0x43;
3148 ath_print(common, ATH_DBG_REGULATORY,
3149 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3150 }
3151
3152 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3153 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3154
3155 if (eeval & AR5416_OPFLAGS_11A) {
3156 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3157 if (ah->config.ht_enable) {
3158 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3159 set_bit(ATH9K_MODE_11NA_HT20,
3160 pCap->wireless_modes);
3161 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3162 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3163 pCap->wireless_modes);
3164 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3165 pCap->wireless_modes);
3166 }
3167 }
3168 }
3169
3170 if (eeval & AR5416_OPFLAGS_11G) {
3171 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3172 if (ah->config.ht_enable) {
3173 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3174 set_bit(ATH9K_MODE_11NG_HT20,
3175 pCap->wireless_modes);
3176 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3177 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3178 pCap->wireless_modes);
3179 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3180 pCap->wireless_modes);
3181 }
3182 }
3183 }
3184
3185 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3186 /*
3187 * For AR9271 we will temporarilly uses the rx chainmax as read from
3188 * the EEPROM.
3189 */
3190 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3191 !(eeval & AR5416_OPFLAGS_11A) &&
3192 !(AR_SREV_9271(ah)))
3193 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3194 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3195 else
3196 /* Use rx_chainmask from EEPROM. */
3197 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3198
3199 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3200 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3201
3202 pCap->low_2ghz_chan = 2312;
3203 pCap->high_2ghz_chan = 2732;
3204
3205 pCap->low_5ghz_chan = 4920;
3206 pCap->high_5ghz_chan = 6100;
3207
3208 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3209 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3210 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3211
3212 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3213 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3214 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3215
3216 if (ah->config.ht_enable)
3217 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3218 else
3219 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3220
3221 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3222 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3223 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3224 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3225
3226 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3227 pCap->total_queues =
3228 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3229 else
3230 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3231
3232 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3233 pCap->keycache_size =
3234 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3235 else
3236 pCap->keycache_size = AR_KEYTABLE_SIZE;
3237
3238 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3239 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3240
3241 if (AR_SREV_9285_10_OR_LATER(ah))
3242 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3243 else if (AR_SREV_9280_10_OR_LATER(ah))
3244 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3245 else
3246 pCap->num_gpio_pins = AR_NUM_GPIO;
3247
3248 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3249 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3250 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3251 } else {
3252 pCap->rts_aggr_limit = (8 * 1024);
3253 }
3254
3255 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3256
3257 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3258 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3259 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3260 ah->rfkill_gpio =
3261 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3262 ah->rfkill_polarity =
3263 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3264
3265 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3266 }
3267 #endif
3268
3269 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3270
3271 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3272 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3273 else
3274 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3275
3276 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3277 pCap->reg_cap =
3278 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3279 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3280 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3281 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3282 } else {
3283 pCap->reg_cap =
3284 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3285 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3286 }
3287
3288 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3289 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3290 AR_SREV_5416(ah))
3291 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3292
3293 pCap->num_antcfg_5ghz =
3294 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3295 pCap->num_antcfg_2ghz =
3296 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3297
3298 if (AR_SREV_9280_10_OR_LATER(ah) &&
3299 ath9k_hw_btcoex_supported(ah)) {
3300 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3301 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3302
3303 if (AR_SREV_9285(ah)) {
3304 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3305 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3306 } else {
3307 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3308 }
3309 } else {
3310 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3311 }
3312 }
3313
3314 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3315 u32 capability, u32 *result)
3316 {
3317 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3318 switch (type) {
3319 case ATH9K_CAP_CIPHER:
3320 switch (capability) {
3321 case ATH9K_CIPHER_AES_CCM:
3322 case ATH9K_CIPHER_AES_OCB:
3323 case ATH9K_CIPHER_TKIP:
3324 case ATH9K_CIPHER_WEP:
3325 case ATH9K_CIPHER_MIC:
3326 case ATH9K_CIPHER_CLR:
3327 return true;
3328 default:
3329 return false;
3330 }
3331 case ATH9K_CAP_TKIP_MIC:
3332 switch (capability) {
3333 case 0:
3334 return true;
3335 case 1:
3336 return (ah->sta_id1_defaults &
3337 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3338 false;
3339 }
3340 case ATH9K_CAP_TKIP_SPLIT:
3341 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3342 false : true;
3343 case ATH9K_CAP_DIVERSITY:
3344 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3345 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3346 true : false;
3347 case ATH9K_CAP_MCAST_KEYSRCH:
3348 switch (capability) {
3349 case 0:
3350 return true;
3351 case 1:
3352 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3353 return false;
3354 } else {
3355 return (ah->sta_id1_defaults &
3356 AR_STA_ID1_MCAST_KSRCH) ? true :
3357 false;
3358 }
3359 }
3360 return false;
3361 case ATH9K_CAP_TXPOW:
3362 switch (capability) {
3363 case 0:
3364 return 0;
3365 case 1:
3366 *result = regulatory->power_limit;
3367 return 0;
3368 case 2:
3369 *result = regulatory->max_power_level;
3370 return 0;
3371 case 3:
3372 *result = regulatory->tp_scale;
3373 return 0;
3374 }
3375 return false;
3376 case ATH9K_CAP_DS:
3377 return (AR_SREV_9280_20_OR_LATER(ah) &&
3378 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3379 ? false : true;
3380 default:
3381 return false;
3382 }
3383 }
3384 EXPORT_SYMBOL(ath9k_hw_getcapability);
3385
3386 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3387 u32 capability, u32 setting, int *status)
3388 {
3389 u32 v;
3390
3391 switch (type) {
3392 case ATH9K_CAP_TKIP_MIC:
3393 if (setting)
3394 ah->sta_id1_defaults |=
3395 AR_STA_ID1_CRPT_MIC_ENABLE;
3396 else
3397 ah->sta_id1_defaults &=
3398 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3399 return true;
3400 case ATH9K_CAP_DIVERSITY:
3401 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3402 if (setting)
3403 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3404 else
3405 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3406 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3407 return true;
3408 case ATH9K_CAP_MCAST_KEYSRCH:
3409 if (setting)
3410 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3411 else
3412 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3413 return true;
3414 default:
3415 return false;
3416 }
3417 }
3418 EXPORT_SYMBOL(ath9k_hw_setcapability);
3419
3420 /****************************/
3421 /* GPIO / RFKILL / Antennae */
3422 /****************************/
3423
3424 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3425 u32 gpio, u32 type)
3426 {
3427 int addr;
3428 u32 gpio_shift, tmp;
3429
3430 if (gpio > 11)
3431 addr = AR_GPIO_OUTPUT_MUX3;
3432 else if (gpio > 5)
3433 addr = AR_GPIO_OUTPUT_MUX2;
3434 else
3435 addr = AR_GPIO_OUTPUT_MUX1;
3436
3437 gpio_shift = (gpio % 6) * 5;
3438
3439 if (AR_SREV_9280_20_OR_LATER(ah)
3440 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3441 REG_RMW(ah, addr, (type << gpio_shift),
3442 (0x1f << gpio_shift));
3443 } else {
3444 tmp = REG_READ(ah, addr);
3445 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3446 tmp &= ~(0x1f << gpio_shift);
3447 tmp |= (type << gpio_shift);
3448 REG_WRITE(ah, addr, tmp);
3449 }
3450 }
3451
3452 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3453 {
3454 u32 gpio_shift;
3455
3456 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3457
3458 gpio_shift = gpio << 1;
3459
3460 REG_RMW(ah,
3461 AR_GPIO_OE_OUT,
3462 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3463 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3464 }
3465 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3466
3467 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3468 {
3469 #define MS_REG_READ(x, y) \
3470 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3471
3472 if (gpio >= ah->caps.num_gpio_pins)
3473 return 0xffffffff;
3474
3475 if (AR_SREV_9287_10_OR_LATER(ah))
3476 return MS_REG_READ(AR9287, gpio) != 0;
3477 else if (AR_SREV_9285_10_OR_LATER(ah))
3478 return MS_REG_READ(AR9285, gpio) != 0;
3479 else if (AR_SREV_9280_10_OR_LATER(ah))
3480 return MS_REG_READ(AR928X, gpio) != 0;
3481 else
3482 return MS_REG_READ(AR, gpio) != 0;
3483 }
3484 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3485
3486 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3487 u32 ah_signal_type)
3488 {
3489 u32 gpio_shift;
3490
3491 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3492
3493 gpio_shift = 2 * gpio;
3494
3495 REG_RMW(ah,
3496 AR_GPIO_OE_OUT,
3497 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3498 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3499 }
3500 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3501
3502 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3503 {
3504 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3505 AR_GPIO_BIT(gpio));
3506 }
3507 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3508
3509 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3510 {
3511 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3512 }
3513 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3514
3515 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3516 {
3517 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3518 }
3519 EXPORT_SYMBOL(ath9k_hw_setantenna);
3520
3521 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3522 enum ath9k_ant_setting settings,
3523 struct ath9k_channel *chan,
3524 u8 *tx_chainmask,
3525 u8 *rx_chainmask,
3526 u8 *antenna_cfgd)
3527 {
3528 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3529
3530 if (AR_SREV_9280(ah)) {
3531 if (!tx_chainmask_cfg) {
3532
3533 tx_chainmask_cfg = *tx_chainmask;
3534 rx_chainmask_cfg = *rx_chainmask;
3535 }
3536
3537 switch (settings) {
3538 case ATH9K_ANT_FIXED_A:
3539 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3540 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3541 *antenna_cfgd = true;
3542 break;
3543 case ATH9K_ANT_FIXED_B:
3544 if (ah->caps.tx_chainmask >
3545 ATH9K_ANTENNA1_CHAINMASK) {
3546 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3547 }
3548 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3549 *antenna_cfgd = true;
3550 break;
3551 case ATH9K_ANT_VARIABLE:
3552 *tx_chainmask = tx_chainmask_cfg;
3553 *rx_chainmask = rx_chainmask_cfg;
3554 *antenna_cfgd = true;
3555 break;
3556 default:
3557 break;
3558 }
3559 } else {
3560 ah->config.diversity_control = settings;
3561 }
3562
3563 return true;
3564 }
3565
3566 /*********************/
3567 /* General Operation */
3568 /*********************/
3569
3570 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3571 {
3572 u32 bits = REG_READ(ah, AR_RX_FILTER);
3573 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3574
3575 if (phybits & AR_PHY_ERR_RADAR)
3576 bits |= ATH9K_RX_FILTER_PHYRADAR;
3577 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3578 bits |= ATH9K_RX_FILTER_PHYERR;
3579
3580 return bits;
3581 }
3582 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3583
3584 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3585 {
3586 u32 phybits;
3587
3588 REG_WRITE(ah, AR_RX_FILTER, bits);
3589
3590 phybits = 0;
3591 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3592 phybits |= AR_PHY_ERR_RADAR;
3593 if (bits & ATH9K_RX_FILTER_PHYERR)
3594 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3595 REG_WRITE(ah, AR_PHY_ERR, phybits);
3596
3597 if (phybits)
3598 REG_WRITE(ah, AR_RXCFG,
3599 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3600 else
3601 REG_WRITE(ah, AR_RXCFG,
3602 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3603 }
3604 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3605
3606 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3607 {
3608 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3609 return false;
3610
3611 ath9k_hw_init_pll(ah, NULL);
3612 return true;
3613 }
3614 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3615
3616 bool ath9k_hw_disable(struct ath_hw *ah)
3617 {
3618 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3619 return false;
3620
3621 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3622 return false;
3623
3624 ath9k_hw_init_pll(ah, NULL);
3625 return true;
3626 }
3627 EXPORT_SYMBOL(ath9k_hw_disable);
3628
3629 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3630 {
3631 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3632 struct ath9k_channel *chan = ah->curchan;
3633 struct ieee80211_channel *channel = chan->chan;
3634
3635 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3636
3637 ah->eep_ops->set_txpower(ah, chan,
3638 ath9k_regd_get_ctl(regulatory, chan),
3639 channel->max_antenna_gain * 2,
3640 channel->max_power * 2,
3641 min((u32) MAX_RATE_POWER,
3642 (u32) regulatory->power_limit));
3643 }
3644 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3645
3646 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3647 {
3648 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3649 }
3650 EXPORT_SYMBOL(ath9k_hw_setmac);
3651
3652 void ath9k_hw_setopmode(struct ath_hw *ah)
3653 {
3654 ath9k_hw_set_operating_mode(ah, ah->opmode);
3655 }
3656 EXPORT_SYMBOL(ath9k_hw_setopmode);
3657
3658 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3659 {
3660 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3661 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3662 }
3663 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3664
3665 void ath9k_hw_write_associd(struct ath_hw *ah)
3666 {
3667 struct ath_common *common = ath9k_hw_common(ah);
3668
3669 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3670 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3671 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3672 }
3673 EXPORT_SYMBOL(ath9k_hw_write_associd);
3674
3675 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3676 {
3677 u64 tsf;
3678
3679 tsf = REG_READ(ah, AR_TSF_U32);
3680 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3681
3682 return tsf;
3683 }
3684 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3685
3686 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3687 {
3688 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3689 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3690 }
3691 EXPORT_SYMBOL(ath9k_hw_settsf64);
3692
3693 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3694 {
3695 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3696 AH_TSF_WRITE_TIMEOUT))
3697 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3698 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3699
3700 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3701 }
3702 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3703
3704 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3705 {
3706 if (setting)
3707 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3708 else
3709 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3710 }
3711 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3712
3713 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3714 {
3715 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3716 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3717 "bad slot time %u\n", us);
3718 ah->slottime = (u32) -1;
3719 return false;
3720 } else {
3721 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3722 ah->slottime = us;
3723 return true;
3724 }
3725 }
3726 EXPORT_SYMBOL(ath9k_hw_setslottime);
3727
3728 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3729 {
3730 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3731 u32 macmode;
3732
3733 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3734 macmode = AR_2040_JOINED_RX_CLEAR;
3735 else
3736 macmode = 0;
3737
3738 REG_WRITE(ah, AR_2040_MODE, macmode);
3739 }
3740
3741 /* HW Generic timers configuration */
3742
3743 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3744 {
3745 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3746 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3747 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3748 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3749 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3750 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3751 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3752 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3753 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3754 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3755 AR_NDP2_TIMER_MODE, 0x0002},
3756 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3757 AR_NDP2_TIMER_MODE, 0x0004},
3758 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3759 AR_NDP2_TIMER_MODE, 0x0008},
3760 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3761 AR_NDP2_TIMER_MODE, 0x0010},
3762 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3763 AR_NDP2_TIMER_MODE, 0x0020},
3764 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3765 AR_NDP2_TIMER_MODE, 0x0040},
3766 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3767 AR_NDP2_TIMER_MODE, 0x0080}
3768 };
3769
3770 /* HW generic timer primitives */
3771
3772 /* compute and clear index of rightmost 1 */
3773 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3774 {
3775 u32 b;
3776
3777 b = *mask;
3778 b &= (0-b);
3779 *mask &= ~b;
3780 b *= debruijn32;
3781 b >>= 27;
3782
3783 return timer_table->gen_timer_index[b];
3784 }
3785
3786 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3787 {
3788 return REG_READ(ah, AR_TSF_L32);
3789 }
3790 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3791
3792 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3793 void (*trigger)(void *),
3794 void (*overflow)(void *),
3795 void *arg,
3796 u8 timer_index)
3797 {
3798 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3799 struct ath_gen_timer *timer;
3800
3801 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3802
3803 if (timer == NULL) {
3804 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3805 "Failed to allocate memory"
3806 "for hw timer[%d]\n", timer_index);
3807 return NULL;
3808 }
3809
3810 /* allocate a hardware generic timer slot */
3811 timer_table->timers[timer_index] = timer;
3812 timer->index = timer_index;
3813 timer->trigger = trigger;
3814 timer->overflow = overflow;
3815 timer->arg = arg;
3816
3817 return timer;
3818 }
3819 EXPORT_SYMBOL(ath_gen_timer_alloc);
3820
3821 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3822 struct ath_gen_timer *timer,
3823 u32 timer_next,
3824 u32 timer_period)
3825 {
3826 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3827 u32 tsf;
3828
3829 BUG_ON(!timer_period);
3830
3831 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3832
3833 tsf = ath9k_hw_gettsf32(ah);
3834
3835 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3836 "curent tsf %x period %x"
3837 "timer_next %x\n", tsf, timer_period, timer_next);
3838
3839 /*
3840 * Pull timer_next forward if the current TSF already passed it
3841 * because of software latency
3842 */
3843 if (timer_next < tsf)
3844 timer_next = tsf + timer_period;
3845
3846 /*
3847 * Program generic timer registers
3848 */
3849 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3850 timer_next);
3851 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3852 timer_period);
3853 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3854 gen_tmr_configuration[timer->index].mode_mask);
3855
3856 /* Enable both trigger and thresh interrupt masks */
3857 REG_SET_BIT(ah, AR_IMR_S5,
3858 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3859 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3860 }
3861 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3862
3863 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3864 {
3865 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3866
3867 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3868 (timer->index >= ATH_MAX_GEN_TIMER)) {
3869 return;
3870 }
3871
3872 /* Clear generic timer enable bits. */
3873 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3874 gen_tmr_configuration[timer->index].mode_mask);
3875
3876 /* Disable both trigger and thresh interrupt masks */
3877 REG_CLR_BIT(ah, AR_IMR_S5,
3878 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3879 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3880
3881 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3882 }
3883 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3884
3885 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3886 {
3887 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3888
3889 /* free the hardware generic timer slot */
3890 timer_table->timers[timer->index] = NULL;
3891 kfree(timer);
3892 }
3893 EXPORT_SYMBOL(ath_gen_timer_free);
3894
3895 /*
3896 * Generic Timer Interrupts handling
3897 */
3898 void ath_gen_timer_isr(struct ath_hw *ah)
3899 {
3900 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3901 struct ath_gen_timer *timer;
3902 struct ath_common *common = ath9k_hw_common(ah);
3903 u32 trigger_mask, thresh_mask, index;
3904
3905 /* get hardware generic timer interrupt status */
3906 trigger_mask = ah->intr_gen_timer_trigger;
3907 thresh_mask = ah->intr_gen_timer_thresh;
3908 trigger_mask &= timer_table->timer_mask.val;
3909 thresh_mask &= timer_table->timer_mask.val;
3910
3911 trigger_mask &= ~thresh_mask;
3912
3913 while (thresh_mask) {
3914 index = rightmost_index(timer_table, &thresh_mask);
3915 timer = timer_table->timers[index];
3916 BUG_ON(!timer);
3917 ath_print(common, ATH_DBG_HWTIMER,
3918 "TSF overflow for Gen timer %d\n", index);
3919 timer->overflow(timer->arg);
3920 }
3921
3922 while (trigger_mask) {
3923 index = rightmost_index(timer_table, &trigger_mask);
3924 timer = timer_table->timers[index];
3925 BUG_ON(!timer);
3926 ath_print(common, ATH_DBG_HWTIMER,
3927 "Gen timer[%d] trigger\n", index);
3928 timer->trigger(timer->arg);
3929 }
3930 }
3931 EXPORT_SYMBOL(ath_gen_timer_isr);
3932
3933 static struct {
3934 u32 version;
3935 const char * name;
3936 } ath_mac_bb_names[] = {
3937 /* Devices with external radios */
3938 { AR_SREV_VERSION_5416_PCI, "5416" },
3939 { AR_SREV_VERSION_5416_PCIE, "5418" },
3940 { AR_SREV_VERSION_9100, "9100" },
3941 { AR_SREV_VERSION_9160, "9160" },
3942 /* Single-chip solutions */
3943 { AR_SREV_VERSION_9280, "9280" },
3944 { AR_SREV_VERSION_9285, "9285" },
3945 { AR_SREV_VERSION_9287, "9287" },
3946 { AR_SREV_VERSION_9271, "9271" },
3947 };
3948
3949 /* For devices with external radios */
3950 static struct {
3951 u16 version;
3952 const char * name;
3953 } ath_rf_names[] = {
3954 { 0, "5133" },
3955 { AR_RAD5133_SREV_MAJOR, "5133" },
3956 { AR_RAD5122_SREV_MAJOR, "5122" },
3957 { AR_RAD2133_SREV_MAJOR, "2133" },
3958 { AR_RAD2122_SREV_MAJOR, "2122" }
3959 };
3960
3961 /*
3962 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3963 */
3964 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3965 {
3966 int i;
3967
3968 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3969 if (ath_mac_bb_names[i].version == mac_bb_version) {
3970 return ath_mac_bb_names[i].name;
3971 }
3972 }
3973
3974 return "????";
3975 }
3976
3977 /*
3978 * Return the RF name. "????" is returned if the RF is unknown.
3979 * Used for devices with external radios.
3980 */
3981 static const char *ath9k_hw_rf_name(u16 rf_version)
3982 {
3983 int i;
3984
3985 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3986 if (ath_rf_names[i].version == rf_version) {
3987 return ath_rf_names[i].name;
3988 }
3989 }
3990
3991 return "????";
3992 }
3993
3994 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3995 {
3996 int used;
3997
3998 /* chipsets >= AR9280 are single-chip */
3999 if (AR_SREV_9280_10_OR_LATER(ah)) {
4000 used = snprintf(hw_name, len,
4001 "Atheros AR%s Rev:%x",
4002 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
4003 ah->hw_version.macRev);
4004 }
4005 else {
4006 used = snprintf(hw_name, len,
4007 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
4008 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
4009 ah->hw_version.macRev,
4010 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
4011 AR_RADIO_SREV_MAJOR)),
4012 ah->hw_version.phyRev);
4013 }
4014
4015 hw_name[used] = '\0';
4016 }
4017 EXPORT_SYMBOL(ath9k_hw_name);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree