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ath9k: use u8 for the tx key index
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / hw.h
blobc8af86c795e55d18d6d03daa993db465eae08292
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23
24 #include "mac.h"
25 #include "ani.h"
26 #include "eeprom.h"
27 #include "calib.h"
28 #include "reg.h"
29 #include "phy.h"
30 #include "btcoex.h"
31
32 #include "../regd.h"
33
34 #define ATHEROS_VENDOR_ID 0x168c
35
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9340 0x0031
47 #define AR9300_DEVID_AR9485_PCIE 0x0032
48 #define AR9300_DEVID_AR9580 0x0033
49 #define AR9300_DEVID_AR9330 0x0035
50
51 #define AR5416_AR9100_DEVID 0x000b
52
53 #define AR_SUBVENDOR_ID_NOG 0x0e11
54 #define AR_SUBVENDOR_ID_NEW_A 0x7065
55 #define AR5416_MAGIC 0x19641014
56
57 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
58 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
59 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
60
61 #define AR9300_NUM_BT_WEIGHTS 4
62 #define AR9300_NUM_WLAN_WEIGHTS 4
63
64 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
65
66 #define ATH_DEFAULT_NOISE_FLOOR -95
67
68 #define ATH9K_RSSI_BAD -128
69
70 #define ATH9K_NUM_CHANNELS 38
71
72 /* Register read/write primitives */
73 #define REG_WRITE(_ah, _reg, _val) \
74 (_ah)->reg_ops.write((_ah), (_val), (_reg))
75
76 #define REG_READ(_ah, _reg) \
77 (_ah)->reg_ops.read((_ah), (_reg))
78
79 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
80 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
81
82 #define REG_RMW(_ah, _reg, _set, _clr) \
83 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
84
85 #define ENABLE_REGWRITE_BUFFER(_ah) \
86 do { \
87 if ((_ah)->reg_ops.enable_write_buffer) \
88 (_ah)->reg_ops.enable_write_buffer((_ah)); \
89 } while (0)
90
91 #define REGWRITE_BUFFER_FLUSH(_ah) \
92 do { \
93 if ((_ah)->reg_ops.write_flush) \
94 (_ah)->reg_ops.write_flush((_ah)); \
95 } while (0)
96
97 #define PR_EEP(_s, _val) \
98 do { \
99 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
100 _s, (_val)); \
101 } while (0)
102
103 #define SM(_v, _f) (((_v) << _f##_S) & _f)
104 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
105 #define REG_RMW_FIELD(_a, _r, _f, _v) \
106 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
107 #define REG_READ_FIELD(_a, _r, _f) \
108 (((REG_READ(_a, _r) & _f) >> _f##_S))
109 #define REG_SET_BIT(_a, _r, _f) \
110 REG_RMW(_a, _r, (_f), 0)
111 #define REG_CLR_BIT(_a, _r, _f) \
112 REG_RMW(_a, _r, 0, (_f))
113
114 #define DO_DELAY(x) do { \
115 if (((++(x) % 64) == 0) && \
116 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
117 != ATH_USB)) \
118 udelay(1); \
119 } while (0)
120
121 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
122 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
123
124 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
125 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
126 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
127 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
128 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
129 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
130 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
131
132 #define AR_GPIOD_MASK 0x00001FFF
133 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
134
135 #define BASE_ACTIVATE_DELAY 100
136 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
137 #define COEF_SCALE_S 24
138 #define HT40_CHANNEL_CENTER_SHIFT 10
139
140 #define ATH9K_ANTENNA0_CHAINMASK 0x1
141 #define ATH9K_ANTENNA1_CHAINMASK 0x2
142
143 #define ATH9K_NUM_DMA_DEBUG_REGS 8
144 #define ATH9K_NUM_QUEUES 10
145
146 #define MAX_RATE_POWER 63
147 #define AH_WAIT_TIMEOUT 100000 /* (us) */
148 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
149 #define AH_TIME_QUANTUM 10
150 #define AR_KEYTABLE_SIZE 128
151 #define POWER_UP_TIME 10000
152 #define SPUR_RSSI_THRESH 40
153 #define UPPER_5G_SUB_BAND_START 5700
154 #define MID_5G_SUB_BAND_START 5400
155
156 #define CAB_TIMEOUT_VAL 10
157 #define BEACON_TIMEOUT_VAL 10
158 #define MIN_BEACON_TIMEOUT_VAL 1
159 #define SLEEP_SLOP 3
160
161 #define INIT_CONFIG_STATUS 0x00000000
162 #define INIT_RSSI_THR 0x00000700
163 #define INIT_BCON_CNTRL_REG 0x00000000
164
165 #define TU_TO_USEC(_tu) ((_tu) << 10)
166
167 #define ATH9K_HW_RX_HP_QDEPTH 16
168 #define ATH9K_HW_RX_LP_QDEPTH 128
169
170 #define PAPRD_GAIN_TABLE_ENTRIES 32
171 #define PAPRD_TABLE_SZ 24
172 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
173
174 enum ath_hw_txq_subtype {
175 ATH_TXQ_AC_BE = 0,
176 ATH_TXQ_AC_BK = 1,
177 ATH_TXQ_AC_VI = 2,
178 ATH_TXQ_AC_VO = 3,
179 };
180
181 enum ath_ini_subsys {
182 ATH_INI_PRE = 0,
183 ATH_INI_CORE,
184 ATH_INI_POST,
185 ATH_INI_NUM_SPLIT,
186 };
187
188 enum ath9k_hw_caps {
189 ATH9K_HW_CAP_HT = BIT(0),
190 ATH9K_HW_CAP_RFSILENT = BIT(1),
191 ATH9K_HW_CAP_CST = BIT(2),
192 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
193 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
194 ATH9K_HW_CAP_EDMA = BIT(6),
195 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
196 ATH9K_HW_CAP_LDPC = BIT(8),
197 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
198 ATH9K_HW_CAP_SGI_20 = BIT(10),
199 ATH9K_HW_CAP_PAPRD = BIT(11),
200 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
201 ATH9K_HW_CAP_2GHZ = BIT(13),
202 ATH9K_HW_CAP_5GHZ = BIT(14),
203 ATH9K_HW_CAP_APM = BIT(15),
204 };
205
206 struct ath9k_hw_capabilities {
207 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
208 u16 rts_aggr_limit;
209 u8 tx_chainmask;
210 u8 rx_chainmask;
211 u8 max_txchains;
212 u8 max_rxchains;
213 u8 num_gpio_pins;
214 u8 rx_hp_qdepth;
215 u8 rx_lp_qdepth;
216 u8 rx_status_len;
217 u8 tx_desc_len;
218 u8 txs_len;
219 u16 pcie_lcr_offset;
220 bool pcie_lcr_extsync_en;
221 };
222
223 struct ath9k_ops_config {
224 int dma_beacon_response_time;
225 int sw_beacon_response_time;
226 int additional_swba_backoff;
227 int ack_6mb;
228 u32 cwm_ignore_extcca;
229 bool pcieSerDesWrite;
230 u8 pcie_clock_req;
231 u32 pcie_waen;
232 u8 analog_shiftreg;
233 u8 paprd_disable;
234 u32 ofdm_trig_low;
235 u32 ofdm_trig_high;
236 u32 cck_trig_high;
237 u32 cck_trig_low;
238 u32 enable_ani;
239 int serialize_regmode;
240 bool rx_intr_mitigation;
241 bool tx_intr_mitigation;
242 #define SPUR_DISABLE 0
243 #define SPUR_ENABLE_IOCTL 1
244 #define SPUR_ENABLE_EEPROM 2
245 #define AR_SPUR_5413_1 1640
246 #define AR_SPUR_5413_2 1200
247 #define AR_NO_SPUR 0x8000
248 #define AR_BASE_FREQ_2GHZ 2300
249 #define AR_BASE_FREQ_5GHZ 4900
250 #define AR_SPUR_FEEQ_BOUND_HT40 19
251 #define AR_SPUR_FEEQ_BOUND_HT20 10
252 int spurmode;
253 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
254 u8 max_txtrig_level;
255 u16 ani_poll_interval; /* ANI poll interval in ms */
256 };
257
258 enum ath9k_int {
259 ATH9K_INT_RX = 0x00000001,
260 ATH9K_INT_RXDESC = 0x00000002,
261 ATH9K_INT_RXHP = 0x00000001,
262 ATH9K_INT_RXLP = 0x00000002,
263 ATH9K_INT_RXNOFRM = 0x00000008,
264 ATH9K_INT_RXEOL = 0x00000010,
265 ATH9K_INT_RXORN = 0x00000020,
266 ATH9K_INT_TX = 0x00000040,
267 ATH9K_INT_TXDESC = 0x00000080,
268 ATH9K_INT_TIM_TIMER = 0x00000100,
269 ATH9K_INT_BB_WATCHDOG = 0x00000400,
270 ATH9K_INT_TXURN = 0x00000800,
271 ATH9K_INT_MIB = 0x00001000,
272 ATH9K_INT_RXPHY = 0x00004000,
273 ATH9K_INT_RXKCM = 0x00008000,
274 ATH9K_INT_SWBA = 0x00010000,
275 ATH9K_INT_BMISS = 0x00040000,
276 ATH9K_INT_BNR = 0x00100000,
277 ATH9K_INT_TIM = 0x00200000,
278 ATH9K_INT_DTIM = 0x00400000,
279 ATH9K_INT_DTIMSYNC = 0x00800000,
280 ATH9K_INT_GPIO = 0x01000000,
281 ATH9K_INT_CABEND = 0x02000000,
282 ATH9K_INT_TSFOOR = 0x04000000,
283 ATH9K_INT_GENTIMER = 0x08000000,
284 ATH9K_INT_CST = 0x10000000,
285 ATH9K_INT_GTT = 0x20000000,
286 ATH9K_INT_FATAL = 0x40000000,
287 ATH9K_INT_GLOBAL = 0x80000000,
288 ATH9K_INT_BMISC = ATH9K_INT_TIM |
289 ATH9K_INT_DTIM |
290 ATH9K_INT_DTIMSYNC |
291 ATH9K_INT_TSFOOR |
292 ATH9K_INT_CABEND,
293 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
294 ATH9K_INT_RXDESC |
295 ATH9K_INT_RXEOL |
296 ATH9K_INT_RXORN |
297 ATH9K_INT_TXURN |
298 ATH9K_INT_TXDESC |
299 ATH9K_INT_MIB |
300 ATH9K_INT_RXPHY |
301 ATH9K_INT_RXKCM |
302 ATH9K_INT_SWBA |
303 ATH9K_INT_BMISS |
304 ATH9K_INT_GPIO,
305 ATH9K_INT_NOCARD = 0xffffffff
306 };
307
308 #define CHANNEL_CW_INT 0x00002
309 #define CHANNEL_CCK 0x00020
310 #define CHANNEL_OFDM 0x00040
311 #define CHANNEL_2GHZ 0x00080
312 #define CHANNEL_5GHZ 0x00100
313 #define CHANNEL_PASSIVE 0x00200
314 #define CHANNEL_DYN 0x00400
315 #define CHANNEL_HALF 0x04000
316 #define CHANNEL_QUARTER 0x08000
317 #define CHANNEL_HT20 0x10000
318 #define CHANNEL_HT40PLUS 0x20000
319 #define CHANNEL_HT40MINUS 0x40000
320
321 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
322 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
323 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
324 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
325 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
326 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
327 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
328 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
329 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
330 #define CHANNEL_ALL \
331 (CHANNEL_OFDM| \
332 CHANNEL_CCK| \
333 CHANNEL_2GHZ | \
334 CHANNEL_5GHZ | \
335 CHANNEL_HT20 | \
336 CHANNEL_HT40PLUS | \
337 CHANNEL_HT40MINUS)
338
339 struct ath9k_hw_cal_data {
340 u16 channel;
341 u32 channelFlags;
342 int32_t CalValid;
343 int8_t iCoff;
344 int8_t qCoff;
345 bool paprd_done;
346 bool nfcal_pending;
347 bool nfcal_interference;
348 u16 small_signal_gain[AR9300_MAX_CHAINS];
349 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
350 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
351 };
352
353 struct ath9k_channel {
354 struct ieee80211_channel *chan;
355 struct ar5416AniState ani;
356 u16 channel;
357 u32 channelFlags;
358 u32 chanmode;
359 s16 noisefloor;
360 };
361
362 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
363 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
364 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
365 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
366 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
367 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
368 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
369 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
370 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
371 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
372 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
373 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
374
375 /* These macros check chanmode and not channelFlags */
376 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
377 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
378 ((_c)->chanmode == CHANNEL_G_HT20))
379 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
380 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
381 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
382 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
383 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
384
385 enum ath9k_power_mode {
386 ATH9K_PM_AWAKE = 0,
387 ATH9K_PM_FULL_SLEEP,
388 ATH9K_PM_NETWORK_SLEEP,
389 ATH9K_PM_UNDEFINED
390 };
391
392 enum ath9k_tp_scale {
393 ATH9K_TP_SCALE_MAX = 0,
394 ATH9K_TP_SCALE_50,
395 ATH9K_TP_SCALE_25,
396 ATH9K_TP_SCALE_12,
397 ATH9K_TP_SCALE_MIN
398 };
399
400 enum ser_reg_mode {
401 SER_REG_MODE_OFF = 0,
402 SER_REG_MODE_ON = 1,
403 SER_REG_MODE_AUTO = 2,
404 };
405
406 enum ath9k_rx_qtype {
407 ATH9K_RX_QUEUE_HP,
408 ATH9K_RX_QUEUE_LP,
409 ATH9K_RX_QUEUE_MAX,
410 };
411
412 struct ath9k_beacon_state {
413 u32 bs_nexttbtt;
414 u32 bs_nextdtim;
415 u32 bs_intval;
416 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
417 u32 bs_dtimperiod;
418 u16 bs_cfpperiod;
419 u16 bs_cfpmaxduration;
420 u32 bs_cfpnext;
421 u16 bs_timoffset;
422 u16 bs_bmissthreshold;
423 u32 bs_sleepduration;
424 u32 bs_tsfoor_threshold;
425 };
426
427 struct chan_centers {
428 u16 synth_center;
429 u16 ctl_center;
430 u16 ext_center;
431 };
432
433 enum {
434 ATH9K_RESET_POWER_ON,
435 ATH9K_RESET_WARM,
436 ATH9K_RESET_COLD,
437 };
438
439 struct ath9k_hw_version {
440 u32 magic;
441 u16 devid;
442 u16 subvendorid;
443 u32 macVersion;
444 u16 macRev;
445 u16 phyRev;
446 u16 analog5GhzRev;
447 u16 analog2GhzRev;
448 enum ath_usb_dev usbdev;
449 };
450
451 /* Generic TSF timer definitions */
452
453 #define ATH_MAX_GEN_TIMER 16
454
455 #define AR_GENTMR_BIT(_index) (1 << (_index))
456
457 /*
458 * Using de Bruijin sequence to look up 1's index in a 32 bit number
459 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
460 */
461 #define debruijn32 0x077CB531U
462
463 struct ath_gen_timer_configuration {
464 u32 next_addr;
465 u32 period_addr;
466 u32 mode_addr;
467 u32 mode_mask;
468 };
469
470 struct ath_gen_timer {
471 void (*trigger)(void *arg);
472 void (*overflow)(void *arg);
473 void *arg;
474 u8 index;
475 };
476
477 struct ath_gen_timer_table {
478 u32 gen_timer_index[32];
479 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
480 union {
481 unsigned long timer_bits;
482 u16 val;
483 } timer_mask;
484 };
485
486 struct ath_hw_antcomb_conf {
487 u8 main_lna_conf;
488 u8 alt_lna_conf;
489 u8 fast_div_bias;
490 u8 main_gaintb;
491 u8 alt_gaintb;
492 int lna1_lna2_delta;
493 u8 div_group;
494 };
495
496 /**
497 * struct ath_hw_radar_conf - radar detection initialization parameters
498 *
499 * @pulse_inband: threshold for checking the ratio of in-band power
500 * to total power for short radar pulses (half dB steps)
501 * @pulse_inband_step: threshold for checking an in-band power to total
502 * power ratio increase for short radar pulses (half dB steps)
503 * @pulse_height: threshold for detecting the beginning of a short
504 * radar pulse (dB step)
505 * @pulse_rssi: threshold for detecting if a short radar pulse is
506 * gone (dB step)
507 * @pulse_maxlen: maximum pulse length (0.8 us steps)
508 *
509 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
510 * @radar_inband: threshold for checking the ratio of in-band power
511 * to total power for long radar pulses (half dB steps)
512 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
513 *
514 * @ext_channel: enable extension channel radar detection
515 */
516 struct ath_hw_radar_conf {
517 unsigned int pulse_inband;
518 unsigned int pulse_inband_step;
519 unsigned int pulse_height;
520 unsigned int pulse_rssi;
521 unsigned int pulse_maxlen;
522
523 unsigned int radar_rssi;
524 unsigned int radar_inband;
525 int fir_power;
526
527 bool ext_channel;
528 };
529
530 /**
531 * struct ath_hw_private_ops - callbacks used internally by hardware code
532 *
533 * This structure contains private callbacks designed to only be used internally
534 * by the hardware core.
535 *
536 * @init_cal_settings: setup types of calibrations supported
537 * @init_cal: starts actual calibration
538 *
539 * @init_mode_regs: Initializes mode registers
540 * @init_mode_gain_regs: Initialize TX/RX gain registers
541 *
542 * @rf_set_freq: change frequency
543 * @spur_mitigate_freq: spur mitigation
544 * @rf_alloc_ext_banks:
545 * @rf_free_ext_banks:
546 * @set_rf_regs:
547 * @compute_pll_control: compute the PLL control value to use for
548 * AR_RTC_PLL_CONTROL for a given channel
549 * @setup_calibration: set up calibration
550 * @iscal_supported: used to query if a type of calibration is supported
551 *
552 * @ani_cache_ini_regs: cache the values for ANI from the initial
553 * register settings through the register initialization.
554 */
555 struct ath_hw_private_ops {
556 /* Calibration ops */
557 void (*init_cal_settings)(struct ath_hw *ah);
558 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
559
560 void (*init_mode_regs)(struct ath_hw *ah);
561 void (*init_mode_gain_regs)(struct ath_hw *ah);
562 void (*setup_calibration)(struct ath_hw *ah,
563 struct ath9k_cal_list *currCal);
564
565 /* PHY ops */
566 int (*rf_set_freq)(struct ath_hw *ah,
567 struct ath9k_channel *chan);
568 void (*spur_mitigate_freq)(struct ath_hw *ah,
569 struct ath9k_channel *chan);
570 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
571 void (*rf_free_ext_banks)(struct ath_hw *ah);
572 bool (*set_rf_regs)(struct ath_hw *ah,
573 struct ath9k_channel *chan,
574 u16 modesIndex);
575 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
576 void (*init_bb)(struct ath_hw *ah,
577 struct ath9k_channel *chan);
578 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
579 void (*olc_init)(struct ath_hw *ah);
580 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
581 void (*mark_phy_inactive)(struct ath_hw *ah);
582 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
583 bool (*rfbus_req)(struct ath_hw *ah);
584 void (*rfbus_done)(struct ath_hw *ah);
585 void (*restore_chainmask)(struct ath_hw *ah);
586 void (*set_diversity)(struct ath_hw *ah, bool value);
587 u32 (*compute_pll_control)(struct ath_hw *ah,
588 struct ath9k_channel *chan);
589 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
590 int param);
591 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
592 void (*set_radar_params)(struct ath_hw *ah,
593 struct ath_hw_radar_conf *conf);
594
595 /* ANI */
596 void (*ani_cache_ini_regs)(struct ath_hw *ah);
597 };
598
599 /**
600 * struct ath_hw_ops - callbacks used by hardware code and driver code
601 *
602 * This structure contains callbacks designed to to be used internally by
603 * hardware code and also by the lower level driver.
604 *
605 * @config_pci_powersave:
606 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
607 */
608 struct ath_hw_ops {
609 void (*config_pci_powersave)(struct ath_hw *ah,
610 bool power_off);
611 void (*rx_enable)(struct ath_hw *ah);
612 void (*set_desc_link)(void *ds, u32 link);
613 bool (*calibrate)(struct ath_hw *ah,
614 struct ath9k_channel *chan,
615 u8 rxchainmask,
616 bool longcal);
617 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
618 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
619 bool is_firstseg, bool is_is_lastseg,
620 const void *ds0, dma_addr_t buf_addr,
621 unsigned int qcu);
622 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
623 struct ath_tx_status *ts);
624 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
625 u32 pktLen, enum ath9k_pkt_type type,
626 u32 txPower, u8 keyIx,
627 enum ath9k_key_type keyType,
628 u32 flags);
629 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
630 void *lastds,
631 u32 durUpdateEn, u32 rtsctsRate,
632 u32 rtsctsDuration,
633 struct ath9k_11n_rate_series series[],
634 u32 nseries, u32 flags);
635 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
636 u32 aggrLen);
637 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
638 u32 numDelims);
639 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
640 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
641 void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
642 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
643 struct ath_hw_antcomb_conf *antconf);
644 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
645 struct ath_hw_antcomb_conf *antconf);
646
647 };
648
649 struct ath_nf_limits {
650 s16 max;
651 s16 min;
652 s16 nominal;
653 };
654
655 /* ah_flags */
656 #define AH_USE_EEPROM 0x1
657 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
658
659 struct ath_hw {
660 struct ath_ops reg_ops;
661
662 struct ieee80211_hw *hw;
663 struct ath_common common;
664 struct ath9k_hw_version hw_version;
665 struct ath9k_ops_config config;
666 struct ath9k_hw_capabilities caps;
667 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
668 struct ath9k_channel *curchan;
669
670 union {
671 struct ar5416_eeprom_def def;
672 struct ar5416_eeprom_4k map4k;
673 struct ar9287_eeprom map9287;
674 struct ar9300_eeprom ar9300_eep;
675 } eeprom;
676 const struct eeprom_ops *eep_ops;
677
678 bool sw_mgmt_crypto;
679 bool is_pciexpress;
680 bool aspm_enabled;
681 bool is_monitoring;
682 bool need_an_top2_fixup;
683 u16 tx_trig_level;
684
685 u32 nf_regs[6];
686 struct ath_nf_limits nf_2g;
687 struct ath_nf_limits nf_5g;
688 u16 rfsilent;
689 u32 rfkill_gpio;
690 u32 rfkill_polarity;
691 u32 ah_flags;
692
693 bool htc_reset_init;
694
695 enum nl80211_iftype opmode;
696 enum ath9k_power_mode power_mode;
697
698 s8 noise;
699 struct ath9k_hw_cal_data *caldata;
700 struct ath9k_pacal_info pacal_info;
701 struct ar5416Stats stats;
702 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
703
704 int16_t curchan_rad_index;
705 enum ath9k_int imask;
706 u32 imrs2_reg;
707 u32 txok_interrupt_mask;
708 u32 txerr_interrupt_mask;
709 u32 txdesc_interrupt_mask;
710 u32 txeol_interrupt_mask;
711 u32 txurn_interrupt_mask;
712 atomic_t intr_ref_cnt;
713 bool chip_fullsleep;
714 u32 atim_window;
715
716 /* Calibration */
717 u32 supp_cals;
718 struct ath9k_cal_list iq_caldata;
719 struct ath9k_cal_list adcgain_caldata;
720 struct ath9k_cal_list adcdc_caldata;
721 struct ath9k_cal_list tempCompCalData;
722 struct ath9k_cal_list *cal_list;
723 struct ath9k_cal_list *cal_list_last;
724 struct ath9k_cal_list *cal_list_curr;
725 #define totalPowerMeasI meas0.unsign
726 #define totalPowerMeasQ meas1.unsign
727 #define totalIqCorrMeas meas2.sign
728 #define totalAdcIOddPhase meas0.unsign
729 #define totalAdcIEvenPhase meas1.unsign
730 #define totalAdcQOddPhase meas2.unsign
731 #define totalAdcQEvenPhase meas3.unsign
732 #define totalAdcDcOffsetIOddPhase meas0.sign
733 #define totalAdcDcOffsetIEvenPhase meas1.sign
734 #define totalAdcDcOffsetQOddPhase meas2.sign
735 #define totalAdcDcOffsetQEvenPhase meas3.sign
736 union {
737 u32 unsign[AR5416_MAX_CHAINS];
738 int32_t sign[AR5416_MAX_CHAINS];
739 } meas0;
740 union {
741 u32 unsign[AR5416_MAX_CHAINS];
742 int32_t sign[AR5416_MAX_CHAINS];
743 } meas1;
744 union {
745 u32 unsign[AR5416_MAX_CHAINS];
746 int32_t sign[AR5416_MAX_CHAINS];
747 } meas2;
748 union {
749 u32 unsign[AR5416_MAX_CHAINS];
750 int32_t sign[AR5416_MAX_CHAINS];
751 } meas3;
752 u16 cal_samples;
753
754 u32 sta_id1_defaults;
755 u32 misc_mode;
756 enum {
757 AUTO_32KHZ,
758 USE_32KHZ,
759 DONT_USE_32KHZ,
760 } enable_32kHz_clock;
761
762 /* Private to hardware code */
763 struct ath_hw_private_ops private_ops;
764 /* Accessed by the lower level driver */
765 struct ath_hw_ops ops;
766
767 /* Used to program the radio on non single-chip devices */
768 u32 *analogBank0Data;
769 u32 *analogBank1Data;
770 u32 *analogBank2Data;
771 u32 *analogBank3Data;
772 u32 *analogBank6Data;
773 u32 *analogBank6TPCData;
774 u32 *analogBank7Data;
775 u32 *addac5416_21;
776 u32 *bank6Temp;
777
778 u8 txpower_limit;
779 int coverage_class;
780 u32 slottime;
781 u32 globaltxtimeout;
782
783 /* ANI */
784 u32 proc_phyerr;
785 u32 aniperiod;
786 int totalSizeDesired[5];
787 int coarse_high[5];
788 int coarse_low[5];
789 int firpwr[5];
790 enum ath9k_ani_cmd ani_function;
791
792 /* Bluetooth coexistance */
793 struct ath_btcoex_hw btcoex_hw;
794 u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS];
795 u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS];
796
797 u32 intr_txqs;
798 u8 txchainmask;
799 u8 rxchainmask;
800
801 struct ath_hw_radar_conf radar_conf;
802
803 u32 originalGain[22];
804 int initPDADC;
805 int PDADCdelta;
806 int led_pin;
807 u32 gpio_mask;
808 u32 gpio_val;
809
810 struct ar5416IniArray iniModes;
811 struct ar5416IniArray iniCommon;
812 struct ar5416IniArray iniBank0;
813 struct ar5416IniArray iniBB_RfGain;
814 struct ar5416IniArray iniBank1;
815 struct ar5416IniArray iniBank2;
816 struct ar5416IniArray iniBank3;
817 struct ar5416IniArray iniBank6;
818 struct ar5416IniArray iniBank6TPC;
819 struct ar5416IniArray iniBank7;
820 struct ar5416IniArray iniAddac;
821 struct ar5416IniArray iniPcieSerdes;
822 struct ar5416IniArray iniPcieSerdesLowPower;
823 struct ar5416IniArray iniModesAdditional;
824 struct ar5416IniArray iniModesAdditional_40M;
825 struct ar5416IniArray iniModesRxGain;
826 struct ar5416IniArray iniModesTxGain;
827 struct ar5416IniArray iniModes_9271_1_0_only;
828 struct ar5416IniArray iniCckfirNormal;
829 struct ar5416IniArray iniCckfirJapan2484;
830 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
831 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
832 struct ar5416IniArray iniModes_9271_ANI_reg;
833 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
834 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
835
836 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
837 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
838 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
839 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
840
841 u32 intr_gen_timer_trigger;
842 u32 intr_gen_timer_thresh;
843 struct ath_gen_timer_table hw_gen_timers;
844
845 struct ar9003_txs *ts_ring;
846 void *ts_start;
847 u32 ts_paddr_start;
848 u32 ts_paddr_end;
849 u16 ts_tail;
850 u8 ts_size;
851
852 u32 bb_watchdog_last_status;
853 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
854 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
855
856 unsigned int paprd_target_power;
857 unsigned int paprd_training_power;
858 unsigned int paprd_ratemask;
859 unsigned int paprd_ratemask_ht40;
860 bool paprd_table_write_done;
861 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
862 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
863 /*
864 * Store the permanent value of Reg 0x4004in WARegVal
865 * so we dont have to R/M/W. We should not be reading
866 * this register when in sleep states.
867 */
868 u32 WARegVal;
869
870 /* Enterprise mode cap */
871 u32 ent_mode;
872
873 bool is_clk_25mhz;
874 int (*get_mac_revision)(void);
875 int (*external_reset)(void);
876 };
877
878 struct ath_bus_ops {
879 enum ath_bus_type ath_bus_type;
880 void (*read_cachesize)(struct ath_common *common, int *csz);
881 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
882 void (*bt_coex_prep)(struct ath_common *common);
883 void (*extn_synch_en)(struct ath_common *common);
884 void (*aspm_init)(struct ath_common *common);
885 };
886
887 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
888 {
889 return &ah->common;
890 }
891
892 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
893 {
894 return &(ath9k_hw_common(ah)->regulatory);
895 }
896
897 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
898 {
899 return &ah->private_ops;
900 }
901
902 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
903 {
904 return &ah->ops;
905 }
906
907 static inline u8 get_streams(int mask)
908 {
909 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
910 }
911
912 /* Initialization, Detach, Reset */
913 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
914 void ath9k_hw_deinit(struct ath_hw *ah);
915 int ath9k_hw_init(struct ath_hw *ah);
916 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
917 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
918 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
919 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
920
921 /* GPIO / RFKILL / Antennae */
922 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
923 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
924 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
925 u32 ah_signal_type);
926 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
927 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
928 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
929
930 /* General Operation */
931 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
932 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
933 int column, unsigned int *writecnt);
934 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
935 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
936 u8 phy, int kbps,
937 u32 frameLen, u16 rateix, bool shortPreamble);
938 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
939 struct ath9k_channel *chan,
940 struct chan_centers *centers);
941 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
942 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
943 bool ath9k_hw_phy_disable(struct ath_hw *ah);
944 bool ath9k_hw_disable(struct ath_hw *ah);
945 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
946 void ath9k_hw_setopmode(struct ath_hw *ah);
947 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
948 void ath9k_hw_setbssidmask(struct ath_hw *ah);
949 void ath9k_hw_write_associd(struct ath_hw *ah);
950 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
951 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
952 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
953 void ath9k_hw_reset_tsf(struct ath_hw *ah);
954 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
955 void ath9k_hw_init_global_settings(struct ath_hw *ah);
956 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
957 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
958 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
959 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
960 const struct ath9k_beacon_state *bs);
961 bool ath9k_hw_check_alive(struct ath_hw *ah);
962
963 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
964
965 /* Generic hw timer primitives */
966 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
967 void (*trigger)(void *),
968 void (*overflow)(void *),
969 void *arg,
970 u8 timer_index);
971 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
972 struct ath_gen_timer *timer,
973 u32 timer_next,
974 u32 timer_period);
975 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
976
977 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
978 void ath_gen_timer_isr(struct ath_hw *hw);
979
980 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
981
982 /* HTC */
983 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
984
985 /* PHY */
986 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
987 u32 *coef_mantissa, u32 *coef_exponent);
988
989 /*
990 * Code Specific to AR5008, AR9001 or AR9002,
991 * we stuff these here to avoid callbacks for AR9003.
992 */
993 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
994 int ar9002_hw_rf_claim(struct ath_hw *ah);
995 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
996
997 /*
998 * Code specific to AR9003, we stuff these here to avoid callbacks
999 * for older families
1000 */
1001 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1002 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1003 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1004 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1005 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1006 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1007 struct ath9k_hw_cal_data *caldata,
1008 int chain);
1009 int ar9003_paprd_create_curve(struct ath_hw *ah,
1010 struct ath9k_hw_cal_data *caldata, int chain);
1011 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1012 int ar9003_paprd_init_table(struct ath_hw *ah);
1013 bool ar9003_paprd_is_done(struct ath_hw *ah);
1014 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
1015
1016 /* Hardware family op attach helpers */
1017 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1018 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1019 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1020
1021 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1022 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1023
1024 void ar9002_hw_attach_ops(struct ath_hw *ah);
1025 void ar9003_hw_attach_ops(struct ath_hw *ah);
1026
1027 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1028 /*
1029 * ANI work can be shared between all families but a next
1030 * generation implementation of ANI will be used only for AR9003 only
1031 * for now as the other families still need to be tested with the same
1032 * next generation ANI. Feel free to start testing it though for the
1033 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1034 */
1035 extern int modparam_force_new_ani;
1036 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1037 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1038 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1039
1040 #define ATH9K_CLOCK_RATE_CCK 22
1041 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1042 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1043 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1044
1045 #endif
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree