drivers/scsi/ipr.h

   1 /*
   2  * ipr.h -- driver for IBM Power Linux RAID adapters
   3  *
   4  * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
   5  *
   6  * Copyright (C) 2003, 2004 IBM Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  *
  22  * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
  23  *                              that broke 64bit platforms.
  24  */
  25
  26 #ifndef _IPR_H
  27 #define _IPR_H
  28
  29 #include <asm/unaligned.h>
  30 #include <linux/types.h>
  31 #include <linux/completion.h>
  32 #include <linux/libata.h>
  33 #include <linux/list.h>
  34 #include <linux/kref.h>
  35 #include <scsi/scsi.h>
  36 #include <scsi/scsi_cmnd.h>
  37
  38 /*
  39  * Literals
  40  */
  41 #define IPR_DRIVER_VERSION "2.5.1"
  42 #define IPR_DRIVER_DATE "(August 10, 2010)"
  43
  44 /*
  45  * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
  46  *      ops per device for devices not running tagged command queuing.
  47  *      This can be adjusted at runtime through sysfs device attributes.
  48  */
  49 #define IPR_MAX_CMD_PER_LUN                             6
  50 #define IPR_MAX_CMD_PER_ATA_LUN                 1
  51
  52 /*
  53  * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
  54  *      ops the mid-layer can send to the adapter.
  55  */
  56 #define IPR_NUM_BASE_CMD_BLKS                           100
  57
  58 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E    0x0339
  59
  60 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2          0x033D
  61 #define PCI_DEVICE_ID_IBM_CROC_ASIC_E2          0x034A
  62
  63 #define IPR_SUBS_DEV_ID_2780    0x0264
  64 #define IPR_SUBS_DEV_ID_5702    0x0266
  65 #define IPR_SUBS_DEV_ID_5703    0x0278
  66 #define IPR_SUBS_DEV_ID_572E    0x028D
  67 #define IPR_SUBS_DEV_ID_573E    0x02D3
  68 #define IPR_SUBS_DEV_ID_573D    0x02D4
  69 #define IPR_SUBS_DEV_ID_571A    0x02C0
  70 #define IPR_SUBS_DEV_ID_571B    0x02BE
  71 #define IPR_SUBS_DEV_ID_571E    0x02BF
  72 #define IPR_SUBS_DEV_ID_571F    0x02D5
  73 #define IPR_SUBS_DEV_ID_572A    0x02C1
  74 #define IPR_SUBS_DEV_ID_572B    0x02C2
  75 #define IPR_SUBS_DEV_ID_572F    0x02C3
  76 #define IPR_SUBS_DEV_ID_574E    0x030A
  77 #define IPR_SUBS_DEV_ID_575B    0x030D
  78 #define IPR_SUBS_DEV_ID_575C    0x0338
  79 #define IPR_SUBS_DEV_ID_57B3    0x033A
  80 #define IPR_SUBS_DEV_ID_57B7    0x0360
  81 #define IPR_SUBS_DEV_ID_57B8    0x02C2
  82
  83 #define IPR_SUBS_DEV_ID_57B4    0x033B
  84 #define IPR_SUBS_DEV_ID_57B2    0x035F
  85 #define IPR_SUBS_DEV_ID_57C6    0x0357
  86 #define IPR_SUBS_DEV_ID_57CC    0x035C
  87
  88 #define IPR_SUBS_DEV_ID_57B5    0x033C
  89 #define IPR_SUBS_DEV_ID_57CE    0x035E
  90 #define IPR_SUBS_DEV_ID_57B1    0x0355
  91
  92 #define IPR_SUBS_DEV_ID_574D    0x0356
  93 #define IPR_SUBS_DEV_ID_575D    0x035D
  94
  95 #define IPR_NAME                                "ipr"
  96
  97 /*
  98  * Return codes
  99  */
 100 #define IPR_RC_JOB_CONTINUE             1
 101 #define IPR_RC_JOB_RETURN               2
 102
 103 /*
 104  * IOASCs
 105  */
 106 #define IPR_IOASC_NR_INIT_CMD_REQUIRED          0x02040200
 107 #define IPR_IOASC_NR_IOA_RESET_REQUIRED         0x02048000
 108 #define IPR_IOASC_SYNC_REQUIRED                 0x023f0000
 109 #define IPR_IOASC_MED_DO_NOT_REALLOC            0x03110C00
 110 #define IPR_IOASC_HW_SEL_TIMEOUT                        0x04050000
 111 #define IPR_IOASC_HW_DEV_BUS_STATUS                     0x04448500
 112 #define IPR_IOASC_IOASC_MASK                    0xFFFFFF00
 113 #define IPR_IOASC_SCSI_STATUS_MASK              0x000000FF
 114 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT    0x05240000
 115 #define IPR_IOASC_IR_RESOURCE_HANDLE            0x05250000
 116 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA         0x05258100
 117 #define IPR_IOASA_IR_DUAL_IOA_DISABLED          0x052C8000
 118 #define IPR_IOASC_BUS_WAS_RESET                 0x06290000
 119 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER                0x06298000
 120 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST      0x0B5A0000
 121
 122 #define IPR_FIRST_DRIVER_IOASC                  0x10000000
 123 #define IPR_IOASC_IOA_WAS_RESET                 0x10000001
 124 #define IPR_IOASC_PCI_ACCESS_ERROR                      0x10000002
 125
 126 /* Driver data flags */
 127 #define IPR_USE_LONG_TRANSOP_TIMEOUT            0x00000001
 128 #define IPR_USE_PCI_WARM_RESET                  0x00000002
 129
 130 #define IPR_DEFAULT_MAX_ERROR_DUMP                      984
 131 #define IPR_NUM_LOG_HCAMS                               2
 132 #define IPR_NUM_CFG_CHG_HCAMS                           2
 133 #define IPR_NUM_HCAMS   (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
 134
 135 #define IPR_MAX_SIS64_TARGETS_PER_BUS                   1024
 136 #define IPR_MAX_SIS64_LUNS_PER_TARGET                   0xffffffff
 137
 138 #define IPR_MAX_NUM_TARGETS_PER_BUS                     256
 139 #define IPR_MAX_NUM_LUNS_PER_TARGET                     256
 140 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET        8
 141 #define IPR_VSET_BUS                                    0xff
 142 #define IPR_IOA_BUS                                             0xff
 143 #define IPR_IOA_TARGET                                  0xff
 144 #define IPR_IOA_LUN                                             0xff
 145 #define IPR_MAX_NUM_BUSES                               16
 146 #define IPR_MAX_BUS_TO_SCAN                             IPR_MAX_NUM_BUSES
 147
 148 #define IPR_NUM_RESET_RELOAD_RETRIES            3
 149
 150 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
 151 #define IPR_NUM_INTERNAL_CMD_BLKS       (IPR_NUM_HCAMS + \
 152                                      ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
 153
 154 #define IPR_MAX_COMMANDS                IPR_NUM_BASE_CMD_BLKS
 155 #define IPR_NUM_CMD_BLKS                (IPR_NUM_BASE_CMD_BLKS + \
 156                                                 IPR_NUM_INTERNAL_CMD_BLKS)
 157
 158 #define IPR_MAX_PHYSICAL_DEVS                           192
 159 #define IPR_DEFAULT_SIS64_DEVS                          1024
 160 #define IPR_MAX_SIS64_DEVS                              4096
 161
 162 #define IPR_MAX_SGLIST                                  64
 163 #define IPR_IOA_MAX_SECTORS                             32767
 164 #define IPR_VSET_MAX_SECTORS                            512
 165 #define IPR_MAX_CDB_LEN                                 16
 166 #define IPR_MAX_HRRQ_RETRIES                            3
 167
 168 #define IPR_DEFAULT_BUS_WIDTH                           16
 169 #define IPR_80MBs_SCSI_RATE             ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 170 #define IPR_U160_SCSI_RATE      ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 171 #define IPR_U320_SCSI_RATE      ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
 172 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
 173
 174 #define IPR_IOA_RES_HANDLE                              0xffffffff
 175 #define IPR_INVALID_RES_HANDLE                  0
 176 #define IPR_IOA_RES_ADDR                                0x00ffffff
 177
 178 /*
 179  * Adapter Commands
 180  */
 181 #define IPR_QUERY_RSRC_STATE                            0xC2
 182 #define IPR_RESET_DEVICE                                0xC3
 183 #define IPR_RESET_TYPE_SELECT                           0x80
 184 #define IPR_LUN_RESET                                   0x40
 185 #define IPR_TARGET_RESET                                        0x20
 186 #define IPR_BUS_RESET                                   0x10
 187 #define IPR_ATA_PHY_RESET                                       0x80
 188 #define IPR_ID_HOST_RR_Q                                0xC4
 189 #define IPR_QUERY_IOA_CONFIG                            0xC5
 190 #define IPR_CANCEL_ALL_REQUESTS                 0xCE
 191 #define IPR_HOST_CONTROLLED_ASYNC                       0xCF
 192 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE      0x01
 193 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA           0x02
 194 #define IPR_SET_SUPPORTED_DEVICES                       0xFB
 195 #define IPR_SET_ALL_SUPPORTED_DEVICES                   0x80
 196 #define IPR_IOA_SHUTDOWN                                0xF7
 197 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE                    0x05
 198
 199 /*
 200  * Timeouts
 201  */
 202 #define IPR_SHUTDOWN_TIMEOUT                    (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
 203 #define IPR_VSET_RW_TIMEOUT                     (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
 204 #define IPR_ABBREV_SHUTDOWN_TIMEOUT             (10 * HZ)
 205 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO   (2 * 60 * HZ)
 206 #define IPR_DEVICE_RESET_TIMEOUT                (ipr_fastfail ? 10 * HZ : 30 * HZ)
 207 #define IPR_CANCEL_ALL_TIMEOUT          (ipr_fastfail ? 10 * HZ : 30 * HZ)
 208 #define IPR_ABORT_TASK_TIMEOUT          (ipr_fastfail ? 10 * HZ : 30 * HZ)
 209 #define IPR_INTERNAL_TIMEOUT                    (ipr_fastfail ? 10 * HZ : 30 * HZ)
 210 #define IPR_WRITE_BUFFER_TIMEOUT                (10 * 60 * HZ)
 211 #define IPR_SET_SUP_DEVICE_TIMEOUT              (2 * 60 * HZ)
 212 #define IPR_REQUEST_SENSE_TIMEOUT               (10 * HZ)
 213 #define IPR_OPERATIONAL_TIMEOUT         (5 * 60)
 214 #define IPR_LONG_OPERATIONAL_TIMEOUT    (12 * 60)
 215 #define IPR_WAIT_FOR_RESET_TIMEOUT              (2 * HZ)
 216 #define IPR_CHECK_FOR_RESET_TIMEOUT             (HZ / 10)
 217 #define IPR_WAIT_FOR_BIST_TIMEOUT               (2 * HZ)
 218 #define IPR_PCI_RESET_TIMEOUT                   (HZ / 2)
 219 #define IPR_DUMP_TIMEOUT                        (15 * HZ)
 220
 221 /*
 222  * SCSI Literals
 223  */
 224 #define IPR_VENDOR_ID_LEN                       8
 225 #define IPR_PROD_ID_LEN                         16
 226 #define IPR_SERIAL_NUM_LEN                      8
 227
 228 /*
 229  * Hardware literals
 230  */
 231 #define IPR_FMT2_MBX_ADDR_MASK                          0x0fffffff
 232 #define IPR_FMT2_MBX_BAR_SEL_MASK                       0xf0000000
 233 #define IPR_FMT2_MKR_BAR_SEL_SHIFT                      28
 234 #define IPR_GET_FMT2_BAR_SEL(mbx) \
 235 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
 236 #define IPR_SDT_FMT2_BAR0_SEL                           0x0
 237 #define IPR_SDT_FMT2_BAR1_SEL                           0x1
 238 #define IPR_SDT_FMT2_BAR2_SEL                           0x2
 239 #define IPR_SDT_FMT2_BAR3_SEL                           0x3
 240 #define IPR_SDT_FMT2_BAR4_SEL                           0x4
 241 #define IPR_SDT_FMT2_BAR5_SEL                           0x5
 242 #define IPR_SDT_FMT2_EXP_ROM_SEL                        0x8
 243 #define IPR_FMT2_SDT_READY_TO_USE                       0xC4D4E3F2
 244 #define IPR_FMT3_SDT_READY_TO_USE                       0xC4D4E3F3
 245 #define IPR_DOORBELL                                    0x82800000
 246 #define IPR_RUNTIME_RESET                               0x40000000
 247
 248 #define IPR_IPL_INIT_MIN_STAGE_TIME                     5
 249 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME                 15
 250 #define IPR_IPL_INIT_STAGE_UNKNOWN                      0x0
 251 #define IPR_IPL_INIT_STAGE_TRANSOP                      0xB0000000
 252 #define IPR_IPL_INIT_STAGE_MASK                         0xff000000
 253 #define IPR_IPL_INIT_STAGE_TIME_MASK                    0x0000ffff
 254 #define IPR_PCII_IPL_STAGE_CHANGE                       (0x80000000 >> 0)
 255
 256 #define IPR_PCII_IOA_TRANS_TO_OPER                      (0x80000000 >> 0)
 257 #define IPR_PCII_IOARCB_XFER_FAILED                     (0x80000000 >> 3)
 258 #define IPR_PCII_IOA_UNIT_CHECKED                       (0x80000000 >> 4)
 259 #define IPR_PCII_NO_HOST_RRQ                            (0x80000000 >> 5)
 260 #define IPR_PCII_CRITICAL_OPERATION                     (0x80000000 >> 6)
 261 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE           (0x80000000 >> 7)
 262 #define IPR_PCII_IOARRIN_LOST                           (0x80000000 >> 27)
 263 #define IPR_PCII_MMIO_ERROR                             (0x80000000 >> 28)
 264 #define IPR_PCII_PROC_ERR_STATE                 (0x80000000 >> 29)
 265 #define IPR_PCII_HRRQ_UPDATED                           (0x80000000 >> 30)
 266 #define IPR_PCII_CORE_ISSUED_RST_REQ            (0x80000000 >> 31)
 267
 268 #define IPR_PCII_ERROR_INTERRUPTS \
 269 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
 270 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
 271
 272 #define IPR_PCII_OPER_INTERRUPTS \
 273 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
 274
 275 #define IPR_UPROCI_RESET_ALERT                  (0x80000000 >> 7)
 276 #define IPR_UPROCI_IO_DEBUG_ALERT                       (0x80000000 >> 9)
 277 #define IPR_UPROCI_SIS64_START_BIST                     (0x80000000 >> 23)
 278
 279 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC            200000  /* 200 ms */
 280 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC           200000  /* 200 ms */
 281
 282 /*
 283  * Dump literals
 284  */
 285 #define IPR_MAX_IOA_DUMP_SIZE                           (4 * 1024 * 1024)
 286 #define IPR_NUM_SDT_ENTRIES                             511
 287 #define IPR_MAX_NUM_DUMP_PAGES  ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
 288
 289 /*
 290  * Misc literals
 291  */
 292 #define IPR_NUM_IOADL_ENTRIES                   IPR_MAX_SGLIST
 293
 294 /*
 295  * Adapter interface types
 296  */
 297
 298 struct ipr_res_addr {
 299         u8 reserved;
 300         u8 bus;
 301         u8 target;
 302         u8 lun;
 303 #define IPR_GET_PHYS_LOC(res_addr) \
 304         (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
 305 }__attribute__((packed, aligned (4)));
 306
 307 struct ipr_std_inq_vpids {
 308         u8 vendor_id[IPR_VENDOR_ID_LEN];
 309         u8 product_id[IPR_PROD_ID_LEN];
 310 }__attribute__((packed));
 311
 312 struct ipr_vpd {
 313         struct ipr_std_inq_vpids vpids;
 314         u8 sn[IPR_SERIAL_NUM_LEN];
 315 }__attribute__((packed));
 316
 317 struct ipr_ext_vpd {
 318         struct ipr_vpd vpd;
 319         __be32 wwid[2];
 320 }__attribute__((packed));
 321
 322 struct ipr_ext_vpd64 {
 323         struct ipr_vpd vpd;
 324         __be32 wwid[4];
 325 }__attribute__((packed));
 326
 327 struct ipr_std_inq_data {
 328         u8 peri_qual_dev_type;
 329 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
 330 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
 331
 332         u8 removeable_medium_rsvd;
 333 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
 334
 335 #define IPR_IS_DASD_DEVICE(std_inq) \
 336 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
 337 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
 338
 339 #define IPR_IS_SES_DEVICE(std_inq) \
 340 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
 341
 342         u8 version;
 343         u8 aen_naca_fmt;
 344         u8 additional_len;
 345         u8 sccs_rsvd;
 346         u8 bq_enc_multi;
 347         u8 sync_cmdq_flags;
 348
 349         struct ipr_std_inq_vpids vpids;
 350
 351         u8 ros_rsvd_ram_rsvd[4];
 352
 353         u8 serial_num[IPR_SERIAL_NUM_LEN];
 354 }__attribute__ ((packed));
 355
 356 #define IPR_RES_TYPE_AF_DASD            0x00
 357 #define IPR_RES_TYPE_GENERIC_SCSI       0x01
 358 #define IPR_RES_TYPE_VOLUME_SET         0x02
 359 #define IPR_RES_TYPE_REMOTE_AF_DASD     0x03
 360 #define IPR_RES_TYPE_GENERIC_ATA        0x04
 361 #define IPR_RES_TYPE_ARRAY              0x05
 362 #define IPR_RES_TYPE_IOAFP              0xff
 363
 364 struct ipr_config_table_entry {
 365         u8 proto;
 366 #define IPR_PROTO_SATA                  0x02
 367 #define IPR_PROTO_SATA_ATAPI            0x03
 368 #define IPR_PROTO_SAS_STP               0x06
 369 #define IPR_PROTO_SAS_STP_ATAPI         0x07
 370         u8 array_id;
 371         u8 flags;
 372 #define IPR_IS_IOA_RESOURCE             0x80
 373         u8 rsvd_subtype;
 374
 375 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
 376 #define IPR_QUEUE_FROZEN_MODEL          0
 377 #define IPR_QUEUE_NACA_MODEL            1
 378
 379         struct ipr_res_addr res_addr;
 380         __be32 res_handle;
 381         __be32 lun_wwn[2];
 382         struct ipr_std_inq_data std_inq_data;
 383 }__attribute__ ((packed, aligned (4)));
 384
 385 struct ipr_config_table_entry64 {
 386         u8 res_type;
 387         u8 proto;
 388         u8 vset_num;
 389         u8 array_id;
 390         __be16 flags;
 391         __be16 res_flags;
 392 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
 393         __be32 res_handle;
 394         u8 dev_id_type;
 395         u8 reserved[3];
 396         __be64 dev_id;
 397         __be64 lun;
 398         __be64 lun_wwn[2];
 399 #define IPR_MAX_RES_PATH_LENGTH         24
 400         __be64 res_path;
 401         struct ipr_std_inq_data std_inq_data;
 402         u8 reserved2[4];
 403         __be64 reserved3[2];
 404         u8 reserved4[8];
 405 }__attribute__ ((packed, aligned (8)));
 406
 407 struct ipr_config_table_hdr {
 408         u8 num_entries;
 409         u8 flags;
 410 #define IPR_UCODE_DOWNLOAD_REQ  0x10
 411         __be16 reserved;
 412 }__attribute__((packed, aligned (4)));
 413
 414 struct ipr_config_table_hdr64 {
 415         __be16 num_entries;
 416         __be16 reserved;
 417         u8 flags;
 418         u8 reserved2[11];
 419 }__attribute__((packed, aligned (4)));
 420
 421 struct ipr_config_table {
 422         struct ipr_config_table_hdr hdr;
 423         struct ipr_config_table_entry dev[0];
 424 }__attribute__((packed, aligned (4)));
 425
 426 struct ipr_config_table64 {
 427         struct ipr_config_table_hdr64 hdr64;
 428         struct ipr_config_table_entry64 dev[0];
 429 }__attribute__((packed, aligned (8)));
 430
 431 struct ipr_config_table_entry_wrapper {
 432         union {
 433                 struct ipr_config_table_entry *cfgte;
 434                 struct ipr_config_table_entry64 *cfgte64;
 435         } u;
 436 };
 437
 438 struct ipr_hostrcb_cfg_ch_not {
 439         union {
 440                 struct ipr_config_table_entry cfgte;
 441                 struct ipr_config_table_entry64 cfgte64;
 442         } u;
 443         u8 reserved[936];
 444 }__attribute__((packed, aligned (4)));
 445
 446 struct ipr_supported_device {
 447         __be16 data_length;
 448         u8 reserved;
 449         u8 num_records;
 450         struct ipr_std_inq_vpids vpids;
 451         u8 reserved2[16];
 452 }__attribute__((packed, aligned (4)));
 453
 454 /* Command packet structure */
 455 struct ipr_cmd_pkt {
 456         __be16 reserved;                /* Reserved by IOA */
 457         u8 request_type;
 458 #define IPR_RQTYPE_SCSICDB              0x00
 459 #define IPR_RQTYPE_IOACMD               0x01
 460 #define IPR_RQTYPE_HCAM                 0x02
 461 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
 462
 463         u8 reserved2;
 464
 465         u8 flags_hi;
 466 #define IPR_FLAGS_HI_WRITE_NOT_READ             0x80
 467 #define IPR_FLAGS_HI_NO_ULEN_CHK                0x20
 468 #define IPR_FLAGS_HI_SYNC_OVERRIDE              0x10
 469 #define IPR_FLAGS_HI_SYNC_COMPLETE              0x08
 470 #define IPR_FLAGS_HI_NO_LINK_DESC               0x04
 471
 472         u8 flags_lo;
 473 #define IPR_FLAGS_LO_ALIGNED_BFR                0x20
 474 #define IPR_FLAGS_LO_DELAY_AFTER_RST    0x10
 475 #define IPR_FLAGS_LO_UNTAGGED_TASK              0x00
 476 #define IPR_FLAGS_LO_SIMPLE_TASK                0x02
 477 #define IPR_FLAGS_LO_ORDERED_TASK               0x04
 478 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK             0x06
 479 #define IPR_FLAGS_LO_ACA_TASK                   0x08
 480
 481         u8 cdb[16];
 482         __be16 timeout;
 483 }__attribute__ ((packed, aligned(4)));
 484
 485 struct ipr_ioarcb_ata_regs {    /* 22 bytes */
 486         u8 flags;
 487 #define IPR_ATA_FLAG_PACKET_CMD                 0x80
 488 #define IPR_ATA_FLAG_XFER_TYPE_DMA                      0x40
 489 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION  0x20
 490         u8 reserved[3];
 491
 492         __be16 data;
 493         u8 feature;
 494         u8 nsect;
 495         u8 lbal;
 496         u8 lbam;
 497         u8 lbah;
 498         u8 device;
 499         u8 command;
 500         u8 reserved2[3];
 501         u8 hob_feature;
 502         u8 hob_nsect;
 503         u8 hob_lbal;
 504         u8 hob_lbam;
 505         u8 hob_lbah;
 506         u8 ctl;
 507 }__attribute__ ((packed, aligned(4)));
 508
 509 struct ipr_ioadl_desc {
 510         __be32 flags_and_data_len;
 511 #define IPR_IOADL_FLAGS_MASK            0xff000000
 512 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
 513 #define IPR_IOADL_DATA_LEN_MASK         0x00ffffff
 514 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
 515 #define IPR_IOADL_FLAGS_READ            0x48000000
 516 #define IPR_IOADL_FLAGS_READ_LAST       0x49000000
 517 #define IPR_IOADL_FLAGS_WRITE           0x68000000
 518 #define IPR_IOADL_FLAGS_WRITE_LAST      0x69000000
 519 #define IPR_IOADL_FLAGS_LAST            0x01000000
 520
 521         __be32 address;
 522 }__attribute__((packed, aligned (8)));
 523
 524 struct ipr_ioadl64_desc {
 525         __be32 flags;
 526         __be32 data_len;
 527         __be64 address;
 528 }__attribute__((packed, aligned (16)));
 529
 530 struct ipr_ata64_ioadl {
 531         struct ipr_ioarcb_ata_regs regs;
 532         u16 reserved[5];
 533         struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
 534 }__attribute__((packed, aligned (16)));
 535
 536 struct ipr_ioarcb_add_data {
 537         union {
 538                 struct ipr_ioarcb_ata_regs regs;
 539                 struct ipr_ioadl_desc ioadl[5];
 540                 __be32 add_cmd_parms[10];
 541         } u;
 542 }__attribute__ ((packed, aligned (4)));
 543
 544 struct ipr_ioarcb_sis64_add_addr_ecb {
 545         __be64 ioasa_host_pci_addr;
 546         __be64 data_ioadl_addr;
 547         __be64 reserved;
 548         __be32 ext_control_buf[4];
 549 }__attribute__((packed, aligned (8)));
 550
 551 /* IOA Request Control Block    128 bytes  */
 552 struct ipr_ioarcb {
 553         union {
 554                 __be32 ioarcb_host_pci_addr;
 555                 __be64 ioarcb_host_pci_addr64;
 556         } a;
 557         __be32 res_handle;
 558         __be32 host_response_handle;
 559         __be32 reserved1;
 560         __be32 reserved2;
 561         __be32 reserved3;
 562
 563         __be32 data_transfer_length;
 564         __be32 read_data_transfer_length;
 565         __be32 write_ioadl_addr;
 566         __be32 ioadl_len;
 567         __be32 read_ioadl_addr;
 568         __be32 read_ioadl_len;
 569
 570         __be32 ioasa_host_pci_addr;
 571         __be16 ioasa_len;
 572         __be16 reserved4;
 573
 574         struct ipr_cmd_pkt cmd_pkt;
 575
 576         __be16 add_cmd_parms_offset;
 577         __be16 add_cmd_parms_len;
 578
 579         union {
 580                 struct ipr_ioarcb_add_data add_data;
 581                 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
 582         } u;
 583
 584 }__attribute__((packed, aligned (4)));
 585
 586 struct ipr_ioasa_vset {
 587         __be32 failing_lba_hi;
 588         __be32 failing_lba_lo;
 589         __be32 reserved;
 590 }__attribute__((packed, aligned (4)));
 591
 592 struct ipr_ioasa_af_dasd {
 593         __be32 failing_lba;
 594         __be32 reserved[2];
 595 }__attribute__((packed, aligned (4)));
 596
 597 struct ipr_ioasa_gpdd {
 598         u8 end_state;
 599         u8 bus_phase;
 600         __be16 reserved;
 601         __be32 ioa_data[2];
 602 }__attribute__((packed, aligned (4)));
 603
 604 struct ipr_ioasa_gata {
 605         u8 error;
 606         u8 nsect;               /* Interrupt reason */
 607         u8 lbal;
 608         u8 lbam;
 609         u8 lbah;
 610         u8 device;
 611         u8 status;
 612         u8 alt_status;  /* ATA CTL */
 613         u8 hob_nsect;
 614         u8 hob_lbal;
 615         u8 hob_lbam;
 616         u8 hob_lbah;
 617 }__attribute__((packed, aligned (4)));
 618
 619 struct ipr_auto_sense {
 620         __be16 auto_sense_len;
 621         __be16 ioa_data_len;
 622         __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
 623 };
 624
 625 struct ipr_ioasa_hdr {
 626         __be32 ioasc;
 627 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
 628 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
 629 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
 630 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
 631
 632         __be16 ret_stat_len;    /* Length of the returned IOASA */
 633
 634         __be16 avail_stat_len;  /* Total Length of status available. */
 635
 636         __be32 residual_data_len;       /* number of bytes in the host data */
 637         /* buffers that were not used by the IOARCB command. */
 638
 639         __be32 ilid;
 640 #define IPR_NO_ILID                     0
 641 #define IPR_DRIVER_ILID         0xffffffff
 642
 643         __be32 fd_ioasc;
 644
 645         __be32 fd_phys_locator;
 646
 647         __be32 fd_res_handle;
 648
 649         __be32 ioasc_specific;  /* status code specific field */
 650 #define IPR_ADDITIONAL_STATUS_FMT               0x80000000
 651 #define IPR_AUTOSENSE_VALID                     0x40000000
 652 #define IPR_ATA_DEVICE_WAS_RESET                0x20000000
 653 #define IPR_IOASC_SPECIFIC_MASK         0x00ffffff
 654 #define IPR_FIELD_POINTER_VALID         (0x80000000 >> 8)
 655 #define IPR_FIELD_POINTER_MASK          0x0000ffff
 656
 657 }__attribute__((packed, aligned (4)));
 658
 659 struct ipr_ioasa {
 660         struct ipr_ioasa_hdr hdr;
 661
 662         union {
 663                 struct ipr_ioasa_vset vset;
 664                 struct ipr_ioasa_af_dasd dasd;
 665                 struct ipr_ioasa_gpdd gpdd;
 666                 struct ipr_ioasa_gata gata;
 667         } u;
 668
 669         struct ipr_auto_sense auto_sense;
 670 }__attribute__((packed, aligned (4)));
 671
 672 struct ipr_ioasa64 {
 673         struct ipr_ioasa_hdr hdr;
 674         u8 fd_res_path[8];
 675
 676         union {
 677                 struct ipr_ioasa_vset vset;
 678                 struct ipr_ioasa_af_dasd dasd;
 679                 struct ipr_ioasa_gpdd gpdd;
 680                 struct ipr_ioasa_gata gata;
 681         } u;
 682
 683         struct ipr_auto_sense auto_sense;
 684 }__attribute__((packed, aligned (4)));
 685
 686 struct ipr_mode_parm_hdr {
 687         u8 length;
 688         u8 medium_type;
 689         u8 device_spec_parms;
 690         u8 block_desc_len;
 691 }__attribute__((packed));
 692
 693 struct ipr_mode_pages {
 694         struct ipr_mode_parm_hdr hdr;
 695         u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
 696 }__attribute__((packed));
 697
 698 struct ipr_mode_page_hdr {
 699         u8 ps_page_code;
 700 #define IPR_MODE_PAGE_PS        0x80
 701 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
 702         u8 page_length;
 703 }__attribute__ ((packed));
 704
 705 struct ipr_dev_bus_entry {
 706         struct ipr_res_addr res_addr;
 707         u8 flags;
 708 #define IPR_SCSI_ATTR_ENABLE_QAS                        0x80
 709 #define IPR_SCSI_ATTR_DISABLE_QAS                       0x40
 710 #define IPR_SCSI_ATTR_QAS_MASK                          0xC0
 711 #define IPR_SCSI_ATTR_ENABLE_TM                         0x20
 712 #define IPR_SCSI_ATTR_NO_TERM_PWR                       0x10
 713 #define IPR_SCSI_ATTR_TM_SUPPORTED                      0x08
 714 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED     0x04
 715
 716         u8 scsi_id;
 717         u8 bus_width;
 718         u8 extended_reset_delay;
 719 #define IPR_EXTENDED_RESET_DELAY        7
 720
 721         __be32 max_xfer_rate;
 722
 723         u8 spinup_delay;
 724         u8 reserved3;
 725         __be16 reserved4;
 726 }__attribute__((packed, aligned (4)));
 727
 728 struct ipr_mode_page28 {
 729         struct ipr_mode_page_hdr hdr;
 730         u8 num_entries;
 731         u8 entry_length;
 732         struct ipr_dev_bus_entry bus[0];
 733 }__attribute__((packed));
 734
 735 struct ipr_mode_page24 {
 736         struct ipr_mode_page_hdr hdr;
 737         u8 flags;
 738 #define IPR_ENABLE_DUAL_IOA_AF 0x80
 739 }__attribute__((packed));
 740
 741 struct ipr_ioa_vpd {
 742         struct ipr_std_inq_data std_inq_data;
 743         u8 ascii_part_num[12];
 744         u8 reserved[40];
 745         u8 ascii_plant_code[4];
 746 }__attribute__((packed));
 747
 748 struct ipr_inquiry_page3 {
 749         u8 peri_qual_dev_type;
 750         u8 page_code;
 751         u8 reserved1;
 752         u8 page_length;
 753         u8 ascii_len;
 754         u8 reserved2[3];
 755         u8 load_id[4];
 756         u8 major_release;
 757         u8 card_type;
 758         u8 minor_release[2];
 759         u8 ptf_number[4];
 760         u8 patch_number[4];
 761 }__attribute__((packed));
 762
 763 struct ipr_inquiry_cap {
 764         u8 peri_qual_dev_type;
 765         u8 page_code;
 766         u8 reserved1;
 767         u8 page_length;
 768         u8 ascii_len;
 769         u8 reserved2;
 770         u8 sis_version[2];
 771         u8 cap;
 772 #define IPR_CAP_DUAL_IOA_RAID           0x80
 773         u8 reserved3[15];
 774 }__attribute__((packed));
 775
 776 #define IPR_INQUIRY_PAGE0_ENTRIES 20
 777 struct ipr_inquiry_page0 {
 778         u8 peri_qual_dev_type;
 779         u8 page_code;
 780         u8 reserved1;
 781         u8 len;
 782         u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
 783 }__attribute__((packed));
 784
 785 struct ipr_hostrcb_device_data_entry {
 786         struct ipr_vpd vpd;
 787         struct ipr_res_addr dev_res_addr;
 788         struct ipr_vpd new_vpd;
 789         struct ipr_vpd ioa_last_with_dev_vpd;
 790         struct ipr_vpd cfc_last_with_dev_vpd;
 791         __be32 ioa_data[5];
 792 }__attribute__((packed, aligned (4)));
 793
 794 struct ipr_hostrcb_device_data_entry_enhanced {
 795         struct ipr_ext_vpd vpd;
 796         u8 ccin[4];
 797         struct ipr_res_addr dev_res_addr;
 798         struct ipr_ext_vpd new_vpd;
 799         u8 new_ccin[4];
 800         struct ipr_ext_vpd ioa_last_with_dev_vpd;
 801         struct ipr_ext_vpd cfc_last_with_dev_vpd;
 802 }__attribute__((packed, aligned (4)));
 803
 804 struct ipr_hostrcb64_device_data_entry_enhanced {
 805         struct ipr_ext_vpd vpd;
 806         u8 ccin[4];
 807         u8 res_path[8];
 808         struct ipr_ext_vpd new_vpd;
 809         u8 new_ccin[4];
 810         struct ipr_ext_vpd ioa_last_with_dev_vpd;
 811         struct ipr_ext_vpd cfc_last_with_dev_vpd;
 812 }__attribute__((packed, aligned (4)));
 813
 814 struct ipr_hostrcb_array_data_entry {
 815         struct ipr_vpd vpd;
 816         struct ipr_res_addr expected_dev_res_addr;
 817         struct ipr_res_addr dev_res_addr;
 818 }__attribute__((packed, aligned (4)));
 819
 820 struct ipr_hostrcb64_array_data_entry {
 821         struct ipr_ext_vpd vpd;
 822         u8 ccin[4];
 823         u8 expected_res_path[8];
 824         u8 res_path[8];
 825 }__attribute__((packed, aligned (4)));
 826
 827 struct ipr_hostrcb_array_data_entry_enhanced {
 828         struct ipr_ext_vpd vpd;
 829         u8 ccin[4];
 830         struct ipr_res_addr expected_dev_res_addr;
 831         struct ipr_res_addr dev_res_addr;
 832 }__attribute__((packed, aligned (4)));
 833
 834 struct ipr_hostrcb_type_ff_error {
 835         __be32 ioa_data[758];
 836 }__attribute__((packed, aligned (4)));
 837
 838 struct ipr_hostrcb_type_01_error {
 839         __be32 seek_counter;
 840         __be32 read_counter;
 841         u8 sense_data[32];
 842         __be32 ioa_data[236];
 843 }__attribute__((packed, aligned (4)));
 844
 845 struct ipr_hostrcb_type_02_error {
 846         struct ipr_vpd ioa_vpd;
 847         struct ipr_vpd cfc_vpd;
 848         struct ipr_vpd ioa_last_attached_to_cfc_vpd;
 849         struct ipr_vpd cfc_last_attached_to_ioa_vpd;
 850         __be32 ioa_data[3];
 851 }__attribute__((packed, aligned (4)));
 852
 853 struct ipr_hostrcb_type_12_error {
 854         struct ipr_ext_vpd ioa_vpd;
 855         struct ipr_ext_vpd cfc_vpd;
 856         struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
 857         struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
 858         __be32 ioa_data[3];
 859 }__attribute__((packed, aligned (4)));
 860
 861 struct ipr_hostrcb_type_03_error {
 862         struct ipr_vpd ioa_vpd;
 863         struct ipr_vpd cfc_vpd;
 864         __be32 errors_detected;
 865         __be32 errors_logged;
 866         u8 ioa_data[12];
 867         struct ipr_hostrcb_device_data_entry dev[3];
 868 }__attribute__((packed, aligned (4)));
 869
 870 struct ipr_hostrcb_type_13_error {
 871         struct ipr_ext_vpd ioa_vpd;
 872         struct ipr_ext_vpd cfc_vpd;
 873         __be32 errors_detected;
 874         __be32 errors_logged;
 875         struct ipr_hostrcb_device_data_entry_enhanced dev[3];
 876 }__attribute__((packed, aligned (4)));
 877
 878 struct ipr_hostrcb_type_23_error {
 879         struct ipr_ext_vpd ioa_vpd;
 880         struct ipr_ext_vpd cfc_vpd;
 881         __be32 errors_detected;
 882         __be32 errors_logged;
 883         struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
 884 }__attribute__((packed, aligned (4)));
 885
 886 struct ipr_hostrcb_type_04_error {
 887         struct ipr_vpd ioa_vpd;
 888         struct ipr_vpd cfc_vpd;
 889         u8 ioa_data[12];
 890         struct ipr_hostrcb_array_data_entry array_member[10];
 891         __be32 exposed_mode_adn;
 892         __be32 array_id;
 893         struct ipr_vpd incomp_dev_vpd;
 894         __be32 ioa_data2;
 895         struct ipr_hostrcb_array_data_entry array_member2[8];
 896         struct ipr_res_addr last_func_vset_res_addr;
 897         u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
 898         u8 protection_level[8];
 899 }__attribute__((packed, aligned (4)));
 900
 901 struct ipr_hostrcb_type_14_error {
 902         struct ipr_ext_vpd ioa_vpd;
 903         struct ipr_ext_vpd cfc_vpd;
 904         __be32 exposed_mode_adn;
 905         __be32 array_id;
 906         struct ipr_res_addr last_func_vset_res_addr;
 907         u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
 908         u8 protection_level[8];
 909         __be32 num_entries;
 910         struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
 911 }__attribute__((packed, aligned (4)));
 912
 913 struct ipr_hostrcb_type_24_error {
 914         struct ipr_ext_vpd ioa_vpd;
 915         struct ipr_ext_vpd cfc_vpd;
 916         u8 reserved[2];
 917         u8 exposed_mode_adn;
 918 #define IPR_INVALID_ARRAY_DEV_NUM               0xff
 919         u8 array_id;
 920         u8 last_res_path[8];
 921         u8 protection_level[8];
 922         struct ipr_ext_vpd64 array_vpd;
 923         u8 description[16];
 924         u8 reserved2[3];
 925         u8 num_entries;
 926         struct ipr_hostrcb64_array_data_entry array_member[32];
 927 }__attribute__((packed, aligned (4)));
 928
 929 struct ipr_hostrcb_type_07_error {
 930         u8 failure_reason[64];
 931         struct ipr_vpd vpd;
 932         u32 data[222];
 933 }__attribute__((packed, aligned (4)));
 934
 935 struct ipr_hostrcb_type_17_error {
 936         u8 failure_reason[64];
 937         struct ipr_ext_vpd vpd;
 938         u32 data[476];
 939 }__attribute__((packed, aligned (4)));
 940
 941 struct ipr_hostrcb_config_element {
 942         u8 type_status;
 943 #define IPR_PATH_CFG_TYPE_MASK  0xF0
 944 #define IPR_PATH_CFG_NOT_EXIST  0x00
 945 #define IPR_PATH_CFG_IOA_PORT           0x10
 946 #define IPR_PATH_CFG_EXP_PORT           0x20
 947 #define IPR_PATH_CFG_DEVICE_PORT        0x30
 948 #define IPR_PATH_CFG_DEVICE_LUN 0x40
 949
 950 #define IPR_PATH_CFG_STATUS_MASK        0x0F
 951 #define IPR_PATH_CFG_NO_PROB            0x00
 952 #define IPR_PATH_CFG_DEGRADED           0x01
 953 #define IPR_PATH_CFG_FAILED             0x02
 954 #define IPR_PATH_CFG_SUSPECT            0x03
 955 #define IPR_PATH_NOT_DETECTED           0x04
 956 #define IPR_PATH_INCORRECT_CONN 0x05
 957
 958         u8 cascaded_expander;
 959         u8 phy;
 960         u8 link_rate;
 961 #define IPR_PHY_LINK_RATE_MASK  0x0F
 962
 963         __be32 wwid[2];
 964 }__attribute__((packed, aligned (4)));
 965
 966 struct ipr_hostrcb64_config_element {
 967         __be16 length;
 968         u8 descriptor_id;
 969 #define IPR_DESCRIPTOR_MASK             0xC0
 970 #define IPR_DESCRIPTOR_SIS64            0x00
 971
 972         u8 reserved;
 973         u8 type_status;
 974
 975         u8 reserved2[2];
 976         u8 link_rate;
 977
 978         u8 res_path[8];
 979         __be32 wwid[2];
 980 }__attribute__((packed, aligned (8)));
 981
 982 struct ipr_hostrcb_fabric_desc {
 983         __be16 length;
 984         u8 ioa_port;
 985         u8 cascaded_expander;
 986         u8 phy;
 987         u8 path_state;
 988 #define IPR_PATH_ACTIVE_MASK            0xC0
 989 #define IPR_PATH_NO_INFO                0x00
 990 #define IPR_PATH_ACTIVE                 0x40
 991 #define IPR_PATH_NOT_ACTIVE             0x80
 992
 993 #define IPR_PATH_STATE_MASK             0x0F
 994 #define IPR_PATH_STATE_NO_INFO  0x00
 995 #define IPR_PATH_HEALTHY                0x01
 996 #define IPR_PATH_DEGRADED               0x02
 997 #define IPR_PATH_FAILED                 0x03
 998
 999         __be16 num_entries;
1000         struct ipr_hostrcb_config_element elem[1];
1001 }__attribute__((packed, aligned (4)));
1002
1003 struct ipr_hostrcb64_fabric_desc {
1004         __be16 length;
1005         u8 descriptor_id;
1006
1007         u8 reserved[2];
1008         u8 path_state;
1009
1010         u8 reserved2[2];
1011         u8 res_path[8];
1012         u8 reserved3[6];
1013         __be16 num_entries;
1014         struct ipr_hostrcb64_config_element elem[1];
1015 }__attribute__((packed, aligned (8)));
1016
1017 #define for_each_fabric_cfg(fabric, cfg) \
1018                 for (cfg = (fabric)->elem; \
1019                         cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1020                         cfg++)
1021
1022 struct ipr_hostrcb_type_20_error {
1023         u8 failure_reason[64];
1024         u8 reserved[3];
1025         u8 num_entries;
1026         struct ipr_hostrcb_fabric_desc desc[1];
1027 }__attribute__((packed, aligned (4)));
1028
1029 struct ipr_hostrcb_type_30_error {
1030         u8 failure_reason[64];
1031         u8 reserved[3];
1032         u8 num_entries;
1033         struct ipr_hostrcb64_fabric_desc desc[1];
1034 }__attribute__((packed, aligned (4)));
1035
1036 struct ipr_hostrcb_error {
1037         __be32 fd_ioasc;
1038         struct ipr_res_addr fd_res_addr;
1039         __be32 fd_res_handle;
1040         __be32 prc;
1041         union {
1042                 struct ipr_hostrcb_type_ff_error type_ff_error;
1043                 struct ipr_hostrcb_type_01_error type_01_error;
1044                 struct ipr_hostrcb_type_02_error type_02_error;
1045                 struct ipr_hostrcb_type_03_error type_03_error;
1046                 struct ipr_hostrcb_type_04_error type_04_error;
1047                 struct ipr_hostrcb_type_07_error type_07_error;
1048                 struct ipr_hostrcb_type_12_error type_12_error;
1049                 struct ipr_hostrcb_type_13_error type_13_error;
1050                 struct ipr_hostrcb_type_14_error type_14_error;
1051                 struct ipr_hostrcb_type_17_error type_17_error;
1052                 struct ipr_hostrcb_type_20_error type_20_error;
1053         } u;
1054 }__attribute__((packed, aligned (4)));
1055
1056 struct ipr_hostrcb64_error {
1057         __be32 fd_ioasc;
1058         __be32 ioa_fw_level;
1059         __be32 fd_res_handle;
1060         __be32 prc;
1061         __be64 fd_dev_id;
1062         __be64 fd_lun;
1063         u8 fd_res_path[8];
1064         __be64 time_stamp;
1065         u8 reserved[16];
1066         union {
1067                 struct ipr_hostrcb_type_ff_error type_ff_error;
1068                 struct ipr_hostrcb_type_12_error type_12_error;
1069                 struct ipr_hostrcb_type_17_error type_17_error;
1070                 struct ipr_hostrcb_type_23_error type_23_error;
1071                 struct ipr_hostrcb_type_24_error type_24_error;
1072                 struct ipr_hostrcb_type_30_error type_30_error;
1073         } u;
1074 }__attribute__((packed, aligned (8)));
1075
1076 struct ipr_hostrcb_raw {
1077         __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1078 }__attribute__((packed, aligned (4)));
1079
1080 struct ipr_hcam {
1081         u8 op_code;
1082 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE                      0xE1
1083 #define IPR_HOST_RCB_OP_CODE_LOG_DATA                           0xE2
1084
1085         u8 notify_type;
1086 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED        0x00
1087 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY                       0x01
1088 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY                       0x02
1089 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY         0x10
1090 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY       0x11
1091
1092         u8 notifications_lost;
1093 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST                      0
1094 #define IPR_HOST_RCB_NOTIFICATIONS_LOST                         0x80
1095
1096         u8 flags;
1097 #define IPR_HOSTRCB_INTERNAL_OPER       0x80
1098 #define IPR_HOSTRCB_ERR_RESP_SENT       0x40
1099
1100         u8 overlay_id;
1101 #define IPR_HOST_RCB_OVERLAY_ID_1                               0x01
1102 #define IPR_HOST_RCB_OVERLAY_ID_2                               0x02
1103 #define IPR_HOST_RCB_OVERLAY_ID_3                               0x03
1104 #define IPR_HOST_RCB_OVERLAY_ID_4                               0x04
1105 #define IPR_HOST_RCB_OVERLAY_ID_6                               0x06
1106 #define IPR_HOST_RCB_OVERLAY_ID_7                               0x07
1107 #define IPR_HOST_RCB_OVERLAY_ID_12                              0x12
1108 #define IPR_HOST_RCB_OVERLAY_ID_13                              0x13
1109 #define IPR_HOST_RCB_OVERLAY_ID_14                              0x14
1110 #define IPR_HOST_RCB_OVERLAY_ID_16                              0x16
1111 #define IPR_HOST_RCB_OVERLAY_ID_17                              0x17
1112 #define IPR_HOST_RCB_OVERLAY_ID_20                              0x20
1113 #define IPR_HOST_RCB_OVERLAY_ID_23                              0x23
1114 #define IPR_HOST_RCB_OVERLAY_ID_24                              0x24
1115 #define IPR_HOST_RCB_OVERLAY_ID_26                              0x26
1116 #define IPR_HOST_RCB_OVERLAY_ID_30                              0x30
1117 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT                         0xFF
1118
1119         u8 reserved1[3];
1120         __be32 ilid;
1121         __be32 time_since_last_ioa_reset;
1122         __be32 reserved2;
1123         __be32 length;
1124
1125         union {
1126                 struct ipr_hostrcb_error error;
1127                 struct ipr_hostrcb64_error error64;
1128                 struct ipr_hostrcb_cfg_ch_not ccn;
1129                 struct ipr_hostrcb_raw raw;
1130         } u;
1131 }__attribute__((packed, aligned (4)));
1132
1133 struct ipr_hostrcb {
1134         struct ipr_hcam hcam;
1135         dma_addr_t hostrcb_dma;
1136         struct list_head queue;
1137         struct ipr_ioa_cfg *ioa_cfg;
1138         char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1139 };
1140
1141 /* IPR smart dump table structures */
1142 struct ipr_sdt_entry {
1143         __be32 start_token;
1144         __be32 end_token;
1145         u8 reserved[4];
1146
1147         u8 flags;
1148 #define IPR_SDT_ENDIAN          0x80
1149 #define IPR_SDT_VALID_ENTRY     0x20
1150
1151         u8 resv;
1152         __be16 priority;
1153 }__attribute__((packed, aligned (4)));
1154
1155 struct ipr_sdt_header {
1156         __be32 state;
1157         __be32 num_entries;
1158         __be32 num_entries_used;
1159         __be32 dump_size;
1160 }__attribute__((packed, aligned (4)));
1161
1162 struct ipr_sdt {
1163         struct ipr_sdt_header hdr;
1164         struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1165 }__attribute__((packed, aligned (4)));
1166
1167 struct ipr_uc_sdt {
1168         struct ipr_sdt_header hdr;
1169         struct ipr_sdt_entry entry[1];
1170 }__attribute__((packed, aligned (4)));
1171
1172 /*
1173  * Driver types
1174  */
1175 struct ipr_bus_attributes {
1176         u8 bus;
1177         u8 qas_enabled;
1178         u8 bus_width;
1179         u8 reserved;
1180         u32 max_xfer_rate;
1181 };
1182
1183 struct ipr_sata_port {
1184         struct ipr_ioa_cfg *ioa_cfg;
1185         struct ata_port *ap;
1186         struct ipr_resource_entry *res;
1187         struct ipr_ioasa_gata ioasa;
1188 };
1189
1190 struct ipr_resource_entry {
1191         u8 needs_sync_complete:1;
1192         u8 in_erp:1;
1193         u8 add_to_ml:1;
1194         u8 del_from_ml:1;
1195         u8 resetting_device:1;
1196
1197         u32 bus;                /* AKA channel */
1198         u32 target;             /* AKA id */
1199         u32 lun;
1200 #define IPR_ARRAY_VIRTUAL_BUS                   0x1
1201 #define IPR_VSET_VIRTUAL_BUS                    0x2
1202 #define IPR_IOAFP_VIRTUAL_BUS                   0x3
1203
1204 #define IPR_GET_RES_PHYS_LOC(res) \
1205         (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1206
1207         u8 ata_class;
1208
1209         u8 flags;
1210         __be16 res_flags;
1211
1212         u8 type;
1213
1214         u8 qmodel;
1215         struct ipr_std_inq_data std_inq_data;
1216
1217         __be32 res_handle;
1218         __be64 dev_id;
1219         __be64 lun_wwn;
1220         struct scsi_lun dev_lun;
1221         u8 res_path[8];
1222
1223         struct ipr_ioa_cfg *ioa_cfg;
1224         struct scsi_device *sdev;
1225         struct ipr_sata_port *sata_port;
1226         struct list_head queue;
1227 }; /* struct ipr_resource_entry */
1228
1229 struct ipr_resource_hdr {
1230         u16 num_entries;
1231         u16 reserved;
1232 };
1233
1234 struct ipr_misc_cbs {
1235         struct ipr_ioa_vpd ioa_vpd;
1236         struct ipr_inquiry_page0 page0_data;
1237         struct ipr_inquiry_page3 page3_data;
1238         struct ipr_inquiry_cap cap;
1239         struct ipr_mode_pages mode_pages;
1240         struct ipr_supported_device supp_dev;
1241 };
1242
1243 struct ipr_interrupt_offsets {
1244         unsigned long set_interrupt_mask_reg;
1245         unsigned long clr_interrupt_mask_reg;
1246         unsigned long clr_interrupt_mask_reg32;
1247         unsigned long sense_interrupt_mask_reg;
1248         unsigned long sense_interrupt_mask_reg32;
1249         unsigned long clr_interrupt_reg;
1250         unsigned long clr_interrupt_reg32;
1251
1252         unsigned long sense_interrupt_reg;
1253         unsigned long sense_interrupt_reg32;
1254         unsigned long ioarrin_reg;
1255         unsigned long sense_uproc_interrupt_reg;
1256         unsigned long sense_uproc_interrupt_reg32;
1257         unsigned long set_uproc_interrupt_reg;
1258         unsigned long set_uproc_interrupt_reg32;
1259         unsigned long clr_uproc_interrupt_reg;
1260         unsigned long clr_uproc_interrupt_reg32;
1261
1262         unsigned long init_feedback_reg;
1263
1264         unsigned long dump_addr_reg;
1265         unsigned long dump_data_reg;
1266
1267 #define IPR_ENDIAN_SWAP_KEY             0x00080800
1268         unsigned long endian_swap_reg;
1269 };
1270
1271 struct ipr_interrupts {
1272         void __iomem *set_interrupt_mask_reg;
1273         void __iomem *clr_interrupt_mask_reg;
1274         void __iomem *clr_interrupt_mask_reg32;
1275         void __iomem *sense_interrupt_mask_reg;
1276         void __iomem *sense_interrupt_mask_reg32;
1277         void __iomem *clr_interrupt_reg;
1278         void __iomem *clr_interrupt_reg32;
1279
1280         void __iomem *sense_interrupt_reg;
1281         void __iomem *sense_interrupt_reg32;
1282         void __iomem *ioarrin_reg;
1283         void __iomem *sense_uproc_interrupt_reg;
1284         void __iomem *sense_uproc_interrupt_reg32;
1285         void __iomem *set_uproc_interrupt_reg;
1286         void __iomem *set_uproc_interrupt_reg32;
1287         void __iomem *clr_uproc_interrupt_reg;
1288         void __iomem *clr_uproc_interrupt_reg32;
1289
1290         void __iomem *init_feedback_reg;
1291
1292         void __iomem *dump_addr_reg;
1293         void __iomem *dump_data_reg;
1294
1295         void __iomem *endian_swap_reg;
1296 };
1297
1298 struct ipr_chip_cfg_t {
1299         u32 mailbox;
1300         u8 cache_line_size;
1301         struct ipr_interrupt_offsets regs;
1302 };
1303
1304 struct ipr_chip_t {
1305         u16 vendor;
1306         u16 device;
1307         u16 intr_type;
1308 #define IPR_USE_LSI                     0x00
1309 #define IPR_USE_MSI                     0x01
1310         u16 sis_type;
1311 #define IPR_SIS32                       0x00
1312 #define IPR_SIS64                       0x01
1313         u16 bist_method;
1314 #define IPR_PCI_CFG                     0x00
1315 #define IPR_MMIO                        0x01
1316         const struct ipr_chip_cfg_t *cfg;
1317 };
1318
1319 enum ipr_shutdown_type {
1320         IPR_SHUTDOWN_NORMAL = 0x00,
1321         IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1322         IPR_SHUTDOWN_ABBREV = 0x80,
1323         IPR_SHUTDOWN_NONE = 0x100
1324 };
1325
1326 struct ipr_trace_entry {
1327         u32 time;
1328
1329         u8 op_code;
1330         u8 ata_op_code;
1331         u8 type;
1332 #define IPR_TRACE_START                 0x00
1333 #define IPR_TRACE_FINISH                0xff
1334         u8 cmd_index;
1335
1336         __be32 res_handle;
1337         union {
1338                 u32 ioasc;
1339                 u32 add_data;
1340                 u32 res_addr;
1341         } u;
1342 };
1343
1344 struct ipr_sglist {
1345         u32 order;
1346         u32 num_sg;
1347         u32 num_dma_sg;
1348         u32 buffer_len;
1349         struct scatterlist scatterlist[1];
1350 };
1351
1352 enum ipr_sdt_state {
1353         INACTIVE,
1354         WAIT_FOR_DUMP,
1355         GET_DUMP,
1356         ABORT_DUMP,
1357         DUMP_OBTAINED
1358 };
1359
1360 /* Per-controller data */
1361 struct ipr_ioa_cfg {
1362         char eye_catcher[8];
1363 #define IPR_EYECATCHER                  "iprcfg"
1364
1365         struct list_head queue;
1366
1367         u8 allow_interrupts:1;
1368         u8 in_reset_reload:1;
1369         u8 in_ioa_bringdown:1;
1370         u8 ioa_unit_checked:1;
1371         u8 ioa_is_dead:1;
1372         u8 dump_taken:1;
1373         u8 allow_cmds:1;
1374         u8 allow_ml_add_del:1;
1375         u8 needs_hard_reset:1;
1376         u8 dual_raid:1;
1377         u8 needs_warm_reset:1;
1378         u8 msi_received:1;
1379         u8 sis64:1;
1380
1381         u8 revid;
1382
1383         /*
1384          * Bitmaps for SIS64 generated target values
1385          */
1386         unsigned long *target_ids;
1387         unsigned long *array_ids;
1388         unsigned long *vset_ids;
1389
1390         u16 type; /* CCIN of the card */
1391
1392         u8 log_level;
1393 #define IPR_MAX_LOG_LEVEL                       4
1394 #define IPR_DEFAULT_LOG_LEVEL           2
1395
1396 #define IPR_NUM_TRACE_INDEX_BITS        8
1397 #define IPR_NUM_TRACE_ENTRIES           (1 << IPR_NUM_TRACE_INDEX_BITS)
1398 #define IPR_TRACE_SIZE  (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1399         char trace_start[8];
1400 #define IPR_TRACE_START_LABEL                   "trace"
1401         struct ipr_trace_entry *trace;
1402         u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1403
1404         /*
1405          * Queue for free command blocks
1406          */
1407         char ipr_free_label[8];
1408 #define IPR_FREEQ_LABEL                 "free-q"
1409         struct list_head free_q;
1410
1411         /*
1412          * Queue for command blocks outstanding to the adapter
1413          */
1414         char ipr_pending_label[8];
1415 #define IPR_PENDQ_LABEL                 "pend-q"
1416         struct list_head pending_q;
1417
1418         char cfg_table_start[8];
1419 #define IPR_CFG_TBL_START               "cfg"
1420         union {
1421                 struct ipr_config_table *cfg_table;
1422                 struct ipr_config_table64 *cfg_table64;
1423         } u;
1424         dma_addr_t cfg_table_dma;
1425         u32 cfg_table_size;
1426         u32 max_devs_supported;
1427
1428         char resource_table_label[8];
1429 #define IPR_RES_TABLE_LABEL             "res_tbl"
1430         struct ipr_resource_entry *res_entries;
1431         struct list_head free_res_q;
1432         struct list_head used_res_q;
1433
1434         char ipr_hcam_label[8];
1435 #define IPR_HCAM_LABEL                  "hcams"
1436         struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1437         dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1438         struct list_head hostrcb_free_q;
1439         struct list_head hostrcb_pending_q;
1440
1441         __be32 *host_rrq;
1442         dma_addr_t host_rrq_dma;
1443 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK   0xfffffffc
1444 #define IPR_HRRQ_RESP_BIT_SET                   0x00000002
1445 #define IPR_HRRQ_TOGGLE_BIT                             0x00000001
1446 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT  2
1447         volatile __be32 *hrrq_start;
1448         volatile __be32 *hrrq_end;
1449         volatile __be32 *hrrq_curr;
1450         volatile u32 toggle_bit;
1451
1452         struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1453
1454         unsigned int transop_timeout;
1455         const struct ipr_chip_cfg_t *chip_cfg;
1456         const struct ipr_chip_t *ipr_chip;
1457
1458         void __iomem *hdw_dma_regs;     /* iomapped PCI memory space */
1459         unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1460         void __iomem *ioa_mailbox;
1461         struct ipr_interrupts regs;
1462
1463         u16 saved_pcix_cmd_reg;
1464         u16 reset_retries;
1465
1466         u32 errors_logged;
1467         u32 doorbell;
1468
1469         struct Scsi_Host *host;
1470         struct pci_dev *pdev;
1471         struct ipr_sglist *ucode_sglist;
1472         u8 saved_mode_page_len;
1473
1474         struct work_struct work_q;
1475
1476         wait_queue_head_t reset_wait_q;
1477         wait_queue_head_t msi_wait_q;
1478
1479         struct ipr_dump *dump;
1480         enum ipr_sdt_state sdt_state;
1481
1482         struct ipr_misc_cbs *vpd_cbs;
1483         dma_addr_t vpd_cbs_dma;
1484
1485         struct pci_pool *ipr_cmd_pool;
1486
1487         struct ipr_cmnd *reset_cmd;
1488         int (*reset) (struct ipr_cmnd *);
1489
1490         struct ata_host ata_host;
1491         char ipr_cmd_label[8];
1492 #define IPR_CMD_LABEL           "ipr_cmd"
1493         struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1494         dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1495 }; /* struct ipr_ioa_cfg */
1496
1497 struct ipr_cmnd {
1498         struct ipr_ioarcb ioarcb;
1499         union {
1500                 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1501                 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1502                 struct ipr_ata64_ioadl ata_ioadl;
1503         } i;
1504         union {
1505                 struct ipr_ioasa ioasa;
1506                 struct ipr_ioasa64 ioasa64;
1507         } s;
1508         struct list_head queue;
1509         struct scsi_cmnd *scsi_cmd;
1510         struct ata_queued_cmd *qc;
1511         struct completion completion;
1512         struct timer_list timer;
1513         void (*done) (struct ipr_cmnd *);
1514         int (*job_step) (struct ipr_cmnd *);
1515         int (*job_step_failed) (struct ipr_cmnd *);
1516         u16 cmd_index;
1517         u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1518         dma_addr_t sense_buffer_dma;
1519         unsigned short dma_use_sg;
1520         dma_addr_t dma_addr;
1521         struct ipr_cmnd *sibling;
1522         union {
1523                 enum ipr_shutdown_type shutdown_type;
1524                 struct ipr_hostrcb *hostrcb;
1525                 unsigned long time_left;
1526                 unsigned long scratch;
1527                 struct ipr_resource_entry *res;
1528                 struct scsi_device *sdev;
1529         } u;
1530
1531         struct ipr_ioa_cfg *ioa_cfg;
1532 };
1533
1534 struct ipr_ses_table_entry {
1535         char product_id[17];
1536         char compare_product_id_byte[17];
1537         u32 max_bus_speed_limit;        /* MB/sec limit for this backplane */
1538 };
1539
1540 struct ipr_dump_header {
1541         u32 eye_catcher;
1542 #define IPR_DUMP_EYE_CATCHER            0xC5D4E3F2
1543         u32 len;
1544         u32 num_entries;
1545         u32 first_entry_offset;
1546         u32 status;
1547 #define IPR_DUMP_STATUS_SUCCESS                 0
1548 #define IPR_DUMP_STATUS_QUAL_SUCCESS            2
1549 #define IPR_DUMP_STATUS_FAILED                  0xffffffff
1550         u32 os;
1551 #define IPR_DUMP_OS_LINUX       0x4C4E5558
1552         u32 driver_name;
1553 #define IPR_DUMP_DRIVER_NAME    0x49505232
1554 }__attribute__((packed, aligned (4)));
1555
1556 struct ipr_dump_entry_header {
1557         u32 eye_catcher;
1558 #define IPR_DUMP_EYE_CATCHER            0xC5D4E3F2
1559         u32 len;
1560         u32 num_elems;
1561         u32 offset;
1562         u32 data_type;
1563 #define IPR_DUMP_DATA_TYPE_ASCII        0x41534349
1564 #define IPR_DUMP_DATA_TYPE_BINARY       0x42494E41
1565         u32 id;
1566 #define IPR_DUMP_IOA_DUMP_ID            0x494F4131
1567 #define IPR_DUMP_LOCATION_ID            0x4C4F4341
1568 #define IPR_DUMP_TRACE_ID               0x54524143
1569 #define IPR_DUMP_DRIVER_VERSION_ID      0x44525652
1570 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1571 #define IPR_DUMP_IOA_CTRL_BLK           0x494F4342
1572 #define IPR_DUMP_PEND_OPS               0x414F5053
1573         u32 status;
1574 }__attribute__((packed, aligned (4)));
1575
1576 struct ipr_dump_location_entry {
1577         struct ipr_dump_entry_header hdr;
1578         u8 location[20];
1579 }__attribute__((packed));
1580
1581 struct ipr_dump_trace_entry {
1582         struct ipr_dump_entry_header hdr;
1583         u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1584 }__attribute__((packed, aligned (4)));
1585
1586 struct ipr_dump_version_entry {
1587         struct ipr_dump_entry_header hdr;
1588         u8 version[sizeof(IPR_DRIVER_VERSION)];
1589 };
1590
1591 struct ipr_dump_ioa_type_entry {
1592         struct ipr_dump_entry_header hdr;
1593         u32 type;
1594         u32 fw_version;
1595 };
1596
1597 struct ipr_driver_dump {
1598         struct ipr_dump_header hdr;
1599         struct ipr_dump_version_entry version_entry;
1600         struct ipr_dump_location_entry location_entry;
1601         struct ipr_dump_ioa_type_entry ioa_type_entry;
1602         struct ipr_dump_trace_entry trace_entry;
1603 }__attribute__((packed));
1604
1605 struct ipr_ioa_dump {
1606         struct ipr_dump_entry_header hdr;
1607         struct ipr_sdt sdt;
1608         __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1609         u32 reserved;
1610         u32 next_page_index;
1611         u32 page_offset;
1612         u32 format;
1613 }__attribute__((packed, aligned (4)));
1614
1615 struct ipr_dump {
1616         struct kref kref;
1617         struct ipr_ioa_cfg *ioa_cfg;
1618         struct ipr_driver_dump driver_dump;
1619         struct ipr_ioa_dump ioa_dump;
1620 };
1621
1622 struct ipr_error_table_t {
1623         u32 ioasc;
1624         int log_ioasa;
1625         int log_hcam;
1626         char *error;
1627 };
1628
1629 struct ipr_software_inq_lid_info {
1630         __be32 load_id;
1631         __be32 timestamp[3];
1632 }__attribute__((packed, aligned (4)));
1633
1634 struct ipr_ucode_image_header {
1635         __be32 header_length;
1636         __be32 lid_table_offset;
1637         u8 major_release;
1638         u8 card_type;
1639         u8 minor_release[2];
1640         u8 reserved[20];
1641         char eyecatcher[16];
1642         __be32 num_lids;
1643         struct ipr_software_inq_lid_info lid[1];
1644 }__attribute__((packed, aligned (4)));
1645
1646 /*
1647  * Macros
1648  */
1649 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1650
1651 #ifdef CONFIG_SCSI_IPR_TRACE
1652 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1653 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1654 #else
1655 #define ipr_create_trace_file(kobj, attr) 0
1656 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1657 #endif
1658
1659 #ifdef CONFIG_SCSI_IPR_DUMP
1660 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1661 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1662 #else
1663 #define ipr_create_dump_file(kobj, attr) 0
1664 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1665 #endif
1666
1667 /*
1668  * Error logging macros
1669  */
1670 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1671 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1672 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1673
1674 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1675         printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1676                 bus, target, lun, ##__VA_ARGS__)
1677
1678 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1679         ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1680
1681 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1682         printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1683                 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1684
1685 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1686         ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1687
1688 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...)                        \
1689 {                                                                       \
1690         if ((res).bus >= IPR_MAX_NUM_BUSES) {                           \
1691                 ipr_err(fmt": unknown\n", ##__VA_ARGS__);               \
1692         } else {                                                        \
1693                 ipr_err(fmt": %d:%d:%d:%d\n",                           \
1694                         ##__VA_ARGS__, (ioa_cfg)->host->host_no,        \
1695                         (res).bus, (res).target, (res).lun);            \
1696         }                                                               \
1697 }
1698
1699 #define ipr_hcam_err(hostrcb, fmt, ...)                                 \
1700 {                                                                       \
1701         if (ipr_is_device(hostrcb)) {                                   \
1702                 if ((hostrcb)->ioa_cfg->sis64) {                        \
1703                         printk(KERN_ERR IPR_NAME ": %s: " fmt,          \
1704                                 ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
1705                                         hostrcb->rp_buffer,             \
1706                                         sizeof(hostrcb->rp_buffer)),    \
1707                                 __VA_ARGS__);                           \
1708                 } else {                                                \
1709                         ipr_ra_err((hostrcb)->ioa_cfg,                  \
1710                                 (hostrcb)->hcam.u.error.fd_res_addr,    \
1711                                 fmt, __VA_ARGS__);                      \
1712                 }                                                       \
1713         } else {                                                        \
1714                 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1715         }                                                               \
1716 }
1717
1718 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1719         __FILE__, __func__, __LINE__)
1720
1721 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1722 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1723
1724 #define ipr_err_separator \
1725 ipr_err("----------------------------------------------------------\n")
1726
1727
1728 /*
1729  * Inlines
1730  */
1731
1732 /**
1733  * ipr_is_ioa_resource - Determine if a resource is the IOA
1734  * @res:        resource entry struct
1735  *
1736  * Return value:
1737  *      1 if IOA / 0 if not IOA
1738  **/
1739 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1740 {
1741         return res->type == IPR_RES_TYPE_IOAFP;
1742 }
1743
1744 /**
1745  * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1746  * @res:        resource entry struct
1747  *
1748  * Return value:
1749  *      1 if AF DASD / 0 if not AF DASD
1750  **/
1751 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1752 {
1753         return res->type == IPR_RES_TYPE_AF_DASD ||
1754                 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1755 }
1756
1757 /**
1758  * ipr_is_vset_device - Determine if a resource is a VSET
1759  * @res:        resource entry struct
1760  *
1761  * Return value:
1762  *      1 if VSET / 0 if not VSET
1763  **/
1764 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1765 {
1766         return res->type == IPR_RES_TYPE_VOLUME_SET;
1767 }
1768
1769 /**
1770  * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1771  * @res:        resource entry struct
1772  *
1773  * Return value:
1774  *      1 if GSCSI / 0 if not GSCSI
1775  **/
1776 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1777 {
1778         return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1779 }
1780
1781 /**
1782  * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1783  * @res:        resource entry struct
1784  *
1785  * Return value:
1786  *      1 if SCSI disk / 0 if not SCSI disk
1787  **/
1788 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1789 {
1790         if (ipr_is_af_dasd_device(res) ||
1791             (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1792                 return 1;
1793         else
1794                 return 0;
1795 }
1796
1797 /**
1798  * ipr_is_gata - Determine if a resource is a generic ATA resource
1799  * @res:        resource entry struct
1800  *
1801  * Return value:
1802  *      1 if GATA / 0 if not GATA
1803  **/
1804 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1805 {
1806         return res->type == IPR_RES_TYPE_GENERIC_ATA;
1807 }
1808
1809 /**
1810  * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1811  * @res:        resource entry struct
1812  *
1813  * Return value:
1814  *      1 if NACA queueing model / 0 if not NACA queueing model
1815  **/
1816 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1817 {
1818         if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1819                 return 1;
1820         return 0;
1821 }
1822
1823 /**
1824  * ipr_is_device - Determine if the hostrcb structure is related to a device
1825  * @hostrcb:    host resource control blocks struct
1826  *
1827  * Return value:
1828  *      1 if AF / 0 if not AF
1829  **/
1830 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1831 {
1832         struct ipr_res_addr *res_addr;
1833         u8 *res_path;
1834
1835         if (hostrcb->ioa_cfg->sis64) {
1836                 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1837                 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1838                     res_path[0] == 0x81) && res_path[2] != 0xFF)
1839                         return 1;
1840         } else {
1841                 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1842
1843                 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1844                     (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1845                         return 1;
1846         }
1847         return 0;
1848 }
1849
1850 /**
1851  * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1852  * @sdt_word:   SDT address
1853  *
1854  * Return value:
1855  *      1 if format 2 / 0 if not
1856  **/
1857 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1858 {
1859         u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1860
1861         switch (bar_sel) {
1862         case IPR_SDT_FMT2_BAR0_SEL:
1863         case IPR_SDT_FMT2_BAR1_SEL:
1864         case IPR_SDT_FMT2_BAR2_SEL:
1865         case IPR_SDT_FMT2_BAR3_SEL:
1866         case IPR_SDT_FMT2_BAR4_SEL:
1867         case IPR_SDT_FMT2_BAR5_SEL:
1868         case IPR_SDT_FMT2_EXP_ROM_SEL:
1869                 return 1;
1870         };
1871
1872         return 0;
1873 }
1874
1875 #ifndef writeq
1876 static inline void writeq(u64 val, void __iomem *addr)
1877 {
1878         writel(((u32) (val >> 32)), addr);
1879         writel(((u32) (val)), (addr + 4));
1880 }
1881 #endif
1882
1883 #endif /* _IPR_H */