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drm/i915: range-restricted eviction support
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / jme.c
blobd7a975ee2add393010e9db6ad38fbd1c770603a4
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/mii.h>
34 #include <linux/crc32.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <linux/ipv6.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/if_vlan.h>
43 #include <linux/slab.h>
44 #include <net/ip6_checksum.h>
45 #include "jme.h"
46
47 static int force_pseudohp = -1;
48 static int no_pseudohp = -1;
49 static int no_extplug = -1;
50 module_param(force_pseudohp, int, 0);
51 MODULE_PARM_DESC(force_pseudohp,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53 module_param(no_pseudohp, int, 0);
54 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55 module_param(no_extplug, int, 0);
56 MODULE_PARM_DESC(no_extplug,
57 "Do not use external plug signal for pseudo hot-plug.");
58
59 static int
60 jme_mdio_read(struct net_device *netdev, int phy, int reg)
61 {
62 struct jme_adapter *jme = netdev_priv(netdev);
63 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
64
65 read_again:
66 jwrite32(jme, JME_SMI, SMI_OP_REQ |
67 smi_phy_addr(phy) |
68 smi_reg_addr(reg));
69
70 wmb();
71 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
72 udelay(20);
73 val = jread32(jme, JME_SMI);
74 if ((val & SMI_OP_REQ) == 0)
75 break;
76 }
77
78 if (i == 0) {
79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
80 return 0;
81 }
82
83 if (again--)
84 goto read_again;
85
86 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
87 }
88
89 static void
90 jme_mdio_write(struct net_device *netdev,
91 int phy, int reg, int val)
92 {
93 struct jme_adapter *jme = netdev_priv(netdev);
94 int i;
95
96 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98 smi_phy_addr(phy) | smi_reg_addr(reg));
99
100 wmb();
101 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 udelay(20);
103 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104 break;
105 }
106
107 if (i == 0)
108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
109 }
110
111 static inline void
112 jme_reset_phy_processor(struct jme_adapter *jme)
113 {
114 u32 val;
115
116 jme_mdio_write(jme->dev,
117 jme->mii_if.phy_id,
118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
120
121 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
122 jme_mdio_write(jme->dev,
123 jme->mii_if.phy_id,
124 MII_CTRL1000,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
126
127 val = jme_mdio_read(jme->dev,
128 jme->mii_if.phy_id,
129 MII_BMCR);
130
131 jme_mdio_write(jme->dev,
132 jme->mii_if.phy_id,
133 MII_BMCR, val | BMCR_RESET);
134 }
135
136 static void
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
139 {
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161 }
162
163 static inline void
164 jme_reset_mac_processor(struct jme_adapter *jme)
165 {
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
169 int i;
170
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172 udelay(2);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
188 if (jme->fpgaver)
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194 }
195
196 static inline void
197 jme_reset_ghc_speed(struct jme_adapter *jme)
198 {
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201 }
202
203 static inline void
204 jme_clear_pm(struct jme_adapter *jme)
205 {
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
209 }
210
211 static int
212 jme_reload_eeprom(struct jme_adapter *jme)
213 {
214 u32 val;
215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
219 if (val & SMBCSR_EEPROMD) {
220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
232 if (i == 0) {
233 pr_err("eeprom reload timeout\n");
234 return -EIO;
235 }
236 }
237
238 return 0;
239 }
240
241 static void
242 jme_load_macaddr(struct net_device *netdev)
243 {
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
246 u32 val;
247
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
259 }
260
261 static inline void
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
263 {
264 switch (p) {
265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
288 wmb();
289
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
292 }
293
294 static void
295 jme_start_irq(struct jme_adapter *jme)
296 {
297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
307 PCCTXQ0_EN
308 );
309
310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314 }
315
316 static inline void
317 jme_stop_irq(struct jme_adapter *jme)
318 {
319 /*
320 * Disable Interrupts
321 */
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
323 }
324
325 static u32
326 jme_linkstat_from_phy(struct jme_adapter *jme)
327 {
328 u32 phylink, bmsr;
329
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
332 if (bmsr & BMSR_ANCOMP)
333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
334
335 return phylink;
336 }
337
338 static inline void
339 jme_set_phyfifoa(struct jme_adapter *jme)
340 {
341 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
342 }
343
344 static inline void
345 jme_set_phyfifob(struct jme_adapter *jme)
346 {
347 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
348 }
349
350 static int
351 jme_check_link(struct net_device *netdev, int testonly)
352 {
353 struct jme_adapter *jme = netdev_priv(netdev);
354 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
355 char linkmsg[64];
356 int rc = 0;
357
358 linkmsg[0] = '\0';
359
360 if (jme->fpgaver)
361 phylink = jme_linkstat_from_phy(jme);
362 else
363 phylink = jread32(jme, JME_PHY_LINK);
364
365 if (phylink & PHY_LINK_UP) {
366 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
367 /*
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
370 */
371 phylink = PHY_LINK_UP;
372
373 bmcr = jme_mdio_read(jme->dev,
374 jme->mii_if.phy_id,
375 MII_BMCR);
376
377 phylink |= ((bmcr & BMCR_SPEED1000) &&
378 (bmcr & BMCR_SPEED100) == 0) ?
379 PHY_LINK_SPEED_1000M :
380 (bmcr & BMCR_SPEED100) ?
381 PHY_LINK_SPEED_100M :
382 PHY_LINK_SPEED_10M;
383
384 phylink |= (bmcr & BMCR_FULLDPLX) ?
385 PHY_LINK_DUPLEX : 0;
386
387 strcat(linkmsg, "Forced: ");
388 } else {
389 /*
390 * Keep polling for speed/duplex resolve complete
391 */
392 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
393 --cnt) {
394
395 udelay(1);
396
397 if (jme->fpgaver)
398 phylink = jme_linkstat_from_phy(jme);
399 else
400 phylink = jread32(jme, JME_PHY_LINK);
401 }
402 if (!cnt)
403 pr_err("Waiting speed resolve timeout\n");
404
405 strcat(linkmsg, "ANed: ");
406 }
407
408 if (jme->phylink == phylink) {
409 rc = 1;
410 goto out;
411 }
412 if (testonly)
413 goto out;
414
415 jme->phylink = phylink;
416
417 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
418 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
419 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
420 switch (phylink & PHY_LINK_SPEED_MASK) {
421 case PHY_LINK_SPEED_10M:
422 ghc |= GHC_SPEED_10M |
423 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
424 strcat(linkmsg, "10 Mbps, ");
425 break;
426 case PHY_LINK_SPEED_100M:
427 ghc |= GHC_SPEED_100M |
428 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
429 strcat(linkmsg, "100 Mbps, ");
430 break;
431 case PHY_LINK_SPEED_1000M:
432 ghc |= GHC_SPEED_1000M |
433 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
434 strcat(linkmsg, "1000 Mbps, ");
435 break;
436 default:
437 break;
438 }
439
440 if (phylink & PHY_LINK_DUPLEX) {
441 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
442 ghc |= GHC_DPX;
443 } else {
444 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
445 TXMCS_BACKOFF |
446 TXMCS_CARRIERSENSE |
447 TXMCS_COLLISION);
448 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
449 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
450 TXTRHD_TXREN |
451 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
452 }
453
454 gpreg1 = GPREG1_DEFAULT;
455 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
456 if (!(phylink & PHY_LINK_DUPLEX))
457 gpreg1 |= GPREG1_HALFMODEPATCH;
458 switch (phylink & PHY_LINK_SPEED_MASK) {
459 case PHY_LINK_SPEED_10M:
460 jme_set_phyfifoa(jme);
461 gpreg1 |= GPREG1_RSSPATCH;
462 break;
463 case PHY_LINK_SPEED_100M:
464 jme_set_phyfifob(jme);
465 gpreg1 |= GPREG1_RSSPATCH;
466 break;
467 case PHY_LINK_SPEED_1000M:
468 jme_set_phyfifoa(jme);
469 break;
470 default:
471 break;
472 }
473 }
474
475 jwrite32(jme, JME_GPREG1, gpreg1);
476 jwrite32(jme, JME_GHC, ghc);
477 jme->reg_ghc = ghc;
478
479 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
480 "Full-Duplex, " :
481 "Half-Duplex, ");
482 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
483 "MDI-X" :
484 "MDI");
485 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
486 netif_carrier_on(netdev);
487 } else {
488 if (testonly)
489 goto out;
490
491 netif_info(jme, link, jme->dev, "Link is down\n");
492 jme->phylink = 0;
493 netif_carrier_off(netdev);
494 }
495
496 out:
497 return rc;
498 }
499
500 static int
501 jme_setup_tx_resources(struct jme_adapter *jme)
502 {
503 struct jme_ring *txring = &(jme->txring[0]);
504
505 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
506 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
507 &(txring->dmaalloc),
508 GFP_ATOMIC);
509
510 if (!txring->alloc)
511 goto err_set_null;
512
513 /*
514 * 16 Bytes align
515 */
516 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
517 RING_DESC_ALIGN);
518 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
519 txring->next_to_use = 0;
520 atomic_set(&txring->next_to_clean, 0);
521 atomic_set(&txring->nr_free, jme->tx_ring_size);
522
523 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
524 jme->tx_ring_size, GFP_ATOMIC);
525 if (unlikely(!(txring->bufinf)))
526 goto err_free_txring;
527
528 /*
529 * Initialize Transmit Descriptors
530 */
531 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
532 memset(txring->bufinf, 0,
533 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
534
535 return 0;
536
537 err_free_txring:
538 dma_free_coherent(&(jme->pdev->dev),
539 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
540 txring->alloc,
541 txring->dmaalloc);
542
543 err_set_null:
544 txring->desc = NULL;
545 txring->dmaalloc = 0;
546 txring->dma = 0;
547 txring->bufinf = NULL;
548
549 return -ENOMEM;
550 }
551
552 static void
553 jme_free_tx_resources(struct jme_adapter *jme)
554 {
555 int i;
556 struct jme_ring *txring = &(jme->txring[0]);
557 struct jme_buffer_info *txbi;
558
559 if (txring->alloc) {
560 if (txring->bufinf) {
561 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
562 txbi = txring->bufinf + i;
563 if (txbi->skb) {
564 dev_kfree_skb(txbi->skb);
565 txbi->skb = NULL;
566 }
567 txbi->mapping = 0;
568 txbi->len = 0;
569 txbi->nr_desc = 0;
570 txbi->start_xmit = 0;
571 }
572 kfree(txring->bufinf);
573 }
574
575 dma_free_coherent(&(jme->pdev->dev),
576 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
577 txring->alloc,
578 txring->dmaalloc);
579
580 txring->alloc = NULL;
581 txring->desc = NULL;
582 txring->dmaalloc = 0;
583 txring->dma = 0;
584 txring->bufinf = NULL;
585 }
586 txring->next_to_use = 0;
587 atomic_set(&txring->next_to_clean, 0);
588 atomic_set(&txring->nr_free, 0);
589 }
590
591 static inline void
592 jme_enable_tx_engine(struct jme_adapter *jme)
593 {
594 /*
595 * Select Queue 0
596 */
597 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
598 wmb();
599
600 /*
601 * Setup TX Queue 0 DMA Bass Address
602 */
603 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
604 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
605 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
606
607 /*
608 * Setup TX Descptor Count
609 */
610 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
611
612 /*
613 * Enable TX Engine
614 */
615 wmb();
616 jwrite32(jme, JME_TXCS, jme->reg_txcs |
617 TXCS_SELECT_QUEUE0 |
618 TXCS_ENABLE);
619
620 }
621
622 static inline void
623 jme_restart_tx_engine(struct jme_adapter *jme)
624 {
625 /*
626 * Restart TX Engine
627 */
628 jwrite32(jme, JME_TXCS, jme->reg_txcs |
629 TXCS_SELECT_QUEUE0 |
630 TXCS_ENABLE);
631 }
632
633 static inline void
634 jme_disable_tx_engine(struct jme_adapter *jme)
635 {
636 int i;
637 u32 val;
638
639 /*
640 * Disable TX Engine
641 */
642 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
643 wmb();
644
645 val = jread32(jme, JME_TXCS);
646 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
647 mdelay(1);
648 val = jread32(jme, JME_TXCS);
649 rmb();
650 }
651
652 if (!i)
653 pr_err("Disable TX engine timeout\n");
654 }
655
656 static void
657 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
658 {
659 struct jme_ring *rxring = &(jme->rxring[0]);
660 register struct rxdesc *rxdesc = rxring->desc;
661 struct jme_buffer_info *rxbi = rxring->bufinf;
662 rxdesc += i;
663 rxbi += i;
664
665 rxdesc->dw[0] = 0;
666 rxdesc->dw[1] = 0;
667 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
668 rxdesc->desc1.bufaddrl = cpu_to_le32(
669 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
670 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
671 if (jme->dev->features & NETIF_F_HIGHDMA)
672 rxdesc->desc1.flags = RXFLAG_64BIT;
673 wmb();
674 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
675 }
676
677 static int
678 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
679 {
680 struct jme_ring *rxring = &(jme->rxring[0]);
681 struct jme_buffer_info *rxbi = rxring->bufinf + i;
682 struct sk_buff *skb;
683
684 skb = netdev_alloc_skb(jme->dev,
685 jme->dev->mtu + RX_EXTRA_LEN);
686 if (unlikely(!skb))
687 return -ENOMEM;
688
689 rxbi->skb = skb;
690 rxbi->len = skb_tailroom(skb);
691 rxbi->mapping = pci_map_page(jme->pdev,
692 virt_to_page(skb->data),
693 offset_in_page(skb->data),
694 rxbi->len,
695 PCI_DMA_FROMDEVICE);
696
697 return 0;
698 }
699
700 static void
701 jme_free_rx_buf(struct jme_adapter *jme, int i)
702 {
703 struct jme_ring *rxring = &(jme->rxring[0]);
704 struct jme_buffer_info *rxbi = rxring->bufinf;
705 rxbi += i;
706
707 if (rxbi->skb) {
708 pci_unmap_page(jme->pdev,
709 rxbi->mapping,
710 rxbi->len,
711 PCI_DMA_FROMDEVICE);
712 dev_kfree_skb(rxbi->skb);
713 rxbi->skb = NULL;
714 rxbi->mapping = 0;
715 rxbi->len = 0;
716 }
717 }
718
719 static void
720 jme_free_rx_resources(struct jme_adapter *jme)
721 {
722 int i;
723 struct jme_ring *rxring = &(jme->rxring[0]);
724
725 if (rxring->alloc) {
726 if (rxring->bufinf) {
727 for (i = 0 ; i < jme->rx_ring_size ; ++i)
728 jme_free_rx_buf(jme, i);
729 kfree(rxring->bufinf);
730 }
731
732 dma_free_coherent(&(jme->pdev->dev),
733 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
734 rxring->alloc,
735 rxring->dmaalloc);
736 rxring->alloc = NULL;
737 rxring->desc = NULL;
738 rxring->dmaalloc = 0;
739 rxring->dma = 0;
740 rxring->bufinf = NULL;
741 }
742 rxring->next_to_use = 0;
743 atomic_set(&rxring->next_to_clean, 0);
744 }
745
746 static int
747 jme_setup_rx_resources(struct jme_adapter *jme)
748 {
749 int i;
750 struct jme_ring *rxring = &(jme->rxring[0]);
751
752 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
753 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
754 &(rxring->dmaalloc),
755 GFP_ATOMIC);
756 if (!rxring->alloc)
757 goto err_set_null;
758
759 /*
760 * 16 Bytes align
761 */
762 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
763 RING_DESC_ALIGN);
764 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
765 rxring->next_to_use = 0;
766 atomic_set(&rxring->next_to_clean, 0);
767
768 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
769 jme->rx_ring_size, GFP_ATOMIC);
770 if (unlikely(!(rxring->bufinf)))
771 goto err_free_rxring;
772
773 /*
774 * Initiallize Receive Descriptors
775 */
776 memset(rxring->bufinf, 0,
777 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
778 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
779 if (unlikely(jme_make_new_rx_buf(jme, i))) {
780 jme_free_rx_resources(jme);
781 return -ENOMEM;
782 }
783
784 jme_set_clean_rxdesc(jme, i);
785 }
786
787 return 0;
788
789 err_free_rxring:
790 dma_free_coherent(&(jme->pdev->dev),
791 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
792 rxring->alloc,
793 rxring->dmaalloc);
794 err_set_null:
795 rxring->desc = NULL;
796 rxring->dmaalloc = 0;
797 rxring->dma = 0;
798 rxring->bufinf = NULL;
799
800 return -ENOMEM;
801 }
802
803 static inline void
804 jme_enable_rx_engine(struct jme_adapter *jme)
805 {
806 /*
807 * Select Queue 0
808 */
809 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
810 RXCS_QUEUESEL_Q0);
811 wmb();
812
813 /*
814 * Setup RX DMA Bass Address
815 */
816 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
817 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
818 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
819
820 /*
821 * Setup RX Descriptor Count
822 */
823 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
824
825 /*
826 * Setup Unicast Filter
827 */
828 jme_set_multi(jme->dev);
829
830 /*
831 * Enable RX Engine
832 */
833 wmb();
834 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
835 RXCS_QUEUESEL_Q0 |
836 RXCS_ENABLE |
837 RXCS_QST);
838 }
839
840 static inline void
841 jme_restart_rx_engine(struct jme_adapter *jme)
842 {
843 /*
844 * Start RX Engine
845 */
846 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
847 RXCS_QUEUESEL_Q0 |
848 RXCS_ENABLE |
849 RXCS_QST);
850 }
851
852 static inline void
853 jme_disable_rx_engine(struct jme_adapter *jme)
854 {
855 int i;
856 u32 val;
857
858 /*
859 * Disable RX Engine
860 */
861 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
862 wmb();
863
864 val = jread32(jme, JME_RXCS);
865 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
866 mdelay(1);
867 val = jread32(jme, JME_RXCS);
868 rmb();
869 }
870
871 if (!i)
872 pr_err("Disable RX engine timeout\n");
873
874 }
875
876 static int
877 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
878 {
879 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
880 return false;
881
882 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
883 == RXWBFLAG_TCPON)) {
884 if (flags & RXWBFLAG_IPV4)
885 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
886 return false;
887 }
888
889 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
890 == RXWBFLAG_UDPON)) {
891 if (flags & RXWBFLAG_IPV4)
892 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
893 return false;
894 }
895
896 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
897 == RXWBFLAG_IPV4)) {
898 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
899 return false;
900 }
901
902 return true;
903 }
904
905 static void
906 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
907 {
908 struct jme_ring *rxring = &(jme->rxring[0]);
909 struct rxdesc *rxdesc = rxring->desc;
910 struct jme_buffer_info *rxbi = rxring->bufinf;
911 struct sk_buff *skb;
912 int framesize;
913
914 rxdesc += idx;
915 rxbi += idx;
916
917 skb = rxbi->skb;
918 pci_dma_sync_single_for_cpu(jme->pdev,
919 rxbi->mapping,
920 rxbi->len,
921 PCI_DMA_FROMDEVICE);
922
923 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
924 pci_dma_sync_single_for_device(jme->pdev,
925 rxbi->mapping,
926 rxbi->len,
927 PCI_DMA_FROMDEVICE);
928
929 ++(NET_STAT(jme).rx_dropped);
930 } else {
931 framesize = le16_to_cpu(rxdesc->descwb.framesize)
932 - RX_PREPAD_SIZE;
933
934 skb_reserve(skb, RX_PREPAD_SIZE);
935 skb_put(skb, framesize);
936 skb->protocol = eth_type_trans(skb, jme->dev);
937
938 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
939 skb->ip_summed = CHECKSUM_UNNECESSARY;
940 else
941 skb_checksum_none_assert(skb);
942
943 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
944 if (jme->vlgrp) {
945 jme->jme_vlan_rx(skb, jme->vlgrp,
946 le16_to_cpu(rxdesc->descwb.vlan));
947 NET_STAT(jme).rx_bytes += 4;
948 } else {
949 dev_kfree_skb(skb);
950 }
951 } else {
952 jme->jme_rx(skb);
953 }
954
955 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
956 cpu_to_le16(RXWBFLAG_DEST_MUL))
957 ++(NET_STAT(jme).multicast);
958
959 NET_STAT(jme).rx_bytes += framesize;
960 ++(NET_STAT(jme).rx_packets);
961 }
962
963 jme_set_clean_rxdesc(jme, idx);
964
965 }
966
967 static int
968 jme_process_receive(struct jme_adapter *jme, int limit)
969 {
970 struct jme_ring *rxring = &(jme->rxring[0]);
971 struct rxdesc *rxdesc = rxring->desc;
972 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
973
974 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
975 goto out_inc;
976
977 if (unlikely(atomic_read(&jme->link_changing) != 1))
978 goto out_inc;
979
980 if (unlikely(!netif_carrier_ok(jme->dev)))
981 goto out_inc;
982
983 i = atomic_read(&rxring->next_to_clean);
984 while (limit > 0) {
985 rxdesc = rxring->desc;
986 rxdesc += i;
987
988 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
989 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
990 goto out;
991 --limit;
992
993 rmb();
994 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
995
996 if (unlikely(desccnt > 1 ||
997 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
998
999 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1000 ++(NET_STAT(jme).rx_crc_errors);
1001 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1002 ++(NET_STAT(jme).rx_fifo_errors);
1003 else
1004 ++(NET_STAT(jme).rx_errors);
1005
1006 if (desccnt > 1)
1007 limit -= desccnt - 1;
1008
1009 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1010 jme_set_clean_rxdesc(jme, j);
1011 j = (j + 1) & (mask);
1012 }
1013
1014 } else {
1015 jme_alloc_and_feed_skb(jme, i);
1016 }
1017
1018 i = (i + desccnt) & (mask);
1019 }
1020
1021 out:
1022 atomic_set(&rxring->next_to_clean, i);
1023
1024 out_inc:
1025 atomic_inc(&jme->rx_cleaning);
1026
1027 return limit > 0 ? limit : 0;
1028
1029 }
1030
1031 static void
1032 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1033 {
1034 if (likely(atmp == dpi->cur)) {
1035 dpi->cnt = 0;
1036 return;
1037 }
1038
1039 if (dpi->attempt == atmp) {
1040 ++(dpi->cnt);
1041 } else {
1042 dpi->attempt = atmp;
1043 dpi->cnt = 0;
1044 }
1045
1046 }
1047
1048 static void
1049 jme_dynamic_pcc(struct jme_adapter *jme)
1050 {
1051 register struct dynpcc_info *dpi = &(jme->dpi);
1052
1053 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1054 jme_attempt_pcc(dpi, PCC_P3);
1055 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1056 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1057 jme_attempt_pcc(dpi, PCC_P2);
1058 else
1059 jme_attempt_pcc(dpi, PCC_P1);
1060
1061 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1062 if (dpi->attempt < dpi->cur)
1063 tasklet_schedule(&jme->rxclean_task);
1064 jme_set_rx_pcc(jme, dpi->attempt);
1065 dpi->cur = dpi->attempt;
1066 dpi->cnt = 0;
1067 }
1068 }
1069
1070 static void
1071 jme_start_pcc_timer(struct jme_adapter *jme)
1072 {
1073 struct dynpcc_info *dpi = &(jme->dpi);
1074 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1075 dpi->last_pkts = NET_STAT(jme).rx_packets;
1076 dpi->intr_cnt = 0;
1077 jwrite32(jme, JME_TMCSR,
1078 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1079 }
1080
1081 static inline void
1082 jme_stop_pcc_timer(struct jme_adapter *jme)
1083 {
1084 jwrite32(jme, JME_TMCSR, 0);
1085 }
1086
1087 static void
1088 jme_shutdown_nic(struct jme_adapter *jme)
1089 {
1090 u32 phylink;
1091
1092 phylink = jme_linkstat_from_phy(jme);
1093
1094 if (!(phylink & PHY_LINK_UP)) {
1095 /*
1096 * Disable all interrupt before issue timer
1097 */
1098 jme_stop_irq(jme);
1099 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1100 }
1101 }
1102
1103 static void
1104 jme_pcc_tasklet(unsigned long arg)
1105 {
1106 struct jme_adapter *jme = (struct jme_adapter *)arg;
1107 struct net_device *netdev = jme->dev;
1108
1109 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1110 jme_shutdown_nic(jme);
1111 return;
1112 }
1113
1114 if (unlikely(!netif_carrier_ok(netdev) ||
1115 (atomic_read(&jme->link_changing) != 1)
1116 )) {
1117 jme_stop_pcc_timer(jme);
1118 return;
1119 }
1120
1121 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1122 jme_dynamic_pcc(jme);
1123
1124 jme_start_pcc_timer(jme);
1125 }
1126
1127 static inline void
1128 jme_polling_mode(struct jme_adapter *jme)
1129 {
1130 jme_set_rx_pcc(jme, PCC_OFF);
1131 }
1132
1133 static inline void
1134 jme_interrupt_mode(struct jme_adapter *jme)
1135 {
1136 jme_set_rx_pcc(jme, PCC_P1);
1137 }
1138
1139 static inline int
1140 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1141 {
1142 u32 apmc;
1143 apmc = jread32(jme, JME_APMC);
1144 return apmc & JME_APMC_PSEUDO_HP_EN;
1145 }
1146
1147 static void
1148 jme_start_shutdown_timer(struct jme_adapter *jme)
1149 {
1150 u32 apmc;
1151
1152 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1153 apmc &= ~JME_APMC_EPIEN_CTRL;
1154 if (!no_extplug) {
1155 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1156 wmb();
1157 }
1158 jwrite32f(jme, JME_APMC, apmc);
1159
1160 jwrite32f(jme, JME_TIMER2, 0);
1161 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1162 jwrite32(jme, JME_TMCSR,
1163 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1164 }
1165
1166 static void
1167 jme_stop_shutdown_timer(struct jme_adapter *jme)
1168 {
1169 u32 apmc;
1170
1171 jwrite32f(jme, JME_TMCSR, 0);
1172 jwrite32f(jme, JME_TIMER2, 0);
1173 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1174
1175 apmc = jread32(jme, JME_APMC);
1176 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1177 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1178 wmb();
1179 jwrite32f(jme, JME_APMC, apmc);
1180 }
1181
1182 static void
1183 jme_link_change_tasklet(unsigned long arg)
1184 {
1185 struct jme_adapter *jme = (struct jme_adapter *)arg;
1186 struct net_device *netdev = jme->dev;
1187 int rc;
1188
1189 while (!atomic_dec_and_test(&jme->link_changing)) {
1190 atomic_inc(&jme->link_changing);
1191 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1192 while (atomic_read(&jme->link_changing) != 1)
1193 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1194 }
1195
1196 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1197 goto out;
1198
1199 jme->old_mtu = netdev->mtu;
1200 netif_stop_queue(netdev);
1201 if (jme_pseudo_hotplug_enabled(jme))
1202 jme_stop_shutdown_timer(jme);
1203
1204 jme_stop_pcc_timer(jme);
1205 tasklet_disable(&jme->txclean_task);
1206 tasklet_disable(&jme->rxclean_task);
1207 tasklet_disable(&jme->rxempty_task);
1208
1209 if (netif_carrier_ok(netdev)) {
1210 jme_reset_ghc_speed(jme);
1211 jme_disable_rx_engine(jme);
1212 jme_disable_tx_engine(jme);
1213 jme_reset_mac_processor(jme);
1214 jme_free_rx_resources(jme);
1215 jme_free_tx_resources(jme);
1216
1217 if (test_bit(JME_FLAG_POLL, &jme->flags))
1218 jme_polling_mode(jme);
1219
1220 netif_carrier_off(netdev);
1221 }
1222
1223 jme_check_link(netdev, 0);
1224 if (netif_carrier_ok(netdev)) {
1225 rc = jme_setup_rx_resources(jme);
1226 if (rc) {
1227 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1228 goto out_enable_tasklet;
1229 }
1230
1231 rc = jme_setup_tx_resources(jme);
1232 if (rc) {
1233 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1234 goto err_out_free_rx_resources;
1235 }
1236
1237 jme_enable_rx_engine(jme);
1238 jme_enable_tx_engine(jme);
1239
1240 netif_start_queue(netdev);
1241
1242 if (test_bit(JME_FLAG_POLL, &jme->flags))
1243 jme_interrupt_mode(jme);
1244
1245 jme_start_pcc_timer(jme);
1246 } else if (jme_pseudo_hotplug_enabled(jme)) {
1247 jme_start_shutdown_timer(jme);
1248 }
1249
1250 goto out_enable_tasklet;
1251
1252 err_out_free_rx_resources:
1253 jme_free_rx_resources(jme);
1254 out_enable_tasklet:
1255 tasklet_enable(&jme->txclean_task);
1256 tasklet_hi_enable(&jme->rxclean_task);
1257 tasklet_hi_enable(&jme->rxempty_task);
1258 out:
1259 atomic_inc(&jme->link_changing);
1260 }
1261
1262 static void
1263 jme_rx_clean_tasklet(unsigned long arg)
1264 {
1265 struct jme_adapter *jme = (struct jme_adapter *)arg;
1266 struct dynpcc_info *dpi = &(jme->dpi);
1267
1268 jme_process_receive(jme, jme->rx_ring_size);
1269 ++(dpi->intr_cnt);
1270
1271 }
1272
1273 static int
1274 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1275 {
1276 struct jme_adapter *jme = jme_napi_priv(holder);
1277 int rest;
1278
1279 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1280
1281 while (atomic_read(&jme->rx_empty) > 0) {
1282 atomic_dec(&jme->rx_empty);
1283 ++(NET_STAT(jme).rx_dropped);
1284 jme_restart_rx_engine(jme);
1285 }
1286 atomic_inc(&jme->rx_empty);
1287
1288 if (rest) {
1289 JME_RX_COMPLETE(netdev, holder);
1290 jme_interrupt_mode(jme);
1291 }
1292
1293 JME_NAPI_WEIGHT_SET(budget, rest);
1294 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1295 }
1296
1297 static void
1298 jme_rx_empty_tasklet(unsigned long arg)
1299 {
1300 struct jme_adapter *jme = (struct jme_adapter *)arg;
1301
1302 if (unlikely(atomic_read(&jme->link_changing) != 1))
1303 return;
1304
1305 if (unlikely(!netif_carrier_ok(jme->dev)))
1306 return;
1307
1308 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1309
1310 jme_rx_clean_tasklet(arg);
1311
1312 while (atomic_read(&jme->rx_empty) > 0) {
1313 atomic_dec(&jme->rx_empty);
1314 ++(NET_STAT(jme).rx_dropped);
1315 jme_restart_rx_engine(jme);
1316 }
1317 atomic_inc(&jme->rx_empty);
1318 }
1319
1320 static void
1321 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1322 {
1323 struct jme_ring *txring = &(jme->txring[0]);
1324
1325 smp_wmb();
1326 if (unlikely(netif_queue_stopped(jme->dev) &&
1327 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1328 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1329 netif_wake_queue(jme->dev);
1330 }
1331
1332 }
1333
1334 static void
1335 jme_tx_clean_tasklet(unsigned long arg)
1336 {
1337 struct jme_adapter *jme = (struct jme_adapter *)arg;
1338 struct jme_ring *txring = &(jme->txring[0]);
1339 struct txdesc *txdesc = txring->desc;
1340 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1341 int i, j, cnt = 0, max, err, mask;
1342
1343 tx_dbg(jme, "Into txclean\n");
1344
1345 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1346 goto out;
1347
1348 if (unlikely(atomic_read(&jme->link_changing) != 1))
1349 goto out;
1350
1351 if (unlikely(!netif_carrier_ok(jme->dev)))
1352 goto out;
1353
1354 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1355 mask = jme->tx_ring_mask;
1356
1357 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1358
1359 ctxbi = txbi + i;
1360
1361 if (likely(ctxbi->skb &&
1362 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1363
1364 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1365 i, ctxbi->nr_desc, jiffies);
1366
1367 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1368
1369 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1370 ttxbi = txbi + ((i + j) & (mask));
1371 txdesc[(i + j) & (mask)].dw[0] = 0;
1372
1373 pci_unmap_page(jme->pdev,
1374 ttxbi->mapping,
1375 ttxbi->len,
1376 PCI_DMA_TODEVICE);
1377
1378 ttxbi->mapping = 0;
1379 ttxbi->len = 0;
1380 }
1381
1382 dev_kfree_skb(ctxbi->skb);
1383
1384 cnt += ctxbi->nr_desc;
1385
1386 if (unlikely(err)) {
1387 ++(NET_STAT(jme).tx_carrier_errors);
1388 } else {
1389 ++(NET_STAT(jme).tx_packets);
1390 NET_STAT(jme).tx_bytes += ctxbi->len;
1391 }
1392
1393 ctxbi->skb = NULL;
1394 ctxbi->len = 0;
1395 ctxbi->start_xmit = 0;
1396
1397 } else {
1398 break;
1399 }
1400
1401 i = (i + ctxbi->nr_desc) & mask;
1402
1403 ctxbi->nr_desc = 0;
1404 }
1405
1406 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1407 atomic_set(&txring->next_to_clean, i);
1408 atomic_add(cnt, &txring->nr_free);
1409
1410 jme_wake_queue_if_stopped(jme);
1411
1412 out:
1413 atomic_inc(&jme->tx_cleaning);
1414 }
1415
1416 static void
1417 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1418 {
1419 /*
1420 * Disable interrupt
1421 */
1422 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1423
1424 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1425 /*
1426 * Link change event is critical
1427 * all other events are ignored
1428 */
1429 jwrite32(jme, JME_IEVE, intrstat);
1430 tasklet_schedule(&jme->linkch_task);
1431 goto out_reenable;
1432 }
1433
1434 if (intrstat & INTR_TMINTR) {
1435 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1436 tasklet_schedule(&jme->pcc_task);
1437 }
1438
1439 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1440 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1441 tasklet_schedule(&jme->txclean_task);
1442 }
1443
1444 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1445 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1446 INTR_PCCRX0 |
1447 INTR_RX0EMP)) |
1448 INTR_RX0);
1449 }
1450
1451 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1452 if (intrstat & INTR_RX0EMP)
1453 atomic_inc(&jme->rx_empty);
1454
1455 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1456 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1457 jme_polling_mode(jme);
1458 JME_RX_SCHEDULE(jme);
1459 }
1460 }
1461 } else {
1462 if (intrstat & INTR_RX0EMP) {
1463 atomic_inc(&jme->rx_empty);
1464 tasklet_hi_schedule(&jme->rxempty_task);
1465 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1466 tasklet_hi_schedule(&jme->rxclean_task);
1467 }
1468 }
1469
1470 out_reenable:
1471 /*
1472 * Re-enable interrupt
1473 */
1474 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1475 }
1476
1477 static irqreturn_t
1478 jme_intr(int irq, void *dev_id)
1479 {
1480 struct net_device *netdev = dev_id;
1481 struct jme_adapter *jme = netdev_priv(netdev);
1482 u32 intrstat;
1483
1484 intrstat = jread32(jme, JME_IEVE);
1485
1486 /*
1487 * Check if it's really an interrupt for us
1488 */
1489 if (unlikely((intrstat & INTR_ENABLE) == 0))
1490 return IRQ_NONE;
1491
1492 /*
1493 * Check if the device still exist
1494 */
1495 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1496 return IRQ_NONE;
1497
1498 jme_intr_msi(jme, intrstat);
1499
1500 return IRQ_HANDLED;
1501 }
1502
1503 static irqreturn_t
1504 jme_msi(int irq, void *dev_id)
1505 {
1506 struct net_device *netdev = dev_id;
1507 struct jme_adapter *jme = netdev_priv(netdev);
1508 u32 intrstat;
1509
1510 intrstat = jread32(jme, JME_IEVE);
1511
1512 jme_intr_msi(jme, intrstat);
1513
1514 return IRQ_HANDLED;
1515 }
1516
1517 static void
1518 jme_reset_link(struct jme_adapter *jme)
1519 {
1520 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1521 }
1522
1523 static void
1524 jme_restart_an(struct jme_adapter *jme)
1525 {
1526 u32 bmcr;
1527
1528 spin_lock_bh(&jme->phy_lock);
1529 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1530 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1531 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1532 spin_unlock_bh(&jme->phy_lock);
1533 }
1534
1535 static int
1536 jme_request_irq(struct jme_adapter *jme)
1537 {
1538 int rc;
1539 struct net_device *netdev = jme->dev;
1540 irq_handler_t handler = jme_intr;
1541 int irq_flags = IRQF_SHARED;
1542
1543 if (!pci_enable_msi(jme->pdev)) {
1544 set_bit(JME_FLAG_MSI, &jme->flags);
1545 handler = jme_msi;
1546 irq_flags = 0;
1547 }
1548
1549 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1550 netdev);
1551 if (rc) {
1552 netdev_err(netdev,
1553 "Unable to request %s interrupt (return: %d)\n",
1554 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1555 rc);
1556
1557 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1558 pci_disable_msi(jme->pdev);
1559 clear_bit(JME_FLAG_MSI, &jme->flags);
1560 }
1561 } else {
1562 netdev->irq = jme->pdev->irq;
1563 }
1564
1565 return rc;
1566 }
1567
1568 static void
1569 jme_free_irq(struct jme_adapter *jme)
1570 {
1571 free_irq(jme->pdev->irq, jme->dev);
1572 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1573 pci_disable_msi(jme->pdev);
1574 clear_bit(JME_FLAG_MSI, &jme->flags);
1575 jme->dev->irq = jme->pdev->irq;
1576 }
1577 }
1578
1579 static inline void
1580 jme_phy_on(struct jme_adapter *jme)
1581 {
1582 u32 bmcr;
1583
1584 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1585 bmcr &= ~BMCR_PDOWN;
1586 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1587 }
1588
1589 static int
1590 jme_open(struct net_device *netdev)
1591 {
1592 struct jme_adapter *jme = netdev_priv(netdev);
1593 int rc;
1594
1595 jme_clear_pm(jme);
1596 JME_NAPI_ENABLE(jme);
1597
1598 tasklet_enable(&jme->linkch_task);
1599 tasklet_enable(&jme->txclean_task);
1600 tasklet_hi_enable(&jme->rxclean_task);
1601 tasklet_hi_enable(&jme->rxempty_task);
1602
1603 rc = jme_request_irq(jme);
1604 if (rc)
1605 goto err_out;
1606
1607 jme_start_irq(jme);
1608
1609 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1610 jme_phy_on(jme);
1611 jme_set_settings(netdev, &jme->old_ecmd);
1612 } else {
1613 jme_reset_phy_processor(jme);
1614 }
1615
1616 jme_reset_link(jme);
1617
1618 return 0;
1619
1620 err_out:
1621 netif_stop_queue(netdev);
1622 netif_carrier_off(netdev);
1623 return rc;
1624 }
1625
1626 #ifdef CONFIG_PM
1627 static void
1628 jme_set_100m_half(struct jme_adapter *jme)
1629 {
1630 u32 bmcr, tmp;
1631
1632 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1633 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1634 BMCR_SPEED1000 | BMCR_FULLDPLX);
1635 tmp |= BMCR_SPEED100;
1636
1637 if (bmcr != tmp)
1638 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1639
1640 if (jme->fpgaver)
1641 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1642 else
1643 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1644 }
1645
1646 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1647 static void
1648 jme_wait_link(struct jme_adapter *jme)
1649 {
1650 u32 phylink, to = JME_WAIT_LINK_TIME;
1651
1652 mdelay(1000);
1653 phylink = jme_linkstat_from_phy(jme);
1654 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1655 mdelay(10);
1656 phylink = jme_linkstat_from_phy(jme);
1657 }
1658 }
1659 #endif
1660
1661 static inline void
1662 jme_phy_off(struct jme_adapter *jme)
1663 {
1664 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1665 }
1666
1667 static int
1668 jme_close(struct net_device *netdev)
1669 {
1670 struct jme_adapter *jme = netdev_priv(netdev);
1671
1672 netif_stop_queue(netdev);
1673 netif_carrier_off(netdev);
1674
1675 jme_stop_irq(jme);
1676 jme_free_irq(jme);
1677
1678 JME_NAPI_DISABLE(jme);
1679
1680 tasklet_disable(&jme->linkch_task);
1681 tasklet_disable(&jme->txclean_task);
1682 tasklet_disable(&jme->rxclean_task);
1683 tasklet_disable(&jme->rxempty_task);
1684
1685 jme_reset_ghc_speed(jme);
1686 jme_disable_rx_engine(jme);
1687 jme_disable_tx_engine(jme);
1688 jme_reset_mac_processor(jme);
1689 jme_free_rx_resources(jme);
1690 jme_free_tx_resources(jme);
1691 jme->phylink = 0;
1692 jme_phy_off(jme);
1693
1694 return 0;
1695 }
1696
1697 static int
1698 jme_alloc_txdesc(struct jme_adapter *jme,
1699 struct sk_buff *skb)
1700 {
1701 struct jme_ring *txring = &(jme->txring[0]);
1702 int idx, nr_alloc, mask = jme->tx_ring_mask;
1703
1704 idx = txring->next_to_use;
1705 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1706
1707 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1708 return -1;
1709
1710 atomic_sub(nr_alloc, &txring->nr_free);
1711
1712 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1713
1714 return idx;
1715 }
1716
1717 static void
1718 jme_fill_tx_map(struct pci_dev *pdev,
1719 struct txdesc *txdesc,
1720 struct jme_buffer_info *txbi,
1721 struct page *page,
1722 u32 page_offset,
1723 u32 len,
1724 u8 hidma)
1725 {
1726 dma_addr_t dmaaddr;
1727
1728 dmaaddr = pci_map_page(pdev,
1729 page,
1730 page_offset,
1731 len,
1732 PCI_DMA_TODEVICE);
1733
1734 pci_dma_sync_single_for_device(pdev,
1735 dmaaddr,
1736 len,
1737 PCI_DMA_TODEVICE);
1738
1739 txdesc->dw[0] = 0;
1740 txdesc->dw[1] = 0;
1741 txdesc->desc2.flags = TXFLAG_OWN;
1742 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1743 txdesc->desc2.datalen = cpu_to_le16(len);
1744 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1745 txdesc->desc2.bufaddrl = cpu_to_le32(
1746 (__u64)dmaaddr & 0xFFFFFFFFUL);
1747
1748 txbi->mapping = dmaaddr;
1749 txbi->len = len;
1750 }
1751
1752 static void
1753 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1754 {
1755 struct jme_ring *txring = &(jme->txring[0]);
1756 struct txdesc *txdesc = txring->desc, *ctxdesc;
1757 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1758 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1759 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1760 int mask = jme->tx_ring_mask;
1761 struct skb_frag_struct *frag;
1762 u32 len;
1763
1764 for (i = 0 ; i < nr_frags ; ++i) {
1765 frag = &skb_shinfo(skb)->frags[i];
1766 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1767 ctxbi = txbi + ((idx + i + 2) & (mask));
1768
1769 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1770 frag->page_offset, frag->size, hidma);
1771 }
1772
1773 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1774 ctxdesc = txdesc + ((idx + 1) & (mask));
1775 ctxbi = txbi + ((idx + 1) & (mask));
1776 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1777 offset_in_page(skb->data), len, hidma);
1778
1779 }
1780
1781 static int
1782 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1783 {
1784 if (unlikely(skb_shinfo(skb)->gso_size &&
1785 skb_header_cloned(skb) &&
1786 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1787 dev_kfree_skb(skb);
1788 return -1;
1789 }
1790
1791 return 0;
1792 }
1793
1794 static int
1795 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1796 {
1797 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1798 if (*mss) {
1799 *flags |= TXFLAG_LSEN;
1800
1801 if (skb->protocol == htons(ETH_P_IP)) {
1802 struct iphdr *iph = ip_hdr(skb);
1803
1804 iph->check = 0;
1805 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1806 iph->daddr, 0,
1807 IPPROTO_TCP,
1808 0);
1809 } else {
1810 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1811
1812 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1813 &ip6h->daddr, 0,
1814 IPPROTO_TCP,
1815 0);
1816 }
1817
1818 return 0;
1819 }
1820
1821 return 1;
1822 }
1823
1824 static void
1825 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1826 {
1827 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1828 u8 ip_proto;
1829
1830 switch (skb->protocol) {
1831 case htons(ETH_P_IP):
1832 ip_proto = ip_hdr(skb)->protocol;
1833 break;
1834 case htons(ETH_P_IPV6):
1835 ip_proto = ipv6_hdr(skb)->nexthdr;
1836 break;
1837 default:
1838 ip_proto = 0;
1839 break;
1840 }
1841
1842 switch (ip_proto) {
1843 case IPPROTO_TCP:
1844 *flags |= TXFLAG_TCPCS;
1845 break;
1846 case IPPROTO_UDP:
1847 *flags |= TXFLAG_UDPCS;
1848 break;
1849 default:
1850 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1851 break;
1852 }
1853 }
1854 }
1855
1856 static inline void
1857 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1858 {
1859 if (vlan_tx_tag_present(skb)) {
1860 *flags |= TXFLAG_TAGON;
1861 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1862 }
1863 }
1864
1865 static int
1866 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1867 {
1868 struct jme_ring *txring = &(jme->txring[0]);
1869 struct txdesc *txdesc;
1870 struct jme_buffer_info *txbi;
1871 u8 flags;
1872
1873 txdesc = (struct txdesc *)txring->desc + idx;
1874 txbi = txring->bufinf + idx;
1875
1876 txdesc->dw[0] = 0;
1877 txdesc->dw[1] = 0;
1878 txdesc->dw[2] = 0;
1879 txdesc->dw[3] = 0;
1880 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1881 /*
1882 * Set OWN bit at final.
1883 * When kernel transmit faster than NIC.
1884 * And NIC trying to send this descriptor before we tell
1885 * it to start sending this TX queue.
1886 * Other fields are already filled correctly.
1887 */
1888 wmb();
1889 flags = TXFLAG_OWN | TXFLAG_INT;
1890 /*
1891 * Set checksum flags while not tso
1892 */
1893 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1894 jme_tx_csum(jme, skb, &flags);
1895 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1896 jme_map_tx_skb(jme, skb, idx);
1897 txdesc->desc1.flags = flags;
1898 /*
1899 * Set tx buffer info after telling NIC to send
1900 * For better tx_clean timing
1901 */
1902 wmb();
1903 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1904 txbi->skb = skb;
1905 txbi->len = skb->len;
1906 txbi->start_xmit = jiffies;
1907 if (!txbi->start_xmit)
1908 txbi->start_xmit = (0UL-1);
1909
1910 return 0;
1911 }
1912
1913 static void
1914 jme_stop_queue_if_full(struct jme_adapter *jme)
1915 {
1916 struct jme_ring *txring = &(jme->txring[0]);
1917 struct jme_buffer_info *txbi = txring->bufinf;
1918 int idx = atomic_read(&txring->next_to_clean);
1919
1920 txbi += idx;
1921
1922 smp_wmb();
1923 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1924 netif_stop_queue(jme->dev);
1925 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1926 smp_wmb();
1927 if (atomic_read(&txring->nr_free)
1928 >= (jme->tx_wake_threshold)) {
1929 netif_wake_queue(jme->dev);
1930 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1931 }
1932 }
1933
1934 if (unlikely(txbi->start_xmit &&
1935 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1936 txbi->skb)) {
1937 netif_stop_queue(jme->dev);
1938 netif_info(jme, tx_queued, jme->dev,
1939 "TX Queue Stopped %d@%lu\n", idx, jiffies);
1940 }
1941 }
1942
1943 /*
1944 * This function is already protected by netif_tx_lock()
1945 */
1946
1947 static netdev_tx_t
1948 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1949 {
1950 struct jme_adapter *jme = netdev_priv(netdev);
1951 int idx;
1952
1953 if (unlikely(jme_expand_header(jme, skb))) {
1954 ++(NET_STAT(jme).tx_dropped);
1955 return NETDEV_TX_OK;
1956 }
1957
1958 idx = jme_alloc_txdesc(jme, skb);
1959
1960 if (unlikely(idx < 0)) {
1961 netif_stop_queue(netdev);
1962 netif_err(jme, tx_err, jme->dev,
1963 "BUG! Tx ring full when queue awake!\n");
1964
1965 return NETDEV_TX_BUSY;
1966 }
1967
1968 jme_fill_tx_desc(jme, skb, idx);
1969
1970 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1971 TXCS_SELECT_QUEUE0 |
1972 TXCS_QUEUE0S |
1973 TXCS_ENABLE);
1974
1975 tx_dbg(jme, "xmit: %d+%d@%lu\n",
1976 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
1977 jme_stop_queue_if_full(jme);
1978
1979 return NETDEV_TX_OK;
1980 }
1981
1982 static int
1983 jme_set_macaddr(struct net_device *netdev, void *p)
1984 {
1985 struct jme_adapter *jme = netdev_priv(netdev);
1986 struct sockaddr *addr = p;
1987 u32 val;
1988
1989 if (netif_running(netdev))
1990 return -EBUSY;
1991
1992 spin_lock_bh(&jme->macaddr_lock);
1993 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1994
1995 val = (addr->sa_data[3] & 0xff) << 24 |
1996 (addr->sa_data[2] & 0xff) << 16 |
1997 (addr->sa_data[1] & 0xff) << 8 |
1998 (addr->sa_data[0] & 0xff);
1999 jwrite32(jme, JME_RXUMA_LO, val);
2000 val = (addr->sa_data[5] & 0xff) << 8 |
2001 (addr->sa_data[4] & 0xff);
2002 jwrite32(jme, JME_RXUMA_HI, val);
2003 spin_unlock_bh(&jme->macaddr_lock);
2004
2005 return 0;
2006 }
2007
2008 static void
2009 jme_set_multi(struct net_device *netdev)
2010 {
2011 struct jme_adapter *jme = netdev_priv(netdev);
2012 u32 mc_hash[2] = {};
2013
2014 spin_lock_bh(&jme->rxmcs_lock);
2015
2016 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2017
2018 if (netdev->flags & IFF_PROMISC) {
2019 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2020 } else if (netdev->flags & IFF_ALLMULTI) {
2021 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2022 } else if (netdev->flags & IFF_MULTICAST) {
2023 struct netdev_hw_addr *ha;
2024 int bit_nr;
2025
2026 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2027 netdev_for_each_mc_addr(ha, netdev) {
2028 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2029 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2030 }
2031
2032 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2033 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2034 }
2035
2036 wmb();
2037 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2038
2039 spin_unlock_bh(&jme->rxmcs_lock);
2040 }
2041
2042 static int
2043 jme_change_mtu(struct net_device *netdev, int new_mtu)
2044 {
2045 struct jme_adapter *jme = netdev_priv(netdev);
2046
2047 if (new_mtu == jme->old_mtu)
2048 return 0;
2049
2050 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2051 ((new_mtu) < IPV6_MIN_MTU))
2052 return -EINVAL;
2053
2054 if (new_mtu > 4000) {
2055 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2056 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2057 jme_restart_rx_engine(jme);
2058 } else {
2059 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2060 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2061 jme_restart_rx_engine(jme);
2062 }
2063
2064 if (new_mtu > 1900) {
2065 netdev->features &= ~(NETIF_F_HW_CSUM |
2066 NETIF_F_TSO |
2067 NETIF_F_TSO6);
2068 } else {
2069 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2070 netdev->features |= NETIF_F_HW_CSUM;
2071 if (test_bit(JME_FLAG_TSO, &jme->flags))
2072 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2073 }
2074
2075 netdev->mtu = new_mtu;
2076 jme_reset_link(jme);
2077
2078 return 0;
2079 }
2080
2081 static void
2082 jme_tx_timeout(struct net_device *netdev)
2083 {
2084 struct jme_adapter *jme = netdev_priv(netdev);
2085
2086 jme->phylink = 0;
2087 jme_reset_phy_processor(jme);
2088 if (test_bit(JME_FLAG_SSET, &jme->flags))
2089 jme_set_settings(netdev, &jme->old_ecmd);
2090
2091 /*
2092 * Force to Reset the link again
2093 */
2094 jme_reset_link(jme);
2095 }
2096
2097 static inline void jme_pause_rx(struct jme_adapter *jme)
2098 {
2099 atomic_dec(&jme->link_changing);
2100
2101 jme_set_rx_pcc(jme, PCC_OFF);
2102 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2103 JME_NAPI_DISABLE(jme);
2104 } else {
2105 tasklet_disable(&jme->rxclean_task);
2106 tasklet_disable(&jme->rxempty_task);
2107 }
2108 }
2109
2110 static inline void jme_resume_rx(struct jme_adapter *jme)
2111 {
2112 struct dynpcc_info *dpi = &(jme->dpi);
2113
2114 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2115 JME_NAPI_ENABLE(jme);
2116 } else {
2117 tasklet_hi_enable(&jme->rxclean_task);
2118 tasklet_hi_enable(&jme->rxempty_task);
2119 }
2120 dpi->cur = PCC_P1;
2121 dpi->attempt = PCC_P1;
2122 dpi->cnt = 0;
2123 jme_set_rx_pcc(jme, PCC_P1);
2124
2125 atomic_inc(&jme->link_changing);
2126 }
2127
2128 static void
2129 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2130 {
2131 struct jme_adapter *jme = netdev_priv(netdev);
2132
2133 jme_pause_rx(jme);
2134 jme->vlgrp = grp;
2135 jme_resume_rx(jme);
2136 }
2137
2138 static void
2139 jme_get_drvinfo(struct net_device *netdev,
2140 struct ethtool_drvinfo *info)
2141 {
2142 struct jme_adapter *jme = netdev_priv(netdev);
2143
2144 strcpy(info->driver, DRV_NAME);
2145 strcpy(info->version, DRV_VERSION);
2146 strcpy(info->bus_info, pci_name(jme->pdev));
2147 }
2148
2149 static int
2150 jme_get_regs_len(struct net_device *netdev)
2151 {
2152 return JME_REG_LEN;
2153 }
2154
2155 static void
2156 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2157 {
2158 int i;
2159
2160 for (i = 0 ; i < len ; i += 4)
2161 p[i >> 2] = jread32(jme, reg + i);
2162 }
2163
2164 static void
2165 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2166 {
2167 int i;
2168 u16 *p16 = (u16 *)p;
2169
2170 for (i = 0 ; i < reg_nr ; ++i)
2171 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2172 }
2173
2174 static void
2175 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2176 {
2177 struct jme_adapter *jme = netdev_priv(netdev);
2178 u32 *p32 = (u32 *)p;
2179
2180 memset(p, 0xFF, JME_REG_LEN);
2181
2182 regs->version = 1;
2183 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2184
2185 p32 += 0x100 >> 2;
2186 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2187
2188 p32 += 0x100 >> 2;
2189 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2190
2191 p32 += 0x100 >> 2;
2192 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2193
2194 p32 += 0x100 >> 2;
2195 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2196 }
2197
2198 static int
2199 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2200 {
2201 struct jme_adapter *jme = netdev_priv(netdev);
2202
2203 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2204 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2205
2206 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2207 ecmd->use_adaptive_rx_coalesce = false;
2208 ecmd->rx_coalesce_usecs = 0;
2209 ecmd->rx_max_coalesced_frames = 0;
2210 return 0;
2211 }
2212
2213 ecmd->use_adaptive_rx_coalesce = true;
2214
2215 switch (jme->dpi.cur) {
2216 case PCC_P1:
2217 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2218 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2219 break;
2220 case PCC_P2:
2221 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2222 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2223 break;
2224 case PCC_P3:
2225 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2226 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2227 break;
2228 default:
2229 break;
2230 }
2231
2232 return 0;
2233 }
2234
2235 static int
2236 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2237 {
2238 struct jme_adapter *jme = netdev_priv(netdev);
2239 struct dynpcc_info *dpi = &(jme->dpi);
2240
2241 if (netif_running(netdev))
2242 return -EBUSY;
2243
2244 if (ecmd->use_adaptive_rx_coalesce &&
2245 test_bit(JME_FLAG_POLL, &jme->flags)) {
2246 clear_bit(JME_FLAG_POLL, &jme->flags);
2247 jme->jme_rx = netif_rx;
2248 jme->jme_vlan_rx = vlan_hwaccel_rx;
2249 dpi->cur = PCC_P1;
2250 dpi->attempt = PCC_P1;
2251 dpi->cnt = 0;
2252 jme_set_rx_pcc(jme, PCC_P1);
2253 jme_interrupt_mode(jme);
2254 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2255 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2256 set_bit(JME_FLAG_POLL, &jme->flags);
2257 jme->jme_rx = netif_receive_skb;
2258 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2259 jme_interrupt_mode(jme);
2260 }
2261
2262 return 0;
2263 }
2264
2265 static void
2266 jme_get_pauseparam(struct net_device *netdev,
2267 struct ethtool_pauseparam *ecmd)
2268 {
2269 struct jme_adapter *jme = netdev_priv(netdev);
2270 u32 val;
2271
2272 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2273 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2274
2275 spin_lock_bh(&jme->phy_lock);
2276 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2277 spin_unlock_bh(&jme->phy_lock);
2278
2279 ecmd->autoneg =
2280 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2281 }
2282
2283 static int
2284 jme_set_pauseparam(struct net_device *netdev,
2285 struct ethtool_pauseparam *ecmd)
2286 {
2287 struct jme_adapter *jme = netdev_priv(netdev);
2288 u32 val;
2289
2290 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2291 (ecmd->tx_pause != 0)) {
2292
2293 if (ecmd->tx_pause)
2294 jme->reg_txpfc |= TXPFC_PF_EN;
2295 else
2296 jme->reg_txpfc &= ~TXPFC_PF_EN;
2297
2298 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2299 }
2300
2301 spin_lock_bh(&jme->rxmcs_lock);
2302 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2303 (ecmd->rx_pause != 0)) {
2304
2305 if (ecmd->rx_pause)
2306 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2307 else
2308 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2309
2310 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2311 }
2312 spin_unlock_bh(&jme->rxmcs_lock);
2313
2314 spin_lock_bh(&jme->phy_lock);
2315 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2316 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2317 (ecmd->autoneg != 0)) {
2318
2319 if (ecmd->autoneg)
2320 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2321 else
2322 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2323
2324 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2325 MII_ADVERTISE, val);
2326 }
2327 spin_unlock_bh(&jme->phy_lock);
2328
2329 return 0;
2330 }
2331
2332 static void
2333 jme_get_wol(struct net_device *netdev,
2334 struct ethtool_wolinfo *wol)
2335 {
2336 struct jme_adapter *jme = netdev_priv(netdev);
2337
2338 wol->supported = WAKE_MAGIC | WAKE_PHY;
2339
2340 wol->wolopts = 0;
2341
2342 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2343 wol->wolopts |= WAKE_PHY;
2344
2345 if (jme->reg_pmcs & PMCS_MFEN)
2346 wol->wolopts |= WAKE_MAGIC;
2347
2348 }
2349
2350 static int
2351 jme_set_wol(struct net_device *netdev,
2352 struct ethtool_wolinfo *wol)
2353 {
2354 struct jme_adapter *jme = netdev_priv(netdev);
2355
2356 if (wol->wolopts & (WAKE_MAGICSECURE |
2357 WAKE_UCAST |
2358 WAKE_MCAST |
2359 WAKE_BCAST |
2360 WAKE_ARP))
2361 return -EOPNOTSUPP;
2362
2363 jme->reg_pmcs = 0;
2364
2365 if (wol->wolopts & WAKE_PHY)
2366 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2367
2368 if (wol->wolopts & WAKE_MAGIC)
2369 jme->reg_pmcs |= PMCS_MFEN;
2370
2371 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2372
2373 return 0;
2374 }
2375
2376 static int
2377 jme_get_settings(struct net_device *netdev,
2378 struct ethtool_cmd *ecmd)
2379 {
2380 struct jme_adapter *jme = netdev_priv(netdev);
2381 int rc;
2382
2383 spin_lock_bh(&jme->phy_lock);
2384 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2385 spin_unlock_bh(&jme->phy_lock);
2386 return rc;
2387 }
2388
2389 static int
2390 jme_set_settings(struct net_device *netdev,
2391 struct ethtool_cmd *ecmd)
2392 {
2393 struct jme_adapter *jme = netdev_priv(netdev);
2394 int rc, fdc = 0;
2395
2396 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2397 return -EINVAL;
2398
2399 /*
2400 * Check If user changed duplex only while force_media.
2401 * Hardware would not generate link change interrupt.
2402 */
2403 if (jme->mii_if.force_media &&
2404 ecmd->autoneg != AUTONEG_ENABLE &&
2405 (jme->mii_if.full_duplex != ecmd->duplex))
2406 fdc = 1;
2407
2408 spin_lock_bh(&jme->phy_lock);
2409 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2410 spin_unlock_bh(&jme->phy_lock);
2411
2412 if (!rc) {
2413 if (fdc)
2414 jme_reset_link(jme);
2415 jme->old_ecmd = *ecmd;
2416 set_bit(JME_FLAG_SSET, &jme->flags);
2417 }
2418
2419 return rc;
2420 }
2421
2422 static int
2423 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2424 {
2425 int rc;
2426 struct jme_adapter *jme = netdev_priv(netdev);
2427 struct mii_ioctl_data *mii_data = if_mii(rq);
2428 unsigned int duplex_chg;
2429
2430 if (cmd == SIOCSMIIREG) {
2431 u16 val = mii_data->val_in;
2432 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2433 (val & BMCR_SPEED1000))
2434 return -EINVAL;
2435 }
2436
2437 spin_lock_bh(&jme->phy_lock);
2438 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2439 spin_unlock_bh(&jme->phy_lock);
2440
2441 if (!rc && (cmd == SIOCSMIIREG)) {
2442 if (duplex_chg)
2443 jme_reset_link(jme);
2444 jme_get_settings(netdev, &jme->old_ecmd);
2445 set_bit(JME_FLAG_SSET, &jme->flags);
2446 }
2447
2448 return rc;
2449 }
2450
2451 static u32
2452 jme_get_link(struct net_device *netdev)
2453 {
2454 struct jme_adapter *jme = netdev_priv(netdev);
2455 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2456 }
2457
2458 static u32
2459 jme_get_msglevel(struct net_device *netdev)
2460 {
2461 struct jme_adapter *jme = netdev_priv(netdev);
2462 return jme->msg_enable;
2463 }
2464
2465 static void
2466 jme_set_msglevel(struct net_device *netdev, u32 value)
2467 {
2468 struct jme_adapter *jme = netdev_priv(netdev);
2469 jme->msg_enable = value;
2470 }
2471
2472 static u32
2473 jme_get_rx_csum(struct net_device *netdev)
2474 {
2475 struct jme_adapter *jme = netdev_priv(netdev);
2476 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2477 }
2478
2479 static int
2480 jme_set_rx_csum(struct net_device *netdev, u32 on)
2481 {
2482 struct jme_adapter *jme = netdev_priv(netdev);
2483
2484 spin_lock_bh(&jme->rxmcs_lock);
2485 if (on)
2486 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2487 else
2488 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2489 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2490 spin_unlock_bh(&jme->rxmcs_lock);
2491
2492 return 0;
2493 }
2494
2495 static int
2496 jme_set_tx_csum(struct net_device *netdev, u32 on)
2497 {
2498 struct jme_adapter *jme = netdev_priv(netdev);
2499
2500 if (on) {
2501 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2502 if (netdev->mtu <= 1900)
2503 netdev->features |= NETIF_F_HW_CSUM;
2504 } else {
2505 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2506 netdev->features &= ~NETIF_F_HW_CSUM;
2507 }
2508
2509 return 0;
2510 }
2511
2512 static int
2513 jme_set_tso(struct net_device *netdev, u32 on)
2514 {
2515 struct jme_adapter *jme = netdev_priv(netdev);
2516
2517 if (on) {
2518 set_bit(JME_FLAG_TSO, &jme->flags);
2519 if (netdev->mtu <= 1900)
2520 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2521 } else {
2522 clear_bit(JME_FLAG_TSO, &jme->flags);
2523 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2524 }
2525
2526 return 0;
2527 }
2528
2529 static int
2530 jme_nway_reset(struct net_device *netdev)
2531 {
2532 struct jme_adapter *jme = netdev_priv(netdev);
2533 jme_restart_an(jme);
2534 return 0;
2535 }
2536
2537 static u8
2538 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2539 {
2540 u32 val;
2541 int to;
2542
2543 val = jread32(jme, JME_SMBCSR);
2544 to = JME_SMB_BUSY_TIMEOUT;
2545 while ((val & SMBCSR_BUSY) && --to) {
2546 msleep(1);
2547 val = jread32(jme, JME_SMBCSR);
2548 }
2549 if (!to) {
2550 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2551 return 0xFF;
2552 }
2553
2554 jwrite32(jme, JME_SMBINTF,
2555 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2556 SMBINTF_HWRWN_READ |
2557 SMBINTF_HWCMD);
2558
2559 val = jread32(jme, JME_SMBINTF);
2560 to = JME_SMB_BUSY_TIMEOUT;
2561 while ((val & SMBINTF_HWCMD) && --to) {
2562 msleep(1);
2563 val = jread32(jme, JME_SMBINTF);
2564 }
2565 if (!to) {
2566 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2567 return 0xFF;
2568 }
2569
2570 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2571 }
2572
2573 static void
2574 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2575 {
2576 u32 val;
2577 int to;
2578
2579 val = jread32(jme, JME_SMBCSR);
2580 to = JME_SMB_BUSY_TIMEOUT;
2581 while ((val & SMBCSR_BUSY) && --to) {
2582 msleep(1);
2583 val = jread32(jme, JME_SMBCSR);
2584 }
2585 if (!to) {
2586 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2587 return;
2588 }
2589
2590 jwrite32(jme, JME_SMBINTF,
2591 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2592 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2593 SMBINTF_HWRWN_WRITE |
2594 SMBINTF_HWCMD);
2595
2596 val = jread32(jme, JME_SMBINTF);
2597 to = JME_SMB_BUSY_TIMEOUT;
2598 while ((val & SMBINTF_HWCMD) && --to) {
2599 msleep(1);
2600 val = jread32(jme, JME_SMBINTF);
2601 }
2602 if (!to) {
2603 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2604 return;
2605 }
2606
2607 mdelay(2);
2608 }
2609
2610 static int
2611 jme_get_eeprom_len(struct net_device *netdev)
2612 {
2613 struct jme_adapter *jme = netdev_priv(netdev);
2614 u32 val;
2615 val = jread32(jme, JME_SMBCSR);
2616 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2617 }
2618
2619 static int
2620 jme_get_eeprom(struct net_device *netdev,
2621 struct ethtool_eeprom *eeprom, u8 *data)
2622 {
2623 struct jme_adapter *jme = netdev_priv(netdev);
2624 int i, offset = eeprom->offset, len = eeprom->len;
2625
2626 /*
2627 * ethtool will check the boundary for us
2628 */
2629 eeprom->magic = JME_EEPROM_MAGIC;
2630 for (i = 0 ; i < len ; ++i)
2631 data[i] = jme_smb_read(jme, i + offset);
2632
2633 return 0;
2634 }
2635
2636 static int
2637 jme_set_eeprom(struct net_device *netdev,
2638 struct ethtool_eeprom *eeprom, u8 *data)
2639 {
2640 struct jme_adapter *jme = netdev_priv(netdev);
2641 int i, offset = eeprom->offset, len = eeprom->len;
2642
2643 if (eeprom->magic != JME_EEPROM_MAGIC)
2644 return -EINVAL;
2645
2646 /*
2647 * ethtool will check the boundary for us
2648 */
2649 for (i = 0 ; i < len ; ++i)
2650 jme_smb_write(jme, i + offset, data[i]);
2651
2652 return 0;
2653 }
2654
2655 static const struct ethtool_ops jme_ethtool_ops = {
2656 .get_drvinfo = jme_get_drvinfo,
2657 .get_regs_len = jme_get_regs_len,
2658 .get_regs = jme_get_regs,
2659 .get_coalesce = jme_get_coalesce,
2660 .set_coalesce = jme_set_coalesce,
2661 .get_pauseparam = jme_get_pauseparam,
2662 .set_pauseparam = jme_set_pauseparam,
2663 .get_wol = jme_get_wol,
2664 .set_wol = jme_set_wol,
2665 .get_settings = jme_get_settings,
2666 .set_settings = jme_set_settings,
2667 .get_link = jme_get_link,
2668 .get_msglevel = jme_get_msglevel,
2669 .set_msglevel = jme_set_msglevel,
2670 .get_rx_csum = jme_get_rx_csum,
2671 .set_rx_csum = jme_set_rx_csum,
2672 .set_tx_csum = jme_set_tx_csum,
2673 .set_tso = jme_set_tso,
2674 .set_sg = ethtool_op_set_sg,
2675 .nway_reset = jme_nway_reset,
2676 .get_eeprom_len = jme_get_eeprom_len,
2677 .get_eeprom = jme_get_eeprom,
2678 .set_eeprom = jme_set_eeprom,
2679 };
2680
2681 static int
2682 jme_pci_dma64(struct pci_dev *pdev)
2683 {
2684 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2685 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2686 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2687 return 1;
2688
2689 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2690 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2691 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2692 return 1;
2693
2694 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2695 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2696 return 0;
2697
2698 return -1;
2699 }
2700
2701 static inline void
2702 jme_phy_init(struct jme_adapter *jme)
2703 {
2704 u16 reg26;
2705
2706 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2707 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2708 }
2709
2710 static inline void
2711 jme_check_hw_ver(struct jme_adapter *jme)
2712 {
2713 u32 chipmode;
2714
2715 chipmode = jread32(jme, JME_CHIPMODE);
2716
2717 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2718 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2719 }
2720
2721 static const struct net_device_ops jme_netdev_ops = {
2722 .ndo_open = jme_open,
2723 .ndo_stop = jme_close,
2724 .ndo_validate_addr = eth_validate_addr,
2725 .ndo_do_ioctl = jme_ioctl,
2726 .ndo_start_xmit = jme_start_xmit,
2727 .ndo_set_mac_address = jme_set_macaddr,
2728 .ndo_set_multicast_list = jme_set_multi,
2729 .ndo_change_mtu = jme_change_mtu,
2730 .ndo_tx_timeout = jme_tx_timeout,
2731 .ndo_vlan_rx_register = jme_vlan_rx_register,
2732 };
2733
2734 static int __devinit
2735 jme_init_one(struct pci_dev *pdev,
2736 const struct pci_device_id *ent)
2737 {
2738 int rc = 0, using_dac, i;
2739 struct net_device *netdev;
2740 struct jme_adapter *jme;
2741 u16 bmcr, bmsr;
2742 u32 apmc;
2743
2744 /*
2745 * set up PCI device basics
2746 */
2747 rc = pci_enable_device(pdev);
2748 if (rc) {
2749 pr_err("Cannot enable PCI device\n");
2750 goto err_out;
2751 }
2752
2753 using_dac = jme_pci_dma64(pdev);
2754 if (using_dac < 0) {
2755 pr_err("Cannot set PCI DMA Mask\n");
2756 rc = -EIO;
2757 goto err_out_disable_pdev;
2758 }
2759
2760 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2761 pr_err("No PCI resource region found\n");
2762 rc = -ENOMEM;
2763 goto err_out_disable_pdev;
2764 }
2765
2766 rc = pci_request_regions(pdev, DRV_NAME);
2767 if (rc) {
2768 pr_err("Cannot obtain PCI resource region\n");
2769 goto err_out_disable_pdev;
2770 }
2771
2772 pci_set_master(pdev);
2773
2774 /*
2775 * alloc and init net device
2776 */
2777 netdev = alloc_etherdev(sizeof(*jme));
2778 if (!netdev) {
2779 pr_err("Cannot allocate netdev structure\n");
2780 rc = -ENOMEM;
2781 goto err_out_release_regions;
2782 }
2783 netdev->netdev_ops = &jme_netdev_ops;
2784 netdev->ethtool_ops = &jme_ethtool_ops;
2785 netdev->watchdog_timeo = TX_TIMEOUT;
2786 netdev->features = NETIF_F_HW_CSUM |
2787 NETIF_F_SG |
2788 NETIF_F_TSO |
2789 NETIF_F_TSO6 |
2790 NETIF_F_HW_VLAN_TX |
2791 NETIF_F_HW_VLAN_RX;
2792 if (using_dac)
2793 netdev->features |= NETIF_F_HIGHDMA;
2794
2795 SET_NETDEV_DEV(netdev, &pdev->dev);
2796 pci_set_drvdata(pdev, netdev);
2797
2798 /*
2799 * init adapter info
2800 */
2801 jme = netdev_priv(netdev);
2802 jme->pdev = pdev;
2803 jme->dev = netdev;
2804 jme->jme_rx = netif_rx;
2805 jme->jme_vlan_rx = vlan_hwaccel_rx;
2806 jme->old_mtu = netdev->mtu = 1500;
2807 jme->phylink = 0;
2808 jme->tx_ring_size = 1 << 10;
2809 jme->tx_ring_mask = jme->tx_ring_size - 1;
2810 jme->tx_wake_threshold = 1 << 9;
2811 jme->rx_ring_size = 1 << 9;
2812 jme->rx_ring_mask = jme->rx_ring_size - 1;
2813 jme->msg_enable = JME_DEF_MSG_ENABLE;
2814 jme->regs = ioremap(pci_resource_start(pdev, 0),
2815 pci_resource_len(pdev, 0));
2816 if (!(jme->regs)) {
2817 pr_err("Mapping PCI resource region error\n");
2818 rc = -ENOMEM;
2819 goto err_out_free_netdev;
2820 }
2821
2822 if (no_pseudohp) {
2823 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2824 jwrite32(jme, JME_APMC, apmc);
2825 } else if (force_pseudohp) {
2826 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2827 jwrite32(jme, JME_APMC, apmc);
2828 }
2829
2830 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2831
2832 spin_lock_init(&jme->phy_lock);
2833 spin_lock_init(&jme->macaddr_lock);
2834 spin_lock_init(&jme->rxmcs_lock);
2835
2836 atomic_set(&jme->link_changing, 1);
2837 atomic_set(&jme->rx_cleaning, 1);
2838 atomic_set(&jme->tx_cleaning, 1);
2839 atomic_set(&jme->rx_empty, 1);
2840
2841 tasklet_init(&jme->pcc_task,
2842 jme_pcc_tasklet,
2843 (unsigned long) jme);
2844 tasklet_init(&jme->linkch_task,
2845 jme_link_change_tasklet,
2846 (unsigned long) jme);
2847 tasklet_init(&jme->txclean_task,
2848 jme_tx_clean_tasklet,
2849 (unsigned long) jme);
2850 tasklet_init(&jme->rxclean_task,
2851 jme_rx_clean_tasklet,
2852 (unsigned long) jme);
2853 tasklet_init(&jme->rxempty_task,
2854 jme_rx_empty_tasklet,
2855 (unsigned long) jme);
2856 tasklet_disable_nosync(&jme->linkch_task);
2857 tasklet_disable_nosync(&jme->txclean_task);
2858 tasklet_disable_nosync(&jme->rxclean_task);
2859 tasklet_disable_nosync(&jme->rxempty_task);
2860 jme->dpi.cur = PCC_P1;
2861
2862 jme->reg_ghc = 0;
2863 jme->reg_rxcs = RXCS_DEFAULT;
2864 jme->reg_rxmcs = RXMCS_DEFAULT;
2865 jme->reg_txpfc = 0;
2866 jme->reg_pmcs = PMCS_MFEN;
2867 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2868 set_bit(JME_FLAG_TSO, &jme->flags);
2869
2870 /*
2871 * Get Max Read Req Size from PCI Config Space
2872 */
2873 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2874 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2875 switch (jme->mrrs) {
2876 case MRRS_128B:
2877 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2878 break;
2879 case MRRS_256B:
2880 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2881 break;
2882 default:
2883 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2884 break;
2885 }
2886
2887 /*
2888 * Must check before reset_mac_processor
2889 */
2890 jme_check_hw_ver(jme);
2891 jme->mii_if.dev = netdev;
2892 if (jme->fpgaver) {
2893 jme->mii_if.phy_id = 0;
2894 for (i = 1 ; i < 32 ; ++i) {
2895 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2896 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2897 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2898 jme->mii_if.phy_id = i;
2899 break;
2900 }
2901 }
2902
2903 if (!jme->mii_if.phy_id) {
2904 rc = -EIO;
2905 pr_err("Can not find phy_id\n");
2906 goto err_out_unmap;
2907 }
2908
2909 jme->reg_ghc |= GHC_LINK_POLL;
2910 } else {
2911 jme->mii_if.phy_id = 1;
2912 }
2913 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2914 jme->mii_if.supports_gmii = true;
2915 else
2916 jme->mii_if.supports_gmii = false;
2917 jme->mii_if.phy_id_mask = 0x1F;
2918 jme->mii_if.reg_num_mask = 0x1F;
2919 jme->mii_if.mdio_read = jme_mdio_read;
2920 jme->mii_if.mdio_write = jme_mdio_write;
2921
2922 jme_clear_pm(jme);
2923 jme_set_phyfifoa(jme);
2924 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2925 if (!jme->fpgaver)
2926 jme_phy_init(jme);
2927 jme_phy_off(jme);
2928
2929 /*
2930 * Reset MAC processor and reload EEPROM for MAC Address
2931 */
2932 jme_reset_mac_processor(jme);
2933 rc = jme_reload_eeprom(jme);
2934 if (rc) {
2935 pr_err("Reload eeprom for reading MAC Address error\n");
2936 goto err_out_unmap;
2937 }
2938 jme_load_macaddr(netdev);
2939
2940 /*
2941 * Tell stack that we are not ready to work until open()
2942 */
2943 netif_carrier_off(netdev);
2944 netif_stop_queue(netdev);
2945
2946 /*
2947 * Register netdev
2948 */
2949 rc = register_netdev(netdev);
2950 if (rc) {
2951 pr_err("Cannot register net device\n");
2952 goto err_out_unmap;
2953 }
2954
2955 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2956 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2957 "JMC250 Gigabit Ethernet" :
2958 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2959 "JMC260 Fast Ethernet" : "Unknown",
2960 (jme->fpgaver != 0) ? " (FPGA)" : "",
2961 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2962 jme->rev, netdev->dev_addr);
2963
2964 return 0;
2965
2966 err_out_unmap:
2967 iounmap(jme->regs);
2968 err_out_free_netdev:
2969 pci_set_drvdata(pdev, NULL);
2970 free_netdev(netdev);
2971 err_out_release_regions:
2972 pci_release_regions(pdev);
2973 err_out_disable_pdev:
2974 pci_disable_device(pdev);
2975 err_out:
2976 return rc;
2977 }
2978
2979 static void __devexit
2980 jme_remove_one(struct pci_dev *pdev)
2981 {
2982 struct net_device *netdev = pci_get_drvdata(pdev);
2983 struct jme_adapter *jme = netdev_priv(netdev);
2984
2985 unregister_netdev(netdev);
2986 iounmap(jme->regs);
2987 pci_set_drvdata(pdev, NULL);
2988 free_netdev(netdev);
2989 pci_release_regions(pdev);
2990 pci_disable_device(pdev);
2991
2992 }
2993
2994 #ifdef CONFIG_PM
2995 static int
2996 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2997 {
2998 struct net_device *netdev = pci_get_drvdata(pdev);
2999 struct jme_adapter *jme = netdev_priv(netdev);
3000
3001 atomic_dec(&jme->link_changing);
3002
3003 netif_device_detach(netdev);
3004 netif_stop_queue(netdev);
3005 jme_stop_irq(jme);
3006
3007 tasklet_disable(&jme->txclean_task);
3008 tasklet_disable(&jme->rxclean_task);
3009 tasklet_disable(&jme->rxempty_task);
3010
3011 if (netif_carrier_ok(netdev)) {
3012 if (test_bit(JME_FLAG_POLL, &jme->flags))
3013 jme_polling_mode(jme);
3014
3015 jme_stop_pcc_timer(jme);
3016 jme_reset_ghc_speed(jme);
3017 jme_disable_rx_engine(jme);
3018 jme_disable_tx_engine(jme);
3019 jme_reset_mac_processor(jme);
3020 jme_free_rx_resources(jme);
3021 jme_free_tx_resources(jme);
3022 netif_carrier_off(netdev);
3023 jme->phylink = 0;
3024 }
3025
3026 tasklet_enable(&jme->txclean_task);
3027 tasklet_hi_enable(&jme->rxclean_task);
3028 tasklet_hi_enable(&jme->rxempty_task);
3029
3030 pci_save_state(pdev);
3031 if (jme->reg_pmcs) {
3032 jme_set_100m_half(jme);
3033
3034 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3035 jme_wait_link(jme);
3036
3037 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3038
3039 pci_enable_wake(pdev, PCI_D3cold, true);
3040 } else {
3041 jme_phy_off(jme);
3042 }
3043 pci_set_power_state(pdev, PCI_D3cold);
3044
3045 return 0;
3046 }
3047
3048 static int
3049 jme_resume(struct pci_dev *pdev)
3050 {
3051 struct net_device *netdev = pci_get_drvdata(pdev);
3052 struct jme_adapter *jme = netdev_priv(netdev);
3053
3054 jme_clear_pm(jme);
3055 pci_restore_state(pdev);
3056
3057 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3058 jme_phy_on(jme);
3059 jme_set_settings(netdev, &jme->old_ecmd);
3060 } else {
3061 jme_reset_phy_processor(jme);
3062 }
3063
3064 jme_start_irq(jme);
3065 netif_device_attach(netdev);
3066
3067 atomic_inc(&jme->link_changing);
3068
3069 jme_reset_link(jme);
3070
3071 return 0;
3072 }
3073 #endif
3074
3075 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3076 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3077 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3078 { }
3079 };
3080
3081 static struct pci_driver jme_driver = {
3082 .name = DRV_NAME,
3083 .id_table = jme_pci_tbl,
3084 .probe = jme_init_one,
3085 .remove = __devexit_p(jme_remove_one),
3086 #ifdef CONFIG_PM
3087 .suspend = jme_suspend,
3088 .resume = jme_resume,
3089 #endif /* CONFIG_PM */
3090 };
3091
3092 static int __init
3093 jme_init_module(void)
3094 {
3095 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3096 return pci_register_driver(&jme_driver);
3097 }
3098
3099 static void __exit
3100 jme_cleanup_module(void)
3101 {
3102 pci_unregister_driver(&jme_driver);
3103 }
3104
3105 module_init(jme_init_module);
3106 module_exit(jme_cleanup_module);
3107
3108 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3109 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3110 MODULE_LICENSE("GPL");
3111 MODULE_VERSION(DRV_VERSION);
3112 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3113
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree