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drm/i915: range-restricted eviction support
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / synclinkmp.c
blob2f9eb4b0dec104fa426e99ca64c8f17cac92b406
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/seq_file.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/ioctl.h>
60
61 #include <asm/system.h>
62 #include <asm/io.h>
63 #include <asm/irq.h>
64 #include <asm/dma.h>
65 #include <linux/bitops.h>
66 #include <asm/types.h>
67 #include <linux/termios.h>
68 #include <linux/workqueue.h>
69 #include <linux/hdlc.h>
70 #include <linux/synclink.h>
71
72 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
73 #define SYNCLINK_GENERIC_HDLC 1
74 #else
75 #define SYNCLINK_GENERIC_HDLC 0
76 #endif
77
78 #define GET_USER(error,value,addr) error = get_user(value,addr)
79 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
80 #define PUT_USER(error,value,addr) error = put_user(value,addr)
81 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
82
83 #include <asm/uaccess.h>
84
85 static MGSL_PARAMS default_params = {
86 MGSL_MODE_HDLC, /* unsigned long mode */
87 0, /* unsigned char loopback; */
88 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
89 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
90 0, /* unsigned long clock_speed; */
91 0xff, /* unsigned char addr_filter; */
92 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
93 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
94 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
95 9600, /* unsigned long data_rate; */
96 8, /* unsigned char data_bits; */
97 1, /* unsigned char stop_bits; */
98 ASYNC_PARITY_NONE /* unsigned char parity; */
99 };
100
101 /* size in bytes of DMA data buffers */
102 #define SCABUFSIZE 1024
103 #define SCA_MEM_SIZE 0x40000
104 #define SCA_BASE_SIZE 512
105 #define SCA_REG_SIZE 16
106 #define SCA_MAX_PORTS 4
107 #define SCAMAXDESC 128
108
109 #define BUFFERLISTSIZE 4096
110
111 /* SCA-I style DMA buffer descriptor */
112 typedef struct _SCADESC
113 {
114 u16 next; /* lower l6 bits of next descriptor addr */
115 u16 buf_ptr; /* lower 16 bits of buffer addr */
116 u8 buf_base; /* upper 8 bits of buffer addr */
117 u8 pad1;
118 u16 length; /* length of buffer */
119 u8 status; /* status of buffer */
120 u8 pad2;
121 } SCADESC, *PSCADESC;
122
123 typedef struct _SCADESC_EX
124 {
125 /* device driver bookkeeping section */
126 char *virt_addr; /* virtual address of data buffer */
127 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
128 } SCADESC_EX, *PSCADESC_EX;
129
130 /* The queue of BH actions to be performed */
131
132 #define BH_RECEIVE 1
133 #define BH_TRANSMIT 2
134 #define BH_STATUS 4
135
136 #define IO_PIN_SHUTDOWN_LIMIT 100
137
138 struct _input_signal_events {
139 int ri_up;
140 int ri_down;
141 int dsr_up;
142 int dsr_down;
143 int dcd_up;
144 int dcd_down;
145 int cts_up;
146 int cts_down;
147 };
148
149 /*
150 * Device instance data structure
151 */
152 typedef struct _synclinkmp_info {
153 void *if_ptr; /* General purpose pointer (used by SPPP) */
154 int magic;
155 struct tty_port port;
156 int line;
157 unsigned short close_delay;
158 unsigned short closing_wait; /* time to wait before closing */
159
160 struct mgsl_icount icount;
161
162 int timeout;
163 int x_char; /* xon/xoff character */
164 u16 read_status_mask1; /* break detection (SR1 indications) */
165 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
166 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
167 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
168 unsigned char *tx_buf;
169 int tx_put;
170 int tx_get;
171 int tx_count;
172
173 wait_queue_head_t status_event_wait_q;
174 wait_queue_head_t event_wait_q;
175 struct timer_list tx_timer; /* HDLC transmit timeout timer */
176 struct _synclinkmp_info *next_device; /* device list link */
177 struct timer_list status_timer; /* input signal status check timer */
178
179 spinlock_t lock; /* spinlock for synchronizing with ISR */
180 struct work_struct task; /* task structure for scheduling bh */
181
182 u32 max_frame_size; /* as set by device config */
183
184 u32 pending_bh;
185
186 bool bh_running; /* Protection from multiple */
187 int isr_overflow;
188 bool bh_requested;
189
190 int dcd_chkcount; /* check counts to prevent */
191 int cts_chkcount; /* too many IRQs if a signal */
192 int dsr_chkcount; /* is floating */
193 int ri_chkcount;
194
195 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
196 unsigned long buffer_list_phys;
197
198 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
199 SCADESC *rx_buf_list; /* list of receive buffer entries */
200 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
201 unsigned int current_rx_buf;
202
203 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
204 SCADESC *tx_buf_list; /* list of transmit buffer entries */
205 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
206 unsigned int last_tx_buf;
207
208 unsigned char *tmp_rx_buf;
209 unsigned int tmp_rx_buf_count;
210
211 bool rx_enabled;
212 bool rx_overflow;
213
214 bool tx_enabled;
215 bool tx_active;
216 u32 idle_mode;
217
218 unsigned char ie0_value;
219 unsigned char ie1_value;
220 unsigned char ie2_value;
221 unsigned char ctrlreg_value;
222 unsigned char old_signals;
223
224 char device_name[25]; /* device instance name */
225
226 int port_count;
227 int adapter_num;
228 int port_num;
229
230 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
231
232 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
233
234 unsigned int irq_level; /* interrupt level */
235 unsigned long irq_flags;
236 bool irq_requested; /* true if IRQ requested */
237
238 MGSL_PARAMS params; /* communications parameters */
239
240 unsigned char serial_signals; /* current serial signal states */
241
242 bool irq_occurred; /* for diagnostics use */
243 unsigned int init_error; /* Initialization startup error */
244
245 u32 last_mem_alloc;
246 unsigned char* memory_base; /* shared memory address (PCI only) */
247 u32 phys_memory_base;
248 int shared_mem_requested;
249
250 unsigned char* sca_base; /* HD64570 SCA Memory address */
251 u32 phys_sca_base;
252 u32 sca_offset;
253 bool sca_base_requested;
254
255 unsigned char* lcr_base; /* local config registers (PCI only) */
256 u32 phys_lcr_base;
257 u32 lcr_offset;
258 int lcr_mem_requested;
259
260 unsigned char* statctrl_base; /* status/control register memory */
261 u32 phys_statctrl_base;
262 u32 statctrl_offset;
263 bool sca_statctrl_requested;
264
265 u32 misc_ctrl_value;
266 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
267 char char_buf[MAX_ASYNC_BUFFER_SIZE];
268 bool drop_rts_on_tx_done;
269
270 struct _input_signal_events input_signal_events;
271
272 /* SPPP/Cisco HDLC device parts */
273 int netcount;
274 spinlock_t netlock;
275
276 #if SYNCLINK_GENERIC_HDLC
277 struct net_device *netdev;
278 #endif
279
280 } SLMP_INFO;
281
282 #define MGSL_MAGIC 0x5401
283
284 /*
285 * define serial signal status change macros
286 */
287 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
288 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
289 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
290 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
291
292 /* Common Register macros */
293 #define LPR 0x00
294 #define PABR0 0x02
295 #define PABR1 0x03
296 #define WCRL 0x04
297 #define WCRM 0x05
298 #define WCRH 0x06
299 #define DPCR 0x08
300 #define DMER 0x09
301 #define ISR0 0x10
302 #define ISR1 0x11
303 #define ISR2 0x12
304 #define IER0 0x14
305 #define IER1 0x15
306 #define IER2 0x16
307 #define ITCR 0x18
308 #define INTVR 0x1a
309 #define IMVR 0x1c
310
311 /* MSCI Register macros */
312 #define TRB 0x20
313 #define TRBL 0x20
314 #define TRBH 0x21
315 #define SR0 0x22
316 #define SR1 0x23
317 #define SR2 0x24
318 #define SR3 0x25
319 #define FST 0x26
320 #define IE0 0x28
321 #define IE1 0x29
322 #define IE2 0x2a
323 #define FIE 0x2b
324 #define CMD 0x2c
325 #define MD0 0x2e
326 #define MD1 0x2f
327 #define MD2 0x30
328 #define CTL 0x31
329 #define SA0 0x32
330 #define SA1 0x33
331 #define IDL 0x34
332 #define TMC 0x35
333 #define RXS 0x36
334 #define TXS 0x37
335 #define TRC0 0x38
336 #define TRC1 0x39
337 #define RRC 0x3a
338 #define CST0 0x3c
339 #define CST1 0x3d
340
341 /* Timer Register Macros */
342 #define TCNT 0x60
343 #define TCNTL 0x60
344 #define TCNTH 0x61
345 #define TCONR 0x62
346 #define TCONRL 0x62
347 #define TCONRH 0x63
348 #define TMCS 0x64
349 #define TEPR 0x65
350
351 /* DMA Controller Register macros */
352 #define DARL 0x80
353 #define DARH 0x81
354 #define DARB 0x82
355 #define BAR 0x80
356 #define BARL 0x80
357 #define BARH 0x81
358 #define BARB 0x82
359 #define SAR 0x84
360 #define SARL 0x84
361 #define SARH 0x85
362 #define SARB 0x86
363 #define CPB 0x86
364 #define CDA 0x88
365 #define CDAL 0x88
366 #define CDAH 0x89
367 #define EDA 0x8a
368 #define EDAL 0x8a
369 #define EDAH 0x8b
370 #define BFL 0x8c
371 #define BFLL 0x8c
372 #define BFLH 0x8d
373 #define BCR 0x8e
374 #define BCRL 0x8e
375 #define BCRH 0x8f
376 #define DSR 0x90
377 #define DMR 0x91
378 #define FCT 0x93
379 #define DIR 0x94
380 #define DCMD 0x95
381
382 /* combine with timer or DMA register address */
383 #define TIMER0 0x00
384 #define TIMER1 0x08
385 #define TIMER2 0x10
386 #define TIMER3 0x18
387 #define RXDMA 0x00
388 #define TXDMA 0x20
389
390 /* SCA Command Codes */
391 #define NOOP 0x00
392 #define TXRESET 0x01
393 #define TXENABLE 0x02
394 #define TXDISABLE 0x03
395 #define TXCRCINIT 0x04
396 #define TXCRCEXCL 0x05
397 #define TXEOM 0x06
398 #define TXABORT 0x07
399 #define MPON 0x08
400 #define TXBUFCLR 0x09
401 #define RXRESET 0x11
402 #define RXENABLE 0x12
403 #define RXDISABLE 0x13
404 #define RXCRCINIT 0x14
405 #define RXREJECT 0x15
406 #define SEARCHMP 0x16
407 #define RXCRCEXCL 0x17
408 #define RXCRCCALC 0x18
409 #define CHRESET 0x21
410 #define HUNT 0x31
411
412 /* DMA command codes */
413 #define SWABORT 0x01
414 #define FEICLEAR 0x02
415
416 /* IE0 */
417 #define TXINTE BIT7
418 #define RXINTE BIT6
419 #define TXRDYE BIT1
420 #define RXRDYE BIT0
421
422 /* IE1 & SR1 */
423 #define UDRN BIT7
424 #define IDLE BIT6
425 #define SYNCD BIT4
426 #define FLGD BIT4
427 #define CCTS BIT3
428 #define CDCD BIT2
429 #define BRKD BIT1
430 #define ABTD BIT1
431 #define GAPD BIT1
432 #define BRKE BIT0
433 #define IDLD BIT0
434
435 /* IE2 & SR2 */
436 #define EOM BIT7
437 #define PMP BIT6
438 #define SHRT BIT6
439 #define PE BIT5
440 #define ABT BIT5
441 #define FRME BIT4
442 #define RBIT BIT4
443 #define OVRN BIT3
444 #define CRCE BIT2
445
446
447 /*
448 * Global linked list of SyncLink devices
449 */
450 static SLMP_INFO *synclinkmp_device_list = NULL;
451 static int synclinkmp_adapter_count = -1;
452 static int synclinkmp_device_count = 0;
453
454 /*
455 * Set this param to non-zero to load eax with the
456 * .text section address and breakpoint on module load.
457 * This is useful for use with gdb and add-symbol-file command.
458 */
459 static int break_on_load = 0;
460
461 /*
462 * Driver major number, defaults to zero to get auto
463 * assigned major number. May be forced as module parameter.
464 */
465 static int ttymajor = 0;
466
467 /*
468 * Array of user specified options for ISA adapters.
469 */
470 static int debug_level = 0;
471 static int maxframe[MAX_DEVICES] = {0,};
472
473 module_param(break_on_load, bool, 0);
474 module_param(ttymajor, int, 0);
475 module_param(debug_level, int, 0);
476 module_param_array(maxframe, int, NULL, 0);
477
478 static char *driver_name = "SyncLink MultiPort driver";
479 static char *driver_version = "$Revision: 4.38 $";
480
481 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
482 static void synclinkmp_remove_one(struct pci_dev *dev);
483
484 static struct pci_device_id synclinkmp_pci_tbl[] = {
485 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
486 { 0, }, /* terminate list */
487 };
488 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
489
490 MODULE_LICENSE("GPL");
491
492 static struct pci_driver synclinkmp_pci_driver = {
493 .name = "synclinkmp",
494 .id_table = synclinkmp_pci_tbl,
495 .probe = synclinkmp_init_one,
496 .remove = __devexit_p(synclinkmp_remove_one),
497 };
498
499
500 static struct tty_driver *serial_driver;
501
502 /* number of characters left in xmit buffer before we ask for more */
503 #define WAKEUP_CHARS 256
504
505
506 /* tty callbacks */
507
508 static int open(struct tty_struct *tty, struct file * filp);
509 static void close(struct tty_struct *tty, struct file * filp);
510 static void hangup(struct tty_struct *tty);
511 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
512
513 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
514 static int put_char(struct tty_struct *tty, unsigned char ch);
515 static void send_xchar(struct tty_struct *tty, char ch);
516 static void wait_until_sent(struct tty_struct *tty, int timeout);
517 static int write_room(struct tty_struct *tty);
518 static void flush_chars(struct tty_struct *tty);
519 static void flush_buffer(struct tty_struct *tty);
520 static void tx_hold(struct tty_struct *tty);
521 static void tx_release(struct tty_struct *tty);
522
523 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
524 static int chars_in_buffer(struct tty_struct *tty);
525 static void throttle(struct tty_struct * tty);
526 static void unthrottle(struct tty_struct * tty);
527 static int set_break(struct tty_struct *tty, int break_state);
528
529 #if SYNCLINK_GENERIC_HDLC
530 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
531 static void hdlcdev_tx_done(SLMP_INFO *info);
532 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
533 static int hdlcdev_init(SLMP_INFO *info);
534 static void hdlcdev_exit(SLMP_INFO *info);
535 #endif
536
537 /* ioctl handlers */
538
539 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
540 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
541 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
542 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
543 static int set_txidle(SLMP_INFO *info, int idle_mode);
544 static int tx_enable(SLMP_INFO *info, int enable);
545 static int tx_abort(SLMP_INFO *info);
546 static int rx_enable(SLMP_INFO *info, int enable);
547 static int modem_input_wait(SLMP_INFO *info,int arg);
548 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
549 static int tiocmget(struct tty_struct *tty, struct file *file);
550 static int tiocmset(struct tty_struct *tty, struct file *file,
551 unsigned int set, unsigned int clear);
552 static int set_break(struct tty_struct *tty, int break_state);
553
554 static void add_device(SLMP_INFO *info);
555 static void device_init(int adapter_num, struct pci_dev *pdev);
556 static int claim_resources(SLMP_INFO *info);
557 static void release_resources(SLMP_INFO *info);
558
559 static int startup(SLMP_INFO *info);
560 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
561 static int carrier_raised(struct tty_port *port);
562 static void shutdown(SLMP_INFO *info);
563 static void program_hw(SLMP_INFO *info);
564 static void change_params(SLMP_INFO *info);
565
566 static bool init_adapter(SLMP_INFO *info);
567 static bool register_test(SLMP_INFO *info);
568 static bool irq_test(SLMP_INFO *info);
569 static bool loopback_test(SLMP_INFO *info);
570 static int adapter_test(SLMP_INFO *info);
571 static bool memory_test(SLMP_INFO *info);
572
573 static void reset_adapter(SLMP_INFO *info);
574 static void reset_port(SLMP_INFO *info);
575 static void async_mode(SLMP_INFO *info);
576 static void hdlc_mode(SLMP_INFO *info);
577
578 static void rx_stop(SLMP_INFO *info);
579 static void rx_start(SLMP_INFO *info);
580 static void rx_reset_buffers(SLMP_INFO *info);
581 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
582 static bool rx_get_frame(SLMP_INFO *info);
583
584 static void tx_start(SLMP_INFO *info);
585 static void tx_stop(SLMP_INFO *info);
586 static void tx_load_fifo(SLMP_INFO *info);
587 static void tx_set_idle(SLMP_INFO *info);
588 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
589
590 static void get_signals(SLMP_INFO *info);
591 static void set_signals(SLMP_INFO *info);
592 static void enable_loopback(SLMP_INFO *info, int enable);
593 static void set_rate(SLMP_INFO *info, u32 data_rate);
594
595 static int bh_action(SLMP_INFO *info);
596 static void bh_handler(struct work_struct *work);
597 static void bh_receive(SLMP_INFO *info);
598 static void bh_transmit(SLMP_INFO *info);
599 static void bh_status(SLMP_INFO *info);
600 static void isr_timer(SLMP_INFO *info);
601 static void isr_rxint(SLMP_INFO *info);
602 static void isr_rxrdy(SLMP_INFO *info);
603 static void isr_txint(SLMP_INFO *info);
604 static void isr_txrdy(SLMP_INFO *info);
605 static void isr_rxdmaok(SLMP_INFO *info);
606 static void isr_rxdmaerror(SLMP_INFO *info);
607 static void isr_txdmaok(SLMP_INFO *info);
608 static void isr_txdmaerror(SLMP_INFO *info);
609 static void isr_io_pin(SLMP_INFO *info, u16 status);
610
611 static int alloc_dma_bufs(SLMP_INFO *info);
612 static void free_dma_bufs(SLMP_INFO *info);
613 static int alloc_buf_list(SLMP_INFO *info);
614 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
615 static int alloc_tmp_rx_buf(SLMP_INFO *info);
616 static void free_tmp_rx_buf(SLMP_INFO *info);
617
618 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
619 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
620 static void tx_timeout(unsigned long context);
621 static void status_timeout(unsigned long context);
622
623 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
624 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
625 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
626 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
627 static unsigned char read_status_reg(SLMP_INFO * info);
628 static void write_control_reg(SLMP_INFO * info);
629
630
631 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
632 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
633 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
634
635 static u32 misc_ctrl_value = 0x007e4040;
636 static u32 lcr1_brdr_value = 0x00800028;
637
638 static u32 read_ahead_count = 8;
639
640 /* DPCR, DMA Priority Control
641 *
642 * 07..05 Not used, must be 0
643 * 04 BRC, bus release condition: 0=all transfers complete
644 * 1=release after 1 xfer on all channels
645 * 03 CCC, channel change condition: 0=every cycle
646 * 1=after each channel completes all xfers
647 * 02..00 PR<2..0>, priority 100=round robin
648 *
649 * 00000100 = 0x00
650 */
651 static unsigned char dma_priority = 0x04;
652
653 // Number of bytes that can be written to shared RAM
654 // in a single write operation
655 static u32 sca_pci_load_interval = 64;
656
657 /*
658 * 1st function defined in .text section. Calling this function in
659 * init_module() followed by a breakpoint allows a remote debugger
660 * (gdb) to get the .text address for the add-symbol-file command.
661 * This allows remote debugging of dynamically loadable modules.
662 */
663 static void* synclinkmp_get_text_ptr(void);
664 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
665
666 static inline int sanity_check(SLMP_INFO *info,
667 char *name, const char *routine)
668 {
669 #ifdef SANITY_CHECK
670 static const char *badmagic =
671 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
672 static const char *badinfo =
673 "Warning: null synclinkmp_struct for (%s) in %s\n";
674
675 if (!info) {
676 printk(badinfo, name, routine);
677 return 1;
678 }
679 if (info->magic != MGSL_MAGIC) {
680 printk(badmagic, name, routine);
681 return 1;
682 }
683 #else
684 if (!info)
685 return 1;
686 #endif
687 return 0;
688 }
689
690 /**
691 * line discipline callback wrappers
692 *
693 * The wrappers maintain line discipline references
694 * while calling into the line discipline.
695 *
696 * ldisc_receive_buf - pass receive data to line discipline
697 */
698
699 static void ldisc_receive_buf(struct tty_struct *tty,
700 const __u8 *data, char *flags, int count)
701 {
702 struct tty_ldisc *ld;
703 if (!tty)
704 return;
705 ld = tty_ldisc_ref(tty);
706 if (ld) {
707 if (ld->ops->receive_buf)
708 ld->ops->receive_buf(tty, data, flags, count);
709 tty_ldisc_deref(ld);
710 }
711 }
712
713 /* tty callbacks */
714
715 /* Called when a port is opened. Init and enable port.
716 */
717 static int open(struct tty_struct *tty, struct file *filp)
718 {
719 SLMP_INFO *info;
720 int retval, line;
721 unsigned long flags;
722
723 line = tty->index;
724 if ((line < 0) || (line >= synclinkmp_device_count)) {
725 printk("%s(%d): open with invalid line #%d.\n",
726 __FILE__,__LINE__,line);
727 return -ENODEV;
728 }
729
730 info = synclinkmp_device_list;
731 while(info && info->line != line)
732 info = info->next_device;
733 if (sanity_check(info, tty->name, "open"))
734 return -ENODEV;
735 if ( info->init_error ) {
736 printk("%s(%d):%s device is not allocated, init error=%d\n",
737 __FILE__,__LINE__,info->device_name,info->init_error);
738 return -ENODEV;
739 }
740
741 tty->driver_data = info;
742 info->port.tty = tty;
743
744 if (debug_level >= DEBUG_LEVEL_INFO)
745 printk("%s(%d):%s open(), old ref count = %d\n",
746 __FILE__,__LINE__,tty->driver->name, info->port.count);
747
748 /* If port is closing, signal caller to try again */
749 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
750 if (info->port.flags & ASYNC_CLOSING)
751 interruptible_sleep_on(&info->port.close_wait);
752 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
753 -EAGAIN : -ERESTARTSYS);
754 goto cleanup;
755 }
756
757 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
758
759 spin_lock_irqsave(&info->netlock, flags);
760 if (info->netcount) {
761 retval = -EBUSY;
762 spin_unlock_irqrestore(&info->netlock, flags);
763 goto cleanup;
764 }
765 info->port.count++;
766 spin_unlock_irqrestore(&info->netlock, flags);
767
768 if (info->port.count == 1) {
769 /* 1st open on this device, init hardware */
770 retval = startup(info);
771 if (retval < 0)
772 goto cleanup;
773 }
774
775 retval = block_til_ready(tty, filp, info);
776 if (retval) {
777 if (debug_level >= DEBUG_LEVEL_INFO)
778 printk("%s(%d):%s block_til_ready() returned %d\n",
779 __FILE__,__LINE__, info->device_name, retval);
780 goto cleanup;
781 }
782
783 if (debug_level >= DEBUG_LEVEL_INFO)
784 printk("%s(%d):%s open() success\n",
785 __FILE__,__LINE__, info->device_name);
786 retval = 0;
787
788 cleanup:
789 if (retval) {
790 if (tty->count == 1)
791 info->port.tty = NULL; /* tty layer will release tty struct */
792 if(info->port.count)
793 info->port.count--;
794 }
795
796 return retval;
797 }
798
799 /* Called when port is closed. Wait for remaining data to be
800 * sent. Disable port and free resources.
801 */
802 static void close(struct tty_struct *tty, struct file *filp)
803 {
804 SLMP_INFO * info = tty->driver_data;
805
806 if (sanity_check(info, tty->name, "close"))
807 return;
808
809 if (debug_level >= DEBUG_LEVEL_INFO)
810 printk("%s(%d):%s close() entry, count=%d\n",
811 __FILE__,__LINE__, info->device_name, info->port.count);
812
813 if (tty_port_close_start(&info->port, tty, filp) == 0)
814 goto cleanup;
815
816 mutex_lock(&info->port.mutex);
817 if (info->port.flags & ASYNC_INITIALIZED)
818 wait_until_sent(tty, info->timeout);
819
820 flush_buffer(tty);
821 tty_ldisc_flush(tty);
822 shutdown(info);
823 mutex_unlock(&info->port.mutex);
824
825 tty_port_close_end(&info->port, tty);
826 info->port.tty = NULL;
827 cleanup:
828 if (debug_level >= DEBUG_LEVEL_INFO)
829 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
830 tty->driver->name, info->port.count);
831 }
832
833 /* Called by tty_hangup() when a hangup is signaled.
834 * This is the same as closing all open descriptors for the port.
835 */
836 static void hangup(struct tty_struct *tty)
837 {
838 SLMP_INFO *info = tty->driver_data;
839 unsigned long flags;
840
841 if (debug_level >= DEBUG_LEVEL_INFO)
842 printk("%s(%d):%s hangup()\n",
843 __FILE__,__LINE__, info->device_name );
844
845 if (sanity_check(info, tty->name, "hangup"))
846 return;
847
848 mutex_lock(&info->port.mutex);
849 flush_buffer(tty);
850 shutdown(info);
851
852 spin_lock_irqsave(&info->port.lock, flags);
853 info->port.count = 0;
854 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
855 info->port.tty = NULL;
856 spin_unlock_irqrestore(&info->port.lock, flags);
857 mutex_unlock(&info->port.mutex);
858
859 wake_up_interruptible(&info->port.open_wait);
860 }
861
862 /* Set new termios settings
863 */
864 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
865 {
866 SLMP_INFO *info = tty->driver_data;
867 unsigned long flags;
868
869 if (debug_level >= DEBUG_LEVEL_INFO)
870 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
871 tty->driver->name );
872
873 change_params(info);
874
875 /* Handle transition to B0 status */
876 if (old_termios->c_cflag & CBAUD &&
877 !(tty->termios->c_cflag & CBAUD)) {
878 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
879 spin_lock_irqsave(&info->lock,flags);
880 set_signals(info);
881 spin_unlock_irqrestore(&info->lock,flags);
882 }
883
884 /* Handle transition away from B0 status */
885 if (!(old_termios->c_cflag & CBAUD) &&
886 tty->termios->c_cflag & CBAUD) {
887 info->serial_signals |= SerialSignal_DTR;
888 if (!(tty->termios->c_cflag & CRTSCTS) ||
889 !test_bit(TTY_THROTTLED, &tty->flags)) {
890 info->serial_signals |= SerialSignal_RTS;
891 }
892 spin_lock_irqsave(&info->lock,flags);
893 set_signals(info);
894 spin_unlock_irqrestore(&info->lock,flags);
895 }
896
897 /* Handle turning off CRTSCTS */
898 if (old_termios->c_cflag & CRTSCTS &&
899 !(tty->termios->c_cflag & CRTSCTS)) {
900 tty->hw_stopped = 0;
901 tx_release(tty);
902 }
903 }
904
905 /* Send a block of data
906 *
907 * Arguments:
908 *
909 * tty pointer to tty information structure
910 * buf pointer to buffer containing send data
911 * count size of send data in bytes
912 *
913 * Return Value: number of characters written
914 */
915 static int write(struct tty_struct *tty,
916 const unsigned char *buf, int count)
917 {
918 int c, ret = 0;
919 SLMP_INFO *info = tty->driver_data;
920 unsigned long flags;
921
922 if (debug_level >= DEBUG_LEVEL_INFO)
923 printk("%s(%d):%s write() count=%d\n",
924 __FILE__,__LINE__,info->device_name,count);
925
926 if (sanity_check(info, tty->name, "write"))
927 goto cleanup;
928
929 if (!info->tx_buf)
930 goto cleanup;
931
932 if (info->params.mode == MGSL_MODE_HDLC) {
933 if (count > info->max_frame_size) {
934 ret = -EIO;
935 goto cleanup;
936 }
937 if (info->tx_active)
938 goto cleanup;
939 if (info->tx_count) {
940 /* send accumulated data from send_char() calls */
941 /* as frame and wait before accepting more data. */
942 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
943 goto start;
944 }
945 ret = info->tx_count = count;
946 tx_load_dma_buffer(info, buf, count);
947 goto start;
948 }
949
950 for (;;) {
951 c = min_t(int, count,
952 min(info->max_frame_size - info->tx_count - 1,
953 info->max_frame_size - info->tx_put));
954 if (c <= 0)
955 break;
956
957 memcpy(info->tx_buf + info->tx_put, buf, c);
958
959 spin_lock_irqsave(&info->lock,flags);
960 info->tx_put += c;
961 if (info->tx_put >= info->max_frame_size)
962 info->tx_put -= info->max_frame_size;
963 info->tx_count += c;
964 spin_unlock_irqrestore(&info->lock,flags);
965
966 buf += c;
967 count -= c;
968 ret += c;
969 }
970
971 if (info->params.mode == MGSL_MODE_HDLC) {
972 if (count) {
973 ret = info->tx_count = 0;
974 goto cleanup;
975 }
976 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
977 }
978 start:
979 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
980 spin_lock_irqsave(&info->lock,flags);
981 if (!info->tx_active)
982 tx_start(info);
983 spin_unlock_irqrestore(&info->lock,flags);
984 }
985
986 cleanup:
987 if (debug_level >= DEBUG_LEVEL_INFO)
988 printk( "%s(%d):%s write() returning=%d\n",
989 __FILE__,__LINE__,info->device_name,ret);
990 return ret;
991 }
992
993 /* Add a character to the transmit buffer.
994 */
995 static int put_char(struct tty_struct *tty, unsigned char ch)
996 {
997 SLMP_INFO *info = tty->driver_data;
998 unsigned long flags;
999 int ret = 0;
1000
1001 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1002 printk( "%s(%d):%s put_char(%d)\n",
1003 __FILE__,__LINE__,info->device_name,ch);
1004 }
1005
1006 if (sanity_check(info, tty->name, "put_char"))
1007 return 0;
1008
1009 if (!info->tx_buf)
1010 return 0;
1011
1012 spin_lock_irqsave(&info->lock,flags);
1013
1014 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1015 !info->tx_active ) {
1016
1017 if (info->tx_count < info->max_frame_size - 1) {
1018 info->tx_buf[info->tx_put++] = ch;
1019 if (info->tx_put >= info->max_frame_size)
1020 info->tx_put -= info->max_frame_size;
1021 info->tx_count++;
1022 ret = 1;
1023 }
1024 }
1025
1026 spin_unlock_irqrestore(&info->lock,flags);
1027 return ret;
1028 }
1029
1030 /* Send a high-priority XON/XOFF character
1031 */
1032 static void send_xchar(struct tty_struct *tty, char ch)
1033 {
1034 SLMP_INFO *info = tty->driver_data;
1035 unsigned long flags;
1036
1037 if (debug_level >= DEBUG_LEVEL_INFO)
1038 printk("%s(%d):%s send_xchar(%d)\n",
1039 __FILE__,__LINE__, info->device_name, ch );
1040
1041 if (sanity_check(info, tty->name, "send_xchar"))
1042 return;
1043
1044 info->x_char = ch;
1045 if (ch) {
1046 /* Make sure transmit interrupts are on */
1047 spin_lock_irqsave(&info->lock,flags);
1048 if (!info->tx_enabled)
1049 tx_start(info);
1050 spin_unlock_irqrestore(&info->lock,flags);
1051 }
1052 }
1053
1054 /* Wait until the transmitter is empty.
1055 */
1056 static void wait_until_sent(struct tty_struct *tty, int timeout)
1057 {
1058 SLMP_INFO * info = tty->driver_data;
1059 unsigned long orig_jiffies, char_time;
1060
1061 if (!info )
1062 return;
1063
1064 if (debug_level >= DEBUG_LEVEL_INFO)
1065 printk("%s(%d):%s wait_until_sent() entry\n",
1066 __FILE__,__LINE__, info->device_name );
1067
1068 if (sanity_check(info, tty->name, "wait_until_sent"))
1069 return;
1070
1071 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1072 goto exit;
1073
1074 orig_jiffies = jiffies;
1075
1076 /* Set check interval to 1/5 of estimated time to
1077 * send a character, and make it at least 1. The check
1078 * interval should also be less than the timeout.
1079 * Note: use tight timings here to satisfy the NIST-PCTS.
1080 */
1081
1082 if ( info->params.data_rate ) {
1083 char_time = info->timeout/(32 * 5);
1084 if (!char_time)
1085 char_time++;
1086 } else
1087 char_time = 1;
1088
1089 if (timeout)
1090 char_time = min_t(unsigned long, char_time, timeout);
1091
1092 if ( info->params.mode == MGSL_MODE_HDLC ) {
1093 while (info->tx_active) {
1094 msleep_interruptible(jiffies_to_msecs(char_time));
1095 if (signal_pending(current))
1096 break;
1097 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1098 break;
1099 }
1100 } else {
1101 /*
1102 * TODO: determine if there is something similar to USC16C32
1103 * TXSTATUS_ALL_SENT status
1104 */
1105 while ( info->tx_active && info->tx_enabled) {
1106 msleep_interruptible(jiffies_to_msecs(char_time));
1107 if (signal_pending(current))
1108 break;
1109 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1110 break;
1111 }
1112 }
1113
1114 exit:
1115 if (debug_level >= DEBUG_LEVEL_INFO)
1116 printk("%s(%d):%s wait_until_sent() exit\n",
1117 __FILE__,__LINE__, info->device_name );
1118 }
1119
1120 /* Return the count of free bytes in transmit buffer
1121 */
1122 static int write_room(struct tty_struct *tty)
1123 {
1124 SLMP_INFO *info = tty->driver_data;
1125 int ret;
1126
1127 if (sanity_check(info, tty->name, "write_room"))
1128 return 0;
1129
1130 if (info->params.mode == MGSL_MODE_HDLC) {
1131 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1132 } else {
1133 ret = info->max_frame_size - info->tx_count - 1;
1134 if (ret < 0)
1135 ret = 0;
1136 }
1137
1138 if (debug_level >= DEBUG_LEVEL_INFO)
1139 printk("%s(%d):%s write_room()=%d\n",
1140 __FILE__, __LINE__, info->device_name, ret);
1141
1142 return ret;
1143 }
1144
1145 /* enable transmitter and send remaining buffered characters
1146 */
1147 static void flush_chars(struct tty_struct *tty)
1148 {
1149 SLMP_INFO *info = tty->driver_data;
1150 unsigned long flags;
1151
1152 if ( debug_level >= DEBUG_LEVEL_INFO )
1153 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1154 __FILE__,__LINE__,info->device_name,info->tx_count);
1155
1156 if (sanity_check(info, tty->name, "flush_chars"))
1157 return;
1158
1159 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1160 !info->tx_buf)
1161 return;
1162
1163 if ( debug_level >= DEBUG_LEVEL_INFO )
1164 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1165 __FILE__,__LINE__,info->device_name );
1166
1167 spin_lock_irqsave(&info->lock,flags);
1168
1169 if (!info->tx_active) {
1170 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1171 info->tx_count ) {
1172 /* operating in synchronous (frame oriented) mode */
1173 /* copy data from circular tx_buf to */
1174 /* transmit DMA buffer. */
1175 tx_load_dma_buffer(info,
1176 info->tx_buf,info->tx_count);
1177 }
1178 tx_start(info);
1179 }
1180
1181 spin_unlock_irqrestore(&info->lock,flags);
1182 }
1183
1184 /* Discard all data in the send buffer
1185 */
1186 static void flush_buffer(struct tty_struct *tty)
1187 {
1188 SLMP_INFO *info = tty->driver_data;
1189 unsigned long flags;
1190
1191 if (debug_level >= DEBUG_LEVEL_INFO)
1192 printk("%s(%d):%s flush_buffer() entry\n",
1193 __FILE__,__LINE__, info->device_name );
1194
1195 if (sanity_check(info, tty->name, "flush_buffer"))
1196 return;
1197
1198 spin_lock_irqsave(&info->lock,flags);
1199 info->tx_count = info->tx_put = info->tx_get = 0;
1200 del_timer(&info->tx_timer);
1201 spin_unlock_irqrestore(&info->lock,flags);
1202
1203 tty_wakeup(tty);
1204 }
1205
1206 /* throttle (stop) transmitter
1207 */
1208 static void tx_hold(struct tty_struct *tty)
1209 {
1210 SLMP_INFO *info = tty->driver_data;
1211 unsigned long flags;
1212
1213 if (sanity_check(info, tty->name, "tx_hold"))
1214 return;
1215
1216 if ( debug_level >= DEBUG_LEVEL_INFO )
1217 printk("%s(%d):%s tx_hold()\n",
1218 __FILE__,__LINE__,info->device_name);
1219
1220 spin_lock_irqsave(&info->lock,flags);
1221 if (info->tx_enabled)
1222 tx_stop(info);
1223 spin_unlock_irqrestore(&info->lock,flags);
1224 }
1225
1226 /* release (start) transmitter
1227 */
1228 static void tx_release(struct tty_struct *tty)
1229 {
1230 SLMP_INFO *info = tty->driver_data;
1231 unsigned long flags;
1232
1233 if (sanity_check(info, tty->name, "tx_release"))
1234 return;
1235
1236 if ( debug_level >= DEBUG_LEVEL_INFO )
1237 printk("%s(%d):%s tx_release()\n",
1238 __FILE__,__LINE__,info->device_name);
1239
1240 spin_lock_irqsave(&info->lock,flags);
1241 if (!info->tx_enabled)
1242 tx_start(info);
1243 spin_unlock_irqrestore(&info->lock,flags);
1244 }
1245
1246 /* Service an IOCTL request
1247 *
1248 * Arguments:
1249 *
1250 * tty pointer to tty instance data
1251 * file pointer to associated file object for device
1252 * cmd IOCTL command code
1253 * arg command argument/context
1254 *
1255 * Return Value: 0 if success, otherwise error code
1256 */
1257 static int ioctl(struct tty_struct *tty, struct file *file,
1258 unsigned int cmd, unsigned long arg)
1259 {
1260 SLMP_INFO *info = tty->driver_data;
1261 void __user *argp = (void __user *)arg;
1262
1263 if (debug_level >= DEBUG_LEVEL_INFO)
1264 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1265 info->device_name, cmd );
1266
1267 if (sanity_check(info, tty->name, "ioctl"))
1268 return -ENODEV;
1269
1270 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1271 (cmd != TIOCMIWAIT)) {
1272 if (tty->flags & (1 << TTY_IO_ERROR))
1273 return -EIO;
1274 }
1275
1276 switch (cmd) {
1277 case MGSL_IOCGPARAMS:
1278 return get_params(info, argp);
1279 case MGSL_IOCSPARAMS:
1280 return set_params(info, argp);
1281 case MGSL_IOCGTXIDLE:
1282 return get_txidle(info, argp);
1283 case MGSL_IOCSTXIDLE:
1284 return set_txidle(info, (int)arg);
1285 case MGSL_IOCTXENABLE:
1286 return tx_enable(info, (int)arg);
1287 case MGSL_IOCRXENABLE:
1288 return rx_enable(info, (int)arg);
1289 case MGSL_IOCTXABORT:
1290 return tx_abort(info);
1291 case MGSL_IOCGSTATS:
1292 return get_stats(info, argp);
1293 case MGSL_IOCWAITEVENT:
1294 return wait_mgsl_event(info, argp);
1295 case MGSL_IOCLOOPTXDONE:
1296 return 0; // TODO: Not supported, need to document
1297 /* Wait for modem input (DCD,RI,DSR,CTS) change
1298 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1299 */
1300 case TIOCMIWAIT:
1301 return modem_input_wait(info,(int)arg);
1302
1303 /*
1304 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1305 * Return: write counters to the user passed counter struct
1306 * NB: both 1->0 and 0->1 transitions are counted except for
1307 * RI where only 0->1 is counted.
1308 */
1309 default:
1310 return -ENOIOCTLCMD;
1311 }
1312 return 0;
1313 }
1314
1315 static int get_icount(struct tty_struct *tty,
1316 struct serial_icounter_struct *icount)
1317 {
1318 SLMP_INFO *info = tty->driver_data;
1319 struct mgsl_icount cnow; /* kernel counter temps */
1320 unsigned long flags;
1321
1322 spin_lock_irqsave(&info->lock,flags);
1323 cnow = info->icount;
1324 spin_unlock_irqrestore(&info->lock,flags);
1325
1326 icount->cts = cnow.cts;
1327 icount->dsr = cnow.dsr;
1328 icount->rng = cnow.rng;
1329 icount->dcd = cnow.dcd;
1330 icount->rx = cnow.rx;
1331 icount->tx = cnow.tx;
1332 icount->frame = cnow.frame;
1333 icount->overrun = cnow.overrun;
1334 icount->parity = cnow.parity;
1335 icount->brk = cnow.brk;
1336 icount->buf_overrun = cnow.buf_overrun;
1337
1338 return 0;
1339 }
1340
1341 /*
1342 * /proc fs routines....
1343 */
1344
1345 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1346 {
1347 char stat_buf[30];
1348 unsigned long flags;
1349
1350 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1351 "\tIRQ=%d MaxFrameSize=%u\n",
1352 info->device_name,
1353 info->phys_sca_base,
1354 info->phys_memory_base,
1355 info->phys_statctrl_base,
1356 info->phys_lcr_base,
1357 info->irq_level,
1358 info->max_frame_size );
1359
1360 /* output current serial signal states */
1361 spin_lock_irqsave(&info->lock,flags);
1362 get_signals(info);
1363 spin_unlock_irqrestore(&info->lock,flags);
1364
1365 stat_buf[0] = 0;
1366 stat_buf[1] = 0;
1367 if (info->serial_signals & SerialSignal_RTS)
1368 strcat(stat_buf, "|RTS");
1369 if (info->serial_signals & SerialSignal_CTS)
1370 strcat(stat_buf, "|CTS");
1371 if (info->serial_signals & SerialSignal_DTR)
1372 strcat(stat_buf, "|DTR");
1373 if (info->serial_signals & SerialSignal_DSR)
1374 strcat(stat_buf, "|DSR");
1375 if (info->serial_signals & SerialSignal_DCD)
1376 strcat(stat_buf, "|CD");
1377 if (info->serial_signals & SerialSignal_RI)
1378 strcat(stat_buf, "|RI");
1379
1380 if (info->params.mode == MGSL_MODE_HDLC) {
1381 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1382 info->icount.txok, info->icount.rxok);
1383 if (info->icount.txunder)
1384 seq_printf(m, " txunder:%d", info->icount.txunder);
1385 if (info->icount.txabort)
1386 seq_printf(m, " txabort:%d", info->icount.txabort);
1387 if (info->icount.rxshort)
1388 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1389 if (info->icount.rxlong)
1390 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1391 if (info->icount.rxover)
1392 seq_printf(m, " rxover:%d", info->icount.rxover);
1393 if (info->icount.rxcrc)
1394 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1395 } else {
1396 seq_printf(m, "\tASYNC tx:%d rx:%d",
1397 info->icount.tx, info->icount.rx);
1398 if (info->icount.frame)
1399 seq_printf(m, " fe:%d", info->icount.frame);
1400 if (info->icount.parity)
1401 seq_printf(m, " pe:%d", info->icount.parity);
1402 if (info->icount.brk)
1403 seq_printf(m, " brk:%d", info->icount.brk);
1404 if (info->icount.overrun)
1405 seq_printf(m, " oe:%d", info->icount.overrun);
1406 }
1407
1408 /* Append serial signal status to end */
1409 seq_printf(m, " %s\n", stat_buf+1);
1410
1411 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1412 info->tx_active,info->bh_requested,info->bh_running,
1413 info->pending_bh);
1414 }
1415
1416 /* Called to print information about devices
1417 */
1418 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1419 {
1420 SLMP_INFO *info;
1421
1422 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1423
1424 info = synclinkmp_device_list;
1425 while( info ) {
1426 line_info(m, info);
1427 info = info->next_device;
1428 }
1429 return 0;
1430 }
1431
1432 static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1433 {
1434 return single_open(file, synclinkmp_proc_show, NULL);
1435 }
1436
1437 static const struct file_operations synclinkmp_proc_fops = {
1438 .owner = THIS_MODULE,
1439 .open = synclinkmp_proc_open,
1440 .read = seq_read,
1441 .llseek = seq_lseek,
1442 .release = single_release,
1443 };
1444
1445 /* Return the count of bytes in transmit buffer
1446 */
1447 static int chars_in_buffer(struct tty_struct *tty)
1448 {
1449 SLMP_INFO *info = tty->driver_data;
1450
1451 if (sanity_check(info, tty->name, "chars_in_buffer"))
1452 return 0;
1453
1454 if (debug_level >= DEBUG_LEVEL_INFO)
1455 printk("%s(%d):%s chars_in_buffer()=%d\n",
1456 __FILE__, __LINE__, info->device_name, info->tx_count);
1457
1458 return info->tx_count;
1459 }
1460
1461 /* Signal remote device to throttle send data (our receive data)
1462 */
1463 static void throttle(struct tty_struct * tty)
1464 {
1465 SLMP_INFO *info = tty->driver_data;
1466 unsigned long flags;
1467
1468 if (debug_level >= DEBUG_LEVEL_INFO)
1469 printk("%s(%d):%s throttle() entry\n",
1470 __FILE__,__LINE__, info->device_name );
1471
1472 if (sanity_check(info, tty->name, "throttle"))
1473 return;
1474
1475 if (I_IXOFF(tty))
1476 send_xchar(tty, STOP_CHAR(tty));
1477
1478 if (tty->termios->c_cflag & CRTSCTS) {
1479 spin_lock_irqsave(&info->lock,flags);
1480 info->serial_signals &= ~SerialSignal_RTS;
1481 set_signals(info);
1482 spin_unlock_irqrestore(&info->lock,flags);
1483 }
1484 }
1485
1486 /* Signal remote device to stop throttling send data (our receive data)
1487 */
1488 static void unthrottle(struct tty_struct * tty)
1489 {
1490 SLMP_INFO *info = tty->driver_data;
1491 unsigned long flags;
1492
1493 if (debug_level >= DEBUG_LEVEL_INFO)
1494 printk("%s(%d):%s unthrottle() entry\n",
1495 __FILE__,__LINE__, info->device_name );
1496
1497 if (sanity_check(info, tty->name, "unthrottle"))
1498 return;
1499
1500 if (I_IXOFF(tty)) {
1501 if (info->x_char)
1502 info->x_char = 0;
1503 else
1504 send_xchar(tty, START_CHAR(tty));
1505 }
1506
1507 if (tty->termios->c_cflag & CRTSCTS) {
1508 spin_lock_irqsave(&info->lock,flags);
1509 info->serial_signals |= SerialSignal_RTS;
1510 set_signals(info);
1511 spin_unlock_irqrestore(&info->lock,flags);
1512 }
1513 }
1514
1515 /* set or clear transmit break condition
1516 * break_state -1=set break condition, 0=clear
1517 */
1518 static int set_break(struct tty_struct *tty, int break_state)
1519 {
1520 unsigned char RegValue;
1521 SLMP_INFO * info = tty->driver_data;
1522 unsigned long flags;
1523
1524 if (debug_level >= DEBUG_LEVEL_INFO)
1525 printk("%s(%d):%s set_break(%d)\n",
1526 __FILE__,__LINE__, info->device_name, break_state);
1527
1528 if (sanity_check(info, tty->name, "set_break"))
1529 return -EINVAL;
1530
1531 spin_lock_irqsave(&info->lock,flags);
1532 RegValue = read_reg(info, CTL);
1533 if (break_state == -1)
1534 RegValue |= BIT3;
1535 else
1536 RegValue &= ~BIT3;
1537 write_reg(info, CTL, RegValue);
1538 spin_unlock_irqrestore(&info->lock,flags);
1539 return 0;
1540 }
1541
1542 #if SYNCLINK_GENERIC_HDLC
1543
1544 /**
1545 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1546 * set encoding and frame check sequence (FCS) options
1547 *
1548 * dev pointer to network device structure
1549 * encoding serial encoding setting
1550 * parity FCS setting
1551 *
1552 * returns 0 if success, otherwise error code
1553 */
1554 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1555 unsigned short parity)
1556 {
1557 SLMP_INFO *info = dev_to_port(dev);
1558 unsigned char new_encoding;
1559 unsigned short new_crctype;
1560
1561 /* return error if TTY interface open */
1562 if (info->port.count)
1563 return -EBUSY;
1564
1565 switch (encoding)
1566 {
1567 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1568 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1569 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1570 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1571 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1572 default: return -EINVAL;
1573 }
1574
1575 switch (parity)
1576 {
1577 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1578 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1579 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1580 default: return -EINVAL;
1581 }
1582
1583 info->params.encoding = new_encoding;
1584 info->params.crc_type = new_crctype;
1585
1586 /* if network interface up, reprogram hardware */
1587 if (info->netcount)
1588 program_hw(info);
1589
1590 return 0;
1591 }
1592
1593 /**
1594 * called by generic HDLC layer to send frame
1595 *
1596 * skb socket buffer containing HDLC frame
1597 * dev pointer to network device structure
1598 */
1599 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1600 struct net_device *dev)
1601 {
1602 SLMP_INFO *info = dev_to_port(dev);
1603 unsigned long flags;
1604
1605 if (debug_level >= DEBUG_LEVEL_INFO)
1606 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1607
1608 /* stop sending until this frame completes */
1609 netif_stop_queue(dev);
1610
1611 /* copy data to device buffers */
1612 info->tx_count = skb->len;
1613 tx_load_dma_buffer(info, skb->data, skb->len);
1614
1615 /* update network statistics */
1616 dev->stats.tx_packets++;
1617 dev->stats.tx_bytes += skb->len;
1618
1619 /* done with socket buffer, so free it */
1620 dev_kfree_skb(skb);
1621
1622 /* save start time for transmit timeout detection */
1623 dev->trans_start = jiffies;
1624
1625 /* start hardware transmitter if necessary */
1626 spin_lock_irqsave(&info->lock,flags);
1627 if (!info->tx_active)
1628 tx_start(info);
1629 spin_unlock_irqrestore(&info->lock,flags);
1630
1631 return NETDEV_TX_OK;
1632 }
1633
1634 /**
1635 * called by network layer when interface enabled
1636 * claim resources and initialize hardware
1637 *
1638 * dev pointer to network device structure
1639 *
1640 * returns 0 if success, otherwise error code
1641 */
1642 static int hdlcdev_open(struct net_device *dev)
1643 {
1644 SLMP_INFO *info = dev_to_port(dev);
1645 int rc;
1646 unsigned long flags;
1647
1648 if (debug_level >= DEBUG_LEVEL_INFO)
1649 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1650
1651 /* generic HDLC layer open processing */
1652 if ((rc = hdlc_open(dev)))
1653 return rc;
1654
1655 /* arbitrate between network and tty opens */
1656 spin_lock_irqsave(&info->netlock, flags);
1657 if (info->port.count != 0 || info->netcount != 0) {
1658 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1659 spin_unlock_irqrestore(&info->netlock, flags);
1660 return -EBUSY;
1661 }
1662 info->netcount=1;
1663 spin_unlock_irqrestore(&info->netlock, flags);
1664
1665 /* claim resources and init adapter */
1666 if ((rc = startup(info)) != 0) {
1667 spin_lock_irqsave(&info->netlock, flags);
1668 info->netcount=0;
1669 spin_unlock_irqrestore(&info->netlock, flags);
1670 return rc;
1671 }
1672
1673 /* assert DTR and RTS, apply hardware settings */
1674 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1675 program_hw(info);
1676
1677 /* enable network layer transmit */
1678 dev->trans_start = jiffies;
1679 netif_start_queue(dev);
1680
1681 /* inform generic HDLC layer of current DCD status */
1682 spin_lock_irqsave(&info->lock, flags);
1683 get_signals(info);
1684 spin_unlock_irqrestore(&info->lock, flags);
1685 if (info->serial_signals & SerialSignal_DCD)
1686 netif_carrier_on(dev);
1687 else
1688 netif_carrier_off(dev);
1689 return 0;
1690 }
1691
1692 /**
1693 * called by network layer when interface is disabled
1694 * shutdown hardware and release resources
1695 *
1696 * dev pointer to network device structure
1697 *
1698 * returns 0 if success, otherwise error code
1699 */
1700 static int hdlcdev_close(struct net_device *dev)
1701 {
1702 SLMP_INFO *info = dev_to_port(dev);
1703 unsigned long flags;
1704
1705 if (debug_level >= DEBUG_LEVEL_INFO)
1706 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1707
1708 netif_stop_queue(dev);
1709
1710 /* shutdown adapter and release resources */
1711 shutdown(info);
1712
1713 hdlc_close(dev);
1714
1715 spin_lock_irqsave(&info->netlock, flags);
1716 info->netcount=0;
1717 spin_unlock_irqrestore(&info->netlock, flags);
1718
1719 return 0;
1720 }
1721
1722 /**
1723 * called by network layer to process IOCTL call to network device
1724 *
1725 * dev pointer to network device structure
1726 * ifr pointer to network interface request structure
1727 * cmd IOCTL command code
1728 *
1729 * returns 0 if success, otherwise error code
1730 */
1731 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1732 {
1733 const size_t size = sizeof(sync_serial_settings);
1734 sync_serial_settings new_line;
1735 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1736 SLMP_INFO *info = dev_to_port(dev);
1737 unsigned int flags;
1738
1739 if (debug_level >= DEBUG_LEVEL_INFO)
1740 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1741
1742 /* return error if TTY interface open */
1743 if (info->port.count)
1744 return -EBUSY;
1745
1746 if (cmd != SIOCWANDEV)
1747 return hdlc_ioctl(dev, ifr, cmd);
1748
1749 switch(ifr->ifr_settings.type) {
1750 case IF_GET_IFACE: /* return current sync_serial_settings */
1751
1752 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1753 if (ifr->ifr_settings.size < size) {
1754 ifr->ifr_settings.size = size; /* data size wanted */
1755 return -ENOBUFS;
1756 }
1757
1758 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1759 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1760 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1761 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1762
1763 switch (flags){
1764 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1765 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1766 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1767 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1768 default: new_line.clock_type = CLOCK_DEFAULT;
1769 }
1770
1771 new_line.clock_rate = info->params.clock_speed;
1772 new_line.loopback = info->params.loopback ? 1:0;
1773
1774 if (copy_to_user(line, &new_line, size))
1775 return -EFAULT;
1776 return 0;
1777
1778 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1779
1780 if(!capable(CAP_NET_ADMIN))
1781 return -EPERM;
1782 if (copy_from_user(&new_line, line, size))
1783 return -EFAULT;
1784
1785 switch (new_line.clock_type)
1786 {
1787 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1788 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1789 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1790 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1791 case CLOCK_DEFAULT: flags = info->params.flags &
1792 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1793 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1794 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1795 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1796 default: return -EINVAL;
1797 }
1798
1799 if (new_line.loopback != 0 && new_line.loopback != 1)
1800 return -EINVAL;
1801
1802 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1803 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1804 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1805 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1806 info->params.flags |= flags;
1807
1808 info->params.loopback = new_line.loopback;
1809
1810 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1811 info->params.clock_speed = new_line.clock_rate;
1812 else
1813 info->params.clock_speed = 0;
1814
1815 /* if network interface up, reprogram hardware */
1816 if (info->netcount)
1817 program_hw(info);
1818 return 0;
1819
1820 default:
1821 return hdlc_ioctl(dev, ifr, cmd);
1822 }
1823 }
1824
1825 /**
1826 * called by network layer when transmit timeout is detected
1827 *
1828 * dev pointer to network device structure
1829 */
1830 static void hdlcdev_tx_timeout(struct net_device *dev)
1831 {
1832 SLMP_INFO *info = dev_to_port(dev);
1833 unsigned long flags;
1834
1835 if (debug_level >= DEBUG_LEVEL_INFO)
1836 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1837
1838 dev->stats.tx_errors++;
1839 dev->stats.tx_aborted_errors++;
1840
1841 spin_lock_irqsave(&info->lock,flags);
1842 tx_stop(info);
1843 spin_unlock_irqrestore(&info->lock,flags);
1844
1845 netif_wake_queue(dev);
1846 }
1847
1848 /**
1849 * called by device driver when transmit completes
1850 * reenable network layer transmit if stopped
1851 *
1852 * info pointer to device instance information
1853 */
1854 static void hdlcdev_tx_done(SLMP_INFO *info)
1855 {
1856 if (netif_queue_stopped(info->netdev))
1857 netif_wake_queue(info->netdev);
1858 }
1859
1860 /**
1861 * called by device driver when frame received
1862 * pass frame to network layer
1863 *
1864 * info pointer to device instance information
1865 * buf pointer to buffer contianing frame data
1866 * size count of data bytes in buf
1867 */
1868 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1869 {
1870 struct sk_buff *skb = dev_alloc_skb(size);
1871 struct net_device *dev = info->netdev;
1872
1873 if (debug_level >= DEBUG_LEVEL_INFO)
1874 printk("hdlcdev_rx(%s)\n",dev->name);
1875
1876 if (skb == NULL) {
1877 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1878 dev->name);
1879 dev->stats.rx_dropped++;
1880 return;
1881 }
1882
1883 memcpy(skb_put(skb, size), buf, size);
1884
1885 skb->protocol = hdlc_type_trans(skb, dev);
1886
1887 dev->stats.rx_packets++;
1888 dev->stats.rx_bytes += size;
1889
1890 netif_rx(skb);
1891 }
1892
1893 static const struct net_device_ops hdlcdev_ops = {
1894 .ndo_open = hdlcdev_open,
1895 .ndo_stop = hdlcdev_close,
1896 .ndo_change_mtu = hdlc_change_mtu,
1897 .ndo_start_xmit = hdlc_start_xmit,
1898 .ndo_do_ioctl = hdlcdev_ioctl,
1899 .ndo_tx_timeout = hdlcdev_tx_timeout,
1900 };
1901
1902 /**
1903 * called by device driver when adding device instance
1904 * do generic HDLC initialization
1905 *
1906 * info pointer to device instance information
1907 *
1908 * returns 0 if success, otherwise error code
1909 */
1910 static int hdlcdev_init(SLMP_INFO *info)
1911 {
1912 int rc;
1913 struct net_device *dev;
1914 hdlc_device *hdlc;
1915
1916 /* allocate and initialize network and HDLC layer objects */
1917
1918 if (!(dev = alloc_hdlcdev(info))) {
1919 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1920 return -ENOMEM;
1921 }
1922
1923 /* for network layer reporting purposes only */
1924 dev->mem_start = info->phys_sca_base;
1925 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1926 dev->irq = info->irq_level;
1927
1928 /* network layer callbacks and settings */
1929 dev->netdev_ops = &hdlcdev_ops;
1930 dev->watchdog_timeo = 10 * HZ;
1931 dev->tx_queue_len = 50;
1932
1933 /* generic HDLC layer callbacks and settings */
1934 hdlc = dev_to_hdlc(dev);
1935 hdlc->attach = hdlcdev_attach;
1936 hdlc->xmit = hdlcdev_xmit;
1937
1938 /* register objects with HDLC layer */
1939 if ((rc = register_hdlc_device(dev))) {
1940 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1941 free_netdev(dev);
1942 return rc;
1943 }
1944
1945 info->netdev = dev;
1946 return 0;
1947 }
1948
1949 /**
1950 * called by device driver when removing device instance
1951 * do generic HDLC cleanup
1952 *
1953 * info pointer to device instance information
1954 */
1955 static void hdlcdev_exit(SLMP_INFO *info)
1956 {
1957 unregister_hdlc_device(info->netdev);
1958 free_netdev(info->netdev);
1959 info->netdev = NULL;
1960 }
1961
1962 #endif /* CONFIG_HDLC */
1963
1964
1965 /* Return next bottom half action to perform.
1966 * Return Value: BH action code or 0 if nothing to do.
1967 */
1968 static int bh_action(SLMP_INFO *info)
1969 {
1970 unsigned long flags;
1971 int rc = 0;
1972
1973 spin_lock_irqsave(&info->lock,flags);
1974
1975 if (info->pending_bh & BH_RECEIVE) {
1976 info->pending_bh &= ~BH_RECEIVE;
1977 rc = BH_RECEIVE;
1978 } else if (info->pending_bh & BH_TRANSMIT) {
1979 info->pending_bh &= ~BH_TRANSMIT;
1980 rc = BH_TRANSMIT;
1981 } else if (info->pending_bh & BH_STATUS) {
1982 info->pending_bh &= ~BH_STATUS;
1983 rc = BH_STATUS;
1984 }
1985
1986 if (!rc) {
1987 /* Mark BH routine as complete */
1988 info->bh_running = false;
1989 info->bh_requested = false;
1990 }
1991
1992 spin_unlock_irqrestore(&info->lock,flags);
1993
1994 return rc;
1995 }
1996
1997 /* Perform bottom half processing of work items queued by ISR.
1998 */
1999 static void bh_handler(struct work_struct *work)
2000 {
2001 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2002 int action;
2003
2004 if (!info)
2005 return;
2006
2007 if ( debug_level >= DEBUG_LEVEL_BH )
2008 printk( "%s(%d):%s bh_handler() entry\n",
2009 __FILE__,__LINE__,info->device_name);
2010
2011 info->bh_running = true;
2012
2013 while((action = bh_action(info)) != 0) {
2014
2015 /* Process work item */
2016 if ( debug_level >= DEBUG_LEVEL_BH )
2017 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2018 __FILE__,__LINE__,info->device_name, action);
2019
2020 switch (action) {
2021
2022 case BH_RECEIVE:
2023 bh_receive(info);
2024 break;
2025 case BH_TRANSMIT:
2026 bh_transmit(info);
2027 break;
2028 case BH_STATUS:
2029 bh_status(info);
2030 break;
2031 default:
2032 /* unknown work item ID */
2033 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2034 __FILE__,__LINE__,info->device_name,action);
2035 break;
2036 }
2037 }
2038
2039 if ( debug_level >= DEBUG_LEVEL_BH )
2040 printk( "%s(%d):%s bh_handler() exit\n",
2041 __FILE__,__LINE__,info->device_name);
2042 }
2043
2044 static void bh_receive(SLMP_INFO *info)
2045 {
2046 if ( debug_level >= DEBUG_LEVEL_BH )
2047 printk( "%s(%d):%s bh_receive()\n",
2048 __FILE__,__LINE__,info->device_name);
2049
2050 while( rx_get_frame(info) );
2051 }
2052
2053 static void bh_transmit(SLMP_INFO *info)
2054 {
2055 struct tty_struct *tty = info->port.tty;
2056
2057 if ( debug_level >= DEBUG_LEVEL_BH )
2058 printk( "%s(%d):%s bh_transmit() entry\n",
2059 __FILE__,__LINE__,info->device_name);
2060
2061 if (tty)
2062 tty_wakeup(tty);
2063 }
2064
2065 static void bh_status(SLMP_INFO *info)
2066 {
2067 if ( debug_level >= DEBUG_LEVEL_BH )
2068 printk( "%s(%d):%s bh_status() entry\n",
2069 __FILE__,__LINE__,info->device_name);
2070
2071 info->ri_chkcount = 0;
2072 info->dsr_chkcount = 0;
2073 info->dcd_chkcount = 0;
2074 info->cts_chkcount = 0;
2075 }
2076
2077 static void isr_timer(SLMP_INFO * info)
2078 {
2079 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2080
2081 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2082 write_reg(info, IER2, 0);
2083
2084 /* TMCS, Timer Control/Status Register
2085 *
2086 * 07 CMF, Compare match flag (read only) 1=match
2087 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2088 * 05 Reserved, must be 0
2089 * 04 TME, Timer Enable
2090 * 03..00 Reserved, must be 0
2091 *
2092 * 0000 0000
2093 */
2094 write_reg(info, (unsigned char)(timer + TMCS), 0);
2095
2096 info->irq_occurred = true;
2097
2098 if ( debug_level >= DEBUG_LEVEL_ISR )
2099 printk("%s(%d):%s isr_timer()\n",
2100 __FILE__,__LINE__,info->device_name);
2101 }
2102
2103 static void isr_rxint(SLMP_INFO * info)
2104 {
2105 struct tty_struct *tty = info->port.tty;
2106 struct mgsl_icount *icount = &info->icount;
2107 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2108 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2109
2110 /* clear status bits */
2111 if (status)
2112 write_reg(info, SR1, status);
2113
2114 if (status2)
2115 write_reg(info, SR2, status2);
2116
2117 if ( debug_level >= DEBUG_LEVEL_ISR )
2118 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2119 __FILE__,__LINE__,info->device_name,status,status2);
2120
2121 if (info->params.mode == MGSL_MODE_ASYNC) {
2122 if (status & BRKD) {
2123 icount->brk++;
2124
2125 /* process break detection if tty control
2126 * is not set to ignore it
2127 */
2128 if ( tty ) {
2129 if (!(status & info->ignore_status_mask1)) {
2130 if (info->read_status_mask1 & BRKD) {
2131 tty_insert_flip_char(tty, 0, TTY_BREAK);
2132 if (info->port.flags & ASYNC_SAK)
2133 do_SAK(tty);
2134 }
2135 }
2136 }
2137 }
2138 }
2139 else {
2140 if (status & (FLGD|IDLD)) {
2141 if (status & FLGD)
2142 info->icount.exithunt++;
2143 else if (status & IDLD)
2144 info->icount.rxidle++;
2145 wake_up_interruptible(&info->event_wait_q);
2146 }
2147 }
2148
2149 if (status & CDCD) {
2150 /* simulate a common modem status change interrupt
2151 * for our handler
2152 */
2153 get_signals( info );
2154 isr_io_pin(info,
2155 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2156 }
2157 }
2158
2159 /*
2160 * handle async rx data interrupts
2161 */
2162 static void isr_rxrdy(SLMP_INFO * info)
2163 {
2164 u16 status;
2165 unsigned char DataByte;
2166 struct tty_struct *tty = info->port.tty;
2167 struct mgsl_icount *icount = &info->icount;
2168
2169 if ( debug_level >= DEBUG_LEVEL_ISR )
2170 printk("%s(%d):%s isr_rxrdy\n",
2171 __FILE__,__LINE__,info->device_name);
2172
2173 while((status = read_reg(info,CST0)) & BIT0)
2174 {
2175 int flag = 0;
2176 bool over = false;
2177 DataByte = read_reg(info,TRB);
2178
2179 icount->rx++;
2180
2181 if ( status & (PE + FRME + OVRN) ) {
2182 printk("%s(%d):%s rxerr=%04X\n",
2183 __FILE__,__LINE__,info->device_name,status);
2184
2185 /* update error statistics */
2186 if (status & PE)
2187 icount->parity++;
2188 else if (status & FRME)
2189 icount->frame++;
2190 else if (status & OVRN)
2191 icount->overrun++;
2192
2193 /* discard char if tty control flags say so */
2194 if (status & info->ignore_status_mask2)
2195 continue;
2196
2197 status &= info->read_status_mask2;
2198
2199 if ( tty ) {
2200 if (status & PE)
2201 flag = TTY_PARITY;
2202 else if (status & FRME)
2203 flag = TTY_FRAME;
2204 if (status & OVRN) {
2205 /* Overrun is special, since it's
2206 * reported immediately, and doesn't
2207 * affect the current character
2208 */
2209 over = true;
2210 }
2211 }
2212 } /* end of if (error) */
2213
2214 if ( tty ) {
2215 tty_insert_flip_char(tty, DataByte, flag);
2216 if (over)
2217 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2218 }
2219 }
2220
2221 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2222 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2223 __FILE__,__LINE__,info->device_name,
2224 icount->rx,icount->brk,icount->parity,
2225 icount->frame,icount->overrun);
2226 }
2227
2228 if ( tty )
2229 tty_flip_buffer_push(tty);
2230 }
2231
2232 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2233 {
2234 if ( debug_level >= DEBUG_LEVEL_ISR )
2235 printk("%s(%d):%s isr_txeom status=%02x\n",
2236 __FILE__,__LINE__,info->device_name,status);
2237
2238 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2239 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2240 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2241
2242 if (status & UDRN) {
2243 write_reg(info, CMD, TXRESET);
2244 write_reg(info, CMD, TXENABLE);
2245 } else
2246 write_reg(info, CMD, TXBUFCLR);
2247
2248 /* disable and clear tx interrupts */
2249 info->ie0_value &= ~TXRDYE;
2250 info->ie1_value &= ~(IDLE + UDRN);
2251 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2252 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2253
2254 if ( info->tx_active ) {
2255 if (info->params.mode != MGSL_MODE_ASYNC) {
2256 if (status & UDRN)
2257 info->icount.txunder++;
2258 else if (status & IDLE)
2259 info->icount.txok++;
2260 }
2261
2262 info->tx_active = false;
2263 info->tx_count = info->tx_put = info->tx_get = 0;
2264
2265 del_timer(&info->tx_timer);
2266
2267 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2268 info->serial_signals &= ~SerialSignal_RTS;
2269 info->drop_rts_on_tx_done = false;
2270 set_signals(info);
2271 }
2272
2273 #if SYNCLINK_GENERIC_HDLC
2274 if (info->netcount)
2275 hdlcdev_tx_done(info);
2276 else
2277 #endif
2278 {
2279 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2280 tx_stop(info);
2281 return;
2282 }
2283 info->pending_bh |= BH_TRANSMIT;
2284 }
2285 }
2286 }
2287
2288
2289 /*
2290 * handle tx status interrupts
2291 */
2292 static void isr_txint(SLMP_INFO * info)
2293 {
2294 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2295
2296 /* clear status bits */
2297 write_reg(info, SR1, status);
2298
2299 if ( debug_level >= DEBUG_LEVEL_ISR )
2300 printk("%s(%d):%s isr_txint status=%02x\n",
2301 __FILE__,__LINE__,info->device_name,status);
2302
2303 if (status & (UDRN + IDLE))
2304 isr_txeom(info, status);
2305
2306 if (status & CCTS) {
2307 /* simulate a common modem status change interrupt
2308 * for our handler
2309 */
2310 get_signals( info );
2311 isr_io_pin(info,
2312 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2313
2314 }
2315 }
2316
2317 /*
2318 * handle async tx data interrupts
2319 */
2320 static void isr_txrdy(SLMP_INFO * info)
2321 {
2322 if ( debug_level >= DEBUG_LEVEL_ISR )
2323 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2324 __FILE__,__LINE__,info->device_name,info->tx_count);
2325
2326 if (info->params.mode != MGSL_MODE_ASYNC) {
2327 /* disable TXRDY IRQ, enable IDLE IRQ */
2328 info->ie0_value &= ~TXRDYE;
2329 info->ie1_value |= IDLE;
2330 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2331 return;
2332 }
2333
2334 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2335 tx_stop(info);
2336 return;
2337 }
2338
2339 if ( info->tx_count )
2340 tx_load_fifo( info );
2341 else {
2342 info->tx_active = false;
2343 info->ie0_value &= ~TXRDYE;
2344 write_reg(info, IE0, info->ie0_value);
2345 }
2346
2347 if (info->tx_count < WAKEUP_CHARS)
2348 info->pending_bh |= BH_TRANSMIT;
2349 }
2350
2351 static void isr_rxdmaok(SLMP_INFO * info)
2352 {
2353 /* BIT7 = EOT (end of transfer)
2354 * BIT6 = EOM (end of message/frame)
2355 */
2356 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2357
2358 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2359 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2360
2361 if ( debug_level >= DEBUG_LEVEL_ISR )
2362 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2363 __FILE__,__LINE__,info->device_name,status);
2364
2365 info->pending_bh |= BH_RECEIVE;
2366 }
2367
2368 static void isr_rxdmaerror(SLMP_INFO * info)
2369 {
2370 /* BIT5 = BOF (buffer overflow)
2371 * BIT4 = COF (counter overflow)
2372 */
2373 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2374
2375 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2376 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2377
2378 if ( debug_level >= DEBUG_LEVEL_ISR )
2379 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2380 __FILE__,__LINE__,info->device_name,status);
2381
2382 info->rx_overflow = true;
2383 info->pending_bh |= BH_RECEIVE;
2384 }
2385
2386 static void isr_txdmaok(SLMP_INFO * info)
2387 {
2388 unsigned char status_reg1 = read_reg(info, SR1);
2389
2390 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2391 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2392 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2393
2394 if ( debug_level >= DEBUG_LEVEL_ISR )
2395 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2396 __FILE__,__LINE__,info->device_name,status_reg1);
2397
2398 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2399 write_reg16(info, TRC0, 0);
2400 info->ie0_value |= TXRDYE;
2401 write_reg(info, IE0, info->ie0_value);
2402 }
2403
2404 static void isr_txdmaerror(SLMP_INFO * info)
2405 {
2406 /* BIT5 = BOF (buffer overflow)
2407 * BIT4 = COF (counter overflow)
2408 */
2409 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2410
2411 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2412 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2413
2414 if ( debug_level >= DEBUG_LEVEL_ISR )
2415 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2416 __FILE__,__LINE__,info->device_name,status);
2417 }
2418
2419 /* handle input serial signal changes
2420 */
2421 static void isr_io_pin( SLMP_INFO *info, u16 status )
2422 {
2423 struct mgsl_icount *icount;
2424
2425 if ( debug_level >= DEBUG_LEVEL_ISR )
2426 printk("%s(%d):isr_io_pin status=%04X\n",
2427 __FILE__,__LINE__,status);
2428
2429 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2430 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2431 icount = &info->icount;
2432 /* update input line counters */
2433 if (status & MISCSTATUS_RI_LATCHED) {
2434 icount->rng++;
2435 if ( status & SerialSignal_RI )
2436 info->input_signal_events.ri_up++;
2437 else
2438 info->input_signal_events.ri_down++;
2439 }
2440 if (status & MISCSTATUS_DSR_LATCHED) {
2441 icount->dsr++;
2442 if ( status & SerialSignal_DSR )
2443 info->input_signal_events.dsr_up++;
2444 else
2445 info->input_signal_events.dsr_down++;
2446 }
2447 if (status & MISCSTATUS_DCD_LATCHED) {
2448 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2449 info->ie1_value &= ~CDCD;
2450 write_reg(info, IE1, info->ie1_value);
2451 }
2452 icount->dcd++;
2453 if (status & SerialSignal_DCD) {
2454 info->input_signal_events.dcd_up++;
2455 } else
2456 info->input_signal_events.dcd_down++;
2457 #if SYNCLINK_GENERIC_HDLC
2458 if (info->netcount) {
2459 if (status & SerialSignal_DCD)
2460 netif_carrier_on(info->netdev);
2461 else
2462 netif_carrier_off(info->netdev);
2463 }
2464 #endif
2465 }
2466 if (status & MISCSTATUS_CTS_LATCHED)
2467 {
2468 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2469 info->ie1_value &= ~CCTS;
2470 write_reg(info, IE1, info->ie1_value);
2471 }
2472 icount->cts++;
2473 if ( status & SerialSignal_CTS )
2474 info->input_signal_events.cts_up++;
2475 else
2476 info->input_signal_events.cts_down++;
2477 }
2478 wake_up_interruptible(&info->status_event_wait_q);
2479 wake_up_interruptible(&info->event_wait_q);
2480
2481 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2482 (status & MISCSTATUS_DCD_LATCHED) ) {
2483 if ( debug_level >= DEBUG_LEVEL_ISR )
2484 printk("%s CD now %s...", info->device_name,
2485 (status & SerialSignal_DCD) ? "on" : "off");
2486 if (status & SerialSignal_DCD)
2487 wake_up_interruptible(&info->port.open_wait);
2488 else {
2489 if ( debug_level >= DEBUG_LEVEL_ISR )
2490 printk("doing serial hangup...");
2491 if (info->port.tty)
2492 tty_hangup(info->port.tty);
2493 }
2494 }
2495
2496 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2497 (status & MISCSTATUS_CTS_LATCHED) ) {
2498 if ( info->port.tty ) {
2499 if (info->port.tty->hw_stopped) {
2500 if (status & SerialSignal_CTS) {
2501 if ( debug_level >= DEBUG_LEVEL_ISR )
2502 printk("CTS tx start...");
2503 info->port.tty->hw_stopped = 0;
2504 tx_start(info);
2505 info->pending_bh |= BH_TRANSMIT;
2506 return;
2507 }
2508 } else {
2509 if (!(status & SerialSignal_CTS)) {
2510 if ( debug_level >= DEBUG_LEVEL_ISR )
2511 printk("CTS tx stop...");
2512 info->port.tty->hw_stopped = 1;
2513 tx_stop(info);
2514 }
2515 }
2516 }
2517 }
2518 }
2519
2520 info->pending_bh |= BH_STATUS;
2521 }
2522
2523 /* Interrupt service routine entry point.
2524 *
2525 * Arguments:
2526 * irq interrupt number that caused interrupt
2527 * dev_id device ID supplied during interrupt registration
2528 * regs interrupted processor context
2529 */
2530 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2531 {
2532 SLMP_INFO *info = dev_id;
2533 unsigned char status, status0, status1=0;
2534 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2535 unsigned char timerstatus0, timerstatus1=0;
2536 unsigned char shift;
2537 unsigned int i;
2538 unsigned short tmp;
2539
2540 if ( debug_level >= DEBUG_LEVEL_ISR )
2541 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2542 __FILE__, __LINE__, info->irq_level);
2543
2544 spin_lock(&info->lock);
2545
2546 for(;;) {
2547
2548 /* get status for SCA0 (ports 0-1) */
2549 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2550 status0 = (unsigned char)tmp;
2551 dmastatus0 = (unsigned char)(tmp>>8);
2552 timerstatus0 = read_reg(info, ISR2);
2553
2554 if ( debug_level >= DEBUG_LEVEL_ISR )
2555 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2556 __FILE__, __LINE__, info->device_name,
2557 status0, dmastatus0, timerstatus0);
2558
2559 if (info->port_count == 4) {
2560 /* get status for SCA1 (ports 2-3) */
2561 tmp = read_reg16(info->port_array[2], ISR0);
2562 status1 = (unsigned char)tmp;
2563 dmastatus1 = (unsigned char)(tmp>>8);
2564 timerstatus1 = read_reg(info->port_array[2], ISR2);
2565
2566 if ( debug_level >= DEBUG_LEVEL_ISR )
2567 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2568 __FILE__,__LINE__,info->device_name,
2569 status1,dmastatus1,timerstatus1);
2570 }
2571
2572 if (!status0 && !dmastatus0 && !timerstatus0 &&
2573 !status1 && !dmastatus1 && !timerstatus1)
2574 break;
2575
2576 for(i=0; i < info->port_count ; i++) {
2577 if (info->port_array[i] == NULL)
2578 continue;
2579 if (i < 2) {
2580 status = status0;
2581 dmastatus = dmastatus0;
2582 } else {
2583 status = status1;
2584 dmastatus = dmastatus1;
2585 }
2586
2587 shift = i & 1 ? 4 :0;
2588
2589 if (status & BIT0 << shift)
2590 isr_rxrdy(info->port_array[i]);
2591 if (status & BIT1 << shift)
2592 isr_txrdy(info->port_array[i]);
2593 if (status & BIT2 << shift)
2594 isr_rxint(info->port_array[i]);
2595 if (status & BIT3 << shift)
2596 isr_txint(info->port_array[i]);
2597
2598 if (dmastatus & BIT0 << shift)
2599 isr_rxdmaerror(info->port_array[i]);
2600 if (dmastatus & BIT1 << shift)
2601 isr_rxdmaok(info->port_array[i]);
2602 if (dmastatus & BIT2 << shift)
2603 isr_txdmaerror(info->port_array[i]);
2604 if (dmastatus & BIT3 << shift)
2605 isr_txdmaok(info->port_array[i]);
2606 }
2607
2608 if (timerstatus0 & (BIT5 | BIT4))
2609 isr_timer(info->port_array[0]);
2610 if (timerstatus0 & (BIT7 | BIT6))
2611 isr_timer(info->port_array[1]);
2612 if (timerstatus1 & (BIT5 | BIT4))
2613 isr_timer(info->port_array[2]);
2614 if (timerstatus1 & (BIT7 | BIT6))
2615 isr_timer(info->port_array[3]);
2616 }
2617
2618 for(i=0; i < info->port_count ; i++) {
2619 SLMP_INFO * port = info->port_array[i];
2620
2621 /* Request bottom half processing if there's something
2622 * for it to do and the bh is not already running.
2623 *
2624 * Note: startup adapter diags require interrupts.
2625 * do not request bottom half processing if the
2626 * device is not open in a normal mode.
2627 */
2628 if ( port && (port->port.count || port->netcount) &&
2629 port->pending_bh && !port->bh_running &&
2630 !port->bh_requested ) {
2631 if ( debug_level >= DEBUG_LEVEL_ISR )
2632 printk("%s(%d):%s queueing bh task.\n",
2633 __FILE__,__LINE__,port->device_name);
2634 schedule_work(&port->task);
2635 port->bh_requested = true;
2636 }
2637 }
2638
2639 spin_unlock(&info->lock);
2640
2641 if ( debug_level >= DEBUG_LEVEL_ISR )
2642 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2643 __FILE__, __LINE__, info->irq_level);
2644 return IRQ_HANDLED;
2645 }
2646
2647 /* Initialize and start device.
2648 */
2649 static int startup(SLMP_INFO * info)
2650 {
2651 if ( debug_level >= DEBUG_LEVEL_INFO )
2652 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2653
2654 if (info->port.flags & ASYNC_INITIALIZED)
2655 return 0;
2656
2657 if (!info->tx_buf) {
2658 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2659 if (!info->tx_buf) {
2660 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2661 __FILE__,__LINE__,info->device_name);
2662 return -ENOMEM;
2663 }
2664 }
2665
2666 info->pending_bh = 0;
2667
2668 memset(&info->icount, 0, sizeof(info->icount));
2669
2670 /* program hardware for current parameters */
2671 reset_port(info);
2672
2673 change_params(info);
2674
2675 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2676
2677 if (info->port.tty)
2678 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2679
2680 info->port.flags |= ASYNC_INITIALIZED;
2681
2682 return 0;
2683 }
2684
2685 /* Called by close() and hangup() to shutdown hardware
2686 */
2687 static void shutdown(SLMP_INFO * info)
2688 {
2689 unsigned long flags;
2690
2691 if (!(info->port.flags & ASYNC_INITIALIZED))
2692 return;
2693
2694 if (debug_level >= DEBUG_LEVEL_INFO)
2695 printk("%s(%d):%s synclinkmp_shutdown()\n",
2696 __FILE__,__LINE__, info->device_name );
2697
2698 /* clear status wait queue because status changes */
2699 /* can't happen after shutting down the hardware */
2700 wake_up_interruptible(&info->status_event_wait_q);
2701 wake_up_interruptible(&info->event_wait_q);
2702
2703 del_timer(&info->tx_timer);
2704 del_timer(&info->status_timer);
2705
2706 kfree(info->tx_buf);
2707 info->tx_buf = NULL;
2708
2709 spin_lock_irqsave(&info->lock,flags);
2710
2711 reset_port(info);
2712
2713 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2714 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2715 set_signals(info);
2716 }
2717
2718 spin_unlock_irqrestore(&info->lock,flags);
2719
2720 if (info->port.tty)
2721 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2722
2723 info->port.flags &= ~ASYNC_INITIALIZED;
2724 }
2725
2726 static void program_hw(SLMP_INFO *info)
2727 {
2728 unsigned long flags;
2729
2730 spin_lock_irqsave(&info->lock,flags);
2731
2732 rx_stop(info);
2733 tx_stop(info);
2734
2735 info->tx_count = info->tx_put = info->tx_get = 0;
2736
2737 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2738 hdlc_mode(info);
2739 else
2740 async_mode(info);
2741
2742 set_signals(info);
2743
2744 info->dcd_chkcount = 0;
2745 info->cts_chkcount = 0;
2746 info->ri_chkcount = 0;
2747 info->dsr_chkcount = 0;
2748
2749 info->ie1_value |= (CDCD|CCTS);
2750 write_reg(info, IE1, info->ie1_value);
2751
2752 get_signals(info);
2753
2754 if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2755 rx_start(info);
2756
2757 spin_unlock_irqrestore(&info->lock,flags);
2758 }
2759
2760 /* Reconfigure adapter based on new parameters
2761 */
2762 static void change_params(SLMP_INFO *info)
2763 {
2764 unsigned cflag;
2765 int bits_per_char;
2766
2767 if (!info->port.tty || !info->port.tty->termios)
2768 return;
2769
2770 if (debug_level >= DEBUG_LEVEL_INFO)
2771 printk("%s(%d):%s change_params()\n",
2772 __FILE__,__LINE__, info->device_name );
2773
2774 cflag = info->port.tty->termios->c_cflag;
2775
2776 /* if B0 rate (hangup) specified then negate DTR and RTS */
2777 /* otherwise assert DTR and RTS */
2778 if (cflag & CBAUD)
2779 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2780 else
2781 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2782
2783 /* byte size and parity */
2784
2785 switch (cflag & CSIZE) {
2786 case CS5: info->params.data_bits = 5; break;
2787 case CS6: info->params.data_bits = 6; break;
2788 case CS7: info->params.data_bits = 7; break;
2789 case CS8: info->params.data_bits = 8; break;
2790 /* Never happens, but GCC is too dumb to figure it out */
2791 default: info->params.data_bits = 7; break;
2792 }
2793
2794 if (cflag & CSTOPB)
2795 info->params.stop_bits = 2;
2796 else
2797 info->params.stop_bits = 1;
2798
2799 info->params.parity = ASYNC_PARITY_NONE;
2800 if (cflag & PARENB) {
2801 if (cflag & PARODD)
2802 info->params.parity = ASYNC_PARITY_ODD;
2803 else
2804 info->params.parity = ASYNC_PARITY_EVEN;
2805 #ifdef CMSPAR
2806 if (cflag & CMSPAR)
2807 info->params.parity = ASYNC_PARITY_SPACE;
2808 #endif
2809 }
2810
2811 /* calculate number of jiffies to transmit a full
2812 * FIFO (32 bytes) at specified data rate
2813 */
2814 bits_per_char = info->params.data_bits +
2815 info->params.stop_bits + 1;
2816
2817 /* if port data rate is set to 460800 or less then
2818 * allow tty settings to override, otherwise keep the
2819 * current data rate.
2820 */
2821 if (info->params.data_rate <= 460800) {
2822 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2823 }
2824
2825 if ( info->params.data_rate ) {
2826 info->timeout = (32*HZ*bits_per_char) /
2827 info->params.data_rate;
2828 }
2829 info->timeout += HZ/50; /* Add .02 seconds of slop */
2830
2831 if (cflag & CRTSCTS)
2832 info->port.flags |= ASYNC_CTS_FLOW;
2833 else
2834 info->port.flags &= ~ASYNC_CTS_FLOW;
2835
2836 if (cflag & CLOCAL)
2837 info->port.flags &= ~ASYNC_CHECK_CD;
2838 else
2839 info->port.flags |= ASYNC_CHECK_CD;
2840
2841 /* process tty input control flags */
2842
2843 info->read_status_mask2 = OVRN;
2844 if (I_INPCK(info->port.tty))
2845 info->read_status_mask2 |= PE | FRME;
2846 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2847 info->read_status_mask1 |= BRKD;
2848 if (I_IGNPAR(info->port.tty))
2849 info->ignore_status_mask2 |= PE | FRME;
2850 if (I_IGNBRK(info->port.tty)) {
2851 info->ignore_status_mask1 |= BRKD;
2852 /* If ignoring parity and break indicators, ignore
2853 * overruns too. (For real raw support).
2854 */
2855 if (I_IGNPAR(info->port.tty))
2856 info->ignore_status_mask2 |= OVRN;
2857 }
2858
2859 program_hw(info);
2860 }
2861
2862 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2863 {
2864 int err;
2865
2866 if (debug_level >= DEBUG_LEVEL_INFO)
2867 printk("%s(%d):%s get_params()\n",
2868 __FILE__,__LINE__, info->device_name);
2869
2870 if (!user_icount) {
2871 memset(&info->icount, 0, sizeof(info->icount));
2872 } else {
2873 mutex_lock(&info->port.mutex);
2874 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2875 mutex_unlock(&info->port.mutex);
2876 if (err)
2877 return -EFAULT;
2878 }
2879
2880 return 0;
2881 }
2882
2883 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2884 {
2885 int err;
2886 if (debug_level >= DEBUG_LEVEL_INFO)
2887 printk("%s(%d):%s get_params()\n",
2888 __FILE__,__LINE__, info->device_name);
2889
2890 mutex_lock(&info->port.mutex);
2891 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2892 mutex_unlock(&info->port.mutex);
2893 if (err) {
2894 if ( debug_level >= DEBUG_LEVEL_INFO )
2895 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2896 __FILE__,__LINE__,info->device_name);
2897 return -EFAULT;
2898 }
2899
2900 return 0;
2901 }
2902
2903 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2904 {
2905 unsigned long flags;
2906 MGSL_PARAMS tmp_params;
2907 int err;
2908
2909 if (debug_level >= DEBUG_LEVEL_INFO)
2910 printk("%s(%d):%s set_params\n",
2911 __FILE__,__LINE__,info->device_name );
2912 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2913 if (err) {
2914 if ( debug_level >= DEBUG_LEVEL_INFO )
2915 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2916 __FILE__,__LINE__,info->device_name);
2917 return -EFAULT;
2918 }
2919
2920 mutex_lock(&info->port.mutex);
2921 spin_lock_irqsave(&info->lock,flags);
2922 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2923 spin_unlock_irqrestore(&info->lock,flags);
2924
2925 change_params(info);
2926 mutex_unlock(&info->port.mutex);
2927
2928 return 0;
2929 }
2930
2931 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2932 {
2933 int err;
2934
2935 if (debug_level >= DEBUG_LEVEL_INFO)
2936 printk("%s(%d):%s get_txidle()=%d\n",
2937 __FILE__,__LINE__, info->device_name, info->idle_mode);
2938
2939 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2940 if (err) {
2941 if ( debug_level >= DEBUG_LEVEL_INFO )
2942 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2943 __FILE__,__LINE__,info->device_name);
2944 return -EFAULT;
2945 }
2946
2947 return 0;
2948 }
2949
2950 static int set_txidle(SLMP_INFO * info, int idle_mode)
2951 {
2952 unsigned long flags;
2953
2954 if (debug_level >= DEBUG_LEVEL_INFO)
2955 printk("%s(%d):%s set_txidle(%d)\n",
2956 __FILE__,__LINE__,info->device_name, idle_mode );
2957
2958 spin_lock_irqsave(&info->lock,flags);
2959 info->idle_mode = idle_mode;
2960 tx_set_idle( info );
2961 spin_unlock_irqrestore(&info->lock,flags);
2962 return 0;
2963 }
2964
2965 static int tx_enable(SLMP_INFO * info, int enable)
2966 {
2967 unsigned long flags;
2968
2969 if (debug_level >= DEBUG_LEVEL_INFO)
2970 printk("%s(%d):%s tx_enable(%d)\n",
2971 __FILE__,__LINE__,info->device_name, enable);
2972
2973 spin_lock_irqsave(&info->lock,flags);
2974 if ( enable ) {
2975 if ( !info->tx_enabled ) {
2976 tx_start(info);
2977 }
2978 } else {
2979 if ( info->tx_enabled )
2980 tx_stop(info);
2981 }
2982 spin_unlock_irqrestore(&info->lock,flags);
2983 return 0;
2984 }
2985
2986 /* abort send HDLC frame
2987 */
2988 static int tx_abort(SLMP_INFO * info)
2989 {
2990 unsigned long flags;
2991
2992 if (debug_level >= DEBUG_LEVEL_INFO)
2993 printk("%s(%d):%s tx_abort()\n",
2994 __FILE__,__LINE__,info->device_name);
2995
2996 spin_lock_irqsave(&info->lock,flags);
2997 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2998 info->ie1_value &= ~UDRN;
2999 info->ie1_value |= IDLE;
3000 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3001 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3002
3003 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3004 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3005
3006 write_reg(info, CMD, TXABORT);
3007 }
3008 spin_unlock_irqrestore(&info->lock,flags);
3009 return 0;
3010 }
3011
3012 static int rx_enable(SLMP_INFO * info, int enable)
3013 {
3014 unsigned long flags;
3015
3016 if (debug_level >= DEBUG_LEVEL_INFO)
3017 printk("%s(%d):%s rx_enable(%d)\n",
3018 __FILE__,__LINE__,info->device_name,enable);
3019
3020 spin_lock_irqsave(&info->lock,flags);
3021 if ( enable ) {
3022 if ( !info->rx_enabled )
3023 rx_start(info);
3024 } else {
3025 if ( info->rx_enabled )
3026 rx_stop(info);
3027 }
3028 spin_unlock_irqrestore(&info->lock,flags);
3029 return 0;
3030 }
3031
3032 /* wait for specified event to occur
3033 */
3034 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3035 {
3036 unsigned long flags;
3037 int s;
3038 int rc=0;
3039 struct mgsl_icount cprev, cnow;
3040 int events;
3041 int mask;
3042 struct _input_signal_events oldsigs, newsigs;
3043 DECLARE_WAITQUEUE(wait, current);
3044
3045 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3046 if (rc) {
3047 return -EFAULT;
3048 }
3049
3050 if (debug_level >= DEBUG_LEVEL_INFO)
3051 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3052 __FILE__,__LINE__,info->device_name,mask);
3053
3054 spin_lock_irqsave(&info->lock,flags);
3055
3056 /* return immediately if state matches requested events */
3057 get_signals(info);
3058 s = info->serial_signals;
3059
3060 events = mask &
3061 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3062 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3063 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3064 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3065 if (events) {
3066 spin_unlock_irqrestore(&info->lock,flags);
3067 goto exit;
3068 }
3069
3070 /* save current irq counts */
3071 cprev = info->icount;
3072 oldsigs = info->input_signal_events;
3073
3074 /* enable hunt and idle irqs if needed */
3075 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3076 unsigned char oldval = info->ie1_value;
3077 unsigned char newval = oldval +
3078 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3079 (mask & MgslEvent_IdleReceived ? IDLD:0);
3080 if ( oldval != newval ) {
3081 info->ie1_value = newval;
3082 write_reg(info, IE1, info->ie1_value);
3083 }
3084 }
3085
3086 set_current_state(TASK_INTERRUPTIBLE);
3087 add_wait_queue(&info->event_wait_q, &wait);
3088
3089 spin_unlock_irqrestore(&info->lock,flags);
3090
3091 for(;;) {
3092 schedule();
3093 if (signal_pending(current)) {
3094 rc = -ERESTARTSYS;
3095 break;
3096 }
3097
3098 /* get current irq counts */
3099 spin_lock_irqsave(&info->lock,flags);
3100 cnow = info->icount;
3101 newsigs = info->input_signal_events;
3102 set_current_state(TASK_INTERRUPTIBLE);
3103 spin_unlock_irqrestore(&info->lock,flags);
3104
3105 /* if no change, wait aborted for some reason */
3106 if (newsigs.dsr_up == oldsigs.dsr_up &&
3107 newsigs.dsr_down == oldsigs.dsr_down &&
3108 newsigs.dcd_up == oldsigs.dcd_up &&
3109 newsigs.dcd_down == oldsigs.dcd_down &&
3110 newsigs.cts_up == oldsigs.cts_up &&
3111 newsigs.cts_down == oldsigs.cts_down &&
3112 newsigs.ri_up == oldsigs.ri_up &&
3113 newsigs.ri_down == oldsigs.ri_down &&
3114 cnow.exithunt == cprev.exithunt &&
3115 cnow.rxidle == cprev.rxidle) {
3116 rc = -EIO;
3117 break;
3118 }
3119
3120 events = mask &
3121 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3122 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3123 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3124 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3125 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3126 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3127 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3128 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3129 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3130 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3131 if (events)
3132 break;
3133
3134 cprev = cnow;
3135 oldsigs = newsigs;
3136 }
3137
3138 remove_wait_queue(&info->event_wait_q, &wait);
3139 set_current_state(TASK_RUNNING);
3140
3141
3142 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3143 spin_lock_irqsave(&info->lock,flags);
3144 if (!waitqueue_active(&info->event_wait_q)) {
3145 /* disable enable exit hunt mode/idle rcvd IRQs */
3146 info->ie1_value &= ~(FLGD|IDLD);
3147 write_reg(info, IE1, info->ie1_value);
3148 }
3149 spin_unlock_irqrestore(&info->lock,flags);
3150 }
3151 exit:
3152 if ( rc == 0 )
3153 PUT_USER(rc, events, mask_ptr);
3154
3155 return rc;
3156 }
3157
3158 static int modem_input_wait(SLMP_INFO *info,int arg)
3159 {
3160 unsigned long flags;
3161 int rc;
3162 struct mgsl_icount cprev, cnow;
3163 DECLARE_WAITQUEUE(wait, current);
3164
3165 /* save current irq counts */
3166 spin_lock_irqsave(&info->lock,flags);
3167 cprev = info->icount;
3168 add_wait_queue(&info->status_event_wait_q, &wait);
3169 set_current_state(TASK_INTERRUPTIBLE);
3170 spin_unlock_irqrestore(&info->lock,flags);
3171
3172 for(;;) {
3173 schedule();
3174 if (signal_pending(current)) {
3175 rc = -ERESTARTSYS;
3176 break;
3177 }
3178
3179 /* get new irq counts */
3180 spin_lock_irqsave(&info->lock,flags);
3181 cnow = info->icount;
3182 set_current_state(TASK_INTERRUPTIBLE);
3183 spin_unlock_irqrestore(&info->lock,flags);
3184
3185 /* if no change, wait aborted for some reason */
3186 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3187 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3188 rc = -EIO;
3189 break;
3190 }
3191
3192 /* check for change in caller specified modem input */
3193 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3194 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3195 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3196 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3197 rc = 0;
3198 break;
3199 }
3200
3201 cprev = cnow;
3202 }
3203 remove_wait_queue(&info->status_event_wait_q, &wait);
3204 set_current_state(TASK_RUNNING);
3205 return rc;
3206 }
3207
3208 /* return the state of the serial control and status signals
3209 */
3210 static int tiocmget(struct tty_struct *tty, struct file *file)
3211 {
3212 SLMP_INFO *info = tty->driver_data;
3213 unsigned int result;
3214 unsigned long flags;
3215
3216 spin_lock_irqsave(&info->lock,flags);
3217 get_signals(info);
3218 spin_unlock_irqrestore(&info->lock,flags);
3219
3220 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3221 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3222 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3223 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3224 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3225 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3226
3227 if (debug_level >= DEBUG_LEVEL_INFO)
3228 printk("%s(%d):%s tiocmget() value=%08X\n",
3229 __FILE__,__LINE__, info->device_name, result );
3230 return result;
3231 }
3232
3233 /* set modem control signals (DTR/RTS)
3234 */
3235 static int tiocmset(struct tty_struct *tty, struct file *file,
3236 unsigned int set, unsigned int clear)
3237 {
3238 SLMP_INFO *info = tty->driver_data;
3239 unsigned long flags;
3240
3241 if (debug_level >= DEBUG_LEVEL_INFO)
3242 printk("%s(%d):%s tiocmset(%x,%x)\n",
3243 __FILE__,__LINE__,info->device_name, set, clear);
3244
3245 if (set & TIOCM_RTS)
3246 info->serial_signals |= SerialSignal_RTS;
3247 if (set & TIOCM_DTR)
3248 info->serial_signals |= SerialSignal_DTR;
3249 if (clear & TIOCM_RTS)
3250 info->serial_signals &= ~SerialSignal_RTS;
3251 if (clear & TIOCM_DTR)
3252 info->serial_signals &= ~SerialSignal_DTR;
3253
3254 spin_lock_irqsave(&info->lock,flags);
3255 set_signals(info);
3256 spin_unlock_irqrestore(&info->lock,flags);
3257
3258 return 0;
3259 }
3260
3261 static int carrier_raised(struct tty_port *port)
3262 {
3263 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3264 unsigned long flags;
3265
3266 spin_lock_irqsave(&info->lock,flags);
3267 get_signals(info);
3268 spin_unlock_irqrestore(&info->lock,flags);
3269
3270 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3271 }
3272
3273 static void dtr_rts(struct tty_port *port, int on)
3274 {
3275 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3276 unsigned long flags;
3277
3278 spin_lock_irqsave(&info->lock,flags);
3279 if (on)
3280 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3281 else
3282 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3283 set_signals(info);
3284 spin_unlock_irqrestore(&info->lock,flags);
3285 }
3286
3287 /* Block the current process until the specified port is ready to open.
3288 */
3289 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3290 SLMP_INFO *info)
3291 {
3292 DECLARE_WAITQUEUE(wait, current);
3293 int retval;
3294 bool do_clocal = false;
3295 bool extra_count = false;
3296 unsigned long flags;
3297 int cd;
3298 struct tty_port *port = &info->port;
3299
3300 if (debug_level >= DEBUG_LEVEL_INFO)
3301 printk("%s(%d):%s block_til_ready()\n",
3302 __FILE__,__LINE__, tty->driver->name );
3303
3304 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3305 /* nonblock mode is set or port is not enabled */
3306 /* just verify that callout device is not active */
3307 port->flags |= ASYNC_NORMAL_ACTIVE;
3308 return 0;
3309 }
3310
3311 if (tty->termios->c_cflag & CLOCAL)
3312 do_clocal = true;
3313
3314 /* Wait for carrier detect and the line to become
3315 * free (i.e., not in use by the callout). While we are in
3316 * this loop, port->count is dropped by one, so that
3317 * close() knows when to free things. We restore it upon
3318 * exit, either normal or abnormal.
3319 */
3320
3321 retval = 0;
3322 add_wait_queue(&port->open_wait, &wait);
3323
3324 if (debug_level >= DEBUG_LEVEL_INFO)
3325 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3326 __FILE__,__LINE__, tty->driver->name, port->count );
3327
3328 spin_lock_irqsave(&info->lock, flags);
3329 if (!tty_hung_up_p(filp)) {
3330 extra_count = true;
3331 port->count--;
3332 }
3333 spin_unlock_irqrestore(&info->lock, flags);
3334 port->blocked_open++;
3335
3336 while (1) {
3337 if (tty->termios->c_cflag & CBAUD)
3338 tty_port_raise_dtr_rts(port);
3339
3340 set_current_state(TASK_INTERRUPTIBLE);
3341
3342 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3343 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3344 -EAGAIN : -ERESTARTSYS;
3345 break;
3346 }
3347
3348 cd = tty_port_carrier_raised(port);
3349
3350 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3351 break;
3352
3353 if (signal_pending(current)) {
3354 retval = -ERESTARTSYS;
3355 break;
3356 }
3357
3358 if (debug_level >= DEBUG_LEVEL_INFO)
3359 printk("%s(%d):%s block_til_ready() count=%d\n",
3360 __FILE__,__LINE__, tty->driver->name, port->count );
3361
3362 tty_unlock();
3363 schedule();
3364 tty_lock();
3365 }
3366
3367 set_current_state(TASK_RUNNING);
3368 remove_wait_queue(&port->open_wait, &wait);
3369
3370 if (extra_count)
3371 port->count++;
3372 port->blocked_open--;
3373
3374 if (debug_level >= DEBUG_LEVEL_INFO)
3375 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3376 __FILE__,__LINE__, tty->driver->name, port->count );
3377
3378 if (!retval)
3379 port->flags |= ASYNC_NORMAL_ACTIVE;
3380
3381 return retval;
3382 }
3383
3384 static int alloc_dma_bufs(SLMP_INFO *info)
3385 {
3386 unsigned short BuffersPerFrame;
3387 unsigned short BufferCount;
3388
3389 // Force allocation to start at 64K boundary for each port.
3390 // This is necessary because *all* buffer descriptors for a port
3391 // *must* be in the same 64K block. All descriptors on a port
3392 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3393 // into the CBP register.
3394 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3395
3396 /* Calculate the number of DMA buffers necessary to hold the */
3397 /* largest allowable frame size. Note: If the max frame size is */
3398 /* not an even multiple of the DMA buffer size then we need to */
3399 /* round the buffer count per frame up one. */
3400
3401 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3402 if ( info->max_frame_size % SCABUFSIZE )
3403 BuffersPerFrame++;
3404
3405 /* calculate total number of data buffers (SCABUFSIZE) possible
3406 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3407 * for the descriptor list (BUFFERLISTSIZE).
3408 */
3409 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3410
3411 /* limit number of buffers to maximum amount of descriptors */
3412 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3413 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3414
3415 /* use enough buffers to transmit one max size frame */
3416 info->tx_buf_count = BuffersPerFrame + 1;
3417
3418 /* never use more than half the available buffers for transmit */
3419 if (info->tx_buf_count > (BufferCount/2))
3420 info->tx_buf_count = BufferCount/2;
3421
3422 if (info->tx_buf_count > SCAMAXDESC)
3423 info->tx_buf_count = SCAMAXDESC;
3424
3425 /* use remaining buffers for receive */
3426 info->rx_buf_count = BufferCount - info->tx_buf_count;
3427
3428 if (info->rx_buf_count > SCAMAXDESC)
3429 info->rx_buf_count = SCAMAXDESC;
3430
3431 if ( debug_level >= DEBUG_LEVEL_INFO )
3432 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3433 __FILE__,__LINE__, info->device_name,
3434 info->tx_buf_count,info->rx_buf_count);
3435
3436 if ( alloc_buf_list( info ) < 0 ||
3437 alloc_frame_bufs(info,
3438 info->rx_buf_list,
3439 info->rx_buf_list_ex,
3440 info->rx_buf_count) < 0 ||
3441 alloc_frame_bufs(info,
3442 info->tx_buf_list,
3443 info->tx_buf_list_ex,
3444 info->tx_buf_count) < 0 ||
3445 alloc_tmp_rx_buf(info) < 0 ) {
3446 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3447 __FILE__,__LINE__, info->device_name);
3448 return -ENOMEM;
3449 }
3450
3451 rx_reset_buffers( info );
3452
3453 return 0;
3454 }
3455
3456 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3457 */
3458 static int alloc_buf_list(SLMP_INFO *info)
3459 {
3460 unsigned int i;
3461
3462 /* build list in adapter shared memory */
3463 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3464 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3465 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3466
3467 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3468
3469 /* Save virtual address pointers to the receive and */
3470 /* transmit buffer lists. (Receive 1st). These pointers will */
3471 /* be used by the processor to access the lists. */
3472 info->rx_buf_list = (SCADESC *)info->buffer_list;
3473
3474 info->tx_buf_list = (SCADESC *)info->buffer_list;
3475 info->tx_buf_list += info->rx_buf_count;
3476
3477 /* Build links for circular buffer entry lists (tx and rx)
3478 *
3479 * Note: links are physical addresses read by the SCA device
3480 * to determine the next buffer entry to use.
3481 */
3482
3483 for ( i = 0; i < info->rx_buf_count; i++ ) {
3484 /* calculate and store physical address of this buffer entry */
3485 info->rx_buf_list_ex[i].phys_entry =
3486 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3487
3488 /* calculate and store physical address of */
3489 /* next entry in cirular list of entries */
3490 info->rx_buf_list[i].next = info->buffer_list_phys;
3491 if ( i < info->rx_buf_count - 1 )
3492 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3493
3494 info->rx_buf_list[i].length = SCABUFSIZE;
3495 }
3496
3497 for ( i = 0; i < info->tx_buf_count; i++ ) {
3498 /* calculate and store physical address of this buffer entry */
3499 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3500 ((info->rx_buf_count + i) * sizeof(SCADESC));
3501
3502 /* calculate and store physical address of */
3503 /* next entry in cirular list of entries */
3504
3505 info->tx_buf_list[i].next = info->buffer_list_phys +
3506 info->rx_buf_count * sizeof(SCADESC);
3507
3508 if ( i < info->tx_buf_count - 1 )
3509 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3510 }
3511
3512 return 0;
3513 }
3514
3515 /* Allocate the frame DMA buffers used by the specified buffer list.
3516 */
3517 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3518 {
3519 int i;
3520 unsigned long phys_addr;
3521
3522 for ( i = 0; i < count; i++ ) {
3523 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3524 phys_addr = info->port_array[0]->last_mem_alloc;
3525 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3526
3527 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3528 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3529 }
3530
3531 return 0;
3532 }
3533
3534 static void free_dma_bufs(SLMP_INFO *info)
3535 {
3536 info->buffer_list = NULL;
3537 info->rx_buf_list = NULL;
3538 info->tx_buf_list = NULL;
3539 }
3540
3541 /* allocate buffer large enough to hold max_frame_size.
3542 * This buffer is used to pass an assembled frame to the line discipline.
3543 */
3544 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3545 {
3546 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3547 if (info->tmp_rx_buf == NULL)
3548 return -ENOMEM;
3549 return 0;
3550 }
3551
3552 static void free_tmp_rx_buf(SLMP_INFO *info)
3553 {
3554 kfree(info->tmp_rx_buf);
3555 info->tmp_rx_buf = NULL;
3556 }
3557
3558 static int claim_resources(SLMP_INFO *info)
3559 {
3560 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3561 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3562 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3563 info->init_error = DiagStatus_AddressConflict;
3564 goto errout;
3565 }
3566 else
3567 info->shared_mem_requested = true;
3568
3569 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3570 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3571 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3572 info->init_error = DiagStatus_AddressConflict;
3573 goto errout;
3574 }
3575 else
3576 info->lcr_mem_requested = true;
3577
3578 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3579 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3580 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3581 info->init_error = DiagStatus_AddressConflict;
3582 goto errout;
3583 }
3584 else
3585 info->sca_base_requested = true;
3586
3587 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3588 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3589 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3590 info->init_error = DiagStatus_AddressConflict;
3591 goto errout;
3592 }
3593 else
3594 info->sca_statctrl_requested = true;
3595
3596 info->memory_base = ioremap_nocache(info->phys_memory_base,
3597 SCA_MEM_SIZE);
3598 if (!info->memory_base) {
3599 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3600 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3601 info->init_error = DiagStatus_CantAssignPciResources;
3602 goto errout;
3603 }
3604
3605 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3606 if (!info->lcr_base) {
3607 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3608 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3609 info->init_error = DiagStatus_CantAssignPciResources;
3610 goto errout;
3611 }
3612 info->lcr_base += info->lcr_offset;
3613
3614 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3615 if (!info->sca_base) {
3616 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3617 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3618 info->init_error = DiagStatus_CantAssignPciResources;
3619 goto errout;
3620 }
3621 info->sca_base += info->sca_offset;
3622
3623 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3624 PAGE_SIZE);
3625 if (!info->statctrl_base) {
3626 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3627 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3628 info->init_error = DiagStatus_CantAssignPciResources;
3629 goto errout;
3630 }
3631 info->statctrl_base += info->statctrl_offset;
3632
3633 if ( !memory_test(info) ) {
3634 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3635 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3636 info->init_error = DiagStatus_MemoryError;
3637 goto errout;
3638 }
3639
3640 return 0;
3641
3642 errout:
3643 release_resources( info );
3644 return -ENODEV;
3645 }
3646
3647 static void release_resources(SLMP_INFO *info)
3648 {
3649 if ( debug_level >= DEBUG_LEVEL_INFO )
3650 printk( "%s(%d):%s release_resources() entry\n",
3651 __FILE__,__LINE__,info->device_name );
3652
3653 if ( info->irq_requested ) {
3654 free_irq(info->irq_level, info);
3655 info->irq_requested = false;
3656 }
3657
3658 if ( info->shared_mem_requested ) {
3659 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3660 info->shared_mem_requested = false;
3661 }
3662 if ( info->lcr_mem_requested ) {
3663 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3664 info->lcr_mem_requested = false;
3665 }
3666 if ( info->sca_base_requested ) {
3667 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3668 info->sca_base_requested = false;
3669 }
3670 if ( info->sca_statctrl_requested ) {
3671 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3672 info->sca_statctrl_requested = false;
3673 }
3674
3675 if (info->memory_base){
3676 iounmap(info->memory_base);
3677 info->memory_base = NULL;
3678 }
3679
3680 if (info->sca_base) {
3681 iounmap(info->sca_base - info->sca_offset);
3682 info->sca_base=NULL;
3683 }
3684
3685 if (info->statctrl_base) {
3686 iounmap(info->statctrl_base - info->statctrl_offset);
3687 info->statctrl_base=NULL;
3688 }
3689
3690 if (info->lcr_base){
3691 iounmap(info->lcr_base - info->lcr_offset);
3692 info->lcr_base = NULL;
3693 }
3694
3695 if ( debug_level >= DEBUG_LEVEL_INFO )
3696 printk( "%s(%d):%s release_resources() exit\n",
3697 __FILE__,__LINE__,info->device_name );
3698 }
3699
3700 /* Add the specified device instance data structure to the
3701 * global linked list of devices and increment the device count.
3702 */
3703 static void add_device(SLMP_INFO *info)
3704 {
3705 info->next_device = NULL;
3706 info->line = synclinkmp_device_count;
3707 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3708
3709 if (info->line < MAX_DEVICES) {
3710 if (maxframe[info->line])
3711 info->max_frame_size = maxframe[info->line];
3712 }
3713
3714 synclinkmp_device_count++;
3715
3716 if ( !synclinkmp_device_list )
3717 synclinkmp_device_list = info;
3718 else {
3719 SLMP_INFO *current_dev = synclinkmp_device_list;
3720 while( current_dev->next_device )
3721 current_dev = current_dev->next_device;
3722 current_dev->next_device = info;
3723 }
3724
3725 if ( info->max_frame_size < 4096 )
3726 info->max_frame_size = 4096;
3727 else if ( info->max_frame_size > 65535 )
3728 info->max_frame_size = 65535;
3729
3730 printk( "SyncLink MultiPort %s: "
3731 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3732 info->device_name,
3733 info->phys_sca_base,
3734 info->phys_memory_base,
3735 info->phys_statctrl_base,
3736 info->phys_lcr_base,
3737 info->irq_level,
3738 info->max_frame_size );
3739
3740 #if SYNCLINK_GENERIC_HDLC
3741 hdlcdev_init(info);
3742 #endif
3743 }
3744
3745 static const struct tty_port_operations port_ops = {
3746 .carrier_raised = carrier_raised,
3747 .dtr_rts = dtr_rts,
3748 };
3749
3750 /* Allocate and initialize a device instance structure
3751 *
3752 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3753 */
3754 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3755 {
3756 SLMP_INFO *info;
3757
3758 info = kzalloc(sizeof(SLMP_INFO),
3759 GFP_KERNEL);
3760
3761 if (!info) {
3762 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3763 __FILE__,__LINE__, adapter_num, port_num);
3764 } else {
3765 tty_port_init(&info->port);
3766 info->port.ops = &port_ops;
3767 info->magic = MGSL_MAGIC;
3768 INIT_WORK(&info->task, bh_handler);
3769 info->max_frame_size = 4096;
3770 info->port.close_delay = 5*HZ/10;
3771 info->port.closing_wait = 30*HZ;
3772 init_waitqueue_head(&info->status_event_wait_q);
3773 init_waitqueue_head(&info->event_wait_q);
3774 spin_lock_init(&info->netlock);
3775 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3776 info->idle_mode = HDLC_TXIDLE_FLAGS;
3777 info->adapter_num = adapter_num;
3778 info->port_num = port_num;
3779
3780 /* Copy configuration info to device instance data */
3781 info->irq_level = pdev->irq;
3782 info->phys_lcr_base = pci_resource_start(pdev,0);
3783 info->phys_sca_base = pci_resource_start(pdev,2);
3784 info->phys_memory_base = pci_resource_start(pdev,3);
3785 info->phys_statctrl_base = pci_resource_start(pdev,4);
3786
3787 /* Because veremap only works on page boundaries we must map
3788 * a larger area than is actually implemented for the LCR
3789 * memory range. We map a full page starting at the page boundary.
3790 */
3791 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3792 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3793
3794 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3795 info->phys_sca_base &= ~(PAGE_SIZE-1);
3796
3797 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3798 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3799
3800 info->bus_type = MGSL_BUS_TYPE_PCI;
3801 info->irq_flags = IRQF_SHARED;
3802
3803 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3804 setup_timer(&info->status_timer, status_timeout,
3805 (unsigned long)info);
3806
3807 /* Store the PCI9050 misc control register value because a flaw
3808 * in the PCI9050 prevents LCR registers from being read if
3809 * BIOS assigns an LCR base address with bit 7 set.
3810 *
3811 * Only the misc control register is accessed for which only
3812 * write access is needed, so set an initial value and change
3813 * bits to the device instance data as we write the value
3814 * to the actual misc control register.
3815 */
3816 info->misc_ctrl_value = 0x087e4546;
3817
3818 /* initial port state is unknown - if startup errors
3819 * occur, init_error will be set to indicate the
3820 * problem. Once the port is fully initialized,
3821 * this value will be set to 0 to indicate the
3822 * port is available.
3823 */
3824 info->init_error = -1;
3825 }
3826
3827 return info;
3828 }
3829
3830 static void device_init(int adapter_num, struct pci_dev *pdev)
3831 {
3832 SLMP_INFO *port_array[SCA_MAX_PORTS];
3833 int port;
3834
3835 /* allocate device instances for up to SCA_MAX_PORTS devices */
3836 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3837 port_array[port] = alloc_dev(adapter_num,port,pdev);
3838 if( port_array[port] == NULL ) {
3839 for ( --port; port >= 0; --port )
3840 kfree(port_array[port]);
3841 return;
3842 }
3843 }
3844
3845 /* give copy of port_array to all ports and add to device list */
3846 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3847 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3848 add_device( port_array[port] );
3849 spin_lock_init(&port_array[port]->lock);
3850 }
3851
3852 /* Allocate and claim adapter resources */
3853 if ( !claim_resources(port_array[0]) ) {
3854
3855 alloc_dma_bufs(port_array[0]);
3856
3857 /* copy resource information from first port to others */
3858 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3859 port_array[port]->lock = port_array[0]->lock;
3860 port_array[port]->irq_level = port_array[0]->irq_level;
3861 port_array[port]->memory_base = port_array[0]->memory_base;
3862 port_array[port]->sca_base = port_array[0]->sca_base;
3863 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3864 port_array[port]->lcr_base = port_array[0]->lcr_base;
3865 alloc_dma_bufs(port_array[port]);
3866 }
3867
3868 if ( request_irq(port_array[0]->irq_level,
3869 synclinkmp_interrupt,
3870 port_array[0]->irq_flags,
3871 port_array[0]->device_name,
3872 port_array[0]) < 0 ) {
3873 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3874 __FILE__,__LINE__,
3875 port_array[0]->device_name,
3876 port_array[0]->irq_level );
3877 }
3878 else {
3879 port_array[0]->irq_requested = true;
3880 adapter_test(port_array[0]);
3881 }
3882 }
3883 }
3884
3885 static const struct tty_operations ops = {
3886 .open = open,
3887 .close = close,
3888 .write = write,
3889 .put_char = put_char,
3890 .flush_chars = flush_chars,
3891 .write_room = write_room,
3892 .chars_in_buffer = chars_in_buffer,
3893 .flush_buffer = flush_buffer,
3894 .ioctl = ioctl,
3895 .throttle = throttle,
3896 .unthrottle = unthrottle,
3897 .send_xchar = send_xchar,
3898 .break_ctl = set_break,
3899 .wait_until_sent = wait_until_sent,
3900 .set_termios = set_termios,
3901 .stop = tx_hold,
3902 .start = tx_release,
3903 .hangup = hangup,
3904 .tiocmget = tiocmget,
3905 .tiocmset = tiocmset,
3906 .get_icount = get_icount,
3907 .proc_fops = &synclinkmp_proc_fops,
3908 };
3909
3910
3911 static void synclinkmp_cleanup(void)
3912 {
3913 int rc;
3914 SLMP_INFO *info;
3915 SLMP_INFO *tmp;
3916
3917 printk("Unloading %s %s\n", driver_name, driver_version);
3918
3919 if (serial_driver) {
3920 if ((rc = tty_unregister_driver(serial_driver)))
3921 printk("%s(%d) failed to unregister tty driver err=%d\n",
3922 __FILE__,__LINE__,rc);
3923 put_tty_driver(serial_driver);
3924 }
3925
3926 /* reset devices */
3927 info = synclinkmp_device_list;
3928 while(info) {
3929 reset_port(info);
3930 info = info->next_device;
3931 }
3932
3933 /* release devices */
3934 info = synclinkmp_device_list;
3935 while(info) {
3936 #if SYNCLINK_GENERIC_HDLC
3937 hdlcdev_exit(info);
3938 #endif
3939 free_dma_bufs(info);
3940 free_tmp_rx_buf(info);
3941 if ( info->port_num == 0 ) {
3942 if (info->sca_base)
3943 write_reg(info, LPR, 1); /* set low power mode */
3944 release_resources(info);
3945 }
3946 tmp = info;
3947 info = info->next_device;
3948 kfree(tmp);
3949 }
3950
3951 pci_unregister_driver(&synclinkmp_pci_driver);
3952 }
3953
3954 /* Driver initialization entry point.
3955 */
3956
3957 static int __init synclinkmp_init(void)
3958 {
3959 int rc;
3960
3961 if (break_on_load) {
3962 synclinkmp_get_text_ptr();
3963 BREAKPOINT();
3964 }
3965
3966 printk("%s %s\n", driver_name, driver_version);
3967
3968 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3969 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3970 return rc;
3971 }
3972
3973 serial_driver = alloc_tty_driver(128);
3974 if (!serial_driver) {
3975 rc = -ENOMEM;
3976 goto error;
3977 }
3978
3979 /* Initialize the tty_driver structure */
3980
3981 serial_driver->owner = THIS_MODULE;
3982 serial_driver->driver_name = "synclinkmp";
3983 serial_driver->name = "ttySLM";
3984 serial_driver->major = ttymajor;
3985 serial_driver->minor_start = 64;
3986 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3987 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3988 serial_driver->init_termios = tty_std_termios;
3989 serial_driver->init_termios.c_cflag =
3990 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3991 serial_driver->init_termios.c_ispeed = 9600;
3992 serial_driver->init_termios.c_ospeed = 9600;
3993 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3994 tty_set_operations(serial_driver, &ops);
3995 if ((rc = tty_register_driver(serial_driver)) < 0) {
3996 printk("%s(%d):Couldn't register serial driver\n",
3997 __FILE__,__LINE__);
3998 put_tty_driver(serial_driver);
3999 serial_driver = NULL;
4000 goto error;
4001 }
4002
4003 printk("%s %s, tty major#%d\n",
4004 driver_name, driver_version,
4005 serial_driver->major);
4006
4007 return 0;
4008
4009 error:
4010 synclinkmp_cleanup();
4011 return rc;
4012 }
4013
4014 static void __exit synclinkmp_exit(void)
4015 {
4016 synclinkmp_cleanup();
4017 }
4018
4019 module_init(synclinkmp_init);
4020 module_exit(synclinkmp_exit);
4021
4022 /* Set the port for internal loopback mode.
4023 * The TxCLK and RxCLK signals are generated from the BRG and
4024 * the TxD is looped back to the RxD internally.
4025 */
4026 static void enable_loopback(SLMP_INFO *info, int enable)
4027 {
4028 if (enable) {
4029 /* MD2 (Mode Register 2)
4030 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4031 */
4032 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4033
4034 /* degate external TxC clock source */
4035 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4036 write_control_reg(info);
4037
4038 /* RXS/TXS (Rx/Tx clock source)
4039 * 07 Reserved, must be 0
4040 * 06..04 Clock Source, 100=BRG
4041 * 03..00 Clock Divisor, 0000=1
4042 */
4043 write_reg(info, RXS, 0x40);
4044 write_reg(info, TXS, 0x40);
4045
4046 } else {
4047 /* MD2 (Mode Register 2)
4048 * 01..00 CNCT<1..0> Channel connection, 0=normal
4049 */
4050 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4051
4052 /* RXS/TXS (Rx/Tx clock source)
4053 * 07 Reserved, must be 0
4054 * 06..04 Clock Source, 000=RxC/TxC Pin
4055 * 03..00 Clock Divisor, 0000=1
4056 */
4057 write_reg(info, RXS, 0x00);
4058 write_reg(info, TXS, 0x00);
4059 }
4060
4061 /* set LinkSpeed if available, otherwise default to 2Mbps */
4062 if (info->params.clock_speed)
4063 set_rate(info, info->params.clock_speed);
4064 else
4065 set_rate(info, 3686400);
4066 }
4067
4068 /* Set the baud rate register to the desired speed
4069 *
4070 * data_rate data rate of clock in bits per second
4071 * A data rate of 0 disables the AUX clock.
4072 */
4073 static void set_rate( SLMP_INFO *info, u32 data_rate )
4074 {
4075 u32 TMCValue;
4076 unsigned char BRValue;
4077 u32 Divisor=0;
4078
4079 /* fBRG = fCLK/(TMC * 2^BR)
4080 */
4081 if (data_rate != 0) {
4082 Divisor = 14745600/data_rate;
4083 if (!Divisor)
4084 Divisor = 1;
4085
4086 TMCValue = Divisor;
4087
4088 BRValue = 0;
4089 if (TMCValue != 1 && TMCValue != 2) {
4090 /* BRValue of 0 provides 50/50 duty cycle *only* when
4091 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4092 * 50/50 duty cycle.
4093 */
4094 BRValue = 1;
4095 TMCValue >>= 1;
4096 }
4097
4098 /* while TMCValue is too big for TMC register, divide
4099 * by 2 and increment BR exponent.
4100 */
4101 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4102 TMCValue >>= 1;
4103
4104 write_reg(info, TXS,
4105 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4106 write_reg(info, RXS,
4107 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4108 write_reg(info, TMC, (unsigned char)TMCValue);
4109 }
4110 else {
4111 write_reg(info, TXS,0);
4112 write_reg(info, RXS,0);
4113 write_reg(info, TMC, 0);
4114 }
4115 }
4116
4117 /* Disable receiver
4118 */
4119 static void rx_stop(SLMP_INFO *info)
4120 {
4121 if (debug_level >= DEBUG_LEVEL_ISR)
4122 printk("%s(%d):%s rx_stop()\n",
4123 __FILE__,__LINE__, info->device_name );
4124
4125 write_reg(info, CMD, RXRESET);
4126
4127 info->ie0_value &= ~RXRDYE;
4128 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4129
4130 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4131 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4132 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4133
4134 info->rx_enabled = false;
4135 info->rx_overflow = false;
4136 }
4137
4138 /* enable the receiver
4139 */
4140 static void rx_start(SLMP_INFO *info)
4141 {
4142 int i;
4143
4144 if (debug_level >= DEBUG_LEVEL_ISR)
4145 printk("%s(%d):%s rx_start()\n",
4146 __FILE__,__LINE__, info->device_name );
4147
4148 write_reg(info, CMD, RXRESET);
4149
4150 if ( info->params.mode == MGSL_MODE_HDLC ) {
4151 /* HDLC, disabe IRQ on rxdata */
4152 info->ie0_value &= ~RXRDYE;
4153 write_reg(info, IE0, info->ie0_value);
4154
4155 /* Reset all Rx DMA buffers and program rx dma */
4156 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4157 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4158
4159 for (i = 0; i < info->rx_buf_count; i++) {
4160 info->rx_buf_list[i].status = 0xff;
4161
4162 // throttle to 4 shared memory writes at a time to prevent
4163 // hogging local bus (keep latency time for DMA requests low).
4164 if (!(i % 4))
4165 read_status_reg(info);
4166 }
4167 info->current_rx_buf = 0;
4168
4169 /* set current/1st descriptor address */
4170 write_reg16(info, RXDMA + CDA,
4171 info->rx_buf_list_ex[0].phys_entry);
4172
4173 /* set new last rx descriptor address */
4174 write_reg16(info, RXDMA + EDA,
4175 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4176
4177 /* set buffer length (shared by all rx dma data buffers) */
4178 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4179
4180 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4181 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4182 } else {
4183 /* async, enable IRQ on rxdata */
4184 info->ie0_value |= RXRDYE;
4185 write_reg(info, IE0, info->ie0_value);
4186 }
4187
4188 write_reg(info, CMD, RXENABLE);
4189
4190 info->rx_overflow = false;
4191 info->rx_enabled = true;
4192 }
4193
4194 /* Enable the transmitter and send a transmit frame if
4195 * one is loaded in the DMA buffers.
4196 */
4197 static void tx_start(SLMP_INFO *info)
4198 {
4199 if (debug_level >= DEBUG_LEVEL_ISR)
4200 printk("%s(%d):%s tx_start() tx_count=%d\n",
4201 __FILE__,__LINE__, info->device_name,info->tx_count );
4202
4203 if (!info->tx_enabled ) {
4204 write_reg(info, CMD, TXRESET);
4205 write_reg(info, CMD, TXENABLE);
4206 info->tx_enabled = true;
4207 }
4208
4209 if ( info->tx_count ) {
4210
4211 /* If auto RTS enabled and RTS is inactive, then assert */
4212 /* RTS and set a flag indicating that the driver should */
4213 /* negate RTS when the transmission completes. */
4214
4215 info->drop_rts_on_tx_done = false;
4216
4217 if (info->params.mode != MGSL_MODE_ASYNC) {
4218
4219 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4220 get_signals( info );
4221 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4222 info->serial_signals |= SerialSignal_RTS;
4223 set_signals( info );
4224 info->drop_rts_on_tx_done = true;
4225 }
4226 }
4227
4228 write_reg16(info, TRC0,
4229 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4230
4231 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4232 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4233
4234 /* set TX CDA (current descriptor address) */
4235 write_reg16(info, TXDMA + CDA,
4236 info->tx_buf_list_ex[0].phys_entry);
4237
4238 /* set TX EDA (last descriptor address) */
4239 write_reg16(info, TXDMA + EDA,
4240 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4241
4242 /* enable underrun IRQ */
4243 info->ie1_value &= ~IDLE;
4244 info->ie1_value |= UDRN;
4245 write_reg(info, IE1, info->ie1_value);
4246 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4247
4248 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4249 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4250
4251 mod_timer(&info->tx_timer, jiffies +
4252 msecs_to_jiffies(5000));
4253 }
4254 else {
4255 tx_load_fifo(info);
4256 /* async, enable IRQ on txdata */
4257 info->ie0_value |= TXRDYE;
4258 write_reg(info, IE0, info->ie0_value);
4259 }
4260
4261 info->tx_active = true;
4262 }
4263 }
4264
4265 /* stop the transmitter and DMA
4266 */
4267 static void tx_stop( SLMP_INFO *info )
4268 {
4269 if (debug_level >= DEBUG_LEVEL_ISR)
4270 printk("%s(%d):%s tx_stop()\n",
4271 __FILE__,__LINE__, info->device_name );
4272
4273 del_timer(&info->tx_timer);
4274
4275 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4276 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4277
4278 write_reg(info, CMD, TXRESET);
4279
4280 info->ie1_value &= ~(UDRN + IDLE);
4281 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4282 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4283
4284 info->ie0_value &= ~TXRDYE;
4285 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4286
4287 info->tx_enabled = false;
4288 info->tx_active = false;
4289 }
4290
4291 /* Fill the transmit FIFO until the FIFO is full or
4292 * there is no more data to load.
4293 */
4294 static void tx_load_fifo(SLMP_INFO *info)
4295 {
4296 u8 TwoBytes[2];
4297
4298 /* do nothing is now tx data available and no XON/XOFF pending */
4299
4300 if ( !info->tx_count && !info->x_char )
4301 return;
4302
4303 /* load the Transmit FIFO until FIFOs full or all data sent */
4304
4305 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4306
4307 /* there is more space in the transmit FIFO and */
4308 /* there is more data in transmit buffer */
4309
4310 if ( (info->tx_count > 1) && !info->x_char ) {
4311 /* write 16-bits */
4312 TwoBytes[0] = info->tx_buf[info->tx_get++];
4313 if (info->tx_get >= info->max_frame_size)
4314 info->tx_get -= info->max_frame_size;
4315 TwoBytes[1] = info->tx_buf[info->tx_get++];
4316 if (info->tx_get >= info->max_frame_size)
4317 info->tx_get -= info->max_frame_size;
4318
4319 write_reg16(info, TRB, *((u16 *)TwoBytes));
4320
4321 info->tx_count -= 2;
4322 info->icount.tx += 2;
4323 } else {
4324 /* only 1 byte left to transmit or 1 FIFO slot left */
4325
4326 if (info->x_char) {
4327 /* transmit pending high priority char */
4328 write_reg(info, TRB, info->x_char);
4329 info->x_char = 0;
4330 } else {
4331 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4332 if (info->tx_get >= info->max_frame_size)
4333 info->tx_get -= info->max_frame_size;
4334 info->tx_count--;
4335 }
4336 info->icount.tx++;
4337 }
4338 }
4339 }
4340
4341 /* Reset a port to a known state
4342 */
4343 static void reset_port(SLMP_INFO *info)
4344 {
4345 if (info->sca_base) {
4346
4347 tx_stop(info);
4348 rx_stop(info);
4349
4350 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4351 set_signals(info);
4352
4353 /* disable all port interrupts */
4354 info->ie0_value = 0;
4355 info->ie1_value = 0;
4356 info->ie2_value = 0;
4357 write_reg(info, IE0, info->ie0_value);
4358 write_reg(info, IE1, info->ie1_value);
4359 write_reg(info, IE2, info->ie2_value);
4360
4361 write_reg(info, CMD, CHRESET);
4362 }
4363 }
4364
4365 /* Reset all the ports to a known state.
4366 */
4367 static void reset_adapter(SLMP_INFO *info)
4368 {
4369 int i;
4370
4371 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4372 if (info->port_array[i])
4373 reset_port(info->port_array[i]);
4374 }
4375 }
4376
4377 /* Program port for asynchronous communications.
4378 */
4379 static void async_mode(SLMP_INFO *info)
4380 {
4381
4382 unsigned char RegValue;
4383
4384 tx_stop(info);
4385 rx_stop(info);
4386
4387 /* MD0, Mode Register 0
4388 *
4389 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4390 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4391 * 03 Reserved, must be 0
4392 * 02 CRCCC, CRC Calculation, 0=disabled
4393 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4394 *
4395 * 0000 0000
4396 */
4397 RegValue = 0x00;
4398 if (info->params.stop_bits != 1)
4399 RegValue |= BIT1;
4400 write_reg(info, MD0, RegValue);
4401
4402 /* MD1, Mode Register 1
4403 *
4404 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4405 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4406 * 03..02 RXCHR<1..0>, rx char size
4407 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4408 *
4409 * 0100 0000
4410 */
4411 RegValue = 0x40;
4412 switch (info->params.data_bits) {
4413 case 7: RegValue |= BIT4 + BIT2; break;
4414 case 6: RegValue |= BIT5 + BIT3; break;
4415 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4416 }
4417 if (info->params.parity != ASYNC_PARITY_NONE) {
4418 RegValue |= BIT1;
4419 if (info->params.parity == ASYNC_PARITY_ODD)
4420 RegValue |= BIT0;
4421 }
4422 write_reg(info, MD1, RegValue);
4423
4424 /* MD2, Mode Register 2
4425 *
4426 * 07..02 Reserved, must be 0
4427 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4428 *
4429 * 0000 0000
4430 */
4431 RegValue = 0x00;
4432 if (info->params.loopback)
4433 RegValue |= (BIT1 + BIT0);
4434 write_reg(info, MD2, RegValue);
4435
4436 /* RXS, Receive clock source
4437 *
4438 * 07 Reserved, must be 0
4439 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4440 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4441 */
4442 RegValue=BIT6;
4443 write_reg(info, RXS, RegValue);
4444
4445 /* TXS, Transmit clock source
4446 *
4447 * 07 Reserved, must be 0
4448 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4449 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4450 */
4451 RegValue=BIT6;
4452 write_reg(info, TXS, RegValue);
4453
4454 /* Control Register
4455 *
4456 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4457 */
4458 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4459 write_control_reg(info);
4460
4461 tx_set_idle(info);
4462
4463 /* RRC Receive Ready Control 0
4464 *
4465 * 07..05 Reserved, must be 0
4466 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4467 */
4468 write_reg(info, RRC, 0x00);
4469
4470 /* TRC0 Transmit Ready Control 0
4471 *
4472 * 07..05 Reserved, must be 0
4473 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4474 */
4475 write_reg(info, TRC0, 0x10);
4476
4477 /* TRC1 Transmit Ready Control 1
4478 *
4479 * 07..05 Reserved, must be 0
4480 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4481 */
4482 write_reg(info, TRC1, 0x1e);
4483
4484 /* CTL, MSCI control register
4485 *
4486 * 07..06 Reserved, set to 0
4487 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4488 * 04 IDLC, idle control, 0=mark 1=idle register
4489 * 03 BRK, break, 0=off 1 =on (async)
4490 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4491 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4492 * 00 RTS, RTS output control, 0=active 1=inactive
4493 *
4494 * 0001 0001
4495 */
4496 RegValue = 0x10;
4497 if (!(info->serial_signals & SerialSignal_RTS))
4498 RegValue |= 0x01;
4499 write_reg(info, CTL, RegValue);
4500
4501 /* enable status interrupts */
4502 info->ie0_value |= TXINTE + RXINTE;
4503 write_reg(info, IE0, info->ie0_value);
4504
4505 /* enable break detect interrupt */
4506 info->ie1_value = BRKD;
4507 write_reg(info, IE1, info->ie1_value);
4508
4509 /* enable rx overrun interrupt */
4510 info->ie2_value = OVRN;
4511 write_reg(info, IE2, info->ie2_value);
4512
4513 set_rate( info, info->params.data_rate * 16 );
4514 }
4515
4516 /* Program the SCA for HDLC communications.
4517 */
4518 static void hdlc_mode(SLMP_INFO *info)
4519 {
4520 unsigned char RegValue;
4521 u32 DpllDivisor;
4522
4523 // Can't use DPLL because SCA outputs recovered clock on RxC when
4524 // DPLL mode selected. This causes output contention with RxC receiver.
4525 // Use of DPLL would require external hardware to disable RxC receiver
4526 // when DPLL mode selected.
4527 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4528
4529 /* disable DMA interrupts */
4530 write_reg(info, TXDMA + DIR, 0);
4531 write_reg(info, RXDMA + DIR, 0);
4532
4533 /* MD0, Mode Register 0
4534 *
4535 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4536 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4537 * 03 Reserved, must be 0
4538 * 02 CRCCC, CRC Calculation, 1=enabled
4539 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4540 * 00 CRC0, CRC initial value, 1 = all 1s
4541 *
4542 * 1000 0001
4543 */
4544 RegValue = 0x81;
4545 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4546 RegValue |= BIT4;
4547 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4548 RegValue |= BIT4;
4549 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4550 RegValue |= BIT2 + BIT1;
4551 write_reg(info, MD0, RegValue);
4552
4553 /* MD1, Mode Register 1
4554 *
4555 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4556 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4557 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4558 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4559 *
4560 * 0000 0000
4561 */
4562 RegValue = 0x00;
4563 write_reg(info, MD1, RegValue);
4564
4565 /* MD2, Mode Register 2
4566 *
4567 * 07 NRZFM, 0=NRZ, 1=FM
4568 * 06..05 CODE<1..0> Encoding, 00=NRZ
4569 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4570 * 02 Reserved, must be 0
4571 * 01..00 CNCT<1..0> Channel connection, 0=normal
4572 *
4573 * 0000 0000
4574 */
4575 RegValue = 0x00;
4576 switch(info->params.encoding) {
4577 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4578 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4579 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4580 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4581 #if 0
4582 case HDLC_ENCODING_NRZB: /* not supported */
4583 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4584 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4585 #endif
4586 }
4587 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4588 DpllDivisor = 16;
4589 RegValue |= BIT3;
4590 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4591 DpllDivisor = 8;
4592 } else {
4593 DpllDivisor = 32;
4594 RegValue |= BIT4;
4595 }
4596 write_reg(info, MD2, RegValue);
4597
4598
4599 /* RXS, Receive clock source
4600 *
4601 * 07 Reserved, must be 0
4602 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4603 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4604 */
4605 RegValue=0;
4606 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4607 RegValue |= BIT6;
4608 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4609 RegValue |= BIT6 + BIT5;
4610 write_reg(info, RXS, RegValue);
4611
4612 /* TXS, Transmit clock source
4613 *
4614 * 07 Reserved, must be 0
4615 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4616 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4617 */
4618 RegValue=0;
4619 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4620 RegValue |= BIT6;
4621 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4622 RegValue |= BIT6 + BIT5;
4623 write_reg(info, TXS, RegValue);
4624
4625 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4626 set_rate(info, info->params.clock_speed * DpllDivisor);
4627 else
4628 set_rate(info, info->params.clock_speed);
4629
4630 /* GPDATA (General Purpose I/O Data Register)
4631 *
4632 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4633 */
4634 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4635 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4636 else
4637 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4638 write_control_reg(info);
4639
4640 /* RRC Receive Ready Control 0
4641 *
4642 * 07..05 Reserved, must be 0
4643 * 04..00 RRC<4..0> Rx FIFO trigger active
4644 */
4645 write_reg(info, RRC, rx_active_fifo_level);
4646
4647 /* TRC0 Transmit Ready Control 0
4648 *
4649 * 07..05 Reserved, must be 0
4650 * 04..00 TRC<4..0> Tx FIFO trigger active
4651 */
4652 write_reg(info, TRC0, tx_active_fifo_level);
4653
4654 /* TRC1 Transmit Ready Control 1
4655 *
4656 * 07..05 Reserved, must be 0
4657 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4658 */
4659 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4660
4661 /* DMR, DMA Mode Register
4662 *
4663 * 07..05 Reserved, must be 0
4664 * 04 TMOD, Transfer Mode: 1=chained-block
4665 * 03 Reserved, must be 0
4666 * 02 NF, Number of Frames: 1=multi-frame
4667 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4668 * 00 Reserved, must be 0
4669 *
4670 * 0001 0100
4671 */
4672 write_reg(info, TXDMA + DMR, 0x14);
4673 write_reg(info, RXDMA + DMR, 0x14);
4674
4675 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4676 write_reg(info, RXDMA + CPB,
4677 (unsigned char)(info->buffer_list_phys >> 16));
4678
4679 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4680 write_reg(info, TXDMA + CPB,
4681 (unsigned char)(info->buffer_list_phys >> 16));
4682
4683 /* enable status interrupts. other code enables/disables
4684 * the individual sources for these two interrupt classes.
4685 */
4686 info->ie0_value |= TXINTE + RXINTE;
4687 write_reg(info, IE0, info->ie0_value);
4688
4689 /* CTL, MSCI control register
4690 *
4691 * 07..06 Reserved, set to 0
4692 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4693 * 04 IDLC, idle control, 0=mark 1=idle register
4694 * 03 BRK, break, 0=off 1 =on (async)
4695 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4696 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4697 * 00 RTS, RTS output control, 0=active 1=inactive
4698 *
4699 * 0001 0001
4700 */
4701 RegValue = 0x10;
4702 if (!(info->serial_signals & SerialSignal_RTS))
4703 RegValue |= 0x01;
4704 write_reg(info, CTL, RegValue);
4705
4706 /* preamble not supported ! */
4707
4708 tx_set_idle(info);
4709 tx_stop(info);
4710 rx_stop(info);
4711
4712 set_rate(info, info->params.clock_speed);
4713
4714 if (info->params.loopback)
4715 enable_loopback(info,1);
4716 }
4717
4718 /* Set the transmit HDLC idle mode
4719 */
4720 static void tx_set_idle(SLMP_INFO *info)
4721 {
4722 unsigned char RegValue = 0xff;
4723
4724 /* Map API idle mode to SCA register bits */
4725 switch(info->idle_mode) {
4726 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4727 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4728 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4729 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4730 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4731 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4732 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4733 }
4734
4735 write_reg(info, IDL, RegValue);
4736 }
4737
4738 /* Query the adapter for the state of the V24 status (input) signals.
4739 */
4740 static void get_signals(SLMP_INFO *info)
4741 {
4742 u16 status = read_reg(info, SR3);
4743 u16 gpstatus = read_status_reg(info);
4744 u16 testbit;
4745
4746 /* clear all serial signals except DTR and RTS */
4747 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4748
4749 /* set serial signal bits to reflect MISR */
4750
4751 if (!(status & BIT3))
4752 info->serial_signals |= SerialSignal_CTS;
4753
4754 if ( !(status & BIT2))
4755 info->serial_signals |= SerialSignal_DCD;
4756
4757 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4758 if (!(gpstatus & testbit))
4759 info->serial_signals |= SerialSignal_RI;
4760
4761 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4762 if (!(gpstatus & testbit))
4763 info->serial_signals |= SerialSignal_DSR;
4764 }
4765
4766 /* Set the state of DTR and RTS based on contents of
4767 * serial_signals member of device context.
4768 */
4769 static void set_signals(SLMP_INFO *info)
4770 {
4771 unsigned char RegValue;
4772 u16 EnableBit;
4773
4774 RegValue = read_reg(info, CTL);
4775 if (info->serial_signals & SerialSignal_RTS)
4776 RegValue &= ~BIT0;
4777 else
4778 RegValue |= BIT0;
4779 write_reg(info, CTL, RegValue);
4780
4781 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4782 EnableBit = BIT1 << (info->port_num*2);
4783 if (info->serial_signals & SerialSignal_DTR)
4784 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4785 else
4786 info->port_array[0]->ctrlreg_value |= EnableBit;
4787 write_control_reg(info);
4788 }
4789
4790 /*******************/
4791 /* DMA Buffer Code */
4792 /*******************/
4793
4794 /* Set the count for all receive buffers to SCABUFSIZE
4795 * and set the current buffer to the first buffer. This effectively
4796 * makes all buffers free and discards any data in buffers.
4797 */
4798 static void rx_reset_buffers(SLMP_INFO *info)
4799 {
4800 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4801 }
4802
4803 /* Free the buffers used by a received frame
4804 *
4805 * info pointer to device instance data
4806 * first index of 1st receive buffer of frame
4807 * last index of last receive buffer of frame
4808 */
4809 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4810 {
4811 bool done = false;
4812
4813 while(!done) {
4814 /* reset current buffer for reuse */
4815 info->rx_buf_list[first].status = 0xff;
4816
4817 if (first == last) {
4818 done = true;
4819 /* set new last rx descriptor address */
4820 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4821 }
4822
4823 first++;
4824 if (first == info->rx_buf_count)
4825 first = 0;
4826 }
4827
4828 /* set current buffer to next buffer after last buffer of frame */
4829 info->current_rx_buf = first;
4830 }
4831
4832 /* Return a received frame from the receive DMA buffers.
4833 * Only frames received without errors are returned.
4834 *
4835 * Return Value: true if frame returned, otherwise false
4836 */
4837 static bool rx_get_frame(SLMP_INFO *info)
4838 {
4839 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4840 unsigned short status;
4841 unsigned int framesize = 0;
4842 bool ReturnCode = false;
4843 unsigned long flags;
4844 struct tty_struct *tty = info->port.tty;
4845 unsigned char addr_field = 0xff;
4846 SCADESC *desc;
4847 SCADESC_EX *desc_ex;
4848
4849 CheckAgain:
4850 /* assume no frame returned, set zero length */
4851 framesize = 0;
4852 addr_field = 0xff;
4853
4854 /*
4855 * current_rx_buf points to the 1st buffer of the next available
4856 * receive frame. To find the last buffer of the frame look for
4857 * a non-zero status field in the buffer entries. (The status
4858 * field is set by the 16C32 after completing a receive frame.
4859 */
4860 StartIndex = EndIndex = info->current_rx_buf;
4861
4862 for ( ;; ) {
4863 desc = &info->rx_buf_list[EndIndex];
4864 desc_ex = &info->rx_buf_list_ex[EndIndex];
4865
4866 if (desc->status == 0xff)
4867 goto Cleanup; /* current desc still in use, no frames available */
4868
4869 if (framesize == 0 && info->params.addr_filter != 0xff)
4870 addr_field = desc_ex->virt_addr[0];
4871
4872 framesize += desc->length;
4873
4874 /* Status != 0 means last buffer of frame */
4875 if (desc->status)
4876 break;
4877
4878 EndIndex++;
4879 if (EndIndex == info->rx_buf_count)
4880 EndIndex = 0;
4881
4882 if (EndIndex == info->current_rx_buf) {
4883 /* all buffers have been 'used' but none mark */
4884 /* the end of a frame. Reset buffers and receiver. */
4885 if ( info->rx_enabled ){
4886 spin_lock_irqsave(&info->lock,flags);
4887 rx_start(info);
4888 spin_unlock_irqrestore(&info->lock,flags);
4889 }
4890 goto Cleanup;
4891 }
4892
4893 }
4894
4895 /* check status of receive frame */
4896
4897 /* frame status is byte stored after frame data
4898 *
4899 * 7 EOM (end of msg), 1 = last buffer of frame
4900 * 6 Short Frame, 1 = short frame
4901 * 5 Abort, 1 = frame aborted
4902 * 4 Residue, 1 = last byte is partial
4903 * 3 Overrun, 1 = overrun occurred during frame reception
4904 * 2 CRC, 1 = CRC error detected
4905 *
4906 */
4907 status = desc->status;
4908
4909 /* ignore CRC bit if not using CRC (bit is undefined) */
4910 /* Note:CRC is not save to data buffer */
4911 if (info->params.crc_type == HDLC_CRC_NONE)
4912 status &= ~BIT2;
4913
4914 if (framesize == 0 ||
4915 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4916 /* discard 0 byte frames, this seems to occur sometime
4917 * when remote is idling flags.
4918 */
4919 rx_free_frame_buffers(info, StartIndex, EndIndex);
4920 goto CheckAgain;
4921 }
4922
4923 if (framesize < 2)
4924 status |= BIT6;
4925
4926 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4927 /* received frame has errors,
4928 * update counts and mark frame size as 0
4929 */
4930 if (status & BIT6)
4931 info->icount.rxshort++;
4932 else if (status & BIT5)
4933 info->icount.rxabort++;
4934 else if (status & BIT3)
4935 info->icount.rxover++;
4936 else
4937 info->icount.rxcrc++;
4938
4939 framesize = 0;
4940 #if SYNCLINK_GENERIC_HDLC
4941 {
4942 info->netdev->stats.rx_errors++;
4943 info->netdev->stats.rx_frame_errors++;
4944 }
4945 #endif
4946 }
4947
4948 if ( debug_level >= DEBUG_LEVEL_BH )
4949 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4950 __FILE__,__LINE__,info->device_name,status,framesize);
4951
4952 if ( debug_level >= DEBUG_LEVEL_DATA )
4953 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4954 min_t(int, framesize,SCABUFSIZE),0);
4955
4956 if (framesize) {
4957 if (framesize > info->max_frame_size)
4958 info->icount.rxlong++;
4959 else {
4960 /* copy dma buffer(s) to contiguous intermediate buffer */
4961 int copy_count = framesize;
4962 int index = StartIndex;
4963 unsigned char *ptmp = info->tmp_rx_buf;
4964 info->tmp_rx_buf_count = framesize;
4965
4966 info->icount.rxok++;
4967
4968 while(copy_count) {
4969 int partial_count = min(copy_count,SCABUFSIZE);
4970 memcpy( ptmp,
4971 info->rx_buf_list_ex[index].virt_addr,
4972 partial_count );
4973 ptmp += partial_count;
4974 copy_count -= partial_count;
4975
4976 if ( ++index == info->rx_buf_count )
4977 index = 0;
4978 }
4979
4980 #if SYNCLINK_GENERIC_HDLC
4981 if (info->netcount)
4982 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4983 else
4984 #endif
4985 ldisc_receive_buf(tty,info->tmp_rx_buf,
4986 info->flag_buf, framesize);
4987 }
4988 }
4989 /* Free the buffers used by this frame. */
4990 rx_free_frame_buffers( info, StartIndex, EndIndex );
4991
4992 ReturnCode = true;
4993
4994 Cleanup:
4995 if ( info->rx_enabled && info->rx_overflow ) {
4996 /* Receiver is enabled, but needs to restarted due to
4997 * rx buffer overflow. If buffers are empty, restart receiver.
4998 */
4999 if (info->rx_buf_list[EndIndex].status == 0xff) {
5000 spin_lock_irqsave(&info->lock,flags);
5001 rx_start(info);
5002 spin_unlock_irqrestore(&info->lock,flags);
5003 }
5004 }
5005
5006 return ReturnCode;
5007 }
5008
5009 /* load the transmit DMA buffer with data
5010 */
5011 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5012 {
5013 unsigned short copy_count;
5014 unsigned int i = 0;
5015 SCADESC *desc;
5016 SCADESC_EX *desc_ex;
5017
5018 if ( debug_level >= DEBUG_LEVEL_DATA )
5019 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5020
5021 /* Copy source buffer to one or more DMA buffers, starting with
5022 * the first transmit dma buffer.
5023 */
5024 for(i=0;;)
5025 {
5026 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5027
5028 desc = &info->tx_buf_list[i];
5029 desc_ex = &info->tx_buf_list_ex[i];
5030
5031 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5032
5033 desc->length = copy_count;
5034 desc->status = 0;
5035
5036 buf += copy_count;
5037 count -= copy_count;
5038
5039 if (!count)
5040 break;
5041
5042 i++;
5043 if (i >= info->tx_buf_count)
5044 i = 0;
5045 }
5046
5047 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5048 info->last_tx_buf = ++i;
5049 }
5050
5051 static bool register_test(SLMP_INFO *info)
5052 {
5053 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5054 static unsigned int count = ARRAY_SIZE(testval);
5055 unsigned int i;
5056 bool rc = true;
5057 unsigned long flags;
5058
5059 spin_lock_irqsave(&info->lock,flags);
5060 reset_port(info);
5061
5062 /* assume failure */
5063 info->init_error = DiagStatus_AddressFailure;
5064
5065 /* Write bit patterns to various registers but do it out of */
5066 /* sync, then read back and verify values. */
5067
5068 for (i = 0 ; i < count ; i++) {
5069 write_reg(info, TMC, testval[i]);
5070 write_reg(info, IDL, testval[(i+1)%count]);
5071 write_reg(info, SA0, testval[(i+2)%count]);
5072 write_reg(info, SA1, testval[(i+3)%count]);
5073
5074 if ( (read_reg(info, TMC) != testval[i]) ||
5075 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5076 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5077 (read_reg(info, SA1) != testval[(i+3)%count]) )
5078 {
5079 rc = false;
5080 break;
5081 }
5082 }
5083
5084 reset_port(info);
5085 spin_unlock_irqrestore(&info->lock,flags);
5086
5087 return rc;
5088 }
5089
5090 static bool irq_test(SLMP_INFO *info)
5091 {
5092 unsigned long timeout;
5093 unsigned long flags;
5094
5095 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5096
5097 spin_lock_irqsave(&info->lock,flags);
5098 reset_port(info);
5099
5100 /* assume failure */
5101 info->init_error = DiagStatus_IrqFailure;
5102 info->irq_occurred = false;
5103
5104 /* setup timer0 on SCA0 to interrupt */
5105
5106 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5107 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5108
5109 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5110 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5111
5112
5113 /* TMCS, Timer Control/Status Register
5114 *
5115 * 07 CMF, Compare match flag (read only) 1=match
5116 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5117 * 05 Reserved, must be 0
5118 * 04 TME, Timer Enable
5119 * 03..00 Reserved, must be 0
5120 *
5121 * 0101 0000
5122 */
5123 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5124
5125 spin_unlock_irqrestore(&info->lock,flags);
5126
5127 timeout=100;
5128 while( timeout-- && !info->irq_occurred ) {
5129 msleep_interruptible(10);
5130 }
5131
5132 spin_lock_irqsave(&info->lock,flags);
5133 reset_port(info);
5134 spin_unlock_irqrestore(&info->lock,flags);
5135
5136 return info->irq_occurred;
5137 }
5138
5139 /* initialize individual SCA device (2 ports)
5140 */
5141 static bool sca_init(SLMP_INFO *info)
5142 {
5143 /* set wait controller to single mem partition (low), no wait states */
5144 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5145 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5146 write_reg(info, WCRL, 0); /* wait controller low range */
5147 write_reg(info, WCRM, 0); /* wait controller mid range */
5148 write_reg(info, WCRH, 0); /* wait controller high range */
5149
5150 /* DPCR, DMA Priority Control
5151 *
5152 * 07..05 Not used, must be 0
5153 * 04 BRC, bus release condition: 0=all transfers complete
5154 * 03 CCC, channel change condition: 0=every cycle
5155 * 02..00 PR<2..0>, priority 100=round robin
5156 *
5157 * 00000100 = 0x04
5158 */
5159 write_reg(info, DPCR, dma_priority);
5160
5161 /* DMA Master Enable, BIT7: 1=enable all channels */
5162 write_reg(info, DMER, 0x80);
5163
5164 /* enable all interrupt classes */
5165 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5166 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5167 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5168
5169 /* ITCR, interrupt control register
5170 * 07 IPC, interrupt priority, 0=MSCI->DMA
5171 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5172 * 04 VOS, Vector Output, 0=unmodified vector
5173 * 03..00 Reserved, must be 0
5174 */
5175 write_reg(info, ITCR, 0);
5176
5177 return true;
5178 }
5179
5180 /* initialize adapter hardware
5181 */
5182 static bool init_adapter(SLMP_INFO *info)
5183 {
5184 int i;
5185
5186 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5187 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5188 u32 readval;
5189
5190 info->misc_ctrl_value |= BIT30;
5191 *MiscCtrl = info->misc_ctrl_value;
5192
5193 /*
5194 * Force at least 170ns delay before clearing
5195 * reset bit. Each read from LCR takes at least
5196 * 30ns so 10 times for 300ns to be safe.
5197 */
5198 for(i=0;i<10;i++)
5199 readval = *MiscCtrl;
5200
5201 info->misc_ctrl_value &= ~BIT30;
5202 *MiscCtrl = info->misc_ctrl_value;
5203
5204 /* init control reg (all DTRs off, all clksel=input) */
5205 info->ctrlreg_value = 0xaa;
5206 write_control_reg(info);
5207
5208 {
5209 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5210 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5211
5212 switch(read_ahead_count)
5213 {
5214 case 16:
5215 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5216 break;
5217 case 8:
5218 lcr1_brdr_value |= BIT5 + BIT4;
5219 break;
5220 case 4:
5221 lcr1_brdr_value |= BIT5 + BIT3;
5222 break;
5223 case 0:
5224 lcr1_brdr_value |= BIT5;
5225 break;
5226 }
5227
5228 *LCR1BRDR = lcr1_brdr_value;
5229 *MiscCtrl = misc_ctrl_value;
5230 }
5231
5232 sca_init(info->port_array[0]);
5233 sca_init(info->port_array[2]);
5234
5235 return true;
5236 }
5237
5238 /* Loopback an HDLC frame to test the hardware
5239 * interrupt and DMA functions.
5240 */
5241 static bool loopback_test(SLMP_INFO *info)
5242 {
5243 #define TESTFRAMESIZE 20
5244
5245 unsigned long timeout;
5246 u16 count = TESTFRAMESIZE;
5247 unsigned char buf[TESTFRAMESIZE];
5248 bool rc = false;
5249 unsigned long flags;
5250
5251 struct tty_struct *oldtty = info->port.tty;
5252 u32 speed = info->params.clock_speed;
5253
5254 info->params.clock_speed = 3686400;
5255 info->port.tty = NULL;
5256
5257 /* assume failure */
5258 info->init_error = DiagStatus_DmaFailure;
5259
5260 /* build and send transmit frame */
5261 for (count = 0; count < TESTFRAMESIZE;++count)
5262 buf[count] = (unsigned char)count;
5263
5264 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5265
5266 /* program hardware for HDLC and enabled receiver */
5267 spin_lock_irqsave(&info->lock,flags);
5268 hdlc_mode(info);
5269 enable_loopback(info,1);
5270 rx_start(info);
5271 info->tx_count = count;
5272 tx_load_dma_buffer(info,buf,count);
5273 tx_start(info);
5274 spin_unlock_irqrestore(&info->lock,flags);
5275
5276 /* wait for receive complete */
5277 /* Set a timeout for waiting for interrupt. */
5278 for ( timeout = 100; timeout; --timeout ) {
5279 msleep_interruptible(10);
5280
5281 if (rx_get_frame(info)) {
5282 rc = true;
5283 break;
5284 }
5285 }
5286
5287 /* verify received frame length and contents */
5288 if (rc &&
5289 ( info->tmp_rx_buf_count != count ||
5290 memcmp(buf, info->tmp_rx_buf,count))) {
5291 rc = false;
5292 }
5293
5294 spin_lock_irqsave(&info->lock,flags);
5295 reset_adapter(info);
5296 spin_unlock_irqrestore(&info->lock,flags);
5297
5298 info->params.clock_speed = speed;
5299 info->port.tty = oldtty;
5300
5301 return rc;
5302 }
5303
5304 /* Perform diagnostics on hardware
5305 */
5306 static int adapter_test( SLMP_INFO *info )
5307 {
5308 unsigned long flags;
5309 if ( debug_level >= DEBUG_LEVEL_INFO )
5310 printk( "%s(%d):Testing device %s\n",
5311 __FILE__,__LINE__,info->device_name );
5312
5313 spin_lock_irqsave(&info->lock,flags);
5314 init_adapter(info);
5315 spin_unlock_irqrestore(&info->lock,flags);
5316
5317 info->port_array[0]->port_count = 0;
5318
5319 if ( register_test(info->port_array[0]) &&
5320 register_test(info->port_array[1])) {
5321
5322 info->port_array[0]->port_count = 2;
5323
5324 if ( register_test(info->port_array[2]) &&
5325 register_test(info->port_array[3]) )
5326 info->port_array[0]->port_count += 2;
5327 }
5328 else {
5329 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5330 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5331 return -ENODEV;
5332 }
5333
5334 if ( !irq_test(info->port_array[0]) ||
5335 !irq_test(info->port_array[1]) ||
5336 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5337 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5338 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5339 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5340 return -ENODEV;
5341 }
5342
5343 if (!loopback_test(info->port_array[0]) ||
5344 !loopback_test(info->port_array[1]) ||
5345 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5346 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5347 printk( "%s(%d):DMA test failure for device %s\n",
5348 __FILE__,__LINE__,info->device_name);
5349 return -ENODEV;
5350 }
5351
5352 if ( debug_level >= DEBUG_LEVEL_INFO )
5353 printk( "%s(%d):device %s passed diagnostics\n",
5354 __FILE__,__LINE__,info->device_name );
5355
5356 info->port_array[0]->init_error = 0;
5357 info->port_array[1]->init_error = 0;
5358 if ( info->port_count > 2 ) {
5359 info->port_array[2]->init_error = 0;
5360 info->port_array[3]->init_error = 0;
5361 }
5362
5363 return 0;
5364 }
5365
5366 /* Test the shared memory on a PCI adapter.
5367 */
5368 static bool memory_test(SLMP_INFO *info)
5369 {
5370 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5371 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5372 unsigned long count = ARRAY_SIZE(testval);
5373 unsigned long i;
5374 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5375 unsigned long * addr = (unsigned long *)info->memory_base;
5376
5377 /* Test data lines with test pattern at one location. */
5378
5379 for ( i = 0 ; i < count ; i++ ) {
5380 *addr = testval[i];
5381 if ( *addr != testval[i] )
5382 return false;
5383 }
5384
5385 /* Test address lines with incrementing pattern over */
5386 /* entire address range. */
5387
5388 for ( i = 0 ; i < limit ; i++ ) {
5389 *addr = i * 4;
5390 addr++;
5391 }
5392
5393 addr = (unsigned long *)info->memory_base;
5394
5395 for ( i = 0 ; i < limit ; i++ ) {
5396 if ( *addr != i * 4 )
5397 return false;
5398 addr++;
5399 }
5400
5401 memset( info->memory_base, 0, SCA_MEM_SIZE );
5402 return true;
5403 }
5404
5405 /* Load data into PCI adapter shared memory.
5406 *
5407 * The PCI9050 releases control of the local bus
5408 * after completing the current read or write operation.
5409 *
5410 * While the PCI9050 write FIFO not empty, the
5411 * PCI9050 treats all of the writes as a single transaction
5412 * and does not release the bus. This causes DMA latency problems
5413 * at high speeds when copying large data blocks to the shared memory.
5414 *
5415 * This function breaks a write into multiple transations by
5416 * interleaving a read which flushes the write FIFO and 'completes'
5417 * the write transation. This allows any pending DMA request to gain control
5418 * of the local bus in a timely fasion.
5419 */
5420 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5421 {
5422 /* A load interval of 16 allows for 4 32-bit writes at */
5423 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5424
5425 unsigned short interval = count / sca_pci_load_interval;
5426 unsigned short i;
5427
5428 for ( i = 0 ; i < interval ; i++ )
5429 {
5430 memcpy(dest, src, sca_pci_load_interval);
5431 read_status_reg(info);
5432 dest += sca_pci_load_interval;
5433 src += sca_pci_load_interval;
5434 }
5435
5436 memcpy(dest, src, count % sca_pci_load_interval);
5437 }
5438
5439 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5440 {
5441 int i;
5442 int linecount;
5443 if (xmit)
5444 printk("%s tx data:\n",info->device_name);
5445 else
5446 printk("%s rx data:\n",info->device_name);
5447
5448 while(count) {
5449 if (count > 16)
5450 linecount = 16;
5451 else
5452 linecount = count;
5453
5454 for(i=0;i<linecount;i++)
5455 printk("%02X ",(unsigned char)data[i]);
5456 for(;i<17;i++)
5457 printk(" ");
5458 for(i=0;i<linecount;i++) {
5459 if (data[i]>=040 && data[i]<=0176)
5460 printk("%c",data[i]);
5461 else
5462 printk(".");
5463 }
5464 printk("\n");
5465
5466 data += linecount;
5467 count -= linecount;
5468 }
5469 } /* end of trace_block() */
5470
5471 /* called when HDLC frame times out
5472 * update stats and do tx completion processing
5473 */
5474 static void tx_timeout(unsigned long context)
5475 {
5476 SLMP_INFO *info = (SLMP_INFO*)context;
5477 unsigned long flags;
5478
5479 if ( debug_level >= DEBUG_LEVEL_INFO )
5480 printk( "%s(%d):%s tx_timeout()\n",
5481 __FILE__,__LINE__,info->device_name);
5482 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5483 info->icount.txtimeout++;
5484 }
5485 spin_lock_irqsave(&info->lock,flags);
5486 info->tx_active = false;
5487 info->tx_count = info->tx_put = info->tx_get = 0;
5488
5489 spin_unlock_irqrestore(&info->lock,flags);
5490
5491 #if SYNCLINK_GENERIC_HDLC
5492 if (info->netcount)
5493 hdlcdev_tx_done(info);
5494 else
5495 #endif
5496 bh_transmit(info);
5497 }
5498
5499 /* called to periodically check the DSR/RI modem signal input status
5500 */
5501 static void status_timeout(unsigned long context)
5502 {
5503 u16 status = 0;
5504 SLMP_INFO *info = (SLMP_INFO*)context;
5505 unsigned long flags;
5506 unsigned char delta;
5507
5508
5509 spin_lock_irqsave(&info->lock,flags);
5510 get_signals(info);
5511 spin_unlock_irqrestore(&info->lock,flags);
5512
5513 /* check for DSR/RI state change */
5514
5515 delta = info->old_signals ^ info->serial_signals;
5516 info->old_signals = info->serial_signals;
5517
5518 if (delta & SerialSignal_DSR)
5519 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5520
5521 if (delta & SerialSignal_RI)
5522 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5523
5524 if (delta & SerialSignal_DCD)
5525 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5526
5527 if (delta & SerialSignal_CTS)
5528 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5529
5530 if (status)
5531 isr_io_pin(info,status);
5532
5533 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5534 }
5535
5536
5537 /* Register Access Routines -
5538 * All registers are memory mapped
5539 */
5540 #define CALC_REGADDR() \
5541 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5542 if (info->port_num > 1) \
5543 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5544 if ( info->port_num & 1) { \
5545 if (Addr > 0x7f) \
5546 RegAddr += 0x40; /* DMA access */ \
5547 else if (Addr > 0x1f && Addr < 0x60) \
5548 RegAddr += 0x20; /* MSCI access */ \
5549 }
5550
5551
5552 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5553 {
5554 CALC_REGADDR();
5555 return *RegAddr;
5556 }
5557 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5558 {
5559 CALC_REGADDR();
5560 *RegAddr = Value;
5561 }
5562
5563 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5564 {
5565 CALC_REGADDR();
5566 return *((u16 *)RegAddr);
5567 }
5568
5569 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5570 {
5571 CALC_REGADDR();
5572 *((u16 *)RegAddr) = Value;
5573 }
5574
5575 static unsigned char read_status_reg(SLMP_INFO * info)
5576 {
5577 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5578 return *RegAddr;
5579 }
5580
5581 static void write_control_reg(SLMP_INFO * info)
5582 {
5583 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5584 *RegAddr = info->port_array[0]->ctrlreg_value;
5585 }
5586
5587
5588 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5589 const struct pci_device_id *ent)
5590 {
5591 if (pci_enable_device(dev)) {
5592 printk("error enabling pci device %p\n", dev);
5593 return -EIO;
5594 }
5595 device_init( ++synclinkmp_adapter_count, dev );
5596 return 0;
5597 }
5598
5599 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5600 {
5601 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree