2 * mfd.c: driver for High Speed UART device of Intel Medfield platform
4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
6 * (C) Copyright 2010 Intel Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
15 * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
17 * are used for RX, odd chans for TX
19 * 2. In A0 stepping, UART will not support TX half empty flag
21 * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
22 * asserted, only when the HW is reset the DDCD and DDSR will
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/console.h>
29 #include <linux/sysrq.h>
30 #include <linux/serial_reg.h>
31 #include <linux/circ_buf.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial_mfd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/pci.h>
41 #include <linux/debugfs.h>
43 #define MFD_HSU_A0_STEPPING 1
45 #define HSU_DMA_BUF_SIZE 2048
47 #define chan_readl(chan, offset) readl(chan->reg + offset)
48 #define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
50 #define mfd_readl(obj, offset) readl(obj->reg + offset)
51 #define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
53 #define HSU_DMA_TIMEOUT_CHECK_FREQ (HZ/10)
55 struct hsu_dma_buffer
{
64 enum dma_data_direction dirt
;
65 struct uart_hsu_port
*uport
;
67 struct timer_list rx_timer
; /* only needed by RX channel */
70 struct uart_hsu_port
{
71 struct uart_port port
;
75 unsigned int lsr_break_flag
;
80 struct hsu_dma_chan
*txc
;
81 struct hsu_dma_chan
*rxc
;
82 struct hsu_dma_buffer txbuf
;
83 struct hsu_dma_buffer rxbuf
;
84 int use_dma
; /* flag for DMA/PIO */
89 /* Top level data structure of HSU */
96 struct uart_hsu_port port
[3];
97 struct hsu_dma_chan chans
[10];
99 struct dentry
*debugfs
;
102 static inline unsigned int serial_in(struct uart_hsu_port
*up
, int offset
)
106 if (offset
> UART_MSR
) {
108 val
= readl(up
->port
.membase
+ offset
);
110 val
= (unsigned int)readb(up
->port
.membase
+ offset
);
115 static inline void serial_out(struct uart_hsu_port
*up
, int offset
, int value
)
117 if (offset
> UART_MSR
) {
119 writel(value
, up
->port
.membase
+ offset
);
121 unsigned char val
= value
& 0xff;
122 writeb(val
, up
->port
.membase
+ offset
);
126 #ifdef CONFIG_DEBUG_FS
128 #define HSU_REGS_BUFSIZE 1024
130 static int hsu_show_regs_open(struct inode
*inode
, struct file
*file
)
132 file
->private_data
= inode
->i_private
;
136 static ssize_t
port_show_regs(struct file
*file
, char __user
*user_buf
,
137 size_t count
, loff_t
*ppos
)
139 struct uart_hsu_port
*up
= file
->private_data
;
144 buf
= kzalloc(HSU_REGS_BUFSIZE
, GFP_KERNEL
);
148 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
149 "MFD HSU port[%d] regs:\n", up
->index
);
151 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
152 "=================================\n");
153 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
154 "IER: \t\t0x%08x\n", serial_in(up
, UART_IER
));
155 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
156 "IIR: \t\t0x%08x\n", serial_in(up
, UART_IIR
));
157 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
158 "LCR: \t\t0x%08x\n", serial_in(up
, UART_LCR
));
159 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
160 "MCR: \t\t0x%08x\n", serial_in(up
, UART_MCR
));
161 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
162 "LSR: \t\t0x%08x\n", serial_in(up
, UART_LSR
));
163 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
164 "MSR: \t\t0x%08x\n", serial_in(up
, UART_MSR
));
165 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
166 "FOR: \t\t0x%08x\n", serial_in(up
, UART_FOR
));
167 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
168 "PS: \t\t0x%08x\n", serial_in(up
, UART_PS
));
169 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
170 "MUL: \t\t0x%08x\n", serial_in(up
, UART_MUL
));
171 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
172 "DIV: \t\t0x%08x\n", serial_in(up
, UART_DIV
));
174 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
179 static ssize_t
dma_show_regs(struct file
*file
, char __user
*user_buf
,
180 size_t count
, loff_t
*ppos
)
182 struct hsu_dma_chan
*chan
= file
->private_data
;
187 buf
= kzalloc(HSU_REGS_BUFSIZE
, GFP_KERNEL
);
191 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
192 "MFD HSU DMA channel [%d] regs:\n", chan
->id
);
194 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
195 "=================================\n");
196 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
197 "CR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_CR
));
198 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
199 "DCR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_DCR
));
200 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
201 "BSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_BSR
));
202 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
203 "MOTSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_MOTSR
));
204 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
205 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D0SAR
));
206 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
207 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D0TSR
));
208 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
209 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D1SAR
));
210 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
211 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D1TSR
));
212 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
213 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D2SAR
));
214 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
215 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D2TSR
));
216 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
217 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D3SAR
));
218 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
219 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D3TSR
));
221 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
226 static const struct file_operations port_regs_ops
= {
227 .owner
= THIS_MODULE
,
228 .open
= hsu_show_regs_open
,
229 .read
= port_show_regs
,
232 static const struct file_operations dma_regs_ops
= {
233 .owner
= THIS_MODULE
,
234 .open
= hsu_show_regs_open
,
235 .read
= dma_show_regs
,
238 static int hsu_debugfs_init(struct hsu_port
*hsu
)
243 hsu
->debugfs
= debugfs_create_dir("hsu", NULL
);
247 for (i
= 0; i
< 3; i
++) {
248 snprintf(name
, sizeof(name
), "port_%d_regs", i
);
249 debugfs_create_file(name
, S_IFREG
| S_IRUGO
,
250 hsu
->debugfs
, (void *)(&hsu
->port
[i
]), &port_regs_ops
);
253 for (i
= 0; i
< 6; i
++) {
254 snprintf(name
, sizeof(name
), "dma_chan_%d_regs", i
);
255 debugfs_create_file(name
, S_IFREG
| S_IRUGO
,
256 hsu
->debugfs
, (void *)&hsu
->chans
[i
], &dma_regs_ops
);
262 static void hsu_debugfs_remove(struct hsu_port
*hsu
)
265 debugfs_remove_recursive(hsu
->debugfs
);
269 static inline int hsu_debugfs_init(struct hsu_port
*hsu
)
274 static inline void hsu_debugfs_remove(struct hsu_port
*hsu
)
277 #endif /* CONFIG_DEBUG_FS */
279 static void serial_hsu_enable_ms(struct uart_port
*port
)
281 struct uart_hsu_port
*up
=
282 container_of(port
, struct uart_hsu_port
, port
);
284 up
->ier
|= UART_IER_MSI
;
285 serial_out(up
, UART_IER
, up
->ier
);
288 void hsu_dma_tx(struct uart_hsu_port
*up
)
290 struct circ_buf
*xmit
= &up
->port
.state
->xmit
;
291 struct hsu_dma_buffer
*dbuf
= &up
->txbuf
;
294 /* test_and_set_bit may be better, but anyway it's in lock protected mode */
298 /* Update the circ buf info */
299 xmit
->tail
+= dbuf
->ofs
;
300 xmit
->tail
&= UART_XMIT_SIZE
- 1;
302 up
->port
.icount
.tx
+= dbuf
->ofs
;
305 /* Disable the channel */
306 chan_writel(up
->txc
, HSU_CH_CR
, 0x0);
308 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&up
->port
)) {
309 dma_sync_single_for_device(up
->port
.dev
,
314 count
= CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
317 /* Reprogram the channel */
318 chan_writel(up
->txc
, HSU_CH_D0SAR
, dbuf
->dma_addr
+ xmit
->tail
);
319 chan_writel(up
->txc
, HSU_CH_D0TSR
, count
);
321 /* Reenable the channel */
322 chan_writel(up
->txc
, HSU_CH_DCR
, 0x1
327 chan_writel(up
->txc
, HSU_CH_CR
, 0x1);
330 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
331 uart_write_wakeup(&up
->port
);
334 /* The buffer is already cache coherent */
335 void hsu_dma_start_rx_chan(struct hsu_dma_chan
*rxc
, struct hsu_dma_buffer
*dbuf
)
339 chan_writel(rxc
, HSU_CH_BSR
, 32);
340 chan_writel(rxc
, HSU_CH_MOTSR
, 4);
342 chan_writel(rxc
, HSU_CH_D0SAR
, dbuf
->dma_addr
);
343 chan_writel(rxc
, HSU_CH_D0TSR
, dbuf
->dma_size
);
344 chan_writel(rxc
, HSU_CH_DCR
, 0x1 | (0x1 << 8)
346 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
348 chan_writel(rxc
, HSU_CH_CR
, 0x3);
350 mod_timer(&rxc
->rx_timer
, jiffies
+ HSU_DMA_TIMEOUT_CHECK_FREQ
);
353 /* Protected by spin_lock_irqsave(port->lock) */
354 static void serial_hsu_start_tx(struct uart_port
*port
)
356 struct uart_hsu_port
*up
=
357 container_of(port
, struct uart_hsu_port
, port
);
361 } else if (!(up
->ier
& UART_IER_THRI
)) {
362 up
->ier
|= UART_IER_THRI
;
363 serial_out(up
, UART_IER
, up
->ier
);
367 static void serial_hsu_stop_tx(struct uart_port
*port
)
369 struct uart_hsu_port
*up
=
370 container_of(port
, struct uart_hsu_port
, port
);
371 struct hsu_dma_chan
*txc
= up
->txc
;
374 chan_writel(txc
, HSU_CH_CR
, 0x0);
375 else if (up
->ier
& UART_IER_THRI
) {
376 up
->ier
&= ~UART_IER_THRI
;
377 serial_out(up
, UART_IER
, up
->ier
);
381 /* This is always called in spinlock protected mode, so
382 * modify timeout timer is safe here */
383 void hsu_dma_rx(struct uart_hsu_port
*up
, u32 int_sts
)
385 struct hsu_dma_buffer
*dbuf
= &up
->rxbuf
;
386 struct hsu_dma_chan
*chan
= up
->rxc
;
387 struct uart_port
*port
= &up
->port
;
388 struct tty_struct
*tty
= port
->state
->port
.tty
;
395 * First need to know how many is already transferred,
396 * then check if its a timeout DMA irq, and return
397 * the trail bytes out, push them up and reenable the
401 /* Timeout IRQ, need wait some time, see Errata 2 */
405 /* Stop the channel */
406 chan_writel(chan
, HSU_CH_CR
, 0x0);
408 count
= chan_readl(chan
, HSU_CH_D0SAR
) - dbuf
->dma_addr
;
410 /* Restart the channel before we leave */
411 chan_writel(chan
, HSU_CH_CR
, 0x3);
414 del_timer(&chan
->rx_timer
);
416 dma_sync_single_for_cpu(port
->dev
, dbuf
->dma_addr
,
417 dbuf
->dma_size
, DMA_FROM_DEVICE
);
420 * Head will only wrap around when we recycle
421 * the DMA buffer, and when that happens, we
422 * explicitly set tail to 0. So head will
423 * always be greater than tail.
425 tty_insert_flip_string(tty
, dbuf
->buf
, count
);
426 port
->icount
.rx
+= count
;
428 dma_sync_single_for_device(up
->port
.dev
, dbuf
->dma_addr
,
429 dbuf
->dma_size
, DMA_FROM_DEVICE
);
431 /* Reprogram the channel */
432 chan_writel(chan
, HSU_CH_D0SAR
, dbuf
->dma_addr
);
433 chan_writel(chan
, HSU_CH_D0TSR
, dbuf
->dma_size
);
434 chan_writel(chan
, HSU_CH_DCR
, 0x1
437 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
439 tty_flip_buffer_push(tty
);
441 chan_writel(chan
, HSU_CH_CR
, 0x3);
442 chan
->rx_timer
.expires
= jiffies
+ HSU_DMA_TIMEOUT_CHECK_FREQ
;
443 add_timer(&chan
->rx_timer
);
447 static void serial_hsu_stop_rx(struct uart_port
*port
)
449 struct uart_hsu_port
*up
=
450 container_of(port
, struct uart_hsu_port
, port
);
451 struct hsu_dma_chan
*chan
= up
->rxc
;
454 chan_writel(chan
, HSU_CH_CR
, 0x2);
456 up
->ier
&= ~UART_IER_RLSI
;
457 up
->port
.read_status_mask
&= ~UART_LSR_DR
;
458 serial_out(up
, UART_IER
, up
->ier
);
462 static inline void receive_chars(struct uart_hsu_port
*up
, int *status
)
464 struct tty_struct
*tty
= up
->port
.state
->port
.tty
;
465 unsigned int ch
, flag
;
466 unsigned int max_count
= 256;
472 ch
= serial_in(up
, UART_RX
);
474 up
->port
.icount
.rx
++;
476 if (unlikely(*status
& (UART_LSR_BI
| UART_LSR_PE
|
477 UART_LSR_FE
| UART_LSR_OE
))) {
479 dev_warn(up
->dev
, "We really rush into ERR/BI case"
480 "status = 0x%02x", *status
);
481 /* For statistics only */
482 if (*status
& UART_LSR_BI
) {
483 *status
&= ~(UART_LSR_FE
| UART_LSR_PE
);
484 up
->port
.icount
.brk
++;
486 * We do the SysRQ and SAK checking
487 * here because otherwise the break
488 * may get masked by ignore_status_mask
489 * or read_status_mask.
491 if (uart_handle_break(&up
->port
))
493 } else if (*status
& UART_LSR_PE
)
494 up
->port
.icount
.parity
++;
495 else if (*status
& UART_LSR_FE
)
496 up
->port
.icount
.frame
++;
497 if (*status
& UART_LSR_OE
)
498 up
->port
.icount
.overrun
++;
500 /* Mask off conditions which should be ignored. */
501 *status
&= up
->port
.read_status_mask
;
503 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
505 up
->port
.cons
->index
== up
->port
.line
) {
506 /* Recover the break flag from console xmit */
507 *status
|= up
->lsr_break_flag
;
508 up
->lsr_break_flag
= 0;
511 if (*status
& UART_LSR_BI
) {
513 } else if (*status
& UART_LSR_PE
)
515 else if (*status
& UART_LSR_FE
)
519 if (uart_handle_sysrq_char(&up
->port
, ch
))
522 uart_insert_char(&up
->port
, *status
, UART_LSR_OE
, ch
, flag
);
524 *status
= serial_in(up
, UART_LSR
);
525 } while ((*status
& UART_LSR_DR
) && max_count
--);
526 tty_flip_buffer_push(tty
);
529 static void transmit_chars(struct uart_hsu_port
*up
)
531 struct circ_buf
*xmit
= &up
->port
.state
->xmit
;
534 if (up
->port
.x_char
) {
535 serial_out(up
, UART_TX
, up
->port
.x_char
);
536 up
->port
.icount
.tx
++;
540 if (uart_circ_empty(xmit
) || uart_tx_stopped(&up
->port
)) {
541 serial_hsu_stop_tx(&up
->port
);
545 #ifndef MFD_HSU_A0_STEPPING
546 count
= up
->port
.fifosize
/ 2;
549 * A0 only supports fully empty IRQ, and the first char written
550 * into it won't clear the EMPT bit, so we may need be cautious
551 * by useing a shorter buffer
553 count
= up
->port
.fifosize
- 4;
556 serial_out(up
, UART_TX
, xmit
->buf
[xmit
->tail
]);
557 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
559 up
->port
.icount
.tx
++;
560 if (uart_circ_empty(xmit
))
562 } while (--count
> 0);
564 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
565 uart_write_wakeup(&up
->port
);
567 if (uart_circ_empty(xmit
))
568 serial_hsu_stop_tx(&up
->port
);
571 static inline void check_modem_status(struct uart_hsu_port
*up
)
575 status
= serial_in(up
, UART_MSR
);
577 if ((status
& UART_MSR_ANY_DELTA
) == 0)
580 if (status
& UART_MSR_TERI
)
581 up
->port
.icount
.rng
++;
582 if (status
& UART_MSR_DDSR
)
583 up
->port
.icount
.dsr
++;
584 /* We may only get DDCD when HW init and reset */
585 if (status
& UART_MSR_DDCD
)
586 uart_handle_dcd_change(&up
->port
, status
& UART_MSR_DCD
);
587 /* Will start/stop_tx accordingly */
588 if (status
& UART_MSR_DCTS
)
589 uart_handle_cts_change(&up
->port
, status
& UART_MSR_CTS
);
591 wake_up_interruptible(&up
->port
.state
->port
.delta_msr_wait
);
595 * This handles the interrupt from one port.
597 static irqreturn_t
port_irq(int irq
, void *dev_id
)
599 struct uart_hsu_port
*up
= dev_id
;
600 unsigned int iir
, lsr
;
603 if (unlikely(!up
->running
))
606 spin_lock_irqsave(&up
->port
.lock
, flags
);
608 lsr
= serial_in(up
, UART_LSR
);
609 if (unlikely(lsr
& (UART_LSR_BI
| UART_LSR_PE
|
610 UART_LSR_FE
| UART_LSR_OE
)))
612 "Got lsr irq while using DMA, lsr = 0x%2x\n",
614 check_modem_status(up
);
615 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
619 iir
= serial_in(up
, UART_IIR
);
620 if (iir
& UART_IIR_NO_INT
) {
621 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
625 lsr
= serial_in(up
, UART_LSR
);
626 if (lsr
& UART_LSR_DR
)
627 receive_chars(up
, &lsr
);
628 check_modem_status(up
);
630 /* lsr will be renewed during the receive_chars */
631 if (lsr
& UART_LSR_THRE
)
634 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
638 static inline void dma_chan_irq(struct hsu_dma_chan
*chan
)
640 struct uart_hsu_port
*up
= chan
->uport
;
644 spin_lock_irqsave(&up
->port
.lock
, flags
);
646 if (!up
->use_dma
|| !up
->running
)
650 * No matter what situation, need read clear the IRQ status
651 * There is a bug, see Errata 5, HSD 2900918
653 int_sts
= chan_readl(chan
, HSU_CH_SR
);
656 if (chan
->dirt
== DMA_FROM_DEVICE
)
657 hsu_dma_rx(up
, int_sts
);
660 if (chan
->dirt
== DMA_TO_DEVICE
) {
661 chan_writel(chan
, HSU_CH_CR
, 0x0);
667 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
671 static irqreturn_t
dma_irq(int irq
, void *dev_id
)
673 struct hsu_port
*hsu
= dev_id
;
676 int_sts
= mfd_readl(hsu
, HSU_GBL_DMAISR
);
678 /* Currently we only have 6 channels may be used */
679 for (i
= 0; i
< 6; i
++) {
681 dma_chan_irq(&hsu
->chans
[i
]);
688 static unsigned int serial_hsu_tx_empty(struct uart_port
*port
)
690 struct uart_hsu_port
*up
=
691 container_of(port
, struct uart_hsu_port
, port
);
695 spin_lock_irqsave(&up
->port
.lock
, flags
);
696 ret
= serial_in(up
, UART_LSR
) & UART_LSR_TEMT
? TIOCSER_TEMT
: 0;
697 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
702 static unsigned int serial_hsu_get_mctrl(struct uart_port
*port
)
704 struct uart_hsu_port
*up
=
705 container_of(port
, struct uart_hsu_port
, port
);
706 unsigned char status
;
709 status
= serial_in(up
, UART_MSR
);
712 if (status
& UART_MSR_DCD
)
714 if (status
& UART_MSR_RI
)
716 if (status
& UART_MSR_DSR
)
718 if (status
& UART_MSR_CTS
)
723 static void serial_hsu_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
725 struct uart_hsu_port
*up
=
726 container_of(port
, struct uart_hsu_port
, port
);
727 unsigned char mcr
= 0;
729 if (mctrl
& TIOCM_RTS
)
731 if (mctrl
& TIOCM_DTR
)
733 if (mctrl
& TIOCM_OUT1
)
734 mcr
|= UART_MCR_OUT1
;
735 if (mctrl
& TIOCM_OUT2
)
736 mcr
|= UART_MCR_OUT2
;
737 if (mctrl
& TIOCM_LOOP
)
738 mcr
|= UART_MCR_LOOP
;
742 serial_out(up
, UART_MCR
, mcr
);
745 static void serial_hsu_break_ctl(struct uart_port
*port
, int break_state
)
747 struct uart_hsu_port
*up
=
748 container_of(port
, struct uart_hsu_port
, port
);
751 spin_lock_irqsave(&up
->port
.lock
, flags
);
752 if (break_state
== -1)
753 up
->lcr
|= UART_LCR_SBC
;
755 up
->lcr
&= ~UART_LCR_SBC
;
756 serial_out(up
, UART_LCR
, up
->lcr
);
757 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
761 * What special to do:
762 * 1. chose the 64B fifo mode
763 * 2. make sure not to select half empty mode for A0 stepping
764 * 3. start dma or pio depends on configuration
765 * 4. we only allocate dma memory when needed
767 static int serial_hsu_startup(struct uart_port
*port
)
769 struct uart_hsu_port
*up
=
770 container_of(port
, struct uart_hsu_port
, port
);
774 * Clear the FIFO buffers and disable them.
775 * (they will be reenabled in set_termios())
777 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
778 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
779 UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
780 serial_out(up
, UART_FCR
, 0);
782 /* Clear the interrupt registers. */
783 (void) serial_in(up
, UART_LSR
);
784 (void) serial_in(up
, UART_RX
);
785 (void) serial_in(up
, UART_IIR
);
786 (void) serial_in(up
, UART_MSR
);
788 /* Now, initialize the UART, default is 8n1 */
789 serial_out(up
, UART_LCR
, UART_LCR_WLEN8
);
791 spin_lock_irqsave(&up
->port
.lock
, flags
);
793 up
->port
.mctrl
|= TIOCM_OUT2
;
794 serial_hsu_set_mctrl(&up
->port
, up
->port
.mctrl
);
797 * Finally, enable interrupts. Note: Modem status interrupts
798 * are set via set_termios(), which will be occurring imminently
799 * anyway, so we don't enable them here.
802 up
->ier
= UART_IER_RLSI
| UART_IER_RDI
| UART_IER_RTOIE
;
805 serial_out(up
, UART_IER
, up
->ier
);
807 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
811 struct hsu_dma_buffer
*dbuf
;
812 struct circ_buf
*xmit
= &port
->state
->xmit
;
816 /* First allocate the RX buffer */
818 dbuf
->buf
= kzalloc(HSU_DMA_BUF_SIZE
, GFP_KERNEL
);
823 dbuf
->dma_addr
= dma_map_single(port
->dev
,
827 dbuf
->dma_size
= HSU_DMA_BUF_SIZE
;
829 /* Start the RX channel right now */
830 hsu_dma_start_rx_chan(up
->rxc
, dbuf
);
832 /* Next init the TX DMA */
834 dbuf
->buf
= xmit
->buf
;
835 dbuf
->dma_addr
= dma_map_single(port
->dev
,
839 dbuf
->dma_size
= UART_XMIT_SIZE
;
841 /* This should not be changed all around */
842 chan_writel(up
->txc
, HSU_CH_BSR
, 32);
843 chan_writel(up
->txc
, HSU_CH_MOTSR
, 4);
848 /* And clear the interrupt registers again for luck. */
849 (void) serial_in(up
, UART_LSR
);
850 (void) serial_in(up
, UART_RX
);
851 (void) serial_in(up
, UART_IIR
);
852 (void) serial_in(up
, UART_MSR
);
858 static void serial_hsu_shutdown(struct uart_port
*port
)
860 struct uart_hsu_port
*up
=
861 container_of(port
, struct uart_hsu_port
, port
);
864 del_timer_sync(&up
->rxc
->rx_timer
);
866 /* Disable interrupts from this port */
868 serial_out(up
, UART_IER
, 0);
871 spin_lock_irqsave(&up
->port
.lock
, flags
);
872 up
->port
.mctrl
&= ~TIOCM_OUT2
;
873 serial_hsu_set_mctrl(&up
->port
, up
->port
.mctrl
);
874 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
876 /* Disable break condition and FIFOs */
877 serial_out(up
, UART_LCR
, serial_in(up
, UART_LCR
) & ~UART_LCR_SBC
);
878 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
879 UART_FCR_CLEAR_RCVR
|
880 UART_FCR_CLEAR_XMIT
);
881 serial_out(up
, UART_FCR
, 0);
885 serial_hsu_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
886 struct ktermios
*old
)
888 struct uart_hsu_port
*up
=
889 container_of(port
, struct uart_hsu_port
, port
);
890 struct tty_struct
*tty
= port
->state
->port
.tty
;
891 unsigned char cval
, fcr
= 0;
893 unsigned int baud
, quot
;
897 switch (termios
->c_cflag
& CSIZE
) {
899 cval
= UART_LCR_WLEN5
;
902 cval
= UART_LCR_WLEN6
;
905 cval
= UART_LCR_WLEN7
;
909 cval
= UART_LCR_WLEN8
;
913 /* CMSPAR isn't supported by this driver */
915 tty
->termios
->c_cflag
&= ~CMSPAR
;
917 if (termios
->c_cflag
& CSTOPB
)
918 cval
|= UART_LCR_STOP
;
919 if (termios
->c_cflag
& PARENB
)
920 cval
|= UART_LCR_PARITY
;
921 if (!(termios
->c_cflag
& PARODD
))
922 cval
|= UART_LCR_EPAR
;
925 * For those basic low baud rate we can get the direct
926 * scalar from 2746800, like 115200 = 2746800/24, for those
927 * higher baud rate, we have to handle them case by case,
928 * but DIV reg is never touched as its default value 0x3d09
930 baud
= uart_get_baud_rate(port
, termios
, old
, 0, 4000000);
931 quot
= uart_get_divisor(port
, baud
);
958 if ((up
->port
.uartclk
/ quot
) < (2400 * 16))
959 fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_HSU_64_1B
;
960 else if ((up
->port
.uartclk
/ quot
) < (230400 * 16))
961 fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_HSU_64_16B
;
963 fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_HSU_64_32B
;
965 fcr
|= UART_FCR_HSU_64B_FIFO
;
966 #ifdef MFD_HSU_A0_STEPPING
967 /* A0 doesn't support half empty IRQ */
968 fcr
|= UART_FCR_FULL_EMPT_TXI
;
972 * Ok, we're now changing the port state. Do it with
973 * interrupts disabled.
975 spin_lock_irqsave(&up
->port
.lock
, flags
);
977 /* Update the per-port timeout */
978 uart_update_timeout(port
, termios
->c_cflag
, baud
);
980 up
->port
.read_status_mask
= UART_LSR_OE
| UART_LSR_THRE
| UART_LSR_DR
;
981 if (termios
->c_iflag
& INPCK
)
982 up
->port
.read_status_mask
|= UART_LSR_FE
| UART_LSR_PE
;
983 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
984 up
->port
.read_status_mask
|= UART_LSR_BI
;
986 /* Characters to ignore */
987 up
->port
.ignore_status_mask
= 0;
988 if (termios
->c_iflag
& IGNPAR
)
989 up
->port
.ignore_status_mask
|= UART_LSR_PE
| UART_LSR_FE
;
990 if (termios
->c_iflag
& IGNBRK
) {
991 up
->port
.ignore_status_mask
|= UART_LSR_BI
;
993 * If we're ignoring parity and break indicators,
994 * ignore overruns too (for real raw support).
996 if (termios
->c_iflag
& IGNPAR
)
997 up
->port
.ignore_status_mask
|= UART_LSR_OE
;
1000 /* Ignore all characters if CREAD is not set */
1001 if ((termios
->c_cflag
& CREAD
) == 0)
1002 up
->port
.ignore_status_mask
|= UART_LSR_DR
;
1005 * CTS flow control flag and modem status interrupts, disable
1008 up
->ier
&= ~UART_IER_MSI
;
1009 if (UART_ENABLE_MS(&up
->port
, termios
->c_cflag
))
1010 up
->ier
|= UART_IER_MSI
;
1012 serial_out(up
, UART_IER
, up
->ier
);
1014 if (termios
->c_cflag
& CRTSCTS
)
1015 up
->mcr
|= UART_MCR_AFE
| UART_MCR_RTS
;
1017 up
->mcr
&= ~UART_MCR_AFE
;
1019 serial_out(up
, UART_LCR
, cval
| UART_LCR_DLAB
); /* set DLAB */
1020 serial_out(up
, UART_DLL
, quot
& 0xff); /* LS of divisor */
1021 serial_out(up
, UART_DLM
, quot
>> 8); /* MS of divisor */
1022 serial_out(up
, UART_LCR
, cval
); /* reset DLAB */
1023 serial_out(up
, UART_MUL
, mul
); /* set MUL */
1024 serial_out(up
, UART_PS
, ps
); /* set PS */
1025 up
->lcr
= cval
; /* Save LCR */
1026 serial_hsu_set_mctrl(&up
->port
, up
->port
.mctrl
);
1027 serial_out(up
, UART_FCR
, fcr
);
1028 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
1032 serial_hsu_pm(struct uart_port
*port
, unsigned int state
,
1033 unsigned int oldstate
)
1037 static void serial_hsu_release_port(struct uart_port
*port
)
1041 static int serial_hsu_request_port(struct uart_port
*port
)
1046 static void serial_hsu_config_port(struct uart_port
*port
, int flags
)
1048 struct uart_hsu_port
*up
=
1049 container_of(port
, struct uart_hsu_port
, port
);
1050 up
->port
.type
= PORT_MFD
;
1054 serial_hsu_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1056 /* We don't want the core code to modify any port params */
1061 serial_hsu_type(struct uart_port
*port
)
1063 struct uart_hsu_port
*up
=
1064 container_of(port
, struct uart_hsu_port
, port
);
1068 /* Mainly for uart console use */
1069 static struct uart_hsu_port
*serial_hsu_ports
[3];
1070 static struct uart_driver serial_hsu_reg
;
1072 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1074 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1076 /* Wait for transmitter & holding register to empty */
1077 static inline void wait_for_xmitr(struct uart_hsu_port
*up
)
1079 unsigned int status
, tmout
= 1000;
1081 /* Wait up to 1ms for the character to be sent. */
1083 status
= serial_in(up
, UART_LSR
);
1085 if (status
& UART_LSR_BI
)
1086 up
->lsr_break_flag
= UART_LSR_BI
;
1091 } while (!(status
& BOTH_EMPTY
));
1093 /* Wait up to 1s for flow control if necessary */
1094 if (up
->port
.flags
& UPF_CONS_FLOW
) {
1097 ((serial_in(up
, UART_MSR
) & UART_MSR_CTS
) == 0))
1102 static void serial_hsu_console_putchar(struct uart_port
*port
, int ch
)
1104 struct uart_hsu_port
*up
=
1105 container_of(port
, struct uart_hsu_port
, port
);
1108 serial_out(up
, UART_TX
, ch
);
1112 * Print a string to the serial port trying not to disturb
1113 * any possible real use of the port...
1115 * The console_lock must be held when we get here.
1118 serial_hsu_console_write(struct console
*co
, const char *s
, unsigned int count
)
1120 struct uart_hsu_port
*up
= serial_hsu_ports
[co
->index
];
1121 unsigned long flags
;
1125 local_irq_save(flags
);
1128 else if (oops_in_progress
) {
1129 locked
= spin_trylock(&up
->port
.lock
);
1131 spin_lock(&up
->port
.lock
);
1133 /* First save the IER then disable the interrupts */
1134 ier
= serial_in(up
, UART_IER
);
1135 serial_out(up
, UART_IER
, 0);
1137 uart_console_write(&up
->port
, s
, count
, serial_hsu_console_putchar
);
1140 * Finally, wait for transmitter to become empty
1141 * and restore the IER
1144 serial_out(up
, UART_IER
, ier
);
1147 spin_unlock(&up
->port
.lock
);
1148 local_irq_restore(flags
);
1151 static struct console serial_hsu_console
;
1154 serial_hsu_console_setup(struct console
*co
, char *options
)
1156 struct uart_hsu_port
*up
;
1163 if (co
->index
== -1 || co
->index
>= serial_hsu_reg
.nr
)
1165 up
= serial_hsu_ports
[co
->index
];
1170 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1172 ret
= uart_set_options(&up
->port
, co
, baud
, parity
, bits
, flow
);
1177 static struct console serial_hsu_console
= {
1179 .write
= serial_hsu_console_write
,
1180 .device
= uart_console_device
,
1181 .setup
= serial_hsu_console_setup
,
1182 .flags
= CON_PRINTBUFFER
,
1184 .data
= &serial_hsu_reg
,
1188 struct uart_ops serial_hsu_pops
= {
1189 .tx_empty
= serial_hsu_tx_empty
,
1190 .set_mctrl
= serial_hsu_set_mctrl
,
1191 .get_mctrl
= serial_hsu_get_mctrl
,
1192 .stop_tx
= serial_hsu_stop_tx
,
1193 .start_tx
= serial_hsu_start_tx
,
1194 .stop_rx
= serial_hsu_stop_rx
,
1195 .enable_ms
= serial_hsu_enable_ms
,
1196 .break_ctl
= serial_hsu_break_ctl
,
1197 .startup
= serial_hsu_startup
,
1198 .shutdown
= serial_hsu_shutdown
,
1199 .set_termios
= serial_hsu_set_termios
,
1200 .pm
= serial_hsu_pm
,
1201 .type
= serial_hsu_type
,
1202 .release_port
= serial_hsu_release_port
,
1203 .request_port
= serial_hsu_request_port
,
1204 .config_port
= serial_hsu_config_port
,
1205 .verify_port
= serial_hsu_verify_port
,
1208 static struct uart_driver serial_hsu_reg
= {
1209 .owner
= THIS_MODULE
,
1210 .driver_name
= "MFD serial",
1211 .dev_name
= "ttyMFD",
1218 static int serial_hsu_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1220 void *priv
= pci_get_drvdata(pdev
);
1221 struct uart_hsu_port
*up
;
1223 /* Make sure this is not the internal dma controller */
1224 if (priv
&& (pdev
->device
!= 0x081E)) {
1226 uart_suspend_port(&serial_hsu_reg
, &up
->port
);
1229 pci_save_state(pdev
);
1230 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1234 static int serial_hsu_resume(struct pci_dev
*pdev
)
1236 void *priv
= pci_get_drvdata(pdev
);
1237 struct uart_hsu_port
*up
;
1240 pci_set_power_state(pdev
, PCI_D0
);
1241 pci_restore_state(pdev
);
1243 ret
= pci_enable_device(pdev
);
1245 dev_warn(&pdev
->dev
,
1246 "HSU: can't re-enable device, try to continue\n");
1248 if (priv
&& (pdev
->device
!= 0x081E)) {
1250 uart_resume_port(&serial_hsu_reg
, &up
->port
);
1255 #define serial_hsu_suspend NULL
1256 #define serial_hsu_resume NULL
1259 /* temp global pointer before we settle down on using one or four PCI dev */
1260 static struct hsu_port
*phsu
;
1262 static int serial_hsu_probe(struct pci_dev
*pdev
,
1263 const struct pci_device_id
*ent
)
1265 struct uart_hsu_port
*uport
;
1268 printk(KERN_INFO
"HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1269 pdev
->vendor
, pdev
->device
);
1271 switch (pdev
->device
) {
1282 /* internal DMA controller */
1286 dev_err(&pdev
->dev
, "HSU: out of index!");
1290 ret
= pci_enable_device(pdev
);
1295 /* DMA controller */
1296 ret
= request_irq(pdev
->irq
, dma_irq
, 0, "hsu_dma", phsu
);
1298 dev_err(&pdev
->dev
, "can not get IRQ\n");
1301 pci_set_drvdata(pdev
, phsu
);
1304 uport
= &phsu
->port
[index
];
1305 uport
->port
.irq
= pdev
->irq
;
1306 uport
->port
.dev
= &pdev
->dev
;
1307 uport
->dev
= &pdev
->dev
;
1309 ret
= request_irq(pdev
->irq
, port_irq
, 0, uport
->name
, uport
);
1311 dev_err(&pdev
->dev
, "can not get IRQ\n");
1314 uart_add_one_port(&serial_hsu_reg
, &uport
->port
);
1316 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1318 register_console(&serial_hsu_console
);
1319 uport
->port
.cons
= &serial_hsu_console
;
1322 pci_set_drvdata(pdev
, uport
);
1328 pci_disable_device(pdev
);
1332 static void hsu_dma_rx_timeout(unsigned long data
)
1334 struct hsu_dma_chan
*chan
= (void *)data
;
1335 struct uart_hsu_port
*up
= chan
->uport
;
1336 struct hsu_dma_buffer
*dbuf
= &up
->rxbuf
;
1338 unsigned long flags
;
1340 spin_lock_irqsave(&up
->port
.lock
, flags
);
1342 count
= chan_readl(chan
, HSU_CH_D0SAR
) - dbuf
->dma_addr
;
1345 mod_timer(&chan
->rx_timer
, jiffies
+ HSU_DMA_TIMEOUT_CHECK_FREQ
);
1351 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
1354 static void hsu_global_init(void)
1356 struct hsu_port
*hsu
;
1357 struct uart_hsu_port
*uport
;
1358 struct hsu_dma_chan
*dchan
;
1361 hsu
= kzalloc(sizeof(struct hsu_port
), GFP_KERNEL
);
1365 /* Get basic io resource and map it */
1366 hsu
->paddr
= 0xffa28000;
1367 hsu
->iolen
= 0x1000;
1369 if (!(request_mem_region(hsu
->paddr
, hsu
->iolen
, "HSU global")))
1370 pr_warning("HSU: error in request mem region\n");
1372 hsu
->reg
= ioremap_nocache((unsigned long)hsu
->paddr
, hsu
->iolen
);
1374 pr_err("HSU: error in ioremap\n");
1376 goto err_free_region
;
1379 /* Initialise the 3 UART ports */
1381 for (i
= 0; i
< 3; i
++) {
1382 uport
->port
.type
= PORT_MFD
;
1383 uport
->port
.iotype
= UPIO_MEM
;
1384 uport
->port
.mapbase
= (resource_size_t
)hsu
->paddr
1385 + HSU_PORT_REG_OFFSET
1386 + i
* HSU_PORT_REG_LENGTH
;
1387 uport
->port
.membase
= hsu
->reg
+ HSU_PORT_REG_OFFSET
1388 + i
* HSU_PORT_REG_LENGTH
;
1390 sprintf(uport
->name
, "hsu_port%d", i
);
1391 uport
->port
.fifosize
= 64;
1392 uport
->port
.ops
= &serial_hsu_pops
;
1393 uport
->port
.line
= i
;
1394 uport
->port
.flags
= UPF_IOREMAP
;
1395 /* set the scalable maxim support rate to 2746800 bps */
1396 uport
->port
.uartclk
= 115200 * 24 * 16;
1399 uport
->txc
= &hsu
->chans
[i
* 2];
1400 uport
->rxc
= &hsu
->chans
[i
* 2 + 1];
1402 serial_hsu_ports
[i
] = uport
;
1407 /* Initialise 6 dma channels */
1409 for (i
= 0; i
< 6; i
++) {
1411 dchan
->dirt
= (i
& 0x1) ? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
1412 dchan
->uport
= &hsu
->port
[i
/2];
1413 dchan
->reg
= hsu
->reg
+ HSU_DMA_CHANS_REG_OFFSET
+
1414 i
* HSU_DMA_CHANS_REG_LENGTH
;
1416 /* Work around for RX */
1417 if (dchan
->dirt
== DMA_FROM_DEVICE
) {
1418 init_timer(&dchan
->rx_timer
);
1419 dchan
->rx_timer
.function
= hsu_dma_rx_timeout
;
1420 dchan
->rx_timer
.data
= (unsigned long)dchan
;
1427 hsu_debugfs_init(hsu
);
1431 release_mem_region(hsu
->paddr
, hsu
->iolen
);
1436 static void serial_hsu_remove(struct pci_dev
*pdev
)
1438 struct hsu_port
*hsu
;
1441 hsu
= pci_get_drvdata(pdev
);
1445 for (i
= 0; i
< 3; i
++)
1446 uart_remove_one_port(&serial_hsu_reg
, &hsu
->port
[i
].port
);
1448 pci_set_drvdata(pdev
, NULL
);
1449 free_irq(hsu
->irq
, hsu
);
1450 pci_disable_device(pdev
);
1453 /* First 3 are UART ports, and the 4th is the DMA */
1454 static const struct pci_device_id pci_ids
[] __devinitdata
= {
1455 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081B) },
1456 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081C) },
1457 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081D) },
1458 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081E) },
1462 static struct pci_driver hsu_pci_driver
= {
1463 .name
= "HSU serial",
1464 .id_table
= pci_ids
,
1465 .probe
= serial_hsu_probe
,
1466 .remove
= __devexit_p(serial_hsu_remove
),
1467 .suspend
= serial_hsu_suspend
,
1468 .resume
= serial_hsu_resume
,
1471 static int __init
hsu_pci_init(void)
1477 ret
= uart_register_driver(&serial_hsu_reg
);
1481 return pci_register_driver(&hsu_pci_driver
);
1484 static void __exit
hsu_pci_exit(void)
1486 pci_unregister_driver(&hsu_pci_driver
);
1487 uart_unregister_driver(&serial_hsu_reg
);
1489 hsu_debugfs_remove(phsu
);
1494 module_init(hsu_pci_init
);
1495 module_exit(hsu_pci_exit
);
1497 MODULE_LICENSE("GPL v2");
1498 MODULE_ALIAS("platform:medfield-hsu");