arch/mips/wrppmc/setup.c

   1 /*
   2  * setup.c: Setup pointers to hardware dependent routines.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org)
   9  * Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com>
  10  */
  11 #include <linux/init.h>
  12 #include <linux/string.h>
  13 #include <linux/kernel.h>
  14 #include <linux/pm.h>
  15
  16 #include <asm/io.h>
  17 #include <asm/bootinfo.h>
  18 #include <asm/reboot.h>
  19 #include <asm/time.h>
  20 #include <asm/gt64120.h>
  21
  22 unsigned long gt64120_base = KSEG1ADDR(0x14000000);
  23
  24 #ifdef WRPPMC_EARLY_DEBUG
  25
  26 static volatile unsigned char * wrppmc_led = \
  27         (volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE);
  28
  29 /*
  30  * PPMC LED control register:
  31  * -) bit[0] controls DS1 LED (1 - OFF, 0 - ON)
  32  * -) bit[1] controls DS2 LED (1 - OFF, 0 - ON)
  33  * -) bit[2] controls DS4 LED (1 - OFF, 0 - ON)
  34  */
  35 void wrppmc_led_on(int mask)
  36 {
  37         unsigned char value = *wrppmc_led;
  38
  39         value &= (0xF8 | mask);
  40         *wrppmc_led = value;
  41 }
  42
  43 /* If mask = 0, turn off all LEDs */
  44 void wrppmc_led_off(int mask)
  45 {
  46         unsigned char value = *wrppmc_led;
  47
  48         value |= (0x7 & mask);
  49         *wrppmc_led = value;
  50 }
  51
  52 /*
  53  * We assume that bootloader has initialized UART16550 correctly
  54  */
  55 void __init wrppmc_early_putc(char ch)
  56 {
  57         static volatile unsigned char *wrppmc_uart = \
  58                 (volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE);
  59         unsigned char value;
  60
  61         /* Wait until Transmit-Holding-Register is empty */
  62         while (1) {
  63                 value = *(wrppmc_uart + 5);
  64                 if (value & 0x20)
  65                         break;
  66         }
  67
  68         *wrppmc_uart = ch;
  69 }
  70
  71 void __init wrppmc_early_printk(const char *fmt, ...)
  72 {
  73         static char pbuf[256] = {'\0', };
  74         char *ch = pbuf;
  75         va_list args;
  76         unsigned int i;
  77
  78         memset(pbuf, 0, 256);
  79         va_start(args, fmt);
  80         i = vsprintf(pbuf, fmt, args);
  81         va_end(args);
  82
  83         /* Print the string */
  84         while (*ch != '\0') {
  85                 wrppmc_early_putc(*ch);
  86                 /* if print '\n', also print '\r' */
  87                 if (*ch++ == '\n')
  88                         wrppmc_early_putc('\r');
  89         }
  90 }
  91 #endif /* WRPPMC_EARLY_DEBUG */
  92
  93 void __init prom_free_prom_memory(void)
  94 {
  95 }
  96
  97 void __init plat_mem_setup(void)
  98 {
  99         extern void wrppmc_machine_restart(char *command);
 100         extern void wrppmc_machine_halt(void);
 101
 102         _machine_restart = wrppmc_machine_restart;
 103         _machine_halt    = wrppmc_machine_halt;
 104         pm_power_off     = wrppmc_machine_halt;
 105
 106         /* This makes the operations of 'in/out[bwl]' to the
 107          * physical address ( < KSEG0) can work via KSEG1
 108          */
 109         set_io_port_base(KSEG1);
 110 }
 111
 112 const char *get_system_type(void)
 113 {
 114         return "Wind River PPMC (GT64120)";
 115 }
 116
 117 /*
 118  * Initializes basic routines and structures pointers, memory size (as
 119  * given by the bios and saves the command line.
 120  */
 121 void __init prom_init(void)
 122 {
 123         add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
 124         add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);
 125
 126         wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n",
 127                         WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE));
 128 }