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1 Booting the Linux/ppc kernel without Open Firmware
2 --------------------------------------------------
4 (c) 2005 Benjamin Herrenschmidt <benh at kernel.crashing.org>,
5 IBM Corp.
6 (c) 2005 Becky Bruce <becky.bruce at freescale.com>,
7 Freescale Semiconductor, FSL SOC and 32-bit additions
8 (c) 2006 MontaVista Software, Inc.
9 Flash chip node definition
11 Table of Contents
12 =================
14 I - Introduction
15 1) Entry point for arch/powerpc
16 2) Board support
18 II - The DT block format
19 1) Header
20 2) Device tree generalities
21 3) Device tree "structure" block
22 4) Device tree "strings" block
24 III - Required content of the device tree
25 1) Note about cells and address representation
26 2) Note about "compatible" properties
27 3) Note about "name" properties
28 4) Note about node and property names and character set
29 5) Required nodes and properties
30 a) The root node
31 b) The /cpus node
32 c) The /cpus/* nodes
33 d) the /memory node(s)
34 e) The /chosen node
35 f) the /soc<SOCname> node
37 IV - "dtc", the device tree compiler
39 V - Recommendations for a bootloader
41 VI - System-on-a-chip devices and nodes
42 1) Defining child nodes of an SOC
43 2) Representing devices without a current OF specification
44 a) MDIO IO device
45 b) Gianfar-compatible ethernet nodes
46 c) PHY nodes
47 d) Interrupt controllers
48 e) I2C
49 f) Freescale SOC USB controllers
50 g) Freescale SOC SEC Security Engines
51 h) Board Control and Status (BCSR)
52 i) Freescale QUICC Engine module (QE)
53 j) CFI or JEDEC memory-mapped NOR flash
54 k) Global Utilities Block
55 l) Freescale Communications Processor Module
56 m) Chipselect/Local Bus
57 n) 4xx/Axon EMAC ethernet nodes
58 o) Xilinx IP cores
59 p) Freescale Synchronous Serial Interface
60 q) USB EHCI controllers
61 r) Freescale Display Interface Unit
62 s) Freescale on board FPGA
63 t) Freescael MSI interrupt controller
64 u) Freescale General-purpose Timers Module
66 VII - Marvell Discovery mv64[345]6x System Controller chips
67 1) The /system-controller node
68 2) Child nodes of /system-controller
69 a) Marvell Discovery MDIO bus
70 b) Marvell Discovery ethernet controller
71 c) Marvell Discovery PHY nodes
72 d) Marvell Discovery SDMA nodes
73 e) Marvell Discovery BRG nodes
74 f) Marvell Discovery CUNIT nodes
75 g) Marvell Discovery MPSCROUTING nodes
76 h) Marvell Discovery MPSCINTR nodes
77 i) Marvell Discovery MPSC nodes
78 j) Marvell Discovery Watch Dog Timer nodes
79 k) Marvell Discovery I2C nodes
80 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
81 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
82 n) Marvell Discovery GPP (General Purpose Pins) nodes
83 o) Marvell Discovery PCI host bridge node
84 p) Marvell Discovery CPU Error nodes
85 q) Marvell Discovery SRAM Controller nodes
86 r) Marvell Discovery PCI Error Handler nodes
87 s) Marvell Discovery Memory Controller nodes
89 VIII - Specifying interrupt information for devices
90 1) interrupts property
91 2) interrupt-parent property
92 3) OpenPIC Interrupt Controllers
93 4) ISA Interrupt Controllers
95 VIII - Specifying GPIO information for devices
96 1) gpios property
97 2) gpio-controller nodes
99 Appendix A - Sample SOC node for MPC8540
102 Revision Information
103 ====================
105 May 18, 2005: Rev 0.1 - Initial draft, no chapter III yet.
107 May 19, 2005: Rev 0.2 - Add chapter III and bits & pieces here or
108 clarifies the fact that a lot of things are
109 optional, the kernel only requires a very
110 small device tree, though it is encouraged
111 to provide an as complete one as possible.
113 May 24, 2005: Rev 0.3 - Precise that DT block has to be in RAM
114 - Misc fixes
115 - Define version 3 and new format version 16
116 for the DT block (version 16 needs kernel
117 patches, will be fwd separately).
118 String block now has a size, and full path
119 is replaced by unit name for more
120 compactness.
121 linux,phandle is made optional, only nodes
122 that are referenced by other nodes need it.
123 "name" property is now automatically
124 deduced from the unit name
126 June 1, 2005: Rev 0.4 - Correct confusion between OF_DT_END and
127 OF_DT_END_NODE in structure definition.
128 - Change version 16 format to always align
129 property data to 4 bytes. Since tokens are
130 already aligned, that means no specific
131 required alignment between property size
132 and property data. The old style variable
133 alignment would make it impossible to do
134 "simple" insertion of properties using
135 memmove (thanks Milton for
136 noticing). Updated kernel patch as well
137 - Correct a few more alignment constraints
138 - Add a chapter about the device-tree
139 compiler and the textural representation of
140 the tree that can be "compiled" by dtc.
142 November 21, 2005: Rev 0.5
143 - Additions/generalizations for 32-bit
144 - Changed to reflect the new arch/powerpc
145 structure
146 - Added chapter VI
149 ToDo:
150 - Add some definitions of interrupt tree (simple/complex)
151 - Add some definitions for PCI host bridges
152 - Add some common address format examples
153 - Add definitions for standard properties and "compatible"
154 names for cells that are not already defined by the existing
155 OF spec.
156 - Compare FSL SOC use of PCI to standard and make sure no new
157 node definition required.
158 - Add more information about node definitions for SOC devices
159 that currently have no standard, like the FSL CPM.
162 I - Introduction
163 ================
165 During the recent development of the Linux/ppc64 kernel, and more
166 specifically, the addition of new platform types outside of the old
167 IBM pSeries/iSeries pair, it was decided to enforce some strict rules
168 regarding the kernel entry and bootloader <-> kernel interfaces, in
169 order to avoid the degeneration that had become the ppc32 kernel entry
170 point and the way a new platform should be added to the kernel. The
171 legacy iSeries platform breaks those rules as it predates this scheme,
172 but no new board support will be accepted in the main tree that
173 doesn't follows them properly. In addition, since the advent of the
174 arch/powerpc merged architecture for ppc32 and ppc64, new 32-bit
175 platforms and 32-bit platforms which move into arch/powerpc will be
176 required to use these rules as well.
178 The main requirement that will be defined in more detail below is
179 the presence of a device-tree whose format is defined after Open
180 Firmware specification. However, in order to make life easier
181 to embedded board vendors, the kernel doesn't require the device-tree
182 to represent every device in the system and only requires some nodes
183 and properties to be present. This will be described in detail in
184 section III, but, for example, the kernel does not require you to
185 create a node for every PCI device in the system. It is a requirement
186 to have a node for PCI host bridges in order to provide interrupt
187 routing informations and memory/IO ranges, among others. It is also
188 recommended to define nodes for on chip devices and other busses that
189 don't specifically fit in an existing OF specification. This creates a
190 great flexibility in the way the kernel can then probe those and match
191 drivers to device, without having to hard code all sorts of tables. It
192 also makes it more flexible for board vendors to do minor hardware
193 upgrades without significantly impacting the kernel code or cluttering
194 it with special cases.
197 1) Entry point for arch/powerpc
198 -------------------------------
200 There is one and one single entry point to the kernel, at the start
201 of the kernel image. That entry point supports two calling
202 conventions:
204 a) Boot from Open Firmware. If your firmware is compatible
205 with Open Firmware (IEEE 1275) or provides an OF compatible
206 client interface API (support for "interpret" callback of
207 forth words isn't required), you can enter the kernel with:
209 r5 : OF callback pointer as defined by IEEE 1275
210 bindings to powerpc. Only the 32-bit client interface
211 is currently supported
213 r3, r4 : address & length of an initrd if any or 0
215 The MMU is either on or off; the kernel will run the
216 trampoline located in arch/powerpc/kernel/prom_init.c to
217 extract the device-tree and other information from open
218 firmware and build a flattened device-tree as described
219 in b). prom_init() will then re-enter the kernel using
220 the second method. This trampoline code runs in the
221 context of the firmware, which is supposed to handle all
222 exceptions during that time.
224 b) Direct entry with a flattened device-tree block. This entry
225 point is called by a) after the OF trampoline and can also be
226 called directly by a bootloader that does not support the Open
227 Firmware client interface. It is also used by "kexec" to
228 implement "hot" booting of a new kernel from a previous
229 running one. This method is what I will describe in more
230 details in this document, as method a) is simply standard Open
231 Firmware, and thus should be implemented according to the
232 various standard documents defining it and its binding to the
233 PowerPC platform. The entry point definition then becomes:
235 r3 : physical pointer to the device-tree block
236 (defined in chapter II) in RAM
238 r4 : physical pointer to the kernel itself. This is
239 used by the assembly code to properly disable the MMU
240 in case you are entering the kernel with MMU enabled
241 and a non-1:1 mapping.
243 r5 : NULL (as to differentiate with method a)
245 Note about SMP entry: Either your firmware puts your other
246 CPUs in some sleep loop or spin loop in ROM where you can get
247 them out via a soft reset or some other means, in which case
248 you don't need to care, or you'll have to enter the kernel
249 with all CPUs. The way to do that with method b) will be
250 described in a later revision of this document.
253 2) Board support
254 ----------------
256 64-bit kernels:
258 Board supports (platforms) are not exclusive config options. An
259 arbitrary set of board supports can be built in a single kernel
260 image. The kernel will "know" what set of functions to use for a
261 given platform based on the content of the device-tree. Thus, you
262 should:
264 a) add your platform support as a _boolean_ option in
265 arch/powerpc/Kconfig, following the example of PPC_PSERIES,
266 PPC_PMAC and PPC_MAPLE. The later is probably a good
267 example of a board support to start from.
269 b) create your main platform file as
270 "arch/powerpc/platforms/myplatform/myboard_setup.c" and add it
271 to the Makefile under the condition of your CONFIG_
272 option. This file will define a structure of type "ppc_md"
273 containing the various callbacks that the generic code will
274 use to get to your platform specific code
276 c) Add a reference to your "ppc_md" structure in the
277 "machines" table in arch/powerpc/kernel/setup_64.c if you are
278 a 64-bit platform.
280 d) request and get assigned a platform number (see PLATFORM_*
281 constants in include/asm-powerpc/processor.h
283 32-bit embedded kernels:
285 Currently, board support is essentially an exclusive config option.
286 The kernel is configured for a single platform. Part of the reason
287 for this is to keep kernels on embedded systems small and efficient;
288 part of this is due to the fact the code is already that way. In the
289 future, a kernel may support multiple platforms, but only if the
290 platforms feature the same core architecture. A single kernel build
291 cannot support both configurations with Book E and configurations
292 with classic Powerpc architectures.
294 32-bit embedded platforms that are moved into arch/powerpc using a
295 flattened device tree should adopt the merged tree practice of
296 setting ppc_md up dynamically, even though the kernel is currently
297 built with support for only a single platform at a time. This allows
298 unification of the setup code, and will make it easier to go to a
299 multiple-platform-support model in the future.
301 NOTE: I believe the above will be true once Ben's done with the merge
302 of the boot sequences.... someone speak up if this is wrong!
304 To add a 32-bit embedded platform support, follow the instructions
305 for 64-bit platforms above, with the exception that the Kconfig
306 option should be set up such that the kernel builds exclusively for
307 the platform selected. The processor type for the platform should
308 enable another config option to select the specific board
309 supported.
311 NOTE: If Ben doesn't merge the setup files, may need to change this to
312 point to setup_32.c
315 I will describe later the boot process and various callbacks that
316 your platform should implement.
319 II - The DT block format
320 ========================
323 This chapter defines the actual format of the flattened device-tree
324 passed to the kernel. The actual content of it and kernel requirements
325 are described later. You can find example of code manipulating that
326 format in various places, including arch/powerpc/kernel/prom_init.c
327 which will generate a flattened device-tree from the Open Firmware
328 representation, or the fs2dt utility which is part of the kexec tools
329 which will generate one from a filesystem representation. It is
330 expected that a bootloader like uboot provides a bit more support,
331 that will be discussed later as well.
333 Note: The block has to be in main memory. It has to be accessible in
334 both real mode and virtual mode with no mapping other than main
335 memory. If you are writing a simple flash bootloader, it should copy
336 the block to RAM before passing it to the kernel.
339 1) Header
340 ---------
342 The kernel is entered with r3 pointing to an area of memory that is
343 roughly described in include/asm-powerpc/prom.h by the structure
344 boot_param_header:
346 struct boot_param_header {
347 u32 magic; /* magic word OF_DT_HEADER */
348 u32 totalsize; /* total size of DT block */
349 u32 off_dt_struct; /* offset to structure */
350 u32 off_dt_strings; /* offset to strings */
351 u32 off_mem_rsvmap; /* offset to memory reserve map
352 */
353 u32 version; /* format version */
354 u32 last_comp_version; /* last compatible version */
356 /* version 2 fields below */
357 u32 boot_cpuid_phys; /* Which physical CPU id we're
358 booting on */
359 /* version 3 fields below */
360 u32 size_dt_strings; /* size of the strings block */
362 /* version 17 fields below */
363 u32 size_dt_struct; /* size of the DT structure block */
364 };
366 Along with the constants:
368 /* Definitions used by the flattened device tree */
369 #define OF_DT_HEADER 0xd00dfeed /* 4: version,
370 4: total size */
371 #define OF_DT_BEGIN_NODE 0x1 /* Start node: full name
372 */
373 #define OF_DT_END_NODE 0x2 /* End node */
374 #define OF_DT_PROP 0x3 /* Property: name off,
375 size, content */
376 #define OF_DT_END 0x9
378 All values in this header are in big endian format, the various
379 fields in this header are defined more precisely below. All
380 "offset" values are in bytes from the start of the header; that is
381 from the value of r3.
383 - magic
385 This is a magic value that "marks" the beginning of the
386 device-tree block header. It contains the value 0xd00dfeed and is
387 defined by the constant OF_DT_HEADER
389 - totalsize
391 This is the total size of the DT block including the header. The
392 "DT" block should enclose all data structures defined in this
393 chapter (who are pointed to by offsets in this header). That is,
394 the device-tree structure, strings, and the memory reserve map.
396 - off_dt_struct
398 This is an offset from the beginning of the header to the start
399 of the "structure" part the device tree. (see 2) device tree)
401 - off_dt_strings
403 This is an offset from the beginning of the header to the start
404 of the "strings" part of the device-tree
406 - off_mem_rsvmap
408 This is an offset from the beginning of the header to the start
409 of the reserved memory map. This map is a list of pairs of 64-
410 bit integers. Each pair is a physical address and a size. The
411 list is terminated by an entry of size 0. This map provides the
412 kernel with a list of physical memory areas that are "reserved"
413 and thus not to be used for memory allocations, especially during
414 early initialization. The kernel needs to allocate memory during
415 boot for things like un-flattening the device-tree, allocating an
416 MMU hash table, etc... Those allocations must be done in such a
417 way to avoid overriding critical things like, on Open Firmware
418 capable machines, the RTAS instance, or on some pSeries, the TCE
419 tables used for the iommu. Typically, the reserve map should
420 contain _at least_ this DT block itself (header,total_size). If
421 you are passing an initrd to the kernel, you should reserve it as
422 well. You do not need to reserve the kernel image itself. The map
423 should be 64-bit aligned.
425 - version
427 This is the version of this structure. Version 1 stops
428 here. Version 2 adds an additional field boot_cpuid_phys.
429 Version 3 adds the size of the strings block, allowing the kernel
430 to reallocate it easily at boot and free up the unused flattened
431 structure after expansion. Version 16 introduces a new more
432 "compact" format for the tree itself that is however not backward
433 compatible. Version 17 adds an additional field, size_dt_struct,
434 allowing it to be reallocated or moved more easily (this is
435 particularly useful for bootloaders which need to make
436 adjustments to a device tree based on probed information). You
437 should always generate a structure of the highest version defined
438 at the time of your implementation. Currently that is version 17,
439 unless you explicitly aim at being backward compatible.
441 - last_comp_version
443 Last compatible version. This indicates down to what version of
444 the DT block you are backward compatible. For example, version 2
445 is backward compatible with version 1 (that is, a kernel build
446 for version 1 will be able to boot with a version 2 format). You
447 should put a 1 in this field if you generate a device tree of
448 version 1 to 3, or 16 if you generate a tree of version 16 or 17
449 using the new unit name format.
451 - boot_cpuid_phys
453 This field only exist on version 2 headers. It indicate which
454 physical CPU ID is calling the kernel entry point. This is used,
455 among others, by kexec. If you are on an SMP system, this value
456 should match the content of the "reg" property of the CPU node in
457 the device-tree corresponding to the CPU calling the kernel entry
458 point (see further chapters for more informations on the required
459 device-tree contents)
461 - size_dt_strings
463 This field only exists on version 3 and later headers. It
464 gives the size of the "strings" section of the device tree (which
465 starts at the offset given by off_dt_strings).
467 - size_dt_struct
469 This field only exists on version 17 and later headers. It gives
470 the size of the "structure" section of the device tree (which
471 starts at the offset given by off_dt_struct).
473 So the typical layout of a DT block (though the various parts don't
474 need to be in that order) looks like this (addresses go from top to
475 bottom):
478 ------------------------------
479 r3 -> | struct boot_param_header |
480 ------------------------------
481 | (alignment gap) (*) |
482 ------------------------------
483 | memory reserve map |
484 ------------------------------
485 | (alignment gap) |
486 ------------------------------
487 | |
488 | device-tree structure |
489 | |
490 ------------------------------
491 | (alignment gap) |
492 ------------------------------
493 | |
494 | device-tree strings |
495 | |
496 -----> ------------------------------
497 |
498 |
499 --- (r3 + totalsize)
501 (*) The alignment gaps are not necessarily present; their presence
502 and size are dependent on the various alignment requirements of
503 the individual data blocks.
506 2) Device tree generalities
507 ---------------------------
509 This device-tree itself is separated in two different blocks, a
510 structure block and a strings block. Both need to be aligned to a 4
511 byte boundary.
513 First, let's quickly describe the device-tree concept before detailing
514 the storage format. This chapter does _not_ describe the detail of the
515 required types of nodes & properties for the kernel, this is done
516 later in chapter III.
518 The device-tree layout is strongly inherited from the definition of
519 the Open Firmware IEEE 1275 device-tree. It's basically a tree of
520 nodes, each node having two or more named properties. A property can
521 have a value or not.
523 It is a tree, so each node has one and only one parent except for the
524 root node who has no parent.
526 A node has 2 names. The actual node name is generally contained in a
527 property of type "name" in the node property list whose value is a
528 zero terminated string and is mandatory for version 1 to 3 of the
529 format definition (as it is in Open Firmware). Version 16 makes it
530 optional as it can generate it from the unit name defined below.
532 There is also a "unit name" that is used to differentiate nodes with
533 the same name at the same level, it is usually made of the node
534 names, the "@" sign, and a "unit address", which definition is
535 specific to the bus type the node sits on.
537 The unit name doesn't exist as a property per-se but is included in
538 the device-tree structure. It is typically used to represent "path" in
539 the device-tree. More details about the actual format of these will be
540 below.
542 The kernel powerpc generic code does not make any formal use of the
543 unit address (though some board support code may do) so the only real
544 requirement here for the unit address is to ensure uniqueness of
545 the node unit name at a given level of the tree. Nodes with no notion
546 of address and no possible sibling of the same name (like /memory or
547 /cpus) may omit the unit address in the context of this specification,
548 or use the "@0" default unit address. The unit name is used to define
549 a node "full path", which is the concatenation of all parent node
550 unit names separated with "/".
552 The root node doesn't have a defined name, and isn't required to have
553 a name property either if you are using version 3 or earlier of the
554 format. It also has no unit address (no @ symbol followed by a unit
555 address). The root node unit name is thus an empty string. The full
556 path to the root node is "/".
558 Every node which actually represents an actual device (that is, a node
559 which isn't only a virtual "container" for more nodes, like "/cpus"
560 is) is also required to have a "device_type" property indicating the
561 type of node .
563 Finally, every node that can be referenced from a property in another
564 node is required to have a "linux,phandle" property. Real open
565 firmware implementations provide a unique "phandle" value for every
566 node that the "prom_init()" trampoline code turns into
567 "linux,phandle" properties. However, this is made optional if the
568 flattened device tree is used directly. An example of a node
569 referencing another node via "phandle" is when laying out the
570 interrupt tree which will be described in a further version of this
571 document.
573 This "linux, phandle" property is a 32-bit value that uniquely
574 identifies a node. You are free to use whatever values or system of
575 values, internal pointers, or whatever to generate these, the only
576 requirement is that every node for which you provide that property has
577 a unique value for it.
579 Here is an example of a simple device-tree. In this example, an "o"
580 designates a node followed by the node unit name. Properties are
581 presented with their name followed by their content. "content"
582 represents an ASCII string (zero terminated) value, while <content>
583 represents a 32-bit hexadecimal value. The various nodes in this
584 example will be discussed in a later chapter. At this point, it is
585 only meant to give you a idea of what a device-tree looks like. I have
586 purposefully kept the "name" and "linux,phandle" properties which
587 aren't necessary in order to give you a better idea of what the tree
588 looks like in practice.
590 / o device-tree
591 |- name = "device-tree"
592 |- model = "MyBoardName"
593 |- compatible = "MyBoardFamilyName"
594 |- #address-cells = <2>
595 |- #size-cells = <2>
596 |- linux,phandle = <0>
597 |
598 o cpus
599 | | - name = "cpus"
600 | | - linux,phandle = <1>
601 | | - #address-cells = <1>
602 | | - #size-cells = <0>
603 | |
604 | o PowerPC,970@0
605 | |- name = "PowerPC,970"
606 | |- device_type = "cpu"
607 | |- reg = <0>
608 | |- clock-frequency = <5f5e1000>
609 | |- 64-bit
610 | |- linux,phandle = <2>
611 |
612 o memory@0
613 | |- name = "memory"
614 | |- device_type = "memory"
615 | |- reg = <00000000 00000000 00000000 20000000>
616 | |- linux,phandle = <3>
617 |
618 o chosen
619 |- name = "chosen"
620 |- bootargs = "root=/dev/sda2"
621 |- linux,phandle = <4>
623 This tree is almost a minimal tree. It pretty much contains the
624 minimal set of required nodes and properties to boot a linux kernel;
625 that is, some basic model informations at the root, the CPUs, and the
626 physical memory layout. It also includes misc information passed
627 through /chosen, like in this example, the platform type (mandatory)
628 and the kernel command line arguments (optional).
630 The /cpus/PowerPC,970@0/64-bit property is an example of a
631 property without a value. All other properties have a value. The
632 significance of the #address-cells and #size-cells properties will be
633 explained in chapter IV which defines precisely the required nodes and
634 properties and their content.
637 3) Device tree "structure" block
639 The structure of the device tree is a linearized tree structure. The
640 "OF_DT_BEGIN_NODE" token starts a new node, and the "OF_DT_END_NODE"
641 ends that node definition. Child nodes are simply defined before
642 "OF_DT_END_NODE" (that is nodes within the node). A 'token' is a 32
643 bit value. The tree has to be "finished" with a OF_DT_END token
645 Here's the basic structure of a single node:
647 * token OF_DT_BEGIN_NODE (that is 0x00000001)
648 * for version 1 to 3, this is the node full path as a zero
649 terminated string, starting with "/". For version 16 and later,
650 this is the node unit name only (or an empty string for the
651 root node)
652 * [align gap to next 4 bytes boundary]
653 * for each property:
654 * token OF_DT_PROP (that is 0x00000003)
655 * 32-bit value of property value size in bytes (or 0 if no
656 value)
657 * 32-bit value of offset in string block of property name
658 * property value data if any
659 * [align gap to next 4 bytes boundary]
660 * [child nodes if any]
661 * token OF_DT_END_NODE (that is 0x00000002)
663 So the node content can be summarized as a start token, a full path,
664 a list of properties, a list of child nodes, and an end token. Every
665 child node is a full node structure itself as defined above.
667 NOTE: The above definition requires that all property definitions for
668 a particular node MUST precede any subnode definitions for that node.
669 Although the structure would not be ambiguous if properties and
670 subnodes were intermingled, the kernel parser requires that the
671 properties come first (up until at least 2.6.22). Any tools
672 manipulating a flattened tree must take care to preserve this
673 constraint.
675 4) Device tree "strings" block
677 In order to save space, property names, which are generally redundant,
678 are stored separately in the "strings" block. This block is simply the
679 whole bunch of zero terminated strings for all property names
680 concatenated together. The device-tree property definitions in the
681 structure block will contain offset values from the beginning of the
682 strings block.
685 III - Required content of the device tree
686 =========================================
688 WARNING: All "linux,*" properties defined in this document apply only
689 to a flattened device-tree. If your platform uses a real
690 implementation of Open Firmware or an implementation compatible with
691 the Open Firmware client interface, those properties will be created
692 by the trampoline code in the kernel's prom_init() file. For example,
693 that's where you'll have to add code to detect your board model and
694 set the platform number. However, when using the flattened device-tree
695 entry point, there is no prom_init() pass, and thus you have to
696 provide those properties yourself.
699 1) Note about cells and address representation
700 ----------------------------------------------
702 The general rule is documented in the various Open Firmware
703 documentations. If you choose to describe a bus with the device-tree
704 and there exist an OF bus binding, then you should follow the
705 specification. However, the kernel does not require every single
706 device or bus to be described by the device tree.
708 In general, the format of an address for a device is defined by the
709 parent bus type, based on the #address-cells and #size-cells
710 properties. Note that the parent's parent definitions of #address-cells
711 and #size-cells are not inhereted so every node with children must specify
712 them. The kernel requires the root node to have those properties defining
713 addresses format for devices directly mapped on the processor bus.
715 Those 2 properties define 'cells' for representing an address and a
716 size. A "cell" is a 32-bit number. For example, if both contain 2
717 like the example tree given above, then an address and a size are both
718 composed of 2 cells, and each is a 64-bit number (cells are
719 concatenated and expected to be in big endian format). Another example
720 is the way Apple firmware defines them, with 2 cells for an address
721 and one cell for a size. Most 32-bit implementations should define
722 #address-cells and #size-cells to 1, which represents a 32-bit value.
723 Some 32-bit processors allow for physical addresses greater than 32
724 bits; these processors should define #address-cells as 2.
726 "reg" properties are always a tuple of the type "address size" where
727 the number of cells of address and size is specified by the bus
728 #address-cells and #size-cells. When a bus supports various address
729 spaces and other flags relative to a given address allocation (like
730 prefetchable, etc...) those flags are usually added to the top level
731 bits of the physical address. For example, a PCI physical address is
732 made of 3 cells, the bottom two containing the actual address itself
733 while the top cell contains address space indication, flags, and pci
734 bus & device numbers.
736 For busses that support dynamic allocation, it's the accepted practice
737 to then not provide the address in "reg" (keep it 0) though while
738 providing a flag indicating the address is dynamically allocated, and
739 then, to provide a separate "assigned-addresses" property that
740 contains the fully allocated addresses. See the PCI OF bindings for
741 details.
743 In general, a simple bus with no address space bits and no dynamic
744 allocation is preferred if it reflects your hardware, as the existing
745 kernel address parsing functions will work out of the box. If you
746 define a bus type with a more complex address format, including things
747 like address space bits, you'll have to add a bus translator to the
748 prom_parse.c file of the recent kernels for your bus type.
750 The "reg" property only defines addresses and sizes (if #size-cells is
751 non-0) within a given bus. In order to translate addresses upward
752 (that is into parent bus addresses, and possibly into CPU physical
753 addresses), all busses must contain a "ranges" property. If the
754 "ranges" property is missing at a given level, it's assumed that
755 translation isn't possible, i.e., the registers are not visible on the
756 parent bus. The format of the "ranges" property for a bus is a list
757 of:
759 bus address, parent bus address, size
761 "bus address" is in the format of the bus this bus node is defining,
762 that is, for a PCI bridge, it would be a PCI address. Thus, (bus
763 address, size) defines a range of addresses for child devices. "parent
764 bus address" is in the format of the parent bus of this bus. For
765 example, for a PCI host controller, that would be a CPU address. For a
766 PCI<->ISA bridge, that would be a PCI address. It defines the base
767 address in the parent bus where the beginning of that range is mapped.
769 For a new 64-bit powerpc board, I recommend either the 2/2 format or
770 Apple's 2/1 format which is slightly more compact since sizes usually
771 fit in a single 32-bit word. New 32-bit powerpc boards should use a
772 1/1 format, unless the processor supports physical addresses greater
773 than 32-bits, in which case a 2/1 format is recommended.
775 Alternatively, the "ranges" property may be empty, indicating that the
776 registers are visible on the parent bus using an identity mapping
777 translation. In other words, the parent bus address space is the same
778 as the child bus address space.
780 2) Note about "compatible" properties
781 -------------------------------------
783 These properties are optional, but recommended in devices and the root
784 node. The format of a "compatible" property is a list of concatenated
785 zero terminated strings. They allow a device to express its
786 compatibility with a family of similar devices, in some cases,
787 allowing a single driver to match against several devices regardless
788 of their actual names.
790 3) Note about "name" properties
791 -------------------------------
793 While earlier users of Open Firmware like OldWorld macintoshes tended
794 to use the actual device name for the "name" property, it's nowadays
795 considered a good practice to use a name that is closer to the device
796 class (often equal to device_type). For example, nowadays, ethernet
797 controllers are named "ethernet", an additional "model" property
798 defining precisely the chip type/model, and "compatible" property
799 defining the family in case a single driver can driver more than one
800 of these chips. However, the kernel doesn't generally put any
801 restriction on the "name" property; it is simply considered good
802 practice to follow the standard and its evolutions as closely as
803 possible.
805 Note also that the new format version 16 makes the "name" property
806 optional. If it's absent for a node, then the node's unit name is then
807 used to reconstruct the name. That is, the part of the unit name
808 before the "@" sign is used (or the entire unit name if no "@" sign
809 is present).
811 4) Note about node and property names and character set
812 -------------------------------------------------------
814 While open firmware provides more flexible usage of 8859-1, this
815 specification enforces more strict rules. Nodes and properties should
816 be comprised only of ASCII characters 'a' to 'z', '0' to
817 '9', ',', '.', '_', '+', '#', '?', and '-'. Node names additionally
818 allow uppercase characters 'A' to 'Z' (property names should be
819 lowercase. The fact that vendors like Apple don't respect this rule is
820 irrelevant here). Additionally, node and property names should always
821 begin with a character in the range 'a' to 'z' (or 'A' to 'Z' for node
822 names).
824 The maximum number of characters for both nodes and property names
825 is 31. In the case of node names, this is only the leftmost part of
826 a unit name (the pure "name" property), it doesn't include the unit
827 address which can extend beyond that limit.
830 5) Required nodes and properties
831 --------------------------------
832 These are all that are currently required. However, it is strongly
833 recommended that you expose PCI host bridges as documented in the
834 PCI binding to open firmware, and your interrupt tree as documented
835 in OF interrupt tree specification.
837 a) The root node
839 The root node requires some properties to be present:
841 - model : this is your board name/model
842 - #address-cells : address representation for "root" devices
843 - #size-cells: the size representation for "root" devices
844 - device_type : This property shouldn't be necessary. However, if
845 you decide to create a device_type for your root node, make sure it
846 is _not_ "chrp" unless your platform is a pSeries or PAPR compliant
847 one for 64-bit, or a CHRP-type machine for 32-bit as this will
848 matched by the kernel this way.
850 Additionally, some recommended properties are:
852 - compatible : the board "family" generally finds its way here,
853 for example, if you have 2 board models with a similar layout,
854 that typically get driven by the same platform code in the
855 kernel, you would use a different "model" property but put a
856 value in "compatible". The kernel doesn't directly use that
857 value but it is generally useful.
859 The root node is also generally where you add additional properties
860 specific to your board like the serial number if any, that sort of
861 thing. It is recommended that if you add any "custom" property whose
862 name may clash with standard defined ones, you prefix them with your
863 vendor name and a comma.
865 b) The /cpus node
867 This node is the parent of all individual CPU nodes. It doesn't
868 have any specific requirements, though it's generally good practice
869 to have at least:
871 #address-cells = <00000001>
872 #size-cells = <00000000>
874 This defines that the "address" for a CPU is a single cell, and has
875 no meaningful size. This is not necessary but the kernel will assume
876 that format when reading the "reg" properties of a CPU node, see
877 below
879 c) The /cpus/* nodes
881 So under /cpus, you are supposed to create a node for every CPU on
882 the machine. There is no specific restriction on the name of the
883 CPU, though It's common practice to call it PowerPC,<name>. For
884 example, Apple uses PowerPC,G5 while IBM uses PowerPC,970FX.
886 Required properties:
888 - device_type : has to be "cpu"
889 - reg : This is the physical CPU number, it's a single 32-bit cell
890 and is also used as-is as the unit number for constructing the
891 unit name in the full path. For example, with 2 CPUs, you would
892 have the full path:
893 /cpus/PowerPC,970FX@0
894 /cpus/PowerPC,970FX@1
895 (unit addresses do not require leading zeroes)
896 - d-cache-block-size : one cell, L1 data cache block size in bytes (*)
897 - i-cache-block-size : one cell, L1 instruction cache block size in
898 bytes
899 - d-cache-size : one cell, size of L1 data cache in bytes
900 - i-cache-size : one cell, size of L1 instruction cache in bytes
902 (*) The cache "block" size is the size on which the cache management
903 instructions operate. Historically, this document used the cache
904 "line" size here which is incorrect. The kernel will prefer the cache
905 block size and will fallback to cache line size for backward
906 compatibility.
908 Recommended properties:
910 - timebase-frequency : a cell indicating the frequency of the
911 timebase in Hz. This is not directly used by the generic code,
912 but you are welcome to copy/paste the pSeries code for setting
913 the kernel timebase/decrementer calibration based on this
914 value.
915 - clock-frequency : a cell indicating the CPU core clock frequency
916 in Hz. A new property will be defined for 64-bit values, but if
917 your frequency is < 4Ghz, one cell is enough. Here as well as
918 for the above, the common code doesn't use that property, but
919 you are welcome to re-use the pSeries or Maple one. A future
920 kernel version might provide a common function for this.
921 - d-cache-line-size : one cell, L1 data cache line size in bytes
922 if different from the block size
923 - i-cache-line-size : one cell, L1 instruction cache line size in
924 bytes if different from the block size
926 You are welcome to add any property you find relevant to your board,
927 like some information about the mechanism used to soft-reset the
928 CPUs. For example, Apple puts the GPIO number for CPU soft reset
929 lines in there as a "soft-reset" property since they start secondary
930 CPUs by soft-resetting them.
933 d) the /memory node(s)
935 To define the physical memory layout of your board, you should
936 create one or more memory node(s). You can either create a single
937 node with all memory ranges in its reg property, or you can create
938 several nodes, as you wish. The unit address (@ part) used for the
939 full path is the address of the first range of memory defined by a
940 given node. If you use a single memory node, this will typically be
941 @0.
943 Required properties:
945 - device_type : has to be "memory"
946 - reg : This property contains all the physical memory ranges of
947 your board. It's a list of addresses/sizes concatenated
948 together, with the number of cells of each defined by the
949 #address-cells and #size-cells of the root node. For example,
950 with both of these properties being 2 like in the example given
951 earlier, a 970 based machine with 6Gb of RAM could typically
952 have a "reg" property here that looks like:
954 00000000 00000000 00000000 80000000
955 00000001 00000000 00000001 00000000
957 That is a range starting at 0 of 0x80000000 bytes and a range
958 starting at 0x100000000 and of 0x100000000 bytes. You can see
959 that there is no memory covering the IO hole between 2Gb and
960 4Gb. Some vendors prefer splitting those ranges into smaller
961 segments, but the kernel doesn't care.
963 e) The /chosen node
965 This node is a bit "special". Normally, that's where open firmware
966 puts some variable environment information, like the arguments, or
967 the default input/output devices.
969 This specification makes a few of these mandatory, but also defines
970 some linux-specific properties that would be normally constructed by
971 the prom_init() trampoline when booting with an OF client interface,
972 but that you have to provide yourself when using the flattened format.
974 Recommended properties:
976 - bootargs : This zero-terminated string is passed as the kernel
977 command line
978 - linux,stdout-path : This is the full path to your standard
979 console device if any. Typically, if you have serial devices on
980 your board, you may want to put the full path to the one set as
981 the default console in the firmware here, for the kernel to pick
982 it up as its own default console. If you look at the function
983 set_preferred_console() in arch/ppc64/kernel/setup.c, you'll see
984 that the kernel tries to find out the default console and has
985 knowledge of various types like 8250 serial ports. You may want
986 to extend this function to add your own.
988 Note that u-boot creates and fills in the chosen node for platforms
989 that use it.
991 (Note: a practice that is now obsolete was to include a property
992 under /chosen called interrupt-controller which had a phandle value
993 that pointed to the main interrupt controller)
995 f) the /soc<SOCname> node
997 This node is used to represent a system-on-a-chip (SOC) and must be
998 present if the processor is a SOC. The top-level soc node contains
999 information that is global to all devices on the SOC. The node name
1000 should contain a unit address for the SOC, which is the base address
1001 of the memory-mapped register set for the SOC. The name of an soc
1002 node should start with "soc", and the remainder of the name should
1003 represent the part number for the soc. For example, the MPC8540's
1004 soc node would be called "soc8540".
1006 Required properties:
1008 - device_type : Should be "soc"
1009 - ranges : Should be defined as specified in 1) to describe the
1010 translation of SOC addresses for memory mapped SOC registers.
1011 - bus-frequency: Contains the bus frequency for the SOC node.
1012 Typically, the value of this field is filled in by the boot
1013 loader.
1016 Recommended properties:
1018 - reg : This property defines the address and size of the
1019 memory-mapped registers that are used for the SOC node itself.
1020 It does not include the child device registers - these will be
1021 defined inside each child node. The address specified in the
1022 "reg" property should match the unit address of the SOC node.
1023 - #address-cells : Address representation for "soc" devices. The
1024 format of this field may vary depending on whether or not the
1025 device registers are memory mapped. For memory mapped
1026 registers, this field represents the number of cells needed to
1027 represent the address of the registers. For SOCs that do not
1028 use MMIO, a special address format should be defined that
1029 contains enough cells to represent the required information.
1030 See 1) above for more details on defining #address-cells.
1031 - #size-cells : Size representation for "soc" devices
1032 - #interrupt-cells : Defines the width of cells used to represent
1033 interrupts. Typically this value is <2>, which includes a
1034 32-bit number that represents the interrupt number, and a
1035 32-bit number that represents the interrupt sense and level.
1036 This field is only needed if the SOC contains an interrupt
1037 controller.
1039 The SOC node may contain child nodes for each SOC device that the
1040 platform uses. Nodes should not be created for devices which exist
1041 on the SOC but are not used by a particular platform. See chapter VI
1042 for more information on how to specify devices that are part of a SOC.
1044 Example SOC node for the MPC8540:
1046 soc8540@e0000000 {
1047 #address-cells = <1>;
1048 #size-cells = <1>;
1049 #interrupt-cells = <2>;
1050 device_type = "soc";
1051 ranges = <00000000 e0000000 00100000>
1052 reg = <e0000000 00003000>;
1053 bus-frequency = <0>;
1054 }
1058 IV - "dtc", the device tree compiler
1059 ====================================
1062 dtc source code can be found at
1063 <http://ozlabs.org/~dgibson/dtc/dtc.tar.gz>
1065 WARNING: This version is still in early development stage; the
1066 resulting device-tree "blobs" have not yet been validated with the
1067 kernel. The current generated bloc lacks a useful reserve map (it will
1068 be fixed to generate an empty one, it's up to the bootloader to fill
1069 it up) among others. The error handling needs work, bugs are lurking,
1070 etc...
1072 dtc basically takes a device-tree in a given format and outputs a
1073 device-tree in another format. The currently supported formats are:
1075 Input formats:
1076 -------------
1078 - "dtb": "blob" format, that is a flattened device-tree block
1079 with
1080 header all in a binary blob.
1081 - "dts": "source" format. This is a text file containing a
1082 "source" for a device-tree. The format is defined later in this
1083 chapter.
1084 - "fs" format. This is a representation equivalent to the
1085 output of /proc/device-tree, that is nodes are directories and
1086 properties are files
1088 Output formats:
1089 ---------------
1091 - "dtb": "blob" format
1092 - "dts": "source" format
1093 - "asm": assembly language file. This is a file that can be
1094 sourced by gas to generate a device-tree "blob". That file can
1095 then simply be added to your Makefile. Additionally, the
1096 assembly file exports some symbols that can be used.
1099 The syntax of the dtc tool is
1101 dtc [-I <input-format>] [-O <output-format>]
1102 [-o output-filename] [-V output_version] input_filename
1105 The "output_version" defines what version of the "blob" format will be
1106 generated. Supported versions are 1,2,3 and 16. The default is
1107 currently version 3 but that may change in the future to version 16.
1109 Additionally, dtc performs various sanity checks on the tree, like the
1110 uniqueness of linux, phandle properties, validity of strings, etc...
1112 The format of the .dts "source" file is "C" like, supports C and C++
1113 style comments.
1115 / {
1116 }
1118 The above is the "device-tree" definition. It's the only statement
1119 supported currently at the toplevel.
1121 / {
1122 property1 = "string_value"; /* define a property containing a 0
1123 * terminated string
1124 */
1126 property2 = <1234abcd>; /* define a property containing a
1127 * numerical 32-bit value (hexadecimal)
1128 */
1130 property3 = <12345678 12345678 deadbeef>;
1131 /* define a property containing 3
1132 * numerical 32-bit values (cells) in
1133 * hexadecimal
1134 */
1135 property4 = [0a 0b 0c 0d de ea ad be ef];
1136 /* define a property whose content is
1137 * an arbitrary array of bytes
1138 */
1140 childnode@addresss { /* define a child node named "childnode"
1141 * whose unit name is "childnode at
1142 * address"
1143 */
1145 childprop = "hello\n"; /* define a property "childprop" of
1146 * childnode (in this case, a string)
1147 */
1148 };
1149 };
1151 Nodes can contain other nodes etc... thus defining the hierarchical
1152 structure of the tree.
1154 Strings support common escape sequences from C: "\n", "\t", "\r",
1155 "\(octal value)", "\x(hex value)".
1157 It is also suggested that you pipe your source file through cpp (gcc
1158 preprocessor) so you can use #include's, #define for constants, etc...
1160 Finally, various options are planned but not yet implemented, like
1161 automatic generation of phandles, labels (exported to the asm file so
1162 you can point to a property content and change it easily from whatever
1163 you link the device-tree with), label or path instead of numeric value
1164 in some cells to "point" to a node (replaced by a phandle at compile
1165 time), export of reserve map address to the asm file, ability to
1166 specify reserve map content at compile time, etc...
1168 We may provide a .h include file with common definitions of that
1169 proves useful for some properties (like building PCI properties or
1170 interrupt maps) though it may be better to add a notion of struct
1171 definitions to the compiler...
1174 V - Recommendations for a bootloader
1175 ====================================
1178 Here are some various ideas/recommendations that have been proposed
1179 while all this has been defined and implemented.
1181 - The bootloader may want to be able to use the device-tree itself
1182 and may want to manipulate it (to add/edit some properties,
1183 like physical memory size or kernel arguments). At this point, 2
1184 choices can be made. Either the bootloader works directly on the
1185 flattened format, or the bootloader has its own internal tree
1186 representation with pointers (similar to the kernel one) and
1187 re-flattens the tree when booting the kernel. The former is a bit
1188 more difficult to edit/modify, the later requires probably a bit
1189 more code to handle the tree structure. Note that the structure
1190 format has been designed so it's relatively easy to "insert"
1191 properties or nodes or delete them by just memmoving things
1192 around. It contains no internal offsets or pointers for this
1193 purpose.
1195 - An example of code for iterating nodes & retrieving properties
1196 directly from the flattened tree format can be found in the kernel
1197 file arch/ppc64/kernel/prom.c, look at scan_flat_dt() function,
1198 its usage in early_init_devtree(), and the corresponding various
1199 early_init_dt_scan_*() callbacks. That code can be re-used in a
1200 GPL bootloader, and as the author of that code, I would be happy
1201 to discuss possible free licensing to any vendor who wishes to
1202 integrate all or part of this code into a non-GPL bootloader.
1206 VI - System-on-a-chip devices and nodes
1207 =======================================
1209 Many companies are now starting to develop system-on-a-chip
1210 processors, where the processor core (CPU) and many peripheral devices
1211 exist on a single piece of silicon. For these SOCs, an SOC node
1212 should be used that defines child nodes for the devices that make
1213 up the SOC. While platforms are not required to use this model in
1214 order to boot the kernel, it is highly encouraged that all SOC
1215 implementations define as complete a flat-device-tree as possible to
1216 describe the devices on the SOC. This will allow for the
1217 genericization of much of the kernel code.
1220 1) Defining child nodes of an SOC
1221 ---------------------------------
1223 Each device that is part of an SOC may have its own node entry inside
1224 the SOC node. For each device that is included in the SOC, the unit
1225 address property represents the address offset for this device's
1226 memory-mapped registers in the parent's address space. The parent's
1227 address space is defined by the "ranges" property in the top-level soc
1228 node. The "reg" property for each node that exists directly under the
1229 SOC node should contain the address mapping from the child address space
1230 to the parent SOC address space and the size of the device's
1231 memory-mapped register file.
1233 For many devices that may exist inside an SOC, there are predefined
1234 specifications for the format of the device tree node. All SOC child
1235 nodes should follow these specifications, except where noted in this
1236 document.
1238 See appendix A for an example partial SOC node definition for the
1239 MPC8540.
1242 2) Representing devices without a current OF specification
1243 ----------------------------------------------------------
1245 Currently, there are many devices on SOCs that do not have a standard
1246 representation pre-defined as part of the open firmware
1247 specifications, mainly because the boards that contain these SOCs are
1248 not currently booted using open firmware. This section contains
1249 descriptions for the SOC devices for which new nodes have been
1250 defined; this list will expand as more and more SOC-containing
1251 platforms are moved over to use the flattened-device-tree model.
1253 a) MDIO IO device
1255 The MDIO is a bus to which the PHY devices are connected. For each
1256 device that exists on this bus, a child node should be created. See
1257 the definition of the PHY node below for an example of how to define
1258 a PHY.
1260 Required properties:
1261 - reg : Offset and length of the register set for the device
1262 - compatible : Should define the compatible device type for the
1263 mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
1265 Example:
1267 mdio@24520 {
1268 reg = <24520 20>;
1269 compatible = "fsl,gianfar-mdio";
1271 ethernet-phy@0 {
1272 ......
1273 };
1274 };
1277 b) Gianfar-compatible ethernet nodes
1279 Required properties:
1281 - device_type : Should be "network"
1282 - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
1283 - compatible : Should be "gianfar"
1284 - reg : Offset and length of the register set for the device
1285 - mac-address : List of bytes representing the ethernet address of
1286 this controller
1287 - interrupts : <a b> where a is the interrupt number and b is a
1288 field that represents an encoding of the sense and level
1289 information for the interrupt. This should be encoded based on
1290 the information in section 2) depending on the type of interrupt
1291 controller you have.
1292 - interrupt-parent : the phandle for the interrupt controller that
1293 services interrupts for this device.
1294 - phy-handle : The phandle for the PHY connected to this ethernet
1295 controller.
1296 - fixed-link : <a b c d e> where a is emulated phy id - choose any,
1297 but unique to the all specified fixed-links, b is duplex - 0 half,
1298 1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
1299 pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
1301 Recommended properties:
1303 - phy-connection-type : a string naming the controller/PHY interface type,
1304 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
1305 "tbi", or "rtbi". This property is only really needed if the connection
1306 is of type "rgmii-id", as all other connection types are detected by
1307 hardware.
1310 Example:
1312 ethernet@24000 {
1313 #size-cells = <0>;
1314 device_type = "network";
1315 model = "TSEC";
1316 compatible = "gianfar";
1317 reg = <24000 1000>;
1318 mac-address = [ 00 E0 0C 00 73 00 ];
1319 interrupts = <d 3 e 3 12 3>;
1320 interrupt-parent = <40000>;
1321 phy-handle = <2452000>
1322 };
1326 c) PHY nodes
1328 Required properties:
1330 - device_type : Should be "ethernet-phy"
1331 - interrupts : <a b> where a is the interrupt number and b is a
1332 field that represents an encoding of the sense and level
1333 information for the interrupt. This should be encoded based on
1334 the information in section 2) depending on the type of interrupt
1335 controller you have.
1336 - interrupt-parent : the phandle for the interrupt controller that
1337 services interrupts for this device.
1338 - reg : The ID number for the phy, usually a small integer
1339 - linux,phandle : phandle for this node; likely referenced by an
1340 ethernet controller node.
1343 Example:
1345 ethernet-phy@0 {
1346 linux,phandle = <2452000>
1347 interrupt-parent = <40000>;
1348 interrupts = <35 1>;
1349 reg = <0>;
1350 device_type = "ethernet-phy";
1351 };
1354 d) Interrupt controllers
1356 Some SOC devices contain interrupt controllers that are different
1357 from the standard Open PIC specification. The SOC device nodes for
1358 these types of controllers should be specified just like a standard
1359 OpenPIC controller. Sense and level information should be encoded
1360 as specified in section 2) of this chapter for each device that
1361 specifies an interrupt.
1363 Example :
1365 pic@40000 {
1366 linux,phandle = <40000>;
1367 interrupt-controller;
1368 #address-cells = <0>;
1369 reg = <40000 40000>;
1370 compatible = "chrp,open-pic";
1371 device_type = "open-pic";
1372 };
1375 e) I2C
1377 Required properties :
1379 - device_type : Should be "i2c"
1380 - reg : Offset and length of the register set for the device
1382 Recommended properties :
1384 - compatible : Should be "fsl-i2c" for parts compatible with
1385 Freescale I2C specifications.
1386 - interrupts : <a b> where a is the interrupt number and b is a
1387 field that represents an encoding of the sense and level
1388 information for the interrupt. This should be encoded based on
1389 the information in section 2) depending on the type of interrupt
1390 controller you have.
1391 - interrupt-parent : the phandle for the interrupt controller that
1392 services interrupts for this device.
1393 - dfsrr : boolean; if defined, indicates that this I2C device has
1394 a digital filter sampling rate register
1395 - fsl5200-clocking : boolean; if defined, indicated that this device
1396 uses the FSL 5200 clocking mechanism.
1398 Example :
1400 i2c@3000 {
1401 interrupt-parent = <40000>;
1402 interrupts = <1b 3>;
1403 reg = <3000 18>;
1404 device_type = "i2c";
1405 compatible = "fsl-i2c";
1406 dfsrr;
1407 };
1410 f) Freescale SOC USB controllers
1412 The device node for a USB controller that is part of a Freescale
1413 SOC is as described in the document "Open Firmware Recommended
1414 Practice : Universal Serial Bus" with the following modifications
1415 and additions :
1417 Required properties :
1418 - compatible : Should be "fsl-usb2-mph" for multi port host USB
1419 controllers, or "fsl-usb2-dr" for dual role USB controllers
1420 - phy_type : For multi port host USB controllers, should be one of
1421 "ulpi", or "serial". For dual role USB controllers, should be
1422 one of "ulpi", "utmi", "utmi_wide", or "serial".
1423 - reg : Offset and length of the register set for the device
1424 - port0 : boolean; if defined, indicates port0 is connected for
1425 fsl-usb2-mph compatible controllers. Either this property or
1426 "port1" (or both) must be defined for "fsl-usb2-mph" compatible
1427 controllers.
1428 - port1 : boolean; if defined, indicates port1 is connected for
1429 fsl-usb2-mph compatible controllers. Either this property or
1430 "port0" (or both) must be defined for "fsl-usb2-mph" compatible
1431 controllers.
1432 - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
1433 controllers. Can be "host", "peripheral", or "otg". Default to
1434 "host" if not defined for backward compatibility.
1436 Recommended properties :
1437 - interrupts : <a b> where a is the interrupt number and b is a
1438 field that represents an encoding of the sense and level
1439 information for the interrupt. This should be encoded based on
1440 the information in section 2) depending on the type of interrupt
1441 controller you have.
1442 - interrupt-parent : the phandle for the interrupt controller that
1443 services interrupts for this device.
1445 Example multi port host USB controller device node :
1446 usb@22000 {
1447 compatible = "fsl-usb2-mph";
1448 reg = <22000 1000>;
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1451 interrupt-parent = <700>;
1452 interrupts = <27 1>;
1453 phy_type = "ulpi";
1454 port0;
1455 port1;
1456 };
1458 Example dual role USB controller device node :
1459 usb@23000 {
1460 compatible = "fsl-usb2-dr";
1461 reg = <23000 1000>;
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1464 interrupt-parent = <700>;
1465 interrupts = <26 1>;
1466 dr_mode = "otg";
1467 phy = "ulpi";
1468 };
1471 g) Freescale SOC SEC Security Engines
1473 Required properties:
1475 - device_type : Should be "crypto"
1476 - model : Model of the device. Should be "SEC1" or "SEC2"
1477 - compatible : Should be "talitos"
1478 - reg : Offset and length of the register set for the device
1479 - interrupts : <a b> where a is the interrupt number and b is a
1480 field that represents an encoding of the sense and level
1481 information for the interrupt. This should be encoded based on
1482 the information in section 2) depending on the type of interrupt
1483 controller you have.
1484 - interrupt-parent : the phandle for the interrupt controller that
1485 services interrupts for this device.
1486 - num-channels : An integer representing the number of channels
1487 available.
1488 - channel-fifo-len : An integer representing the number of
1489 descriptor pointers each channel fetch fifo can hold.
1490 - exec-units-mask : The bitmask representing what execution units
1491 (EUs) are available. It's a single 32-bit cell. EU information
1492 should be encoded following the SEC's Descriptor Header Dword
1493 EU_SEL0 field documentation, i.e. as follows:
1495 bit 0 = reserved - should be 0
1496 bit 1 = set if SEC has the ARC4 EU (AFEU)
1497 bit 2 = set if SEC has the DES/3DES EU (DEU)
1498 bit 3 = set if SEC has the message digest EU (MDEU)
1499 bit 4 = set if SEC has the random number generator EU (RNG)
1500 bit 5 = set if SEC has the public key EU (PKEU)
1501 bit 6 = set if SEC has the AES EU (AESU)
1502 bit 7 = set if SEC has the Kasumi EU (KEU)
1504 bits 8 through 31 are reserved for future SEC EUs.
1506 - descriptor-types-mask : The bitmask representing what descriptors
1507 are available. It's a single 32-bit cell. Descriptor type
1508 information should be encoded following the SEC's Descriptor
1509 Header Dword DESC_TYPE field documentation, i.e. as follows:
1511 bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
1512 bit 1 = set if SEC supports the ipsec_esp descriptor type
1513 bit 2 = set if SEC supports the common_nonsnoop desc. type
1514 bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
1515 bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
1516 bit 5 = set if SEC supports the srtp descriptor type
1517 bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
1518 bit 7 = set if SEC supports the pkeu_assemble descriptor type
1519 bit 8 = set if SEC supports the aesu_key_expand_output desc.type
1520 bit 9 = set if SEC supports the pkeu_ptmul descriptor type
1521 bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
1522 bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
1524 ..and so on and so forth.
1526 Example:
1528 /* MPC8548E */
1529 crypto@30000 {
1530 device_type = "crypto";
1531 model = "SEC2";
1532 compatible = "talitos";
1533 reg = <30000 10000>;
1534 interrupts = <1d 3>;
1535 interrupt-parent = <40000>;
1536 num-channels = <4>;
1537 channel-fifo-len = <18>;
1538 exec-units-mask = <000000fe>;
1539 descriptor-types-mask = <012b0ebf>;
1540 };
1542 h) Board Control and Status (BCSR)
1544 Required properties:
1546 - device_type : Should be "board-control"
1547 - reg : Offset and length of the register set for the device
1549 Example:
1551 bcsr@f8000000 {
1552 device_type = "board-control";
1553 reg = <f8000000 8000>;
1554 };
1556 i) Freescale QUICC Engine module (QE)
1557 This represents qe module that is installed on PowerQUICC II Pro.
1559 NOTE: This is an interim binding; it should be updated to fit
1560 in with the CPM binding later in this document.
1562 Basically, it is a bus of devices, that could act more or less
1563 as a complete entity (UCC, USB etc ). All of them should be siblings on
1564 the "root" qe node, using the common properties from there.
1565 The description below applies to the qe of MPC8360 and
1566 more nodes and properties would be extended in the future.
1568 i) Root QE device
1570 Required properties:
1571 - compatible : should be "fsl,qe";
1572 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
1573 - reg : offset and length of the device registers.
1574 - bus-frequency : the clock frequency for QUICC Engine.
1576 Recommended properties
1577 - brg-frequency : the internal clock source frequency for baud-rate
1578 generators in Hz.
1580 Example:
1581 qe@e0100000 {
1582 #address-cells = <1>;
1583 #size-cells = <1>;
1584 #interrupt-cells = <2>;
1585 compatible = "fsl,qe";
1586 ranges = <0 e0100000 00100000>;
1587 reg = <e0100000 480>;
1588 brg-frequency = <0>;
1589 bus-frequency = <179A7B00>;
1590 }
1593 ii) SPI (Serial Peripheral Interface)
1595 Required properties:
1596 - cell-index : SPI controller index.
1597 - compatible : should be "fsl,spi".
1598 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
1599 - reg : Offset and length of the register set for the device
1600 - interrupts : <a b> where a is the interrupt number and b is a
1601 field that represents an encoding of the sense and level
1602 information for the interrupt. This should be encoded based on
1603 the information in section 2) depending on the type of interrupt
1604 controller you have.
1605 - interrupt-parent : the phandle for the interrupt controller that
1606 services interrupts for this device.
1608 Example:
1609 spi@4c0 {
1610 cell-index = <0>;
1611 compatible = "fsl,spi";
1612 reg = <4c0 40>;
1613 interrupts = <82 0>;
1614 interrupt-parent = <700>;
1615 mode = "cpu";
1616 };
1619 iii) USB (Universal Serial Bus Controller)
1621 Required properties:
1622 - compatible : could be "qe_udc" or "fhci-hcd".
1623 - mode : the could be "host" or "slave".
1624 - reg : Offset and length of the register set for the device
1625 - interrupts : <a b> where a is the interrupt number and b is a
1626 field that represents an encoding of the sense and level
1627 information for the interrupt. This should be encoded based on
1628 the information in section 2) depending on the type of interrupt
1629 controller you have.
1630 - interrupt-parent : the phandle for the interrupt controller that
1631 services interrupts for this device.
1633 Example(slave):
1634 usb@6c0 {
1635 compatible = "qe_udc";
1636 reg = <6c0 40>;
1637 interrupts = <8b 0>;
1638 interrupt-parent = <700>;
1639 mode = "slave";
1640 };
1643 iv) UCC (Unified Communications Controllers)
1645 Required properties:
1646 - device_type : should be "network", "hldc", "uart", "transparent"
1647 "bisync", "atm", or "serial".
1648 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
1649 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
1650 - reg : Offset and length of the register set for the device
1651 - interrupts : <a b> where a is the interrupt number and b is a
1652 field that represents an encoding of the sense and level
1653 information for the interrupt. This should be encoded based on
1654 the information in section 2) depending on the type of interrupt
1655 controller you have.
1656 - interrupt-parent : the phandle for the interrupt controller that
1657 services interrupts for this device.
1658 - pio-handle : The phandle for the Parallel I/O port configuration.
1659 - port-number : for UART drivers, the port number to use, between 0 and 3.
1660 This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
1661 The port number is added to the minor number of the device. Unlike the
1662 CPM UART driver, the port-number is required for the QE UART driver.
1663 - soft-uart : for UART drivers, if specified this means the QE UART device
1664 driver should use "Soft-UART" mode, which is needed on some SOCs that have
1665 broken UART hardware. Soft-UART is provided via a microcode upload.
1666 - rx-clock-name: the UCC receive clock source
1667 "none": clock source is disabled
1668 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
1669 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
1670 - tx-clock-name: the UCC transmit clock source
1671 "none": clock source is disabled
1672 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
1673 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
1674 The following two properties are deprecated. rx-clock has been replaced
1675 with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
1676 Drivers that currently use the deprecated properties should continue to
1677 do so, in order to support older device trees, but they should be updated
1678 to check for the new properties first.
1679 - rx-clock : represents the UCC receive clock source.
1680 0x00 : clock source is disabled;
1681 0x1~0x10 : clock source is BRG1~BRG16 respectively;
1682 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
1683 - tx-clock: represents the UCC transmit clock source;
1684 0x00 : clock source is disabled;
1685 0x1~0x10 : clock source is BRG1~BRG16 respectively;
1686 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
1688 Required properties for network device_type:
1689 - mac-address : list of bytes representing the ethernet address.
1690 - phy-handle : The phandle for the PHY connected to this controller.
1692 Recommended properties:
1693 - phy-connection-type : a string naming the controller/PHY interface type,
1694 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
1695 Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
1696 "tbi", or "rtbi".
1698 Example:
1699 ucc@2000 {
1700 device_type = "network";
1701 compatible = "ucc_geth";
1702 cell-index = <1>;
1703 reg = <2000 200>;
1704 interrupts = <a0 0>;
1705 interrupt-parent = <700>;
1706 mac-address = [ 00 04 9f 00 23 23 ];
1707 rx-clock = "none";
1708 tx-clock = "clk9";
1709 phy-handle = <212000>;
1710 phy-connection-type = "gmii";
1711 pio-handle = <140001>;
1712 };
1715 v) Parallel I/O Ports
1717 This node configures Parallel I/O ports for CPUs with QE support.
1718 The node should reside in the "soc" node of the tree. For each
1719 device that using parallel I/O ports, a child node should be created.
1720 See the definition of the Pin configuration nodes below for more
1721 information.
1723 Required properties:
1724 - device_type : should be "par_io".
1725 - reg : offset to the register set and its length.
1726 - num-ports : number of Parallel I/O ports
1728 Example:
1729 par_io@1400 {
1730 reg = <1400 100>;
1731 #address-cells = <1>;
1732 #size-cells = <0>;
1733 device_type = "par_io";
1734 num-ports = <7>;
1735 ucc_pin@01 {
1736 ......
1737 };
1739 Note that "par_io" nodes are obsolete, and should not be used for
1740 the new device trees. Instead, each Par I/O bank should be represented
1741 via its own gpio-controller node:
1743 Required properties:
1744 - #gpio-cells : should be "2".
1745 - compatible : should be "fsl,<chip>-qe-pario-bank",
1746 "fsl,mpc8323-qe-pario-bank".
1747 - reg : offset to the register set and its length.
1748 - gpio-controller : node to identify gpio controllers.
1750 Example:
1751 qe_pio_a: gpio-controller@1400 {
1752 #gpio-cells = <2>;
1753 compatible = "fsl,mpc8360-qe-pario-bank",
1754 "fsl,mpc8323-qe-pario-bank";
1755 reg = <0x1400 0x18>;
1756 gpio-controller;
1757 };
1759 qe_pio_e: gpio-controller@1460 {
1760 #gpio-cells = <2>;
1761 compatible = "fsl,mpc8360-qe-pario-bank",
1762 "fsl,mpc8323-qe-pario-bank";
1763 reg = <0x1460 0x18>;
1764 gpio-controller;
1765 };
1767 vi) Pin configuration nodes
1769 Required properties:
1770 - linux,phandle : phandle of this node; likely referenced by a QE
1771 device.
1772 - pio-map : array of pin configurations. Each pin is defined by 6
1773 integers. The six numbers are respectively: port, pin, dir,
1774 open_drain, assignment, has_irq.
1775 - port : port number of the pin; 0-6 represent port A-G in UM.
1776 - pin : pin number in the port.
1777 - dir : direction of the pin, should encode as follows:
1779 0 = The pin is disabled
1780 1 = The pin is an output
1781 2 = The pin is an input
1782 3 = The pin is I/O
1784 - open_drain : indicates the pin is normal or wired-OR:
1786 0 = The pin is actively driven as an output
1787 1 = The pin is an open-drain driver. As an output, the pin is
1788 driven active-low, otherwise it is three-stated.
1790 - assignment : function number of the pin according to the Pin Assignment
1791 tables in User Manual. Each pin can have up to 4 possible functions in
1792 QE and two options for CPM.
1793 - has_irq : indicates if the pin is used as source of external
1794 interrupts.
1796 Example:
1797 ucc_pin@01 {
1798 linux,phandle = <140001>;
1799 pio-map = <
1800 /* port pin dir open_drain assignment has_irq */
1801 0 3 1 0 1 0 /* TxD0 */
1802 0 4 1 0 1 0 /* TxD1 */
1803 0 5 1 0 1 0 /* TxD2 */
1804 0 6 1 0 1 0 /* TxD3 */
1805 1 6 1 0 3 0 /* TxD4 */
1806 1 7 1 0 1 0 /* TxD5 */
1807 1 9 1 0 2 0 /* TxD6 */
1808 1 a 1 0 2 0 /* TxD7 */
1809 0 9 2 0 1 0 /* RxD0 */
1810 0 a 2 0 1 0 /* RxD1 */
1811 0 b 2 0 1 0 /* RxD2 */
1812 0 c 2 0 1 0 /* RxD3 */
1813 0 d 2 0 1 0 /* RxD4 */
1814 1 1 2 0 2 0 /* RxD5 */
1815 1 0 2 0 2 0 /* RxD6 */
1816 1 4 2 0 2 0 /* RxD7 */
1817 0 7 1 0 1 0 /* TX_EN */
1818 0 8 1 0 1 0 /* TX_ER */
1819 0 f 2 0 1 0 /* RX_DV */
1820 0 10 2 0 1 0 /* RX_ER */
1821 0 0 2 0 1 0 /* RX_CLK */
1822 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
1823 2 8 2 0 1 0>; /* GTX125 - CLK9 */
1824 };
1826 vii) Multi-User RAM (MURAM)
1828 Required properties:
1829 - compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
1830 - mode : the could be "host" or "slave".
1831 - ranges : Should be defined as specified in 1) to describe the
1832 translation of MURAM addresses.
1833 - data-only : sub-node which defines the address area under MURAM
1834 bus that can be allocated as data/parameter
1836 Example:
1838 muram@10000 {
1839 compatible = "fsl,qe-muram", "fsl,cpm-muram";
1840 ranges = <0 00010000 0000c000>;
1842 data-only@0{
1843 compatible = "fsl,qe-muram-data",
1844 "fsl,cpm-muram-data";
1845 reg = <0 c000>;
1846 };
1847 };
1849 viii) Uploaded QE firmware
1851 If a new firwmare has been uploaded to the QE (usually by the
1852 boot loader), then a 'firmware' child node should be added to the QE
1853 node. This node provides information on the uploaded firmware that
1854 device drivers may need.
1856 Required properties:
1857 - id: The string name of the firmware. This is taken from the 'id'
1858 member of the qe_firmware structure of the uploaded firmware.
1859 Device drivers can search this string to determine if the
1860 firmware they want is already present.
1861 - extended-modes: The Extended Modes bitfield, taken from the
1862 firmware binary. It is a 64-bit number represented
1863 as an array of two 32-bit numbers.
1864 - virtual-traps: The virtual traps, taken from the firmware binary.
1865 It is an array of 8 32-bit numbers.
1867 Example:
1869 firmware {
1870 id = "Soft-UART";
1871 extended-modes = <0 0>;
1872 virtual-traps = <0 0 0 0 0 0 0 0>;
1873 }
1875 j) CFI or JEDEC memory-mapped NOR flash
1877 Flash chips (Memory Technology Devices) are often used for solid state
1878 file systems on embedded devices.
1880 - compatible : should contain the specific model of flash chip(s)
1881 used, if known, followed by either "cfi-flash" or "jedec-flash"
1882 - reg : Address range of the flash chip
1883 - bank-width : Width (in bytes) of the flash bank. Equal to the
1884 device width times the number of interleaved chips.
1885 - device-width : (optional) Width of a single flash chip. If
1886 omitted, assumed to be equal to 'bank-width'.
1887 - #address-cells, #size-cells : Must be present if the flash has
1888 sub-nodes representing partitions (see below). In this case
1889 both #address-cells and #size-cells must be equal to 1.
1891 For JEDEC compatible devices, the following additional properties
1892 are defined:
1894 - vendor-id : Contains the flash chip's vendor id (1 byte).
1895 - device-id : Contains the flash chip's device id (1 byte).
1897 In addition to the information on the flash bank itself, the
1898 device tree may optionally contain additional information
1899 describing partitions of the flash address space. This can be
1900 used on platforms which have strong conventions about which
1901 portions of the flash are used for what purposes, but which don't
1902 use an on-flash partition table such as RedBoot.
1904 Each partition is represented as a sub-node of the flash device.
1905 Each node's name represents the name of the corresponding
1906 partition of the flash device.
1908 Flash partitions
1909 - reg : The partition's offset and size within the flash bank.
1910 - label : (optional) The label / name for this flash partition.
1911 If omitted, the label is taken from the node name (excluding
1912 the unit address).
1913 - read-only : (optional) This parameter, if present, is a hint to
1914 Linux that this flash partition should only be mounted
1915 read-only. This is usually used for flash partitions
1916 containing early-boot firmware images or data which should not
1917 be clobbered.
1919 Example:
1921 flash@ff000000 {
1922 compatible = "amd,am29lv128ml", "cfi-flash";
1923 reg = <ff000000 01000000>;
1924 bank-width = <4>;
1925 device-width = <1>;
1926 #address-cells = <1>;
1927 #size-cells = <1>;
1928 fs@0 {
1929 label = "fs";
1930 reg = <0 f80000>;
1931 };
1932 firmware@f80000 {
1933 label ="firmware";
1934 reg = <f80000 80000>;
1935 read-only;
1936 };
1937 };
1939 k) Global Utilities Block
1941 The global utilities block controls power management, I/O device
1942 enabling, power-on-reset configuration monitoring, general-purpose
1943 I/O signal configuration, alternate function selection for multiplexed
1944 signals, and clock control.
1946 Required properties:
1948 - compatible : Should define the compatible device type for
1949 global-utilities.
1950 - reg : Offset and length of the register set for the device.
1952 Recommended properties:
1954 - fsl,has-rstcr : Indicates that the global utilities register set
1955 contains a functioning "reset control register" (i.e. the board
1956 is wired to reset upon setting the HRESET_REQ bit in this register).
1958 Example:
1960 global-utilities@e0000 { /* global utilities block */
1961 compatible = "fsl,mpc8548-guts";
1962 reg = <e0000 1000>;
1963 fsl,has-rstcr;
1964 };
1966 l) Freescale Communications Processor Module
1968 NOTE: This is an interim binding, and will likely change slightly,
1969 as more devices are supported. The QE bindings especially are
1970 incomplete.
1972 i) Root CPM node
1974 Properties:
1975 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
1976 - reg : A 48-byte region beginning with CPCR.
1978 Example:
1979 cpm@119c0 {
1980 #address-cells = <1>;
1981 #size-cells = <1>;
1982 #interrupt-cells = <2>;
1983 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
1984 reg = <119c0 30>;
1985 }
1987 ii) Properties common to mulitple CPM/QE devices
1989 - fsl,cpm-command : This value is ORed with the opcode and command flag
1990 to specify the device on which a CPM command operates.
1992 - fsl,cpm-brg : Indicates which baud rate generator the device
1993 is associated with. If absent, an unused BRG
1994 should be dynamically allocated. If zero, the
1995 device uses an external clock rather than a BRG.
1997 - reg : Unless otherwise specified, the first resource represents the
1998 scc/fcc/ucc registers, and the second represents the device's
1999 parameter RAM region (if it has one).
2001 iii) Serial
2003 Currently defined compatibles:
2004 - fsl,cpm1-smc-uart
2005 - fsl,cpm2-smc-uart
2006 - fsl,cpm1-scc-uart
2007 - fsl,cpm2-scc-uart
2008 - fsl,qe-uart
2010 Example:
2012 serial@11a00 {
2013 device_type = "serial";
2014 compatible = "fsl,mpc8272-scc-uart",
2015 "fsl,cpm2-scc-uart";
2016 reg = <11a00 20 8000 100>;
2017 interrupts = <28 8>;
2018 interrupt-parent = <&PIC>;
2019 fsl,cpm-brg = <1>;
2020 fsl,cpm-command = <00800000>;
2021 };
2023 iii) Network
2025 Currently defined compatibles:
2026 - fsl,cpm1-scc-enet
2027 - fsl,cpm2-scc-enet
2028 - fsl,cpm1-fec-enet
2029 - fsl,cpm2-fcc-enet (third resource is GFEMR)
2030 - fsl,qe-enet
2032 Example:
2034 ethernet@11300 {
2035 device_type = "network";
2036 compatible = "fsl,mpc8272-fcc-enet",
2037 "fsl,cpm2-fcc-enet";
2038 reg = <11300 20 8400 100 11390 1>;
2039 local-mac-address = [ 00 00 00 00 00 00 ];
2040 interrupts = <20 8>;
2041 interrupt-parent = <&PIC>;
2042 phy-handle = <&PHY0>;
2043 fsl,cpm-command = <12000300>;
2044 };
2046 iv) MDIO
2048 Currently defined compatibles:
2049 fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
2050 fsl,cpm2-mdio-bitbang (reg is port C registers)
2052 Properties for fsl,cpm2-mdio-bitbang:
2053 fsl,mdio-pin : pin of port C controlling mdio data
2054 fsl,mdc-pin : pin of port C controlling mdio clock
2056 Example:
2058 mdio@10d40 {
2059 device_type = "mdio";
2060 compatible = "fsl,mpc8272ads-mdio-bitbang",
2061 "fsl,mpc8272-mdio-bitbang",
2062 "fsl,cpm2-mdio-bitbang";
2063 reg = <10d40 14>;
2064 #address-cells = <1>;
2065 #size-cells = <0>;
2066 fsl,mdio-pin = <12>;
2067 fsl,mdc-pin = <13>;
2068 };
2070 v) Baud Rate Generators
2072 Currently defined compatibles:
2073 fsl,cpm-brg
2074 fsl,cpm1-brg
2075 fsl,cpm2-brg
2077 Properties:
2078 - reg : There may be an arbitrary number of reg resources; BRG
2079 numbers are assigned to these in order.
2080 - clock-frequency : Specifies the base frequency driving
2081 the BRG.
2083 Example:
2085 brg@119f0 {
2086 compatible = "fsl,mpc8272-brg",
2087 "fsl,cpm2-brg",
2088 "fsl,cpm-brg";
2089 reg = <119f0 10 115f0 10>;
2090 clock-frequency = <d#25000000>;
2091 };
2093 vi) Interrupt Controllers
2095 Currently defined compatibles:
2096 - fsl,cpm1-pic
2097 - only one interrupt cell
2098 - fsl,pq1-pic
2099 - fsl,cpm2-pic
2100 - second interrupt cell is level/sense:
2101 - 2 is falling edge
2102 - 8 is active low
2104 Example:
2106 interrupt-controller@10c00 {
2107 #interrupt-cells = <2>;
2108 interrupt-controller;
2109 reg = <10c00 80>;
2110 compatible = "mpc8272-pic", "fsl,cpm2-pic";
2111 };
2113 vii) USB (Universal Serial Bus Controller)
2115 Properties:
2116 - compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
2118 Example:
2119 usb@11bc0 {
2120 #address-cells = <1>;
2121 #size-cells = <0>;
2122 compatible = "fsl,cpm2-usb";
2123 reg = <11b60 18 8b00 100>;
2124 interrupts = <b 8>;
2125 interrupt-parent = <&PIC>;
2126 fsl,cpm-command = <2e600000>;
2127 };
2129 viii) Multi-User RAM (MURAM)
2131 The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
2133 Ranges must be set up subject to the following restrictions:
2135 - Children's reg nodes must be offsets from the start of all muram, even
2136 if the user-data area does not begin at zero.
2137 - If multiple range entries are used, the difference between the parent
2138 address and the child address must be the same in all, so that a single
2139 mapping can cover them all while maintaining the ability to determine
2140 CPM-side offsets with pointer subtraction. It is recommended that
2141 multiple range entries not be used.
2142 - A child address of zero must be translatable, even if no reg resources
2143 contain it.
2145 A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
2146 indicate the portion of muram that is usable by the OS for arbitrary
2147 purposes. The data node may have an arbitrary number of reg resources,
2148 all of which contribute to the allocatable muram pool.
2150 Example, based on mpc8272:
2152 muram@0 {
2153 #address-cells = <1>;
2154 #size-cells = <1>;
2155 ranges = <0 0 10000>;
2157 data@0 {
2158 compatible = "fsl,cpm-muram-data";
2159 reg = <0 2000 9800 800>;
2160 };
2161 };
2163 x) I2C
2165 The I2C controller is expressed as a bus under the CPM node.
2167 Properties:
2168 - compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
2169 - reg : On CPM2 devices, the second resource doesn't specify the I2C
2170 Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
2171 (typically 0x8afc 0x2).
2172 - #address-cells : Should be one. The cell is the i2c device address with
2173 the r/w bit set to zero.
2174 - #size-cells : Should be zero.
2175 - clock-frequency : Can be used to set the i2c clock frequency. If
2176 unspecified, a default frequency of 60kHz is being used.
2177 The following two properties are deprecated. They are only used by legacy
2178 i2c drivers to find the bus to probe:
2179 - linux,i2c-index : Can be used to hard code an i2c bus number. By default,
2180 the bus number is dynamically assigned by the i2c core.
2181 - linux,i2c-class : Can be used to override the i2c class. The class is used
2182 by legacy i2c device drivers to find a bus in a specific context like
2183 system management, video or sound. By default, I2C_CLASS_HWMON (1) is
2184 being used. The definition of the classes can be found in
2185 include/i2c/i2c.h
2187 Example, based on mpc823:
2189 i2c@860 {
2190 compatible = "fsl,mpc823-i2c",
2191 "fsl,cpm1-i2c";
2192 reg = <0x860 0x20 0x3c80 0x30>;
2193 interrupts = <16>;
2194 interrupt-parent = <&CPM_PIC>;
2195 fsl,cpm-command = <0x10>;
2196 #address-cells = <1>;
2197 #size-cells = <0>;
2199 rtc@68 {
2200 compatible = "dallas,ds1307";
2201 reg = <0x68>;
2202 };
2203 };
2205 m) Chipselect/Local Bus
2207 Properties:
2208 - name : Should be localbus
2209 - #address-cells : Should be either two or three. The first cell is the
2210 chipselect number, and the remaining cells are the
2211 offset into the chipselect.
2212 - #size-cells : Either one or two, depending on how large each chipselect
2213 can be.
2214 - ranges : Each range corresponds to a single chipselect, and cover
2215 the entire access window as configured.
2217 Example:
2218 localbus@f0010100 {
2219 compatible = "fsl,mpc8272-localbus",
2220 "fsl,pq2-localbus";
2221 #address-cells = <2>;
2222 #size-cells = <1>;
2223 reg = <f0010100 40>;
2225 ranges = <0 0 fe000000 02000000
2226 1 0 f4500000 00008000>;
2228 flash@0,0 {
2229 compatible = "jedec-flash";
2230 reg = <0 0 2000000>;
2231 bank-width = <4>;
2232 device-width = <1>;
2233 };
2235 board-control@1,0 {
2236 reg = <1 0 20>;
2237 compatible = "fsl,mpc8272ads-bcsr";
2238 };
2239 };
2242 n) 4xx/Axon EMAC ethernet nodes
2244 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
2245 the Axon bridge. To operate this needs to interact with a ths
2246 special McMAL DMA controller, and sometimes an RGMII or ZMII
2247 interface. In addition to the nodes and properties described
2248 below, the node for the OPB bus on which the EMAC sits must have a
2249 correct clock-frequency property.
2251 i) The EMAC node itself
2253 Required properties:
2254 - device_type : "network"
2256 - compatible : compatible list, contains 2 entries, first is
2257 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
2258 405gp, Axon) and second is either "ibm,emac" or
2259 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
2260 "ibm,emac4"
2261 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
2262 - interrupt-parent : optional, if needed for interrupt mapping
2263 - reg : <registers mapping>
2264 - local-mac-address : 6 bytes, MAC address
2265 - mal-device : phandle of the associated McMAL node
2266 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
2267 with this EMAC
2268 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
2269 with this EMAC
2270 - cell-index : 1 cell, hardware index of the EMAC cell on a given
2271 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
2272 each Axon chip)
2273 - max-frame-size : 1 cell, maximum frame size supported in bytes
2274 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
2275 operations.
2276 For Axon, 2048
2277 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
2278 operations.
2279 For Axon, 2048.
2280 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
2281 thresholds).
2282 For Axon, 0x00000010
2283 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
2284 in bytes.
2285 For Axon, 0x00000100 (I think ...)
2286 - phy-mode : string, mode of operations of the PHY interface.
2287 Supported values are: "mii", "rmii", "smii", "rgmii",
2288 "tbi", "gmii", rtbi", "sgmii".
2289 For Axon on CAB, it is "rgmii"
2290 - mdio-device : 1 cell, required iff using shared MDIO registers
2291 (440EP). phandle of the EMAC to use to drive the
2292 MDIO lines for the PHY used by this EMAC.
2293 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
2294 the ZMII device node
2295 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
2296 channel or 0xffffffff if ZMII is only used for MDIO.
2297 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
2298 of the RGMII device node.
2299 For Axon: phandle of plb5/plb4/opb/rgmii
2300 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
2301 RGMII channel is used by this EMAC.
2302 Fox Axon: present, whatever value is appropriate for each
2303 EMAC, that is the content of the current (bogus) "phy-port"
2304 property.
2306 Optional properties:
2307 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
2308 a search is performed.
2309 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
2310 for, used if phy-address is absent. bit 0x00000001 is
2311 MDIO address 0.
2312 For Axon it can be absent, thouugh my current driver
2313 doesn't handle phy-address yet so for now, keep
2314 0x00ffffff in it.
2315 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
2316 operations (if absent the value is the same as
2317 rx-fifo-size). For Axon, either absent or 2048.
2318 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
2319 operations (if absent the value is the same as
2320 tx-fifo-size). For Axon, either absent or 2048.
2321 - tah-device : 1 cell, optional. If connected to a TAH engine for
2322 offload, phandle of the TAH device node.
2323 - tah-channel : 1 cell, optional. If appropriate, channel used on the
2324 TAH engine.
2326 Example:
2328 EMAC0: ethernet@40000800 {
2329 device_type = "network";
2330 compatible = "ibm,emac-440gp", "ibm,emac";
2331 interrupt-parent = <&UIC1>;
2332 interrupts = <1c 4 1d 4>;
2333 reg = <40000800 70>;
2334 local-mac-address = [00 04 AC E3 1B 1E];
2335 mal-device = <&MAL0>;
2336 mal-tx-channel = <0 1>;
2337 mal-rx-channel = <0>;
2338 cell-index = <0>;
2339 max-frame-size = <5dc>;
2340 rx-fifo-size = <1000>;
2341 tx-fifo-size = <800>;
2342 phy-mode = "rmii";
2343 phy-map = <00000001>;
2344 zmii-device = <&ZMII0>;
2345 zmii-channel = <0>;
2346 };
2348 ii) McMAL node
2350 Required properties:
2351 - device_type : "dma-controller"
2352 - compatible : compatible list, containing 2 entries, first is
2353 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
2354 emac) and the second is either "ibm,mcmal" or
2355 "ibm,mcmal2".
2356 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
2357 - interrupts : <interrupt mapping for the MAL interrupts sources:
2358 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
2359 For Axon: This is _different_ from the current
2360 firmware. We use the "delayed" interrupts for txeob
2361 and rxeob. Thus we end up with mapping those 5 MPIC
2362 interrupts, all level positive sensitive: 10, 11, 32,
2363 33, 34 (in decimal)
2364 - dcr-reg : < DCR registers range >
2365 - dcr-parent : if needed for dcr-reg
2366 - num-tx-chans : 1 cell, number of Tx channels
2367 - num-rx-chans : 1 cell, number of Rx channels
2369 iii) ZMII node
2371 Required properties:
2372 - compatible : compatible list, containing 2 entries, first is
2373 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
2374 EMAC) and the second is "ibm,zmii".
2375 For Axon, there is no ZMII node.
2376 - reg : <registers mapping>
2378 iv) RGMII node
2380 Required properties:
2381 - compatible : compatible list, containing 2 entries, first is
2382 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
2383 EMAC) and the second is "ibm,rgmii".
2384 For Axon, "ibm,rgmii-axon","ibm,rgmii"
2385 - reg : <registers mapping>
2386 - revision : as provided by the RGMII new version register if
2387 available.
2388 For Axon: 0x0000012a
2390 o) Xilinx IP cores
2392 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
2393 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
2394 of standard device types (network, serial, etc.) and miscellanious
2395 devices (gpio, LCD, spi, etc). Also, since these devices are
2396 implemented within the fpga fabric every instance of the device can be
2397 synthesised with different options that change the behaviour.
2399 Each IP-core has a set of parameters which the FPGA designer can use to
2400 control how the core is synthesized. Historically, the EDK tool would
2401 extract the device parameters relevant to device drivers and copy them
2402 into an 'xparameters.h' in the form of #define symbols. This tells the
2403 device drivers how the IP cores are configured, but it requres the kernel
2404 to be recompiled every time the FPGA bitstream is resynthesized.
2406 The new approach is to export the parameters into the device tree and
2407 generate a new device tree each time the FPGA bitstream changes. The
2408 parameters which used to be exported as #defines will now become
2409 properties of the device node. In general, device nodes for IP-cores
2410 will take the following form:
2412 (name): (generic-name)@(base-address) {
2413 compatible = "xlnx,(ip-core-name)-(HW_VER)"
2414 [, (list of compatible devices), ...];
2415 reg = <(baseaddr) (size)>;
2416 interrupt-parent = <&interrupt-controller-phandle>;
2417 interrupts = < ... >;
2418 xlnx,(parameter1) = "(string-value)";
2419 xlnx,(parameter2) = <(int-value)>;
2420 };
2422 (generic-name): an open firmware-style name that describes the
2423 generic class of device. Preferably, this is one word, such
2424 as 'serial' or 'ethernet'.
2425 (ip-core-name): the name of the ip block (given after the BEGIN
2426 directive in system.mhs). Should be in lowercase
2427 and all underscores '_' converted to dashes '-'.
2428 (name): is derived from the "PARAMETER INSTANCE" value.
2429 (parameter#): C_* parameters from system.mhs. The C_ prefix is
2430 dropped from the parameter name, the name is converted
2431 to lowercase and all underscore '_' characters are
2432 converted to dashes '-'.
2433 (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
2434 (HW_VER): from the HW_VER parameter.
2435 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
2437 Typically, the compatible list will include the exact IP core version
2438 followed by an older IP core version which implements the same
2439 interface or any other device with the same interface.
2441 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
2443 For example, the following block from system.mhs:
2445 BEGIN opb_uartlite
2446 PARAMETER INSTANCE = opb_uartlite_0
2447 PARAMETER HW_VER = 1.00.b
2448 PARAMETER C_BAUDRATE = 115200
2449 PARAMETER C_DATA_BITS = 8
2450 PARAMETER C_ODD_PARITY = 0
2451 PARAMETER C_USE_PARITY = 0
2452 PARAMETER C_CLK_FREQ = 50000000
2453 PARAMETER C_BASEADDR = 0xEC100000
2454 PARAMETER C_HIGHADDR = 0xEC10FFFF
2455 BUS_INTERFACE SOPB = opb_7
2456 PORT OPB_Clk = CLK_50MHz
2457 PORT Interrupt = opb_uartlite_0_Interrupt
2458 PORT RX = opb_uartlite_0_RX
2459 PORT TX = opb_uartlite_0_TX
2460 PORT OPB_Rst = sys_bus_reset_0
2461 END
2463 becomes the following device tree node:
2465 opb_uartlite_0: serial@ec100000 {
2466 device_type = "serial";
2467 compatible = "xlnx,opb-uartlite-1.00.b";
2468 reg = <ec100000 10000>;
2469 interrupt-parent = <&opb_intc_0>;
2470 interrupts = <1 0>; // got this from the opb_intc parameters
2471 current-speed = <d#115200>; // standard serial device prop
2472 clock-frequency = <d#50000000>; // standard serial device prop
2473 xlnx,data-bits = <8>;
2474 xlnx,odd-parity = <0>;
2475 xlnx,use-parity = <0>;
2476 };
2478 Some IP cores actually implement 2 or more logical devices. In
2479 this case, the device should still describe the whole IP core with
2480 a single node and add a child node for each logical device. The
2481 ranges property can be used to translate from parent IP-core to the
2482 registers of each device. In addition, the parent node should be
2483 compatible with the bus type 'xlnx,compound', and should contain
2484 #address-cells and #size-cells, as with any other bus. (Note: this
2485 makes the assumption that both logical devices have the same bus
2486 binding. If this is not true, then separate nodes should be used
2487 for each logical device). The 'cell-index' property can be used to
2488 enumerate logical devices within an IP core. For example, the
2489 following is the system.mhs entry for the dual ps2 controller found
2490 on the ml403 reference design.
2492 BEGIN opb_ps2_dual_ref
2493 PARAMETER INSTANCE = opb_ps2_dual_ref_0
2494 PARAMETER HW_VER = 1.00.a
2495 PARAMETER C_BASEADDR = 0xA9000000
2496 PARAMETER C_HIGHADDR = 0xA9001FFF
2497 BUS_INTERFACE SOPB = opb_v20_0
2498 PORT Sys_Intr1 = ps2_1_intr
2499 PORT Sys_Intr2 = ps2_2_intr
2500 PORT Clkin1 = ps2_clk_rx_1
2501 PORT Clkin2 = ps2_clk_rx_2
2502 PORT Clkpd1 = ps2_clk_tx_1
2503 PORT Clkpd2 = ps2_clk_tx_2
2504 PORT Rx1 = ps2_d_rx_1
2505 PORT Rx2 = ps2_d_rx_2
2506 PORT Txpd1 = ps2_d_tx_1
2507 PORT Txpd2 = ps2_d_tx_2
2508 END
2510 It would result in the following device tree nodes:
2512 opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
2513 #address-cells = <1>;
2514 #size-cells = <1>;
2515 compatible = "xlnx,compound";
2516 ranges = <0 a9000000 2000>;
2517 // If this device had extra parameters, then they would
2518 // go here.
2519 ps2@0 {
2520 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
2521 reg = <0 40>;
2522 interrupt-parent = <&opb_intc_0>;
2523 interrupts = <3 0>;
2524 cell-index = <0>;
2525 };
2526 ps2@1000 {
2527 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
2528 reg = <1000 40>;
2529 interrupt-parent = <&opb_intc_0>;
2530 interrupts = <3 0>;
2531 cell-index = <0>;
2532 };
2533 };
2535 Also, the system.mhs file defines bus attachments from the processor
2536 to the devices. The device tree structure should reflect the bus
2537 attachments. Again an example; this system.mhs fragment:
2539 BEGIN ppc405_virtex4
2540 PARAMETER INSTANCE = ppc405_0
2541 PARAMETER HW_VER = 1.01.a
2542 BUS_INTERFACE DPLB = plb_v34_0
2543 BUS_INTERFACE IPLB = plb_v34_0
2544 END
2546 BEGIN opb_intc
2547 PARAMETER INSTANCE = opb_intc_0
2548 PARAMETER HW_VER = 1.00.c
2549 PARAMETER C_BASEADDR = 0xD1000FC0
2550 PARAMETER C_HIGHADDR = 0xD1000FDF
2551 BUS_INTERFACE SOPB = opb_v20_0
2552 END
2554 BEGIN opb_uart16550
2555 PARAMETER INSTANCE = opb_uart16550_0
2556 PARAMETER HW_VER = 1.00.d
2557 PARAMETER C_BASEADDR = 0xa0000000
2558 PARAMETER C_HIGHADDR = 0xa0001FFF
2559 BUS_INTERFACE SOPB = opb_v20_0
2560 END
2562 BEGIN plb_v34
2563 PARAMETER INSTANCE = plb_v34_0
2564 PARAMETER HW_VER = 1.02.a
2565 END
2567 BEGIN plb_bram_if_cntlr
2568 PARAMETER INSTANCE = plb_bram_if_cntlr_0
2569 PARAMETER HW_VER = 1.00.b
2570 PARAMETER C_BASEADDR = 0xFFFF0000
2571 PARAMETER C_HIGHADDR = 0xFFFFFFFF
2572 BUS_INTERFACE SPLB = plb_v34_0
2573 END
2575 BEGIN plb2opb_bridge
2576 PARAMETER INSTANCE = plb2opb_bridge_0
2577 PARAMETER HW_VER = 1.01.a
2578 PARAMETER C_RNG0_BASEADDR = 0x20000000
2579 PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
2580 PARAMETER C_RNG1_BASEADDR = 0x60000000
2581 PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
2582 PARAMETER C_RNG2_BASEADDR = 0x80000000
2583 PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
2584 PARAMETER C_RNG3_BASEADDR = 0xC0000000
2585 PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
2586 BUS_INTERFACE SPLB = plb_v34_0
2587 BUS_INTERFACE MOPB = opb_v20_0
2588 END
2590 Gives this device tree (some properties removed for clarity):
2592 plb@0 {
2593 #address-cells = <1>;
2594 #size-cells = <1>;
2595 compatible = "xlnx,plb-v34-1.02.a";
2596 device_type = "ibm,plb";
2597 ranges; // 1:1 translation
2599 plb_bram_if_cntrl_0: bram@ffff0000 {
2600 reg = <ffff0000 10000>;
2601 }
2603 opb@20000000 {
2604 #address-cells = <1>;
2605 #size-cells = <1>;
2606 ranges = <20000000 20000000 20000000
2607 60000000 60000000 20000000
2608 80000000 80000000 40000000
2609 c0000000 c0000000 20000000>;
2611 opb_uart16550_0: serial@a0000000 {
2612 reg = <a00000000 2000>;
2613 };
2615 opb_intc_0: interrupt-controller@d1000fc0 {
2616 reg = <d1000fc0 20>;
2617 };
2618 };
2619 };
2621 That covers the general approach to binding xilinx IP cores into the
2622 device tree. The following are bindings for specific devices:
2624 i) Xilinx ML300 Framebuffer
2626 Simple framebuffer device from the ML300 reference design (also on the
2627 ML403 reference design as well as others).
2629 Optional properties:
2630 - resolution = <xres yres> : pixel resolution of framebuffer. Some
2631 implementations use a different resolution.
2632 Default is <d#640 d#480>
2633 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
2634 Default is <d#1024 d#480>.
2635 - rotate-display (empty) : rotate display 180 degrees.
2637 ii) Xilinx SystemACE
2639 The Xilinx SystemACE device is used to program FPGAs from an FPGA
2640 bitstream stored on a CF card. It can also be used as a generic CF
2641 interface device.
2643 Optional properties:
2644 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
2646 iii) Xilinx EMAC and Xilinx TEMAC
2648 Xilinx Ethernet devices. In addition to general xilinx properties
2649 listed above, nodes for these devices should include a phy-handle
2650 property, and may include other common network device properties
2651 like local-mac-address.
2653 iv) Xilinx Uartlite
2655 Xilinx uartlite devices are simple fixed speed serial ports.
2657 Requred properties:
2658 - current-speed : Baud rate of uartlite
2660 v) Xilinx hwicap
2662 Xilinx hwicap devices provide access to the configuration logic
2663 of the FPGA through the Internal Configuration Access Port
2664 (ICAP). The ICAP enables partial reconfiguration of the FPGA,
2665 readback of the configuration information, and some control over
2666 'warm boots' of the FPGA fabric.
2668 Required properties:
2669 - xlnx,family : The family of the FPGA, necessary since the
2670 capabilities of the underlying ICAP hardware
2671 differ between different families. May be
2672 'virtex2p', 'virtex4', or 'virtex5'.
2674 vi) Xilinx Uart 16550
2676 Xilinx UART 16550 devices are very similar to the NS16550 but with
2677 different register spacing and an offset from the base address.
2679 Requred properties:
2680 - clock-frequency : Frequency of the clock input
2681 - reg-offset : A value of 3 is required
2682 - reg-shift : A value of 2 is required
2685 p) Freescale Synchronous Serial Interface
2687 The SSI is a serial device that communicates with audio codecs. It can
2688 be programmed in AC97, I2S, left-justified, or right-justified modes.
2690 Required properties:
2691 - compatible : compatible list, containing "fsl,ssi"
2692 - cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
2693 - reg : offset and length of the register set for the device
2694 - interrupts : <a b> where a is the interrupt number and b is a
2695 field that represents an encoding of the sense and
2696 level information for the interrupt. This should be
2697 encoded based on the information in section 2)
2698 depending on the type of interrupt controller you
2699 have.
2700 - interrupt-parent : the phandle for the interrupt controller that
2701 services interrupts for this device.
2702 - fsl,mode : the operating mode for the SSI interface
2703 "i2s-slave" - I2S mode, SSI is clock slave
2704 "i2s-master" - I2S mode, SSI is clock master
2705 "lj-slave" - left-justified mode, SSI is clock slave
2706 "lj-master" - l.j. mode, SSI is clock master
2707 "rj-slave" - right-justified mode, SSI is clock slave
2708 "rj-master" - r.j., SSI is clock master
2709 "ac97-slave" - AC97 mode, SSI is clock slave
2710 "ac97-master" - AC97 mode, SSI is clock master
2712 Optional properties:
2713 - codec-handle : phandle to a 'codec' node that defines an audio
2714 codec connected to this SSI. This node is typically
2715 a child of an I2C or other control node.
2717 Child 'codec' node required properties:
2718 - compatible : compatible list, contains the name of the codec
2720 Child 'codec' node optional properties:
2721 - clock-frequency : The frequency of the input clock, which typically
2722 comes from an on-board dedicated oscillator.
2724 * Freescale 83xx DMA Controller
2726 Freescale PowerPC 83xx have on chip general purpose DMA controllers.
2728 Required properties:
2730 - compatible : compatible list, contains 2 entries, first is
2731 "fsl,CHIP-dma", where CHIP is the processor
2732 (mpc8349, mpc8360, etc.) and the second is
2733 "fsl,elo-dma"
2734 - reg : <registers mapping for DMA general status reg>
2735 - ranges : Should be defined as specified in 1) to describe the
2736 DMA controller channels.
2737 - cell-index : controller index. 0 for controller @ 0x8100
2738 - interrupts : <interrupt mapping for DMA IRQ>
2739 - interrupt-parent : optional, if needed for interrupt mapping
2742 - DMA channel nodes:
2743 - compatible : compatible list, contains 2 entries, first is
2744 "fsl,CHIP-dma-channel", where CHIP is the processor
2745 (mpc8349, mpc8350, etc.) and the second is
2746 "fsl,elo-dma-channel"
2747 - reg : <registers mapping for channel>
2748 - cell-index : dma channel index starts at 0.
2750 Optional properties:
2751 - interrupts : <interrupt mapping for DMA channel IRQ>
2752 (on 83xx this is expected to be identical to
2753 the interrupts property of the parent node)
2754 - interrupt-parent : optional, if needed for interrupt mapping
2756 Example:
2757 dma@82a8 {
2758 #address-cells = <1>;
2759 #size-cells = <1>;
2760 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
2761 reg = <82a8 4>;
2762 ranges = <0 8100 1a4>;
2763 interrupt-parent = <&ipic>;
2764 interrupts = <47 8>;
2765 cell-index = <0>;
2766 dma-channel@0 {
2767 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2768 cell-index = <0>;
2769 reg = <0 80>;
2770 };
2771 dma-channel@80 {
2772 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2773 cell-index = <1>;
2774 reg = <80 80>;
2775 };
2776 dma-channel@100 {
2777 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2778 cell-index = <2>;
2779 reg = <100 80>;
2780 };
2781 dma-channel@180 {
2782 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2783 cell-index = <3>;
2784 reg = <180 80>;
2785 };
2786 };
2788 * Freescale 85xx/86xx DMA Controller
2790 Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
2792 Required properties:
2794 - compatible : compatible list, contains 2 entries, first is
2795 "fsl,CHIP-dma", where CHIP is the processor
2796 (mpc8540, mpc8540, etc.) and the second is
2797 "fsl,eloplus-dma"
2798 - reg : <registers mapping for DMA general status reg>
2799 - cell-index : controller index. 0 for controller @ 0x21000,
2800 1 for controller @ 0xc000
2801 - ranges : Should be defined as specified in 1) to describe the
2802 DMA controller channels.
2804 - DMA channel nodes:
2805 - compatible : compatible list, contains 2 entries, first is
2806 "fsl,CHIP-dma-channel", where CHIP is the processor
2807 (mpc8540, mpc8560, etc.) and the second is
2808 "fsl,eloplus-dma-channel"
2809 - cell-index : dma channel index starts at 0.
2810 - reg : <registers mapping for channel>
2811 - interrupts : <interrupt mapping for DMA channel IRQ>
2812 - interrupt-parent : optional, if needed for interrupt mapping
2814 Example:
2815 dma@21300 {
2816 #address-cells = <1>;
2817 #size-cells = <1>;
2818 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
2819 reg = <21300 4>;
2820 ranges = <0 21100 200>;
2821 cell-index = <0>;
2822 dma-channel@0 {
2823 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2824 reg = <0 80>;
2825 cell-index = <0>;
2826 interrupt-parent = <&mpic>;
2827 interrupts = <14 2>;
2828 };
2829 dma-channel@80 {
2830 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2831 reg = <80 80>;
2832 cell-index = <1>;
2833 interrupt-parent = <&mpic>;
2834 interrupts = <15 2>;
2835 };
2836 dma-channel@100 {
2837 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2838 reg = <100 80>;
2839 cell-index = <2>;
2840 interrupt-parent = <&mpic>;
2841 interrupts = <16 2>;
2842 };
2843 dma-channel@180 {
2844 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2845 reg = <180 80>;
2846 cell-index = <3>;
2847 interrupt-parent = <&mpic>;
2848 interrupts = <17 2>;
2849 };
2850 };
2852 * Freescale 8xxx/3.0 Gb/s SATA nodes
2854 SATA nodes are defined to describe on-chip Serial ATA controllers.
2855 Each SATA port should have its own node.
2857 Required properties:
2858 - compatible : compatible list, contains 2 entries, first is
2859 "fsl,CHIP-sata", where CHIP is the processor
2860 (mpc8315, mpc8379, etc.) and the second is
2861 "fsl,pq-sata"
2862 - interrupts : <interrupt mapping for SATA IRQ>
2863 - cell-index : controller index.
2864 1 for controller @ 0x18000
2865 2 for controller @ 0x19000
2866 3 for controller @ 0x1a000
2867 4 for controller @ 0x1b000
2869 Optional properties:
2870 - interrupt-parent : optional, if needed for interrupt mapping
2871 - reg : <registers mapping>
2873 Example:
2875 sata@18000 {
2876 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
2877 reg = <0x18000 0x1000>;
2878 cell-index = <1>;
2879 interrupts = <2c 8>;
2880 interrupt-parent = < &ipic >;
2881 };
2883 q) USB EHCI controllers
2885 Required properties:
2886 - compatible : should be "usb-ehci".
2887 - reg : should contain at least address and length of the standard EHCI
2888 register set for the device. Optional platform-dependent registers
2889 (debug-port or other) can be also specified here, but only after
2890 definition of standard EHCI registers.
2891 - interrupts : one EHCI interrupt should be described here.
2892 If device registers are implemented in big endian mode, the device
2893 node should have "big-endian-regs" property.
2894 If controller implementation operates with big endian descriptors,
2895 "big-endian-desc" property should be specified.
2896 If both big endian registers and descriptors are used by the controller
2897 implementation, "big-endian" property can be specified instead of having
2898 both "big-endian-regs" and "big-endian-desc".
2900 Example (Sequoia 440EPx):
2901 ehci@e0000300 {
2902 compatible = "ibm,usb-ehci-440epx", "usb-ehci";
2903 interrupt-parent = <&UIC0>;
2904 interrupts = <1a 4>;
2905 reg = <0 e0000300 90 0 e0000390 70>;
2906 big-endian;
2907 };
2909 r) Freescale Display Interface Unit
2911 The Freescale DIU is a LCD controller, with proper hardware, it can also
2912 drive DVI monitors.
2914 Required properties:
2915 - compatible : should be "fsl-diu".
2916 - reg : should contain at least address and length of the DIU register
2917 set.
2918 - Interrupts : one DIU interrupt should be describe here.
2920 Example (MPC8610HPCD)
2921 display@2c000 {
2922 compatible = "fsl,diu";
2923 reg = <0x2c000 100>;
2924 interrupts = <72 2>;
2925 interrupt-parent = <&mpic>;
2926 };
2928 s) Freescale on board FPGA
2930 This is the memory-mapped registers for on board FPGA.
2932 Required properities:
2933 - compatible : should be "fsl,fpga-pixis".
2934 - reg : should contain the address and the lenght of the FPPGA register
2935 set.
2937 Example (MPC8610HPCD)
2938 board-control@e8000000 {
2939 compatible = "fsl,fpga-pixis";
2940 reg = <0xe8000000 32>;
2941 };
2943 t) Freescale MSI interrupt controller
2945 Reguired properities:
2946 - compatible : compatible list, contains 2 entries,
2947 first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
2948 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
2949 the parent type.
2950 - reg : should contain the address and the length of the shared message
2951 interrupt register set.
2952 - msi-available-ranges: use <start count> style section to define which
2953 msi interrupt can be used in the 256 msi interrupts. This property is
2954 optional, without this, all the 256 MSI interrupts can be used.
2955 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
2956 and routed to the host interrupt controller. the interrupts should
2957 be set as edge sensitive.
2958 - interrupt-parent: the phandle for the interrupt controller
2959 that services interrupts for this device. for 83xx cpu, the interrupts
2960 are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
2961 to MPIC.
2963 Example
2964 msi@41600 {
2965 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
2966 reg = <0x41600 0x80>;
2967 msi-available-ranges = <0 0x100>;
2968 interrupts = <
2969 0xe0 0
2970 0xe1 0
2971 0xe2 0
2972 0xe3 0
2973 0xe4 0
2974 0xe5 0
2975 0xe6 0
2976 0xe7 0>;
2977 interrupt-parent = <&mpic>;
2978 };
2980 u) Freescale General-purpose Timers Module
2982 Required properties:
2983 - compatible : should be
2984 "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
2985 "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
2986 "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
2987 - reg : should contain gtm registers location and length (0x40).
2988 - interrupts : should contain four interrupts.
2989 - interrupt-parent : interrupt source phandle.
2990 - clock-frequency : specifies the frequency driving the timer.
2992 Example:
2994 timer@500 {
2995 compatible = "fsl,mpc8360-gtm", "fsl,gtm";
2996 reg = <0x500 0x40>;
2997 interrupts = <90 8 78 8 84 8 72 8>;
2998 interrupt-parent = <&ipic>;
2999 /* filled by u-boot */
3000 clock-frequency = <0>;
3001 };
3003 timer@440 {
3004 compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
3005 reg = <0x440 0x40>;
3006 interrupts = <12 13 14 15>;
3007 interrupt-parent = <&qeic>;
3008 /* filled by u-boot */
3009 clock-frequency = <0>;
3010 };
3012 VII - Marvell Discovery mv64[345]6x System Controller chips
3013 ===========================================================
3015 The Marvell mv64[345]60 series of system controller chips contain
3016 many of the peripherals needed to implement a complete computer
3017 system. In this section, we define device tree nodes to describe
3018 the system controller chip itself and each of the peripherals
3019 which it contains. Compatible string values for each node are
3020 prefixed with the string "marvell,", for Marvell Technology Group Ltd.
3022 1) The /system-controller node
3024 This node is used to represent the system-controller and must be
3025 present when the system uses a system contller chip. The top-level
3026 system-controller node contains information that is global to all
3027 devices within the system controller chip. The node name begins
3028 with "system-controller" followed by the unit address, which is
3029 the base address of the memory-mapped register set for the system
3030 controller chip.
3032 Required properties:
3034 - ranges : Describes the translation of system controller addresses
3035 for memory mapped registers.
3036 - clock-frequency: Contains the main clock frequency for the system
3037 controller chip.
3038 - reg : This property defines the address and size of the
3039 memory-mapped registers contained within the system controller
3040 chip. The address specified in the "reg" property should match
3041 the unit address of the system-controller node.
3042 - #address-cells : Address representation for system controller
3043 devices. This field represents the number of cells needed to
3044 represent the address of the memory-mapped registers of devices
3045 within the system controller chip.
3046 - #size-cells : Size representation for for the memory-mapped
3047 registers within the system controller chip.
3048 - #interrupt-cells : Defines the width of cells used to represent
3049 interrupts.
3051 Optional properties:
3053 - model : The specific model of the system controller chip. Such
3054 as, "mv64360", "mv64460", or "mv64560".
3055 - compatible : A string identifying the compatibility identifiers
3056 of the system controller chip.
3058 The system-controller node contains child nodes for each system
3059 controller device that the platform uses. Nodes should not be created
3060 for devices which exist on the system controller chip but are not used
3062 Example Marvell Discovery mv64360 system-controller node:
3064 system-controller@f1000000 { /* Marvell Discovery mv64360 */
3065 #address-cells = <1>;
3066 #size-cells = <1>;
3067 model = "mv64360"; /* Default */
3068 compatible = "marvell,mv64360";
3069 clock-frequency = <133333333>;
3070 reg = <0xf1000000 0x10000>;
3071 virtual-reg = <0xf1000000>;
3072 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
3073 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
3074 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
3075 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
3076 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
3078 [ child node definitions... ]
3079 }
3081 2) Child nodes of /system-controller
3083 a) Marvell Discovery MDIO bus
3085 The MDIO is a bus to which the PHY devices are connected. For each
3086 device that exists on this bus, a child node should be created. See
3087 the definition of the PHY node below for an example of how to define
3088 a PHY.
3090 Required properties:
3091 - #address-cells : Should be <1>
3092 - #size-cells : Should be <0>
3093 - device_type : Should be "mdio"
3094 - compatible : Should be "marvell,mv64360-mdio"
3096 Example:
3098 mdio {
3099 #address-cells = <1>;
3100 #size-cells = <0>;
3101 device_type = "mdio";
3102 compatible = "marvell,mv64360-mdio";
3104 ethernet-phy@0 {
3105 ......
3106 };
3107 };
3110 b) Marvell Discovery ethernet controller
3112 The Discover ethernet controller is described with two levels
3113 of nodes. The first level describes an ethernet silicon block
3114 and the second level describes up to 3 ethernet nodes within
3115 that block. The reason for the multiple levels is that the
3116 registers for the node are interleaved within a single set
3117 of registers. The "ethernet-block" level describes the
3118 shared register set, and the "ethernet" nodes describe ethernet
3119 port-specific properties.
3121 Ethernet block node
3123 Required properties:
3124 - #address-cells : <1>
3125 - #size-cells : <0>
3126 - compatible : "marvell,mv64360-eth-block"
3127 - reg : Offset and length of the register set for this block
3129 Example Discovery Ethernet block node:
3130 ethernet-block@2000 {
3131 #address-cells = <1>;
3132 #size-cells = <0>;
3133 compatible = "marvell,mv64360-eth-block";
3134 reg = <0x2000 0x2000>;
3135 ethernet@0 {
3136 .......
3137 };
3138 };
3140 Ethernet port node
3142 Required properties:
3143 - device_type : Should be "network".
3144 - compatible : Should be "marvell,mv64360-eth".
3145 - reg : Should be <0>, <1>, or <2>, according to which registers
3146 within the silicon block the device uses.
3147 - interrupts : <a> where a is the interrupt number for the port.
3148 - interrupt-parent : the phandle for the interrupt controller
3149 that services interrupts for this device.
3150 - phy : the phandle for the PHY connected to this ethernet
3151 controller.
3152 - local-mac-address : 6 bytes, MAC address
3154 Example Discovery Ethernet port node:
3155 ethernet@0 {
3156 device_type = "network";
3157 compatible = "marvell,mv64360-eth";
3158 reg = <0>;
3159 interrupts = <32>;
3160 interrupt-parent = <&PIC>;
3161 phy = <&PHY0>;
3162 local-mac-address = [ 00 00 00 00 00 00 ];
3163 };
3167 c) Marvell Discovery PHY nodes
3169 Required properties:
3170 - device_type : Should be "ethernet-phy"
3171 - interrupts : <a> where a is the interrupt number for this phy.
3172 - interrupt-parent : the phandle for the interrupt controller that
3173 services interrupts for this device.
3174 - reg : The ID number for the phy, usually a small integer
3176 Example Discovery PHY node:
3177 ethernet-phy@1 {
3178 device_type = "ethernet-phy";
3179 compatible = "broadcom,bcm5421";
3180 interrupts = <76>; /* GPP 12 */
3181 interrupt-parent = <&PIC>;
3182 reg = <1>;
3183 };
3186 d) Marvell Discovery SDMA nodes
3188 Represent DMA hardware associated with the MPSC (multiprotocol
3189 serial controllers).
3191 Required properties:
3192 - compatible : "marvell,mv64360-sdma"
3193 - reg : Offset and length of the register set for this device
3194 - interrupts : <a> where a is the interrupt number for the DMA
3195 device.
3196 - interrupt-parent : the phandle for the interrupt controller
3197 that services interrupts for this device.
3199 Example Discovery SDMA node:
3200 sdma@4000 {
3201 compatible = "marvell,mv64360-sdma";
3202 reg = <0x4000 0xc18>;
3203 virtual-reg = <0xf1004000>;
3204 interrupts = <36>;
3205 interrupt-parent = <&PIC>;
3206 };
3209 e) Marvell Discovery BRG nodes
3211 Represent baud rate generator hardware associated with the MPSC
3212 (multiprotocol serial controllers).
3214 Required properties:
3215 - compatible : "marvell,mv64360-brg"
3216 - reg : Offset and length of the register set for this device
3217 - clock-src : A value from 0 to 15 which selects the clock
3218 source for the baud rate generator. This value corresponds
3219 to the CLKS value in the BRGx configuration register. See
3220 the mv64x60 User's Manual.
3221 - clock-frequence : The frequency (in Hz) of the baud rate
3222 generator's input clock.
3223 - current-speed : The current speed setting (presumably by
3224 firmware) of the baud rate generator.
3226 Example Discovery BRG node:
3227 brg@b200 {
3228 compatible = "marvell,mv64360-brg";
3229 reg = <0xb200 0x8>;
3230 clock-src = <8>;
3231 clock-frequency = <133333333>;
3232 current-speed = <9600>;
3233 };
3236 f) Marvell Discovery CUNIT nodes
3238 Represent the Serial Communications Unit device hardware.
3240 Required properties:
3241 - reg : Offset and length of the register set for this device
3243 Example Discovery CUNIT node:
3244 cunit@f200 {
3245 reg = <0xf200 0x200>;
3246 };
3249 g) Marvell Discovery MPSCROUTING nodes
3251 Represent the Discovery's MPSC routing hardware
3253 Required properties:
3254 - reg : Offset and length of the register set for this device
3256 Example Discovery CUNIT node:
3257 mpscrouting@b500 {
3258 reg = <0xb400 0xc>;
3259 };
3262 h) Marvell Discovery MPSCINTR nodes
3264 Represent the Discovery's MPSC DMA interrupt hardware registers
3265 (SDMA cause and mask registers).
3267 Required properties:
3268 - reg : Offset and length of the register set for this device
3270 Example Discovery MPSCINTR node:
3271 mpsintr@b800 {
3272 reg = <0xb800 0x100>;
3273 };
3276 i) Marvell Discovery MPSC nodes
3278 Represent the Discovery's MPSC (Multiprotocol Serial Controller)
3279 serial port.
3281 Required properties:
3282 - device_type : "serial"
3283 - compatible : "marvell,mv64360-mpsc"
3284 - reg : Offset and length of the register set for this device
3285 - sdma : the phandle for the SDMA node used by this port
3286 - brg : the phandle for the BRG node used by this port
3287 - cunit : the phandle for the CUNIT node used by this port
3288 - mpscrouting : the phandle for the MPSCROUTING node used by this port
3289 - mpscintr : the phandle for the MPSCINTR node used by this port
3290 - cell-index : the hardware index of this cell in the MPSC core
3291 - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
3292 register
3293 - interrupts : <a> where a is the interrupt number for the MPSC.
3294 - interrupt-parent : the phandle for the interrupt controller
3295 that services interrupts for this device.
3297 Example Discovery MPSCINTR node:
3298 mpsc@8000 {
3299 device_type = "serial";
3300 compatible = "marvell,mv64360-mpsc";
3301 reg = <0x8000 0x38>;
3302 virtual-reg = <0xf1008000>;
3303 sdma = <&SDMA0>;
3304 brg = <&BRG0>;
3305 cunit = <&CUNIT>;
3306 mpscrouting = <&MPSCROUTING>;
3307 mpscintr = <&MPSCINTR>;
3308 cell-index = <0>;
3309 max_idle = <40>;
3310 interrupts = <40>;
3311 interrupt-parent = <&PIC>;
3312 };
3315 j) Marvell Discovery Watch Dog Timer nodes
3317 Represent the Discovery's watchdog timer hardware
3319 Required properties:
3320 - compatible : "marvell,mv64360-wdt"
3321 - reg : Offset and length of the register set for this device
3323 Example Discovery Watch Dog Timer node:
3324 wdt@b410 {
3325 compatible = "marvell,mv64360-wdt";
3326 reg = <0xb410 0x8>;
3327 };
3330 k) Marvell Discovery I2C nodes
3332 Represent the Discovery's I2C hardware
3334 Required properties:
3335 - device_type : "i2c"
3336 - compatible : "marvell,mv64360-i2c"
3337 - reg : Offset and length of the register set for this device
3338 - interrupts : <a> where a is the interrupt number for the I2C.
3339 - interrupt-parent : the phandle for the interrupt controller
3340 that services interrupts for this device.
3342 Example Discovery I2C node:
3343 compatible = "marvell,mv64360-i2c";
3344 reg = <0xc000 0x20>;
3345 virtual-reg = <0xf100c000>;
3346 interrupts = <37>;
3347 interrupt-parent = <&PIC>;
3348 };
3351 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
3353 Represent the Discovery's PIC hardware
3355 Required properties:
3356 - #interrupt-cells : <1>
3357 - #address-cells : <0>
3358 - compatible : "marvell,mv64360-pic"
3359 - reg : Offset and length of the register set for this device
3360 - interrupt-controller
3362 Example Discovery PIC node:
3363 pic {
3364 #interrupt-cells = <1>;
3365 #address-cells = <0>;
3366 compatible = "marvell,mv64360-pic";
3367 reg = <0x0 0x88>;
3368 interrupt-controller;
3369 };
3372 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
3374 Represent the Discovery's MPP hardware
3376 Required properties:
3377 - compatible : "marvell,mv64360-mpp"
3378 - reg : Offset and length of the register set for this device
3380 Example Discovery MPP node:
3381 mpp@f000 {
3382 compatible = "marvell,mv64360-mpp";
3383 reg = <0xf000 0x10>;
3384 };
3387 n) Marvell Discovery GPP (General Purpose Pins) nodes
3389 Represent the Discovery's GPP hardware
3391 Required properties:
3392 - compatible : "marvell,mv64360-gpp"
3393 - reg : Offset and length of the register set for this device
3395 Example Discovery GPP node:
3396 gpp@f000 {
3397 compatible = "marvell,mv64360-gpp";
3398 reg = <0xf100 0x20>;
3399 };
3402 o) Marvell Discovery PCI host bridge node
3404 Represents the Discovery's PCI host bridge device. The properties
3405 for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
3406 1275-1994. A typical value for the compatible property is
3407 "marvell,mv64360-pci".
3409 Example Discovery PCI host bridge node
3410 pci@80000000 {
3411 #address-cells = <3>;
3412 #size-cells = <2>;
3413 #interrupt-cells = <1>;
3414 device_type = "pci";
3415 compatible = "marvell,mv64360-pci";
3416 reg = <0xcf8 0x8>;
3417 ranges = <0x01000000 0x0 0x0
3418 0x88000000 0x0 0x01000000
3419 0x02000000 0x0 0x80000000
3420 0x80000000 0x0 0x08000000>;
3421 bus-range = <0 255>;
3422 clock-frequency = <66000000>;
3423 interrupt-parent = <&PIC>;
3424 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
3425 interrupt-map = <
3426 /* IDSEL 0x0a */
3427 0x5000 0 0 1 &PIC 80
3428 0x5000 0 0 2 &PIC 81
3429 0x5000 0 0 3 &PIC 91
3430 0x5000 0 0 4 &PIC 93
3432 /* IDSEL 0x0b */
3433 0x5800 0 0 1 &PIC 91
3434 0x5800 0 0 2 &PIC 93
3435 0x5800 0 0 3 &PIC 80
3436 0x5800 0 0 4 &PIC 81
3438 /* IDSEL 0x0c */
3439 0x6000 0 0 1 &PIC 91
3440 0x6000 0 0 2 &PIC 93
3441 0x6000 0 0 3 &PIC 80
3442 0x6000 0 0 4 &PIC 81
3444 /* IDSEL 0x0d */
3445 0x6800 0 0 1 &PIC 93
3446 0x6800 0 0 2 &PIC 80
3447 0x6800 0 0 3 &PIC 81
3448 0x6800 0 0 4 &PIC 91
3449 >;
3450 };
3453 p) Marvell Discovery CPU Error nodes
3455 Represent the Discovery's CPU error handler device.
3457 Required properties:
3458 - compatible : "marvell,mv64360-cpu-error"
3459 - reg : Offset and length of the register set for this device
3460 - interrupts : the interrupt number for this device
3461 - interrupt-parent : the phandle for the interrupt controller
3462 that services interrupts for this device.
3464 Example Discovery CPU Error node:
3465 cpu-error@0070 {
3466 compatible = "marvell,mv64360-cpu-error";
3467 reg = <0x70 0x10 0x128 0x28>;
3468 interrupts = <3>;
3469 interrupt-parent = <&PIC>;
3470 };
3473 q) Marvell Discovery SRAM Controller nodes
3475 Represent the Discovery's SRAM controller device.
3477 Required properties:
3478 - compatible : "marvell,mv64360-sram-ctrl"
3479 - reg : Offset and length of the register set for this device
3480 - interrupts : the interrupt number for this device
3481 - interrupt-parent : the phandle for the interrupt controller
3482 that services interrupts for this device.
3484 Example Discovery SRAM Controller node:
3485 sram-ctrl@0380 {
3486 compatible = "marvell,mv64360-sram-ctrl";
3487 reg = <0x380 0x80>;
3488 interrupts = <13>;
3489 interrupt-parent = <&PIC>;
3490 };
3493 r) Marvell Discovery PCI Error Handler nodes
3495 Represent the Discovery's PCI error handler device.
3497 Required properties:
3498 - compatible : "marvell,mv64360-pci-error"
3499 - reg : Offset and length of the register set for this device
3500 - interrupts : the interrupt number for this device
3501 - interrupt-parent : the phandle for the interrupt controller
3502 that services interrupts for this device.
3504 Example Discovery PCI Error Handler node:
3505 pci-error@1d40 {
3506 compatible = "marvell,mv64360-pci-error";
3507 reg = <0x1d40 0x40 0xc28 0x4>;
3508 interrupts = <12>;
3509 interrupt-parent = <&PIC>;
3510 };
3513 s) Marvell Discovery Memory Controller nodes
3515 Represent the Discovery's memory controller device.
3517 Required properties:
3518 - compatible : "marvell,mv64360-mem-ctrl"
3519 - reg : Offset and length of the register set for this device
3520 - interrupts : the interrupt number for this device
3521 - interrupt-parent : the phandle for the interrupt controller
3522 that services interrupts for this device.
3524 Example Discovery Memory Controller node:
3525 mem-ctrl@1400 {
3526 compatible = "marvell,mv64360-mem-ctrl";
3527 reg = <0x1400 0x60>;
3528 interrupts = <17>;
3529 interrupt-parent = <&PIC>;
3530 };
3533 VIII - Specifying interrupt information for devices
3534 ===================================================
3536 The device tree represents the busses and devices of a hardware
3537 system in a form similar to the physical bus topology of the
3538 hardware.
3540 In addition, a logical 'interrupt tree' exists which represents the
3541 hierarchy and routing of interrupts in the hardware.
3543 The interrupt tree model is fully described in the
3544 document "Open Firmware Recommended Practice: Interrupt
3545 Mapping Version 0.9". The document is available at:
3546 <http://playground.sun.com/1275/practice>.
3548 1) interrupts property
3549 ----------------------
3551 Devices that generate interrupts to a single interrupt controller
3552 should use the conventional OF representation described in the
3553 OF interrupt mapping documentation.
3555 Each device which generates interrupts must have an 'interrupt'
3556 property. The interrupt property value is an arbitrary number of
3557 of 'interrupt specifier' values which describe the interrupt or
3558 interrupts for the device.
3560 The encoding of an interrupt specifier is determined by the
3561 interrupt domain in which the device is located in the
3562 interrupt tree. The root of an interrupt domain specifies in
3563 its #interrupt-cells property the number of 32-bit cells
3564 required to encode an interrupt specifier. See the OF interrupt
3565 mapping documentation for a detailed description of domains.
3567 For example, the binding for the OpenPIC interrupt controller
3568 specifies an #interrupt-cells value of 2 to encode the interrupt
3569 number and level/sense information. All interrupt children in an
3570 OpenPIC interrupt domain use 2 cells per interrupt in their interrupts
3571 property.
3573 The PCI bus binding specifies a #interrupt-cell value of 1 to encode
3574 which interrupt pin (INTA,INTB,INTC,INTD) is used.
3576 2) interrupt-parent property
3577 ----------------------------
3579 The interrupt-parent property is specified to define an explicit
3580 link between a device node and its interrupt parent in
3581 the interrupt tree. The value of interrupt-parent is the
3582 phandle of the parent node.
3584 If the interrupt-parent property is not defined for a node, it's
3585 interrupt parent is assumed to be an ancestor in the node's
3586 _device tree_ hierarchy.
3588 3) OpenPIC Interrupt Controllers
3589 --------------------------------
3591 OpenPIC interrupt controllers require 2 cells to encode
3592 interrupt information. The first cell defines the interrupt
3593 number. The second cell defines the sense and level
3594 information.
3596 Sense and level information should be encoded as follows:
3598 0 = low to high edge sensitive type enabled
3599 1 = active low level sensitive type enabled
3600 2 = active high level sensitive type enabled
3601 3 = high to low edge sensitive type enabled
3603 4) ISA Interrupt Controllers
3604 ----------------------------
3606 ISA PIC interrupt controllers require 2 cells to encode
3607 interrupt information. The first cell defines the interrupt
3608 number. The second cell defines the sense and level
3609 information.
3611 ISA PIC interrupt controllers should adhere to the ISA PIC
3612 encodings listed below:
3614 0 = active low level sensitive type enabled
3615 1 = active high level sensitive type enabled
3616 2 = high to low edge sensitive type enabled
3617 3 = low to high edge sensitive type enabled
3619 VIII - Specifying GPIO information for devices
3620 ==============================================
3622 1) gpios property
3623 -----------------
3625 Nodes that makes use of GPIOs should define them using `gpios' property,
3626 format of which is: <&gpio-controller1-phandle gpio1-specifier
3627 &gpio-controller2-phandle gpio2-specifier
3628 0 /* holes are permitted, means no GPIO 3 */
3629 &gpio-controller4-phandle gpio4-specifier
3630 ...>;
3632 Note that gpio-specifier length is controller dependent.
3634 gpio-specifier may encode: bank, pin position inside the bank,
3635 whether pin is open-drain and whether pin is logically inverted.
3637 Example of the node using GPIOs:
3639 node {
3640 gpios = <&qe_pio_e 18 0>;
3641 };
3643 In this example gpio-specifier is "18 0" and encodes GPIO pin number,
3644 and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
3646 2) gpio-controller nodes
3647 ------------------------
3649 Every GPIO controller node must have #gpio-cells property defined,
3650 this information will be used to translate gpio-specifiers.
3652 Example of two SOC GPIO banks defined as gpio-controller nodes:
3654 qe_pio_a: gpio-controller@1400 {
3655 #gpio-cells = <2>;
3656 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
3657 reg = <0x1400 0x18>;
3658 gpio-controller;
3659 };
3661 qe_pio_e: gpio-controller@1460 {
3662 #gpio-cells = <2>;
3663 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
3664 reg = <0x1460 0x18>;
3665 gpio-controller;
3666 };
3668 Appendix A - Sample SOC node for MPC8540
3669 ========================================
3671 Note that the #address-cells and #size-cells for the SoC node
3672 in this example have been explicitly listed; these are likely
3673 not necessary as they are usually the same as the root node.
3675 soc8540@e0000000 {
3676 #address-cells = <1>;
3677 #size-cells = <1>;
3678 #interrupt-cells = <2>;
3679 device_type = "soc";
3680 ranges = <00000000 e0000000 00100000>
3681 reg = <e0000000 00003000>;
3682 bus-frequency = <0>;
3684 mdio@24520 {
3685 reg = <24520 20>;
3686 device_type = "mdio";
3687 compatible = "gianfar";
3689 ethernet-phy@0 {
3690 linux,phandle = <2452000>
3691 interrupt-parent = <40000>;
3692 interrupts = <35 1>;
3693 reg = <0>;
3694 device_type = "ethernet-phy";
3695 };
3697 ethernet-phy@1 {
3698 linux,phandle = <2452001>
3699 interrupt-parent = <40000>;
3700 interrupts = <35 1>;
3701 reg = <1>;
3702 device_type = "ethernet-phy";
3703 };
3705 ethernet-phy@3 {
3706 linux,phandle = <2452002>
3707 interrupt-parent = <40000>;
3708 interrupts = <35 1>;
3709 reg = <3>;
3710 device_type = "ethernet-phy";
3711 };
3713 };
3715 ethernet@24000 {
3716 #size-cells = <0>;
3717 device_type = "network";
3718 model = "TSEC";
3719 compatible = "gianfar";
3720 reg = <24000 1000>;
3721 mac-address = [ 00 E0 0C 00 73 00 ];
3722 interrupts = <d 3 e 3 12 3>;
3723 interrupt-parent = <40000>;
3724 phy-handle = <2452000>;
3725 };
3727 ethernet@25000 {
3728 #address-cells = <1>;
3729 #size-cells = <0>;
3730 device_type = "network";
3731 model = "TSEC";
3732 compatible = "gianfar";
3733 reg = <25000 1000>;
3734 mac-address = [ 00 E0 0C 00 73 01 ];
3735 interrupts = <13 3 14 3 18 3>;
3736 interrupt-parent = <40000>;
3737 phy-handle = <2452001>;
3738 };
3740 ethernet@26000 {
3741 #address-cells = <1>;
3742 #size-cells = <0>;
3743 device_type = "network";
3744 model = "FEC";
3745 compatible = "gianfar";
3746 reg = <26000 1000>;
3747 mac-address = [ 00 E0 0C 00 73 02 ];
3748 interrupts = <19 3>;
3749 interrupt-parent = <40000>;
3750 phy-handle = <2452002>;
3751 };
3753 serial@4500 {
3754 device_type = "serial";
3755 compatible = "ns16550";
3756 reg = <4500 100>;
3757 clock-frequency = <0>;
3758 interrupts = <1a 3>;
3759 interrupt-parent = <40000>;
3760 };
3762 pic@40000 {
3763 linux,phandle = <40000>;
3764 interrupt-controller;
3765 #address-cells = <0>;
3766 reg = <40000 40000>;
3767 compatible = "chrp,open-pic";
3768 device_type = "open-pic";
3769 };
3771 i2c@3000 {
3772 interrupt-parent = <40000>;
3773 interrupts = <1b 3>;
3774 reg = <3000 18>;
3775 device_type = "i2c";
3776 compatible = "fsl-i2c";
3777 dfsrr;
3778 };
3780 };