2 * sata_sx4.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
10 * The contents of this file are subject to the Open
11 * Software License version 1.1 that can be found at
12 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
15 * Alternatively, the contents of this file may be used under the terms
16 * of the GNU General Public License version 2 (the "GPL") as distributed
17 * in the kernel source COPYING file, in which case the provisions of
18 * the GPL are applicable instead of the above. If you wish to allow
19 * the use of your version of this file only under the terms of the
20 * GPL and not to allow others to use your version of this file under
21 * the OSL, indicate your decision by deleting the provisions above and
22 * replace them with the notice and other provisions required by the GPL.
23 * If you do not delete the provisions above, a recipient may use your
24 * version of this file under either the OSL or the GPL.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/blkdev.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
40 #include "sata_promise.h"
42 #define DRV_NAME "sata_sx4"
43 #define DRV_VERSION "0.7"
47 PDC_PRD_TBL
= 0x44, /* Direct command DMA table addr */
49 PDC_PKT_SUBMIT
= 0x40, /* Command packet pointer addr */
50 PDC_HDMA_PKT_SUBMIT
= 0x100, /* Host DMA packet pointer addr */
51 PDC_INT_SEQMASK
= 0x40, /* Mask of asserted SEQ INTs */
52 PDC_HDMA_CTLSTAT
= 0x12C, /* Host DMA control / status */
54 PDC_20621_SEQCTL
= 0x400,
55 PDC_20621_SEQMASK
= 0x480,
56 PDC_20621_GENERAL_CTL
= 0x484,
57 PDC_20621_PAGE_SIZE
= (32 * 1024),
59 /* chosen, not constant, values; we design our own DIMM mem map */
60 PDC_20621_DIMM_WINDOW
= 0x0C, /* page# for 32K DIMM window */
61 PDC_20621_DIMM_BASE
= 0x00200000,
62 PDC_20621_DIMM_DATA
= (64 * 1024),
63 PDC_DIMM_DATA_STEP
= (256 * 1024),
64 PDC_DIMM_WINDOW_STEP
= (8 * 1024),
65 PDC_DIMM_HOST_PRD
= (6 * 1024),
66 PDC_DIMM_HOST_PKT
= (128 * 0),
67 PDC_DIMM_HPKT_PRD
= (128 * 1),
68 PDC_DIMM_ATA_PKT
= (128 * 2),
69 PDC_DIMM_APKT_PRD
= (128 * 3),
70 PDC_DIMM_HEADER_SZ
= PDC_DIMM_APKT_PRD
+ 128,
71 PDC_PAGE_WINDOW
= 0x40,
72 PDC_PAGE_DATA
= PDC_PAGE_WINDOW
+
73 (PDC_20621_DIMM_DATA
/ PDC_20621_PAGE_SIZE
),
74 PDC_PAGE_SET
= PDC_DIMM_DATA_STEP
/ PDC_20621_PAGE_SIZE
,
76 PDC_CHIP0_OFS
= 0xC0000, /* offset of chip #0 */
78 PDC_20621_ERR_MASK
= (1<<19) | (1<<20) | (1<<21) | (1<<22) |
81 board_20621
= 0, /* FastTrak S150 SX4 */
83 PDC_RESET
= (1 << 11), /* HDMA reset */
86 PDC_HDMA_Q_MASK
= (PDC_MAX_HDMA
- 1),
88 PDC_DIMM0_SPD_DEV_ADDRESS
= 0x50,
89 PDC_DIMM1_SPD_DEV_ADDRESS
= 0x51,
90 PDC_MAX_DIMM_MODULE
= 0x02,
91 PDC_I2C_CONTROL_OFFSET
= 0x48,
92 PDC_I2C_ADDR_DATA_OFFSET
= 0x4C,
93 PDC_DIMM0_CONTROL_OFFSET
= 0x80,
94 PDC_DIMM1_CONTROL_OFFSET
= 0x84,
95 PDC_SDRAM_CONTROL_OFFSET
= 0x88,
96 PDC_I2C_WRITE
= 0x00000000,
97 PDC_I2C_READ
= 0x00000040,
98 PDC_I2C_START
= 0x00000080,
99 PDC_I2C_MASK_INT
= 0x00000020,
100 PDC_I2C_COMPLETE
= 0x00010000,
101 PDC_I2C_NO_ACK
= 0x00100000,
102 PDC_DIMM_SPD_SUBADDRESS_START
= 0x00,
103 PDC_DIMM_SPD_SUBADDRESS_END
= 0x7F,
104 PDC_DIMM_SPD_ROW_NUM
= 3,
105 PDC_DIMM_SPD_COLUMN_NUM
= 4,
106 PDC_DIMM_SPD_MODULE_ROW
= 5,
107 PDC_DIMM_SPD_TYPE
= 11,
108 PDC_DIMM_SPD_FRESH_RATE
= 12,
109 PDC_DIMM_SPD_BANK_NUM
= 17,
110 PDC_DIMM_SPD_CAS_LATENCY
= 18,
111 PDC_DIMM_SPD_ATTRIBUTE
= 21,
112 PDC_DIMM_SPD_ROW_PRE_CHARGE
= 27,
113 PDC_DIMM_SPD_ROW_ACTIVE_DELAY
= 28,
114 PDC_DIMM_SPD_RAS_CAS_DELAY
= 29,
115 PDC_DIMM_SPD_ACTIVE_PRECHARGE
= 30,
116 PDC_DIMM_SPD_SYSTEM_FREQ
= 126,
117 PDC_CTL_STATUS
= 0x08,
118 PDC_DIMM_WINDOW_CTLR
= 0x0C,
119 PDC_TIME_CONTROL
= 0x3C,
120 PDC_TIME_PERIOD
= 0x40,
121 PDC_TIME_COUNTER
= 0x44,
122 PDC_GENERAL_CTLR
= 0x484,
123 PCI_PLL_INIT
= 0x8A531824,
124 PCI_X_TCOUNT
= 0xEE1E5CFF
128 struct pdc_port_priv
{
129 u8 dimm_buf
[(ATA_PRD_SZ
* ATA_MAX_PRD
) + 512];
134 struct pdc_host_priv
{
137 unsigned int doing_hdma
;
138 unsigned int hdma_prod
;
139 unsigned int hdma_cons
;
141 struct ata_queued_cmd
*qc
;
143 unsigned long pkt_ofs
;
148 static int pdc_sata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
149 static irqreturn_t
pdc20621_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
150 static void pdc_eng_timeout(struct ata_port
*ap
);
151 static void pdc_20621_phy_reset (struct ata_port
*ap
);
152 static int pdc_port_start(struct ata_port
*ap
);
153 static void pdc_port_stop(struct ata_port
*ap
);
154 static void pdc20621_qc_prep(struct ata_queued_cmd
*qc
);
155 static void pdc_tf_load_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
);
156 static void pdc_exec_command_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
);
157 static void pdc20621_host_stop(struct ata_host_set
*host_set
);
158 static unsigned int pdc20621_dimm_init(struct ata_probe_ent
*pe
);
159 static int pdc20621_detect_dimm(struct ata_probe_ent
*pe
);
160 static unsigned int pdc20621_i2c_read(struct ata_probe_ent
*pe
,
161 u32 device
, u32 subaddr
, u32
*pdata
);
162 static int pdc20621_prog_dimm0(struct ata_probe_ent
*pe
);
163 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent
*pe
);
164 #ifdef ATA_VERBOSE_DEBUG
165 static void pdc20621_get_from_dimm(struct ata_probe_ent
*pe
,
166 void *psource
, u32 offset
, u32 size
);
168 static void pdc20621_put_to_dimm(struct ata_probe_ent
*pe
,
169 void *psource
, u32 offset
, u32 size
);
170 static void pdc20621_irq_clear(struct ata_port
*ap
);
171 static int pdc20621_qc_issue_prot(struct ata_queued_cmd
*qc
);
174 static Scsi_Host_Template pdc_sata_sht
= {
175 .module
= THIS_MODULE
,
177 .ioctl
= ata_scsi_ioctl
,
178 .queuecommand
= ata_scsi_queuecmd
,
179 .eh_strategy_handler
= ata_scsi_error
,
180 .can_queue
= ATA_DEF_QUEUE
,
181 .this_id
= ATA_SHT_THIS_ID
,
182 .sg_tablesize
= LIBATA_MAX_PRD
,
183 .max_sectors
= ATA_MAX_SECTORS
,
184 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
185 .emulated
= ATA_SHT_EMULATED
,
186 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
187 .proc_name
= DRV_NAME
,
188 .dma_boundary
= ATA_DMA_BOUNDARY
,
189 .slave_configure
= ata_scsi_slave_config
,
190 .bios_param
= ata_std_bios_param
,
194 static struct ata_port_operations pdc_20621_ops
= {
195 .port_disable
= ata_port_disable
,
196 .tf_load
= pdc_tf_load_mmio
,
197 .tf_read
= ata_tf_read
,
198 .check_status
= ata_check_status
,
199 .exec_command
= pdc_exec_command_mmio
,
200 .dev_select
= ata_std_dev_select
,
201 .phy_reset
= pdc_20621_phy_reset
,
202 .qc_prep
= pdc20621_qc_prep
,
203 .qc_issue
= pdc20621_qc_issue_prot
,
204 .eng_timeout
= pdc_eng_timeout
,
205 .irq_handler
= pdc20621_interrupt
,
206 .irq_clear
= pdc20621_irq_clear
,
207 .port_start
= pdc_port_start
,
208 .port_stop
= pdc_port_stop
,
209 .host_stop
= pdc20621_host_stop
,
212 static struct ata_port_info pdc_port_info
[] = {
215 .sht
= &pdc_sata_sht
,
216 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
217 ATA_FLAG_SRST
| ATA_FLAG_MMIO
,
218 .pio_mask
= 0x1f, /* pio0-4 */
219 .mwdma_mask
= 0x07, /* mwdma0-2 */
220 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
221 .port_ops
= &pdc_20621_ops
,
226 static struct pci_device_id pdc_sata_pci_tbl
[] = {
227 { PCI_VENDOR_ID_PROMISE
, 0x6622, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
229 { } /* terminate list */
233 static struct pci_driver pdc_sata_pci_driver
= {
235 .id_table
= pdc_sata_pci_tbl
,
236 .probe
= pdc_sata_init_one
,
237 .remove
= ata_pci_remove_one
,
241 static void pdc20621_host_stop(struct ata_host_set
*host_set
)
243 struct pdc_host_priv
*hpriv
= host_set
->private_data
;
244 void *dimm_mmio
= hpriv
->dimm_mmio
;
249 ata_host_stop(host_set
);
252 static int pdc_port_start(struct ata_port
*ap
)
254 struct device
*dev
= ap
->host_set
->dev
;
255 struct pdc_port_priv
*pp
;
258 rc
= ata_port_start(ap
);
262 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
267 memset(pp
, 0, sizeof(*pp
));
269 pp
->pkt
= dma_alloc_coherent(dev
, 128, &pp
->pkt_dma
, GFP_KERNEL
);
275 ap
->private_data
= pp
;
287 static void pdc_port_stop(struct ata_port
*ap
)
289 struct device
*dev
= ap
->host_set
->dev
;
290 struct pdc_port_priv
*pp
= ap
->private_data
;
292 ap
->private_data
= NULL
;
293 dma_free_coherent(dev
, 128, pp
->pkt
, pp
->pkt_dma
);
299 static void pdc_20621_phy_reset (struct ata_port
*ap
)
302 ap
->cbl
= ATA_CBL_SATA
;
307 static inline void pdc20621_ata_sg(struct ata_taskfile
*tf
, u8
*buf
,
309 unsigned int total_len
)
312 unsigned int dw
= PDC_DIMM_APKT_PRD
>> 2;
313 u32
*buf32
= (u32
*) buf
;
315 /* output ATA packet S/G table */
316 addr
= PDC_20621_DIMM_BASE
+ PDC_20621_DIMM_DATA
+
317 (PDC_DIMM_DATA_STEP
* portno
);
318 VPRINTK("ATA sg addr 0x%x, %d\n", addr
, addr
);
319 buf32
[dw
] = cpu_to_le32(addr
);
320 buf32
[dw
+ 1] = cpu_to_le32(total_len
| ATA_PRD_EOT
);
322 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
323 PDC_20621_DIMM_BASE
+
324 (PDC_DIMM_WINDOW_STEP
* portno
) +
326 buf32
[dw
], buf32
[dw
+ 1]);
329 static inline void pdc20621_host_sg(struct ata_taskfile
*tf
, u8
*buf
,
331 unsigned int total_len
)
334 unsigned int dw
= PDC_DIMM_HPKT_PRD
>> 2;
335 u32
*buf32
= (u32
*) buf
;
337 /* output Host DMA packet S/G table */
338 addr
= PDC_20621_DIMM_BASE
+ PDC_20621_DIMM_DATA
+
339 (PDC_DIMM_DATA_STEP
* portno
);
341 buf32
[dw
] = cpu_to_le32(addr
);
342 buf32
[dw
+ 1] = cpu_to_le32(total_len
| ATA_PRD_EOT
);
344 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
345 PDC_20621_DIMM_BASE
+
346 (PDC_DIMM_WINDOW_STEP
* portno
) +
348 buf32
[dw
], buf32
[dw
+ 1]);
351 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile
*tf
,
352 unsigned int devno
, u8
*buf
,
356 u32
*buf32
= (u32
*) buf
;
359 unsigned int dimm_sg
= PDC_20621_DIMM_BASE
+
360 (PDC_DIMM_WINDOW_STEP
* portno
) +
362 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg
, dimm_sg
);
364 i
= PDC_DIMM_ATA_PKT
;
369 if ((tf
->protocol
== ATA_PROT_DMA
) && (!(tf
->flags
& ATA_TFLAG_WRITE
)))
370 buf
[i
++] = PDC_PKT_READ
;
371 else if (tf
->protocol
== ATA_PROT_NODATA
)
372 buf
[i
++] = PDC_PKT_NODATA
;
375 buf
[i
++] = 0; /* reserved */
376 buf
[i
++] = portno
+ 1; /* seq. id */
377 buf
[i
++] = 0xff; /* delay seq. id */
379 /* dimm dma S/G, and next-pkt */
381 if (tf
->protocol
== ATA_PROT_NODATA
)
384 buf32
[dw
] = cpu_to_le32(dimm_sg
);
389 dev_reg
= ATA_DEVICE_OBS
;
391 dev_reg
= ATA_DEVICE_OBS
| ATA_DEV1
;
394 buf
[i
++] = (1 << 5) | PDC_PKT_CLEAR_BSY
| ATA_REG_DEVICE
;
397 /* device control register */
398 buf
[i
++] = (1 << 5) | PDC_REG_DEVCTL
;
404 static inline void pdc20621_host_pkt(struct ata_taskfile
*tf
, u8
*buf
,
408 u32 tmp
, *buf32
= (u32
*) buf
;
410 unsigned int host_sg
= PDC_20621_DIMM_BASE
+
411 (PDC_DIMM_WINDOW_STEP
* portno
) +
413 unsigned int dimm_sg
= PDC_20621_DIMM_BASE
+
414 (PDC_DIMM_WINDOW_STEP
* portno
) +
416 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg
, dimm_sg
);
417 VPRINTK("host_sg == 0x%x, %d\n", host_sg
, host_sg
);
419 dw
= PDC_DIMM_HOST_PKT
>> 2;
422 * Set up Host DMA packet
424 if ((tf
->protocol
== ATA_PROT_DMA
) && (!(tf
->flags
& ATA_TFLAG_WRITE
)))
428 tmp
|= ((portno
+ 1 + 4) << 16); /* seq. id */
429 tmp
|= (0xff << 24); /* delay seq. id */
430 buf32
[dw
+ 0] = cpu_to_le32(tmp
);
431 buf32
[dw
+ 1] = cpu_to_le32(host_sg
);
432 buf32
[dw
+ 2] = cpu_to_le32(dimm_sg
);
435 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
436 PDC_20621_DIMM_BASE
+ (PDC_DIMM_WINDOW_STEP
* portno
) +
444 static void pdc20621_dma_prep(struct ata_queued_cmd
*qc
)
446 struct scatterlist
*sg
= qc
->sg
;
447 struct ata_port
*ap
= qc
->ap
;
448 struct pdc_port_priv
*pp
= ap
->private_data
;
449 void *mmio
= ap
->host_set
->mmio_base
;
450 struct pdc_host_priv
*hpriv
= ap
->host_set
->private_data
;
451 void *dimm_mmio
= hpriv
->dimm_mmio
;
452 unsigned int portno
= ap
->port_no
;
453 unsigned int i
, last
, idx
, total_len
= 0, sgt_len
;
454 u32
*buf
= (u32
*) &pp
->dimm_buf
[PDC_DIMM_HEADER_SZ
];
456 assert(qc
->flags
& ATA_QCFLAG_DMAMAP
);
458 VPRINTK("ata%u: ENTER\n", ap
->id
);
460 /* hard-code chip #0 */
461 mmio
+= PDC_CHIP0_OFS
;
468 for (i
= 0; i
< last
; i
++) {
469 buf
[idx
++] = cpu_to_le32(sg_dma_address(&sg
[i
]));
470 buf
[idx
++] = cpu_to_le32(sg_dma_len(&sg
[i
]));
471 total_len
+= sg
[i
].length
;
473 buf
[idx
- 1] |= cpu_to_le32(ATA_PRD_EOT
);
477 * Build ATA, host DMA packets
479 pdc20621_host_sg(&qc
->tf
, &pp
->dimm_buf
[0], portno
, total_len
);
480 pdc20621_host_pkt(&qc
->tf
, &pp
->dimm_buf
[0], portno
);
482 pdc20621_ata_sg(&qc
->tf
, &pp
->dimm_buf
[0], portno
, total_len
);
483 i
= pdc20621_ata_pkt(&qc
->tf
, qc
->dev
->devno
, &pp
->dimm_buf
[0], portno
);
485 if (qc
->tf
.flags
& ATA_TFLAG_LBA48
)
486 i
= pdc_prep_lba48(&qc
->tf
, &pp
->dimm_buf
[0], i
);
488 i
= pdc_prep_lba28(&qc
->tf
, &pp
->dimm_buf
[0], i
);
490 pdc_pkt_footer(&qc
->tf
, &pp
->dimm_buf
[0], i
);
492 /* copy three S/G tables and two packets to DIMM MMIO window */
493 memcpy_toio(dimm_mmio
+ (portno
* PDC_DIMM_WINDOW_STEP
),
494 &pp
->dimm_buf
, PDC_DIMM_HEADER_SZ
);
495 memcpy_toio(dimm_mmio
+ (portno
* PDC_DIMM_WINDOW_STEP
) +
497 &pp
->dimm_buf
[PDC_DIMM_HEADER_SZ
], sgt_len
);
499 /* force host FIFO dump */
500 writel(0x00000001, mmio
+ PDC_20621_GENERAL_CTL
);
502 readl(dimm_mmio
); /* MMIO PCI posting flush */
504 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i
, sgt_len
);
507 static void pdc20621_nodata_prep(struct ata_queued_cmd
*qc
)
509 struct ata_port
*ap
= qc
->ap
;
510 struct pdc_port_priv
*pp
= ap
->private_data
;
511 void *mmio
= ap
->host_set
->mmio_base
;
512 struct pdc_host_priv
*hpriv
= ap
->host_set
->private_data
;
513 void *dimm_mmio
= hpriv
->dimm_mmio
;
514 unsigned int portno
= ap
->port_no
;
517 VPRINTK("ata%u: ENTER\n", ap
->id
);
519 /* hard-code chip #0 */
520 mmio
+= PDC_CHIP0_OFS
;
522 i
= pdc20621_ata_pkt(&qc
->tf
, qc
->dev
->devno
, &pp
->dimm_buf
[0], portno
);
524 if (qc
->tf
.flags
& ATA_TFLAG_LBA48
)
525 i
= pdc_prep_lba48(&qc
->tf
, &pp
->dimm_buf
[0], i
);
527 i
= pdc_prep_lba28(&qc
->tf
, &pp
->dimm_buf
[0], i
);
529 pdc_pkt_footer(&qc
->tf
, &pp
->dimm_buf
[0], i
);
531 /* copy three S/G tables and two packets to DIMM MMIO window */
532 memcpy_toio(dimm_mmio
+ (portno
* PDC_DIMM_WINDOW_STEP
),
533 &pp
->dimm_buf
, PDC_DIMM_HEADER_SZ
);
535 /* force host FIFO dump */
536 writel(0x00000001, mmio
+ PDC_20621_GENERAL_CTL
);
538 readl(dimm_mmio
); /* MMIO PCI posting flush */
540 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i
);
543 static void pdc20621_qc_prep(struct ata_queued_cmd
*qc
)
545 switch (qc
->tf
.protocol
) {
547 pdc20621_dma_prep(qc
);
549 case ATA_PROT_NODATA
:
550 pdc20621_nodata_prep(qc
);
557 static void __pdc20621_push_hdma(struct ata_queued_cmd
*qc
,
561 struct ata_port
*ap
= qc
->ap
;
562 struct ata_host_set
*host_set
= ap
->host_set
;
563 void *mmio
= host_set
->mmio_base
;
565 /* hard-code chip #0 */
566 mmio
+= PDC_CHIP0_OFS
;
568 writel(0x00000001, mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
569 readl(mmio
+ PDC_20621_SEQCTL
+ (seq
* 4)); /* flush */
571 writel(pkt_ofs
, mmio
+ PDC_HDMA_PKT_SUBMIT
);
572 readl(mmio
+ PDC_HDMA_PKT_SUBMIT
); /* flush */
575 static void pdc20621_push_hdma(struct ata_queued_cmd
*qc
,
579 struct ata_port
*ap
= qc
->ap
;
580 struct pdc_host_priv
*pp
= ap
->host_set
->private_data
;
581 unsigned int idx
= pp
->hdma_prod
& PDC_HDMA_Q_MASK
;
583 if (!pp
->doing_hdma
) {
584 __pdc20621_push_hdma(qc
, seq
, pkt_ofs
);
589 pp
->hdma
[idx
].qc
= qc
;
590 pp
->hdma
[idx
].seq
= seq
;
591 pp
->hdma
[idx
].pkt_ofs
= pkt_ofs
;
595 static void pdc20621_pop_hdma(struct ata_queued_cmd
*qc
)
597 struct ata_port
*ap
= qc
->ap
;
598 struct pdc_host_priv
*pp
= ap
->host_set
->private_data
;
599 unsigned int idx
= pp
->hdma_cons
& PDC_HDMA_Q_MASK
;
601 /* if nothing on queue, we're done */
602 if (pp
->hdma_prod
== pp
->hdma_cons
) {
607 __pdc20621_push_hdma(pp
->hdma
[idx
].qc
, pp
->hdma
[idx
].seq
,
608 pp
->hdma
[idx
].pkt_ofs
);
612 #ifdef ATA_VERBOSE_DEBUG
613 static void pdc20621_dump_hdma(struct ata_queued_cmd
*qc
)
615 struct ata_port
*ap
= qc
->ap
;
616 unsigned int port_no
= ap
->port_no
;
617 struct pdc_host_priv
*hpriv
= ap
->host_set
->private_data
;
618 void *dimm_mmio
= hpriv
->dimm_mmio
;
620 dimm_mmio
+= (port_no
* PDC_DIMM_WINDOW_STEP
);
621 dimm_mmio
+= PDC_DIMM_HOST_PKT
;
623 printk(KERN_ERR
"HDMA[0] == 0x%08X\n", readl(dimm_mmio
));
624 printk(KERN_ERR
"HDMA[1] == 0x%08X\n", readl(dimm_mmio
+ 4));
625 printk(KERN_ERR
"HDMA[2] == 0x%08X\n", readl(dimm_mmio
+ 8));
626 printk(KERN_ERR
"HDMA[3] == 0x%08X\n", readl(dimm_mmio
+ 12));
629 static inline void pdc20621_dump_hdma(struct ata_queued_cmd
*qc
) { }
630 #endif /* ATA_VERBOSE_DEBUG */
632 static void pdc20621_packet_start(struct ata_queued_cmd
*qc
)
634 struct ata_port
*ap
= qc
->ap
;
635 struct ata_host_set
*host_set
= ap
->host_set
;
636 unsigned int port_no
= ap
->port_no
;
637 void *mmio
= host_set
->mmio_base
;
638 unsigned int rw
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
);
639 u8 seq
= (u8
) (port_no
+ 1);
640 unsigned int port_ofs
;
642 /* hard-code chip #0 */
643 mmio
+= PDC_CHIP0_OFS
;
645 VPRINTK("ata%u: ENTER\n", ap
->id
);
647 wmb(); /* flush PRD, pkt writes */
649 port_ofs
= PDC_20621_DIMM_BASE
+ (PDC_DIMM_WINDOW_STEP
* port_no
);
651 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
652 if (rw
&& qc
->tf
.protocol
== ATA_PROT_DMA
) {
655 pdc20621_dump_hdma(qc
);
656 pdc20621_push_hdma(qc
, seq
, port_ofs
+ PDC_DIMM_HOST_PKT
);
657 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
658 port_ofs
+ PDC_DIMM_HOST_PKT
,
659 port_ofs
+ PDC_DIMM_HOST_PKT
,
662 writel(0x00000001, mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
663 readl(mmio
+ PDC_20621_SEQCTL
+ (seq
* 4)); /* flush */
665 writel(port_ofs
+ PDC_DIMM_ATA_PKT
,
666 (void *) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
667 readl((void *) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
668 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
669 port_ofs
+ PDC_DIMM_ATA_PKT
,
670 port_ofs
+ PDC_DIMM_ATA_PKT
,
675 static int pdc20621_qc_issue_prot(struct ata_queued_cmd
*qc
)
677 switch (qc
->tf
.protocol
) {
679 case ATA_PROT_NODATA
:
680 pdc20621_packet_start(qc
);
683 case ATA_PROT_ATAPI_DMA
:
691 return ata_qc_issue_prot(qc
);
694 static inline unsigned int pdc20621_host_intr( struct ata_port
*ap
,
695 struct ata_queued_cmd
*qc
,
696 unsigned int doing_hdma
,
699 unsigned int port_no
= ap
->port_no
;
700 unsigned int port_ofs
=
701 PDC_20621_DIMM_BASE
+ (PDC_DIMM_WINDOW_STEP
* port_no
);
703 unsigned int handled
= 0;
707 if ((qc
->tf
.protocol
== ATA_PROT_DMA
) && /* read */
708 (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
))) {
710 /* step two - DMA from DIMM to host */
712 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap
->id
,
713 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
714 /* get drive status; clear intr; complete txn */
715 ata_qc_complete(qc
, ata_wait_idle(ap
));
716 pdc20621_pop_hdma(qc
);
719 /* step one - exec ATA command */
721 u8 seq
= (u8
) (port_no
+ 1 + 4);
722 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap
->id
,
723 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
725 /* submit hdma pkt */
726 pdc20621_dump_hdma(qc
);
727 pdc20621_push_hdma(qc
, seq
,
728 port_ofs
+ PDC_DIMM_HOST_PKT
);
732 } else if (qc
->tf
.protocol
== ATA_PROT_DMA
) { /* write */
734 /* step one - DMA from host to DIMM */
736 u8 seq
= (u8
) (port_no
+ 1);
737 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap
->id
,
738 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
741 writel(0x00000001, mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
742 readl(mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
743 writel(port_ofs
+ PDC_DIMM_ATA_PKT
,
744 (void *) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
745 readl((void *) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
748 /* step two - execute ATA command */
750 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap
->id
,
751 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
752 /* get drive status; clear intr; complete txn */
753 ata_qc_complete(qc
, ata_wait_idle(ap
));
754 pdc20621_pop_hdma(qc
);
758 /* command completion, but no data xfer */
759 } else if (qc
->tf
.protocol
== ATA_PROT_NODATA
) {
761 status
= ata_busy_wait(ap
, ATA_BUSY
| ATA_DRQ
, 1000);
762 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status
);
763 ata_qc_complete(qc
, status
);
767 ap
->stats
.idle_irq
++;
773 static void pdc20621_irq_clear(struct ata_port
*ap
)
775 struct ata_host_set
*host_set
= ap
->host_set
;
776 void *mmio
= host_set
->mmio_base
;
778 mmio
+= PDC_CHIP0_OFS
;
780 readl(mmio
+ PDC_20621_SEQMASK
);
783 static irqreturn_t
pdc20621_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
785 struct ata_host_set
*host_set
= dev_instance
;
788 unsigned int i
, tmp
, port_no
;
789 unsigned int handled
= 0;
794 if (!host_set
|| !host_set
->mmio_base
) {
795 VPRINTK("QUICK EXIT\n");
799 mmio_base
= host_set
->mmio_base
;
801 /* reading should also clear interrupts */
802 mmio_base
+= PDC_CHIP0_OFS
;
803 mask
= readl(mmio_base
+ PDC_20621_SEQMASK
);
804 VPRINTK("mask == 0x%x\n", mask
);
806 if (mask
== 0xffffffff) {
807 VPRINTK("QUICK EXIT 2\n");
810 mask
&= 0xffff; /* only 16 tags possible */
812 VPRINTK("QUICK EXIT 3\n");
816 spin_lock(&host_set
->lock
);
818 for (i
= 1; i
< 9; i
++) {
822 if (port_no
>= host_set
->n_ports
)
825 ap
= host_set
->ports
[port_no
];
826 tmp
= mask
& (1 << i
);
827 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i
, port_no
, ap
, tmp
);
828 if (tmp
&& ap
&& (!(ap
->flags
& ATA_FLAG_PORT_DISABLED
))) {
829 struct ata_queued_cmd
*qc
;
831 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
832 if (qc
&& (!(qc
->tf
.ctl
& ATA_NIEN
)))
833 handled
+= pdc20621_host_intr(ap
, qc
, (i
> 4),
838 spin_unlock(&host_set
->lock
);
840 VPRINTK("mask == 0x%x\n", mask
);
844 return IRQ_RETVAL(handled
);
847 static void pdc_eng_timeout(struct ata_port
*ap
)
850 struct ata_queued_cmd
*qc
;
854 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
856 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
861 /* hack alert! We cannot use the supplied completion
862 * function from inside the ->eh_strategy_handler() thread.
863 * libata is the only user of ->eh_strategy_handler() in
864 * any kernel, so the default scsi_done() assumes it is
865 * not being called from the SCSI EH.
867 qc
->scsidone
= scsi_finish_command
;
869 switch (qc
->tf
.protocol
) {
871 case ATA_PROT_NODATA
:
872 printk(KERN_ERR
"ata%u: command timeout\n", ap
->id
);
873 ata_qc_complete(qc
, ata_wait_idle(ap
) | ATA_ERR
);
877 drv_stat
= ata_busy_wait(ap
, ATA_BUSY
| ATA_DRQ
, 1000);
879 printk(KERN_ERR
"ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
880 ap
->id
, qc
->tf
.command
, drv_stat
);
882 ata_qc_complete(qc
, drv_stat
);
890 static void pdc_tf_load_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
)
892 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
893 tf
->protocol
== ATA_PROT_NODATA
);
898 static void pdc_exec_command_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
)
900 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
901 tf
->protocol
== ATA_PROT_NODATA
);
902 ata_exec_command(ap
, tf
);
906 static void pdc_sata_setup_port(struct ata_ioports
*port
, unsigned long base
)
908 port
->cmd_addr
= base
;
909 port
->data_addr
= base
;
911 port
->error_addr
= base
+ 0x4;
912 port
->nsect_addr
= base
+ 0x8;
913 port
->lbal_addr
= base
+ 0xc;
914 port
->lbam_addr
= base
+ 0x10;
915 port
->lbah_addr
= base
+ 0x14;
916 port
->device_addr
= base
+ 0x18;
918 port
->status_addr
= base
+ 0x1c;
919 port
->altstatus_addr
=
920 port
->ctl_addr
= base
+ 0x38;
924 #ifdef ATA_VERBOSE_DEBUG
925 static void pdc20621_get_from_dimm(struct ata_probe_ent
*pe
, void *psource
,
926 u32 offset
, u32 size
)
932 void *mmio
= pe
->mmio_base
;
933 struct pdc_host_priv
*hpriv
= pe
->private_data
;
934 void *dimm_mmio
= hpriv
->dimm_mmio
;
936 /* hard-code chip #0 */
937 mmio
+= PDC_CHIP0_OFS
;
940 window_size
= 0x2000 * 4; /* 32K byte uchar size */
941 idx
= (u16
) (offset
/ window_size
);
943 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
944 readl(mmio
+ PDC_GENERAL_CTLR
);
945 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
946 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
948 offset
-= (idx
* window_size
);
950 dist
= ((long) (window_size
- (offset
+ size
))) >= 0 ? size
:
951 (long) (window_size
- offset
);
952 memcpy_fromio((char *) psource
, (char *) (dimm_mmio
+ offset
/ 4),
957 for (; (long) size
>= (long) window_size
;) {
958 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
959 readl(mmio
+ PDC_GENERAL_CTLR
);
960 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
961 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
962 memcpy_fromio((char *) psource
, (char *) (dimm_mmio
),
964 psource
+= window_size
;
970 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
971 readl(mmio
+ PDC_GENERAL_CTLR
);
972 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
973 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
974 memcpy_fromio((char *) psource
, (char *) (dimm_mmio
),
981 static void pdc20621_put_to_dimm(struct ata_probe_ent
*pe
, void *psource
,
982 u32 offset
, u32 size
)
988 void *mmio
= pe
->mmio_base
;
989 struct pdc_host_priv
*hpriv
= pe
->private_data
;
990 void *dimm_mmio
= hpriv
->dimm_mmio
;
992 /* hard-code chip #0 */
993 mmio
+= PDC_CHIP0_OFS
;
996 window_size
= 0x2000 * 4; /* 32K byte uchar size */
997 idx
= (u16
) (offset
/ window_size
);
999 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
1000 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
1001 offset
-= (idx
* window_size
);
1003 dist
= ((long)(s32
)(window_size
- (offset
+ size
))) >= 0 ? size
:
1004 (long) (window_size
- offset
);
1005 memcpy_toio((char *) (dimm_mmio
+ offset
/ 4), (char *) psource
, dist
);
1006 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
1007 readl(mmio
+ PDC_GENERAL_CTLR
);
1011 for (; (long) size
>= (long) window_size
;) {
1012 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
1013 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
1014 memcpy_toio((char *) (dimm_mmio
), (char *) psource
,
1016 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
1017 readl(mmio
+ PDC_GENERAL_CTLR
);
1018 psource
+= window_size
;
1019 size
-= window_size
;
1024 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
1025 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
1026 memcpy_toio((char *) (dimm_mmio
), (char *) psource
, size
/ 4);
1027 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
1028 readl(mmio
+ PDC_GENERAL_CTLR
);
1033 static unsigned int pdc20621_i2c_read(struct ata_probe_ent
*pe
, u32 device
,
1034 u32 subaddr
, u32
*pdata
)
1036 void *mmio
= pe
->mmio_base
;
1041 /* hard-code chip #0 */
1042 mmio
+= PDC_CHIP0_OFS
;
1044 i2creg
|= device
<< 24;
1045 i2creg
|= subaddr
<< 16;
1047 /* Set the device and subaddress */
1048 writel(i2creg
, mmio
+ PDC_I2C_ADDR_DATA_OFFSET
);
1049 readl(mmio
+ PDC_I2C_ADDR_DATA_OFFSET
);
1051 /* Write Control to perform read operation, mask int */
1052 writel(PDC_I2C_READ
| PDC_I2C_START
| PDC_I2C_MASK_INT
,
1053 mmio
+ PDC_I2C_CONTROL_OFFSET
);
1055 for (count
= 0; count
<= 1000; count
++) {
1056 status
= readl(mmio
+ PDC_I2C_CONTROL_OFFSET
);
1057 if (status
& PDC_I2C_COMPLETE
) {
1058 status
= readl(mmio
+ PDC_I2C_ADDR_DATA_OFFSET
);
1060 } else if (count
== 1000)
1064 *pdata
= (status
>> 8) & 0x000000ff;
1069 static int pdc20621_detect_dimm(struct ata_probe_ent
*pe
)
1072 if (pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1073 PDC_DIMM_SPD_SYSTEM_FREQ
, &data
)) {
1079 if (pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
, 9, &data
)) {
1089 static int pdc20621_prog_dimm0(struct ata_probe_ent
*pe
)
1095 void *mmio
= pe
->mmio_base
;
1096 static const struct {
1099 } pdc_i2c_read_data
[] = {
1100 { PDC_DIMM_SPD_TYPE
, 11 },
1101 { PDC_DIMM_SPD_FRESH_RATE
, 12 },
1102 { PDC_DIMM_SPD_COLUMN_NUM
, 4 },
1103 { PDC_DIMM_SPD_ATTRIBUTE
, 21 },
1104 { PDC_DIMM_SPD_ROW_NUM
, 3 },
1105 { PDC_DIMM_SPD_BANK_NUM
, 17 },
1106 { PDC_DIMM_SPD_MODULE_ROW
, 5 },
1107 { PDC_DIMM_SPD_ROW_PRE_CHARGE
, 27 },
1108 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY
, 28 },
1109 { PDC_DIMM_SPD_RAS_CAS_DELAY
, 29 },
1110 { PDC_DIMM_SPD_ACTIVE_PRECHARGE
, 30 },
1111 { PDC_DIMM_SPD_CAS_LATENCY
, 18 },
1114 /* hard-code chip #0 */
1115 mmio
+= PDC_CHIP0_OFS
;
1117 for(i
=0; i
<ARRAY_SIZE(pdc_i2c_read_data
); i
++)
1118 pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1119 pdc_i2c_read_data
[i
].reg
,
1120 &spd0
[pdc_i2c_read_data
[i
].ofs
]);
1122 data
|= (spd0
[4] - 8) | ((spd0
[21] != 0) << 3) | ((spd0
[3]-11) << 4);
1123 data
|= ((spd0
[17] / 4) << 6) | ((spd0
[5] / 2) << 7) |
1124 ((((spd0
[27] + 9) / 10) - 1) << 8) ;
1125 data
|= (((((spd0
[29] > spd0
[28])
1126 ? spd0
[29] : spd0
[28]) + 9) / 10) - 1) << 10;
1127 data
|= ((spd0
[30] - spd0
[29] + 9) / 10 - 2) << 12;
1129 if (spd0
[18] & 0x08)
1130 data
|= ((0x03) << 14);
1131 else if (spd0
[18] & 0x04)
1132 data
|= ((0x02) << 14);
1133 else if (spd0
[18] & 0x01)
1134 data
|= ((0x01) << 14);
1139 Calculate the size of bDIMMSize (power of 2) and
1140 merge the DIMM size by program start/end address.
1143 bdimmsize
= spd0
[4] + (spd0
[5] / 2) + spd0
[3] + (spd0
[17] / 2) + 3;
1144 size
= (1 << bdimmsize
) >> 20; /* size = xxx(MB) */
1145 data
|= (((size
/ 16) - 1) << 16);
1148 writel(data
, mmio
+ PDC_DIMM0_CONTROL_OFFSET
);
1149 readl(mmio
+ PDC_DIMM0_CONTROL_OFFSET
);
1154 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent
*pe
)
1158 void *mmio
= pe
->mmio_base
;
1160 /* hard-code chip #0 */
1161 mmio
+= PDC_CHIP0_OFS
;
1164 Set To Default : DIMM Module Global Control Register (0x022259F1)
1165 DIMM Arbitration Disable (bit 20)
1166 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1167 Refresh Enable (bit 17)
1171 writel(data
, mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1172 readl(mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1174 /* Turn on for ECC */
1175 pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1176 PDC_DIMM_SPD_TYPE
, &spd0
);
1178 data
|= (0x01 << 16);
1179 writel(data
, mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1180 readl(mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1181 printk(KERN_ERR
"Local DIMM ECC Enabled\n");
1184 /* DIMM Initialization Select/Enable (bit 18/19) */
1187 writel(data
, mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1190 for (i
= 1; i
<= 10; i
++) { /* polling ~5 secs */
1191 data
= readl(mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1192 if (!(data
& (1<<19))) {
1202 static unsigned int pdc20621_dimm_init(struct ata_probe_ent
*pe
)
1204 int speed
, size
, length
;
1205 u32 addr
,spd0
,pci_status
;
1212 void *mmio
= pe
->mmio_base
;
1214 /* hard-code chip #0 */
1215 mmio
+= PDC_CHIP0_OFS
;
1217 /* Initialize PLL based upon PCI Bus Frequency */
1219 /* Initialize Time Period Register */
1220 writel(0xffffffff, mmio
+ PDC_TIME_PERIOD
);
1221 time_period
= readl(mmio
+ PDC_TIME_PERIOD
);
1222 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period
);
1225 writel(0x00001a0, mmio
+ PDC_TIME_CONTROL
);
1226 readl(mmio
+ PDC_TIME_CONTROL
);
1228 /* Wait 3 seconds */
1232 When timer is enabled, counter is decreased every internal
1236 tcount
= readl(mmio
+ PDC_TIME_COUNTER
);
1237 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount
);
1240 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1241 register should be >= (0xffffffff - 3x10^8).
1243 if(tcount
>= PCI_X_TCOUNT
) {
1244 ticks
= (time_period
- tcount
);
1245 VPRINTK("Num counters 0x%x (%d)\n", ticks
, ticks
);
1247 clock
= (ticks
/ 300000);
1248 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock
, clock
);
1250 clock
= (clock
* 33);
1251 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock
, clock
);
1253 /* PLL F Param (bit 22:16) */
1254 fparam
= (1400000 / clock
) - 2;
1255 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam
, fparam
);
1257 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1258 pci_status
= (0x8a001824 | (fparam
<< 16));
1260 pci_status
= PCI_PLL_INIT
;
1262 /* Initialize PLL. */
1263 VPRINTK("pci_status: 0x%x\n", pci_status
);
1264 writel(pci_status
, mmio
+ PDC_CTL_STATUS
);
1265 readl(mmio
+ PDC_CTL_STATUS
);
1268 Read SPD of DIMM by I2C interface,
1269 and program the DIMM Module Controller.
1271 if (!(speed
= pdc20621_detect_dimm(pe
))) {
1272 printk(KERN_ERR
"Detect Local DIMM Fail\n");
1273 return 1; /* DIMM error */
1275 VPRINTK("Local DIMM Speed = %d\n", speed
);
1277 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1278 size
= pdc20621_prog_dimm0(pe
);
1279 VPRINTK("Local DIMM Size = %dMB\n",size
);
1281 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1282 if (pdc20621_prog_dimm_global(pe
)) {
1283 printk(KERN_ERR
"Programming DIMM Module Global Control Register Fail\n");
1287 #ifdef ATA_VERBOSE_DEBUG
1289 u8 test_parttern1
[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1290 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1292 '9','8','0','3','1','6','1','2',0,0};
1293 u8 test_parttern2
[40] = {0};
1295 pdc20621_put_to_dimm(pe
, (void *) test_parttern2
, 0x10040, 40);
1296 pdc20621_put_to_dimm(pe
, (void *) test_parttern2
, 0x40, 40);
1298 pdc20621_put_to_dimm(pe
, (void *) test_parttern1
, 0x10040, 40);
1299 pdc20621_get_from_dimm(pe
, (void *) test_parttern2
, 0x40, 40);
1300 printk(KERN_ERR
"%x, %x, %s\n", test_parttern2
[0],
1301 test_parttern2
[1], &(test_parttern2
[2]));
1302 pdc20621_get_from_dimm(pe
, (void *) test_parttern2
, 0x10040,
1304 printk(KERN_ERR
"%x, %x, %s\n", test_parttern2
[0],
1305 test_parttern2
[1], &(test_parttern2
[2]));
1307 pdc20621_put_to_dimm(pe
, (void *) test_parttern1
, 0x40, 40);
1308 pdc20621_get_from_dimm(pe
, (void *) test_parttern2
, 0x40, 40);
1309 printk(KERN_ERR
"%x, %x, %s\n", test_parttern2
[0],
1310 test_parttern2
[1], &(test_parttern2
[2]));
1314 /* ECC initiliazation. */
1316 pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1317 PDC_DIMM_SPD_TYPE
, &spd0
);
1319 VPRINTK("Start ECC initialization\n");
1321 length
= size
* 1024 * 1024;
1322 while (addr
< length
) {
1323 pdc20621_put_to_dimm(pe
, (void *) &tmp
, addr
,
1325 addr
+= sizeof(u32
);
1327 VPRINTK("Finish ECC initialization\n");
1333 static void pdc_20621_init(struct ata_probe_ent
*pe
)
1336 void *mmio
= pe
->mmio_base
;
1338 /* hard-code chip #0 */
1339 mmio
+= PDC_CHIP0_OFS
;
1342 * Select page 0x40 for our 32k DIMM window
1344 tmp
= readl(mmio
+ PDC_20621_DIMM_WINDOW
) & 0xffff0000;
1345 tmp
|= PDC_PAGE_WINDOW
; /* page 40h; arbitrarily selected */
1346 writel(tmp
, mmio
+ PDC_20621_DIMM_WINDOW
);
1351 tmp
= readl(mmio
+ PDC_HDMA_CTLSTAT
);
1353 writel(tmp
, mmio
+ PDC_HDMA_CTLSTAT
);
1354 readl(mmio
+ PDC_HDMA_CTLSTAT
); /* flush */
1358 tmp
= readl(mmio
+ PDC_HDMA_CTLSTAT
);
1360 writel(tmp
, mmio
+ PDC_HDMA_CTLSTAT
);
1361 readl(mmio
+ PDC_HDMA_CTLSTAT
); /* flush */
1364 static int pdc_sata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1366 static int printed_version
;
1367 struct ata_probe_ent
*probe_ent
= NULL
;
1369 void *mmio_base
, *dimm_mmio
= NULL
;
1370 struct pdc_host_priv
*hpriv
= NULL
;
1371 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
1372 int pci_dev_busy
= 0;
1375 if (!printed_version
++)
1376 printk(KERN_DEBUG DRV_NAME
" version " DRV_VERSION
"\n");
1379 * If this driver happens to only be useful on Apple's K2, then
1380 * we should check that here as it has a normal Serverworks ID
1382 rc
= pci_enable_device(pdev
);
1386 rc
= pci_request_regions(pdev
, DRV_NAME
);
1392 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
1394 goto err_out_regions
;
1395 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
1397 goto err_out_regions
;
1399 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1400 if (probe_ent
== NULL
) {
1402 goto err_out_regions
;
1405 memset(probe_ent
, 0, sizeof(*probe_ent
));
1406 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1407 INIT_LIST_HEAD(&probe_ent
->node
);
1409 mmio_base
= ioremap(pci_resource_start(pdev
, 3),
1410 pci_resource_len(pdev
, 3));
1411 if (mmio_base
== NULL
) {
1413 goto err_out_free_ent
;
1415 base
= (unsigned long) mmio_base
;
1417 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1420 goto err_out_iounmap
;
1422 memset(hpriv
, 0, sizeof(*hpriv
));
1424 dimm_mmio
= ioremap(pci_resource_start(pdev
, 4),
1425 pci_resource_len(pdev
, 4));
1429 goto err_out_iounmap
;
1432 hpriv
->dimm_mmio
= dimm_mmio
;
1434 probe_ent
->sht
= pdc_port_info
[board_idx
].sht
;
1435 probe_ent
->host_flags
= pdc_port_info
[board_idx
].host_flags
;
1436 probe_ent
->pio_mask
= pdc_port_info
[board_idx
].pio_mask
;
1437 probe_ent
->mwdma_mask
= pdc_port_info
[board_idx
].mwdma_mask
;
1438 probe_ent
->udma_mask
= pdc_port_info
[board_idx
].udma_mask
;
1439 probe_ent
->port_ops
= pdc_port_info
[board_idx
].port_ops
;
1441 probe_ent
->irq
= pdev
->irq
;
1442 probe_ent
->irq_flags
= SA_SHIRQ
;
1443 probe_ent
->mmio_base
= mmio_base
;
1445 probe_ent
->private_data
= hpriv
;
1446 base
+= PDC_CHIP0_OFS
;
1448 probe_ent
->n_ports
= 4;
1449 pdc_sata_setup_port(&probe_ent
->port
[0], base
+ 0x200);
1450 pdc_sata_setup_port(&probe_ent
->port
[1], base
+ 0x280);
1451 pdc_sata_setup_port(&probe_ent
->port
[2], base
+ 0x300);
1452 pdc_sata_setup_port(&probe_ent
->port
[3], base
+ 0x380);
1454 pci_set_master(pdev
);
1456 /* initialize adapter */
1457 /* initialize local dimm */
1458 if (pdc20621_dimm_init(probe_ent
)) {
1460 goto err_out_iounmap_dimm
;
1462 pdc_20621_init(probe_ent
);
1464 /* FIXME: check ata_device_add return value */
1465 ata_device_add(probe_ent
);
1470 err_out_iounmap_dimm
: /* only get to this label if 20621 */
1478 pci_release_regions(pdev
);
1481 pci_disable_device(pdev
);
1486 static int __init
pdc_sata_init(void)
1488 return pci_module_init(&pdc_sata_pci_driver
);
1492 static void __exit
pdc_sata_exit(void)
1494 pci_unregister_driver(&pdc_sata_pci_driver
);
1498 MODULE_AUTHOR("Jeff Garzik");
1499 MODULE_DESCRIPTION("Promise SATA low-level driver");
1500 MODULE_LICENSE("GPL");
1501 MODULE_DEVICE_TABLE(pci
, pdc_sata_pci_tbl
);
1502 MODULE_VERSION(DRV_VERSION
);
1504 module_init(pdc_sata_init
);
1505 module_exit(pdc_sata_exit
);