?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
KVM: x86: include pvclock MSRs in msrs_to_save
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / x86.c
blob97b31fa63088aa06304d3165e4ab6b1ea862e934
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 #include <linux/kvm_host.h>
22 #include "irq.h"
23 #include "mmu.h"
24 #include "i8254.h"
25 #include "tss.h"
26 #include "kvm_cache_regs.h"
27 #include "x86.h"
28
29 #include <linux/clocksource.h>
30 #include <linux/interrupt.h>
31 #include <linux/kvm.h>
32 #include <linux/fs.h>
33 #include <linux/vmalloc.h>
34 #include <linux/module.h>
35 #include <linux/mman.h>
36 #include <linux/highmem.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/cpufreq.h>
40 #include <trace/events/kvm.h>
41 #undef TRACE_INCLUDE_FILE
42 #define CREATE_TRACE_POINTS
43 #include "trace.h"
44
45 #include <asm/uaccess.h>
46 #include <asm/msr.h>
47 #include <asm/desc.h>
48 #include <asm/mtrr.h>
49 #include <asm/mce.h>
50
51 #define MAX_IO_MSRS 256
52 #define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56 #define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
63
64 #define KVM_MAX_MCE_BANKS 32
65 #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
67 /* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71 #ifdef CONFIG_X86_64
72 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73 #else
74 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75 #endif
76
77 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
79
80 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
81 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
82 struct kvm_cpuid_entry2 __user *entries);
83
84 struct kvm_x86_ops *kvm_x86_ops;
85 EXPORT_SYMBOL_GPL(kvm_x86_ops);
86
87 int ignore_msrs = 0;
88 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
89
90 struct kvm_stats_debugfs_item debugfs_entries[] = {
91 { "pf_fixed", VCPU_STAT(pf_fixed) },
92 { "pf_guest", VCPU_STAT(pf_guest) },
93 { "tlb_flush", VCPU_STAT(tlb_flush) },
94 { "invlpg", VCPU_STAT(invlpg) },
95 { "exits", VCPU_STAT(exits) },
96 { "io_exits", VCPU_STAT(io_exits) },
97 { "mmio_exits", VCPU_STAT(mmio_exits) },
98 { "signal_exits", VCPU_STAT(signal_exits) },
99 { "irq_window", VCPU_STAT(irq_window_exits) },
100 { "nmi_window", VCPU_STAT(nmi_window_exits) },
101 { "halt_exits", VCPU_STAT(halt_exits) },
102 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
103 { "hypercalls", VCPU_STAT(hypercalls) },
104 { "request_irq", VCPU_STAT(request_irq_exits) },
105 { "irq_exits", VCPU_STAT(irq_exits) },
106 { "host_state_reload", VCPU_STAT(host_state_reload) },
107 { "efer_reload", VCPU_STAT(efer_reload) },
108 { "fpu_reload", VCPU_STAT(fpu_reload) },
109 { "insn_emulation", VCPU_STAT(insn_emulation) },
110 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
111 { "irq_injections", VCPU_STAT(irq_injections) },
112 { "nmi_injections", VCPU_STAT(nmi_injections) },
113 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
114 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
115 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
116 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
117 { "mmu_flooded", VM_STAT(mmu_flooded) },
118 { "mmu_recycled", VM_STAT(mmu_recycled) },
119 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
120 { "mmu_unsync", VM_STAT(mmu_unsync) },
121 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
122 { "largepages", VM_STAT(lpages) },
123 { NULL }
124 };
125
126 unsigned long segment_base(u16 selector)
127 {
128 struct descriptor_table gdt;
129 struct desc_struct *d;
130 unsigned long table_base;
131 unsigned long v;
132
133 if (selector == 0)
134 return 0;
135
136 kvm_get_gdt(&gdt);
137 table_base = gdt.base;
138
139 if (selector & 4) { /* from ldt */
140 u16 ldt_selector = kvm_read_ldt();
141
142 table_base = segment_base(ldt_selector);
143 }
144 d = (struct desc_struct *)(table_base + (selector & ~7));
145 v = get_desc_base(d);
146 #ifdef CONFIG_X86_64
147 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
148 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
149 #endif
150 return v;
151 }
152 EXPORT_SYMBOL_GPL(segment_base);
153
154 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
155 {
156 if (irqchip_in_kernel(vcpu->kvm))
157 return vcpu->arch.apic_base;
158 else
159 return vcpu->arch.apic_base;
160 }
161 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
162
163 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
164 {
165 /* TODO: reserve bits check */
166 if (irqchip_in_kernel(vcpu->kvm))
167 kvm_lapic_set_base(vcpu, data);
168 else
169 vcpu->arch.apic_base = data;
170 }
171 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
172
173 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
174 {
175 WARN_ON(vcpu->arch.exception.pending);
176 vcpu->arch.exception.pending = true;
177 vcpu->arch.exception.has_error_code = false;
178 vcpu->arch.exception.nr = nr;
179 }
180 EXPORT_SYMBOL_GPL(kvm_queue_exception);
181
182 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
183 u32 error_code)
184 {
185 ++vcpu->stat.pf_guest;
186
187 if (vcpu->arch.exception.pending) {
188 switch(vcpu->arch.exception.nr) {
189 case DF_VECTOR:
190 /* triple fault -> shutdown */
191 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
192 return;
193 case PF_VECTOR:
194 vcpu->arch.exception.nr = DF_VECTOR;
195 vcpu->arch.exception.error_code = 0;
196 return;
197 default:
198 /* replace previous exception with a new one in a hope
199 that instruction re-execution will regenerate lost
200 exception */
201 vcpu->arch.exception.pending = false;
202 break;
203 }
204 }
205 vcpu->arch.cr2 = addr;
206 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
207 }
208
209 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
210 {
211 vcpu->arch.nmi_pending = 1;
212 }
213 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
214
215 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
216 {
217 WARN_ON(vcpu->arch.exception.pending);
218 vcpu->arch.exception.pending = true;
219 vcpu->arch.exception.has_error_code = true;
220 vcpu->arch.exception.nr = nr;
221 vcpu->arch.exception.error_code = error_code;
222 }
223 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
224
225 /*
226 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
227 * a #GP and return false.
228 */
229 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
230 {
231 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
232 return true;
233 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
234 return false;
235 }
236 EXPORT_SYMBOL_GPL(kvm_require_cpl);
237
238 /*
239 * Load the pae pdptrs. Return true is they are all valid.
240 */
241 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
242 {
243 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
244 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
245 int i;
246 int ret;
247 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
248
249 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
250 offset * sizeof(u64), sizeof(pdpte));
251 if (ret < 0) {
252 ret = 0;
253 goto out;
254 }
255 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
256 if (is_present_gpte(pdpte[i]) &&
257 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
258 ret = 0;
259 goto out;
260 }
261 }
262 ret = 1;
263
264 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
265 __set_bit(VCPU_EXREG_PDPTR,
266 (unsigned long *)&vcpu->arch.regs_avail);
267 __set_bit(VCPU_EXREG_PDPTR,
268 (unsigned long *)&vcpu->arch.regs_dirty);
269 out:
270
271 return ret;
272 }
273 EXPORT_SYMBOL_GPL(load_pdptrs);
274
275 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
276 {
277 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
278 bool changed = true;
279 int r;
280
281 if (is_long_mode(vcpu) || !is_pae(vcpu))
282 return false;
283
284 if (!test_bit(VCPU_EXREG_PDPTR,
285 (unsigned long *)&vcpu->arch.regs_avail))
286 return true;
287
288 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
289 if (r < 0)
290 goto out;
291 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
292 out:
293
294 return changed;
295 }
296
297 void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
298 {
299 if (cr0 & CR0_RESERVED_BITS) {
300 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
301 cr0, vcpu->arch.cr0);
302 kvm_inject_gp(vcpu, 0);
303 return;
304 }
305
306 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
307 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
308 kvm_inject_gp(vcpu, 0);
309 return;
310 }
311
312 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
313 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
314 "and a clear PE flag\n");
315 kvm_inject_gp(vcpu, 0);
316 return;
317 }
318
319 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
320 #ifdef CONFIG_X86_64
321 if ((vcpu->arch.shadow_efer & EFER_LME)) {
322 int cs_db, cs_l;
323
324 if (!is_pae(vcpu)) {
325 printk(KERN_DEBUG "set_cr0: #GP, start paging "
326 "in long mode while PAE is disabled\n");
327 kvm_inject_gp(vcpu, 0);
328 return;
329 }
330 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
331 if (cs_l) {
332 printk(KERN_DEBUG "set_cr0: #GP, start paging "
333 "in long mode while CS.L == 1\n");
334 kvm_inject_gp(vcpu, 0);
335 return;
336
337 }
338 } else
339 #endif
340 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
341 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
342 "reserved bits\n");
343 kvm_inject_gp(vcpu, 0);
344 return;
345 }
346
347 }
348
349 kvm_x86_ops->set_cr0(vcpu, cr0);
350 vcpu->arch.cr0 = cr0;
351
352 kvm_mmu_reset_context(vcpu);
353 return;
354 }
355 EXPORT_SYMBOL_GPL(kvm_set_cr0);
356
357 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
358 {
359 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
360 }
361 EXPORT_SYMBOL_GPL(kvm_lmsw);
362
363 void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
364 {
365 unsigned long old_cr4 = vcpu->arch.cr4;
366 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
367
368 if (cr4 & CR4_RESERVED_BITS) {
369 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
370 kvm_inject_gp(vcpu, 0);
371 return;
372 }
373
374 if (is_long_mode(vcpu)) {
375 if (!(cr4 & X86_CR4_PAE)) {
376 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
377 "in long mode\n");
378 kvm_inject_gp(vcpu, 0);
379 return;
380 }
381 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
382 && ((cr4 ^ old_cr4) & pdptr_bits)
383 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
384 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
385 kvm_inject_gp(vcpu, 0);
386 return;
387 }
388
389 if (cr4 & X86_CR4_VMXE) {
390 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
391 kvm_inject_gp(vcpu, 0);
392 return;
393 }
394 kvm_x86_ops->set_cr4(vcpu, cr4);
395 vcpu->arch.cr4 = cr4;
396 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
397 kvm_mmu_reset_context(vcpu);
398 }
399 EXPORT_SYMBOL_GPL(kvm_set_cr4);
400
401 void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
402 {
403 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
404 kvm_mmu_sync_roots(vcpu);
405 kvm_mmu_flush_tlb(vcpu);
406 return;
407 }
408
409 if (is_long_mode(vcpu)) {
410 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
411 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
412 kvm_inject_gp(vcpu, 0);
413 return;
414 }
415 } else {
416 if (is_pae(vcpu)) {
417 if (cr3 & CR3_PAE_RESERVED_BITS) {
418 printk(KERN_DEBUG
419 "set_cr3: #GP, reserved bits\n");
420 kvm_inject_gp(vcpu, 0);
421 return;
422 }
423 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
424 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
425 "reserved bits\n");
426 kvm_inject_gp(vcpu, 0);
427 return;
428 }
429 }
430 /*
431 * We don't check reserved bits in nonpae mode, because
432 * this isn't enforced, and VMware depends on this.
433 */
434 }
435
436 /*
437 * Does the new cr3 value map to physical memory? (Note, we
438 * catch an invalid cr3 even in real-mode, because it would
439 * cause trouble later on when we turn on paging anyway.)
440 *
441 * A real CPU would silently accept an invalid cr3 and would
442 * attempt to use it - with largely undefined (and often hard
443 * to debug) behavior on the guest side.
444 */
445 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
446 kvm_inject_gp(vcpu, 0);
447 else {
448 vcpu->arch.cr3 = cr3;
449 vcpu->arch.mmu.new_cr3(vcpu);
450 }
451 }
452 EXPORT_SYMBOL_GPL(kvm_set_cr3);
453
454 void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
455 {
456 if (cr8 & CR8_RESERVED_BITS) {
457 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
458 kvm_inject_gp(vcpu, 0);
459 return;
460 }
461 if (irqchip_in_kernel(vcpu->kvm))
462 kvm_lapic_set_tpr(vcpu, cr8);
463 else
464 vcpu->arch.cr8 = cr8;
465 }
466 EXPORT_SYMBOL_GPL(kvm_set_cr8);
467
468 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
469 {
470 if (irqchip_in_kernel(vcpu->kvm))
471 return kvm_lapic_get_cr8(vcpu);
472 else
473 return vcpu->arch.cr8;
474 }
475 EXPORT_SYMBOL_GPL(kvm_get_cr8);
476
477 static inline u32 bit(int bitno)
478 {
479 return 1 << (bitno & 31);
480 }
481
482 /*
483 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
484 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
485 *
486 * This list is modified at module load time to reflect the
487 * capabilities of the host cpu. This capabilities test skips MSRs that are
488 * kvm-specific. Those are put in the beginning of the list.
489 */
490
491 #define KVM_SAVE_MSRS_BEGIN 2
492 static u32 msrs_to_save[] = {
493 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
494 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
495 MSR_K6_STAR,
496 #ifdef CONFIG_X86_64
497 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
498 #endif
499 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
500 };
501
502 static unsigned num_msrs_to_save;
503
504 static u32 emulated_msrs[] = {
505 MSR_IA32_MISC_ENABLE,
506 };
507
508 static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
509 {
510 if (efer & efer_reserved_bits) {
511 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
512 efer);
513 kvm_inject_gp(vcpu, 0);
514 return;
515 }
516
517 if (is_paging(vcpu)
518 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
519 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
520 kvm_inject_gp(vcpu, 0);
521 return;
522 }
523
524 if (efer & EFER_FFXSR) {
525 struct kvm_cpuid_entry2 *feat;
526
527 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
528 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
529 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
530 kvm_inject_gp(vcpu, 0);
531 return;
532 }
533 }
534
535 if (efer & EFER_SVME) {
536 struct kvm_cpuid_entry2 *feat;
537
538 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
539 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
540 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
541 kvm_inject_gp(vcpu, 0);
542 return;
543 }
544 }
545
546 kvm_x86_ops->set_efer(vcpu, efer);
547
548 efer &= ~EFER_LMA;
549 efer |= vcpu->arch.shadow_efer & EFER_LMA;
550
551 vcpu->arch.shadow_efer = efer;
552
553 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
554 kvm_mmu_reset_context(vcpu);
555 }
556
557 void kvm_enable_efer_bits(u64 mask)
558 {
559 efer_reserved_bits &= ~mask;
560 }
561 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
562
563
564 /*
565 * Writes msr value into into the appropriate "register".
566 * Returns 0 on success, non-0 otherwise.
567 * Assumes vcpu_load() was already called.
568 */
569 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
570 {
571 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
572 }
573
574 /*
575 * Adapt set_msr() to msr_io()'s calling convention
576 */
577 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
578 {
579 return kvm_set_msr(vcpu, index, *data);
580 }
581
582 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
583 {
584 static int version;
585 struct pvclock_wall_clock wc;
586 struct timespec now, sys, boot;
587
588 if (!wall_clock)
589 return;
590
591 version++;
592
593 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
594
595 /*
596 * The guest calculates current wall clock time by adding
597 * system time (updated by kvm_write_guest_time below) to the
598 * wall clock specified here. guest system time equals host
599 * system time for us, thus we must fill in host boot time here.
600 */
601 now = current_kernel_time();
602 ktime_get_ts(&sys);
603 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
604
605 wc.sec = boot.tv_sec;
606 wc.nsec = boot.tv_nsec;
607 wc.version = version;
608
609 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
610
611 version++;
612 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
613 }
614
615 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
616 {
617 uint32_t quotient, remainder;
618
619 /* Don't try to replace with do_div(), this one calculates
620 * "(dividend << 32) / divisor" */
621 __asm__ ( "divl %4"
622 : "=a" (quotient), "=d" (remainder)
623 : "0" (0), "1" (dividend), "r" (divisor) );
624 return quotient;
625 }
626
627 static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
628 {
629 uint64_t nsecs = 1000000000LL;
630 int32_t shift = 0;
631 uint64_t tps64;
632 uint32_t tps32;
633
634 tps64 = tsc_khz * 1000LL;
635 while (tps64 > nsecs*2) {
636 tps64 >>= 1;
637 shift--;
638 }
639
640 tps32 = (uint32_t)tps64;
641 while (tps32 <= (uint32_t)nsecs) {
642 tps32 <<= 1;
643 shift++;
644 }
645
646 hv_clock->tsc_shift = shift;
647 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
648
649 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
650 __func__, tsc_khz, hv_clock->tsc_shift,
651 hv_clock->tsc_to_system_mul);
652 }
653
654 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
655
656 static void kvm_write_guest_time(struct kvm_vcpu *v)
657 {
658 struct timespec ts;
659 unsigned long flags;
660 struct kvm_vcpu_arch *vcpu = &v->arch;
661 void *shared_kaddr;
662 unsigned long this_tsc_khz;
663
664 if ((!vcpu->time_page))
665 return;
666
667 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
668 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
669 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
670 vcpu->hv_clock_tsc_khz = this_tsc_khz;
671 }
672 put_cpu_var(cpu_tsc_khz);
673
674 /* Keep irq disabled to prevent changes to the clock */
675 local_irq_save(flags);
676 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
677 ktime_get_ts(&ts);
678 local_irq_restore(flags);
679
680 /* With all the info we got, fill in the values */
681
682 vcpu->hv_clock.system_time = ts.tv_nsec +
683 (NSEC_PER_SEC * (u64)ts.tv_sec);
684 /*
685 * The interface expects us to write an even number signaling that the
686 * update is finished. Since the guest won't see the intermediate
687 * state, we just increase by 2 at the end.
688 */
689 vcpu->hv_clock.version += 2;
690
691 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
692
693 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
694 sizeof(vcpu->hv_clock));
695
696 kunmap_atomic(shared_kaddr, KM_USER0);
697
698 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
699 }
700
701 static int kvm_request_guest_time_update(struct kvm_vcpu *v)
702 {
703 struct kvm_vcpu_arch *vcpu = &v->arch;
704
705 if (!vcpu->time_page)
706 return 0;
707 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
708 return 1;
709 }
710
711 static bool msr_mtrr_valid(unsigned msr)
712 {
713 switch (msr) {
714 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
715 case MSR_MTRRfix64K_00000:
716 case MSR_MTRRfix16K_80000:
717 case MSR_MTRRfix16K_A0000:
718 case MSR_MTRRfix4K_C0000:
719 case MSR_MTRRfix4K_C8000:
720 case MSR_MTRRfix4K_D0000:
721 case MSR_MTRRfix4K_D8000:
722 case MSR_MTRRfix4K_E0000:
723 case MSR_MTRRfix4K_E8000:
724 case MSR_MTRRfix4K_F0000:
725 case MSR_MTRRfix4K_F8000:
726 case MSR_MTRRdefType:
727 case MSR_IA32_CR_PAT:
728 return true;
729 case 0x2f8:
730 return true;
731 }
732 return false;
733 }
734
735 static bool valid_pat_type(unsigned t)
736 {
737 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
738 }
739
740 static bool valid_mtrr_type(unsigned t)
741 {
742 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
743 }
744
745 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
746 {
747 int i;
748
749 if (!msr_mtrr_valid(msr))
750 return false;
751
752 if (msr == MSR_IA32_CR_PAT) {
753 for (i = 0; i < 8; i++)
754 if (!valid_pat_type((data >> (i * 8)) & 0xff))
755 return false;
756 return true;
757 } else if (msr == MSR_MTRRdefType) {
758 if (data & ~0xcff)
759 return false;
760 return valid_mtrr_type(data & 0xff);
761 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
762 for (i = 0; i < 8 ; i++)
763 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
764 return false;
765 return true;
766 }
767
768 /* variable MTRRs */
769 return valid_mtrr_type(data & 0xff);
770 }
771
772 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
773 {
774 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
775
776 if (!mtrr_valid(vcpu, msr, data))
777 return 1;
778
779 if (msr == MSR_MTRRdefType) {
780 vcpu->arch.mtrr_state.def_type = data;
781 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
782 } else if (msr == MSR_MTRRfix64K_00000)
783 p[0] = data;
784 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
785 p[1 + msr - MSR_MTRRfix16K_80000] = data;
786 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
787 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
788 else if (msr == MSR_IA32_CR_PAT)
789 vcpu->arch.pat = data;
790 else { /* Variable MTRRs */
791 int idx, is_mtrr_mask;
792 u64 *pt;
793
794 idx = (msr - 0x200) / 2;
795 is_mtrr_mask = msr - 0x200 - 2 * idx;
796 if (!is_mtrr_mask)
797 pt =
798 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
799 else
800 pt =
801 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
802 *pt = data;
803 }
804
805 kvm_mmu_reset_context(vcpu);
806 return 0;
807 }
808
809 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
810 {
811 u64 mcg_cap = vcpu->arch.mcg_cap;
812 unsigned bank_num = mcg_cap & 0xff;
813
814 switch (msr) {
815 case MSR_IA32_MCG_STATUS:
816 vcpu->arch.mcg_status = data;
817 break;
818 case MSR_IA32_MCG_CTL:
819 if (!(mcg_cap & MCG_CTL_P))
820 return 1;
821 if (data != 0 && data != ~(u64)0)
822 return -1;
823 vcpu->arch.mcg_ctl = data;
824 break;
825 default:
826 if (msr >= MSR_IA32_MC0_CTL &&
827 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
828 u32 offset = msr - MSR_IA32_MC0_CTL;
829 /* only 0 or all 1s can be written to IA32_MCi_CTL */
830 if ((offset & 0x3) == 0 &&
831 data != 0 && data != ~(u64)0)
832 return -1;
833 vcpu->arch.mce_banks[offset] = data;
834 break;
835 }
836 return 1;
837 }
838 return 0;
839 }
840
841 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
842 {
843 switch (msr) {
844 case MSR_EFER:
845 set_efer(vcpu, data);
846 break;
847 case MSR_K7_HWCR:
848 data &= ~(u64)0x40; /* ignore flush filter disable */
849 if (data != 0) {
850 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
851 data);
852 return 1;
853 }
854 break;
855 case MSR_FAM10H_MMIO_CONF_BASE:
856 if (data != 0) {
857 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
858 "0x%llx\n", data);
859 return 1;
860 }
861 break;
862 case MSR_AMD64_NB_CFG:
863 break;
864 case MSR_IA32_DEBUGCTLMSR:
865 if (!data) {
866 /* We support the non-activated case already */
867 break;
868 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
869 /* Values other than LBR and BTF are vendor-specific,
870 thus reserved and should throw a #GP */
871 return 1;
872 }
873 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
874 __func__, data);
875 break;
876 case MSR_IA32_UCODE_REV:
877 case MSR_IA32_UCODE_WRITE:
878 case MSR_VM_HSAVE_PA:
879 case MSR_AMD64_PATCH_LOADER:
880 break;
881 case 0x200 ... 0x2ff:
882 return set_msr_mtrr(vcpu, msr, data);
883 case MSR_IA32_APICBASE:
884 kvm_set_apic_base(vcpu, data);
885 break;
886 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
887 return kvm_x2apic_msr_write(vcpu, msr, data);
888 case MSR_IA32_MISC_ENABLE:
889 vcpu->arch.ia32_misc_enable_msr = data;
890 break;
891 case MSR_KVM_WALL_CLOCK:
892 vcpu->kvm->arch.wall_clock = data;
893 kvm_write_wall_clock(vcpu->kvm, data);
894 break;
895 case MSR_KVM_SYSTEM_TIME: {
896 if (vcpu->arch.time_page) {
897 kvm_release_page_dirty(vcpu->arch.time_page);
898 vcpu->arch.time_page = NULL;
899 }
900
901 vcpu->arch.time = data;
902
903 /* we verify if the enable bit is set... */
904 if (!(data & 1))
905 break;
906
907 /* ...but clean it before doing the actual write */
908 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
909
910 vcpu->arch.time_page =
911 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
912
913 if (is_error_page(vcpu->arch.time_page)) {
914 kvm_release_page_clean(vcpu->arch.time_page);
915 vcpu->arch.time_page = NULL;
916 }
917
918 kvm_request_guest_time_update(vcpu);
919 break;
920 }
921 case MSR_IA32_MCG_CTL:
922 case MSR_IA32_MCG_STATUS:
923 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
924 return set_msr_mce(vcpu, msr, data);
925
926 /* Performance counters are not protected by a CPUID bit,
927 * so we should check all of them in the generic path for the sake of
928 * cross vendor migration.
929 * Writing a zero into the event select MSRs disables them,
930 * which we perfectly emulate ;-). Any other value should be at least
931 * reported, some guests depend on them.
932 */
933 case MSR_P6_EVNTSEL0:
934 case MSR_P6_EVNTSEL1:
935 case MSR_K7_EVNTSEL0:
936 case MSR_K7_EVNTSEL1:
937 case MSR_K7_EVNTSEL2:
938 case MSR_K7_EVNTSEL3:
939 if (data != 0)
940 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
941 "0x%x data 0x%llx\n", msr, data);
942 break;
943 /* at least RHEL 4 unconditionally writes to the perfctr registers,
944 * so we ignore writes to make it happy.
945 */
946 case MSR_P6_PERFCTR0:
947 case MSR_P6_PERFCTR1:
948 case MSR_K7_PERFCTR0:
949 case MSR_K7_PERFCTR1:
950 case MSR_K7_PERFCTR2:
951 case MSR_K7_PERFCTR3:
952 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
953 "0x%x data 0x%llx\n", msr, data);
954 break;
955 default:
956 if (!ignore_msrs) {
957 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
958 msr, data);
959 return 1;
960 } else {
961 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
962 msr, data);
963 break;
964 }
965 }
966 return 0;
967 }
968 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
969
970
971 /*
972 * Reads an msr value (of 'msr_index') into 'pdata'.
973 * Returns 0 on success, non-0 otherwise.
974 * Assumes vcpu_load() was already called.
975 */
976 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
977 {
978 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
979 }
980
981 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
982 {
983 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
984
985 if (!msr_mtrr_valid(msr))
986 return 1;
987
988 if (msr == MSR_MTRRdefType)
989 *pdata = vcpu->arch.mtrr_state.def_type +
990 (vcpu->arch.mtrr_state.enabled << 10);
991 else if (msr == MSR_MTRRfix64K_00000)
992 *pdata = p[0];
993 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
994 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
995 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
996 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
997 else if (msr == MSR_IA32_CR_PAT)
998 *pdata = vcpu->arch.pat;
999 else { /* Variable MTRRs */
1000 int idx, is_mtrr_mask;
1001 u64 *pt;
1002
1003 idx = (msr - 0x200) / 2;
1004 is_mtrr_mask = msr - 0x200 - 2 * idx;
1005 if (!is_mtrr_mask)
1006 pt =
1007 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1008 else
1009 pt =
1010 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1011 *pdata = *pt;
1012 }
1013
1014 return 0;
1015 }
1016
1017 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1018 {
1019 u64 data;
1020 u64 mcg_cap = vcpu->arch.mcg_cap;
1021 unsigned bank_num = mcg_cap & 0xff;
1022
1023 switch (msr) {
1024 case MSR_IA32_P5_MC_ADDR:
1025 case MSR_IA32_P5_MC_TYPE:
1026 data = 0;
1027 break;
1028 case MSR_IA32_MCG_CAP:
1029 data = vcpu->arch.mcg_cap;
1030 break;
1031 case MSR_IA32_MCG_CTL:
1032 if (!(mcg_cap & MCG_CTL_P))
1033 return 1;
1034 data = vcpu->arch.mcg_ctl;
1035 break;
1036 case MSR_IA32_MCG_STATUS:
1037 data = vcpu->arch.mcg_status;
1038 break;
1039 default:
1040 if (msr >= MSR_IA32_MC0_CTL &&
1041 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1042 u32 offset = msr - MSR_IA32_MC0_CTL;
1043 data = vcpu->arch.mce_banks[offset];
1044 break;
1045 }
1046 return 1;
1047 }
1048 *pdata = data;
1049 return 0;
1050 }
1051
1052 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1053 {
1054 u64 data;
1055
1056 switch (msr) {
1057 case MSR_IA32_PLATFORM_ID:
1058 case MSR_IA32_UCODE_REV:
1059 case MSR_IA32_EBL_CR_POWERON:
1060 case MSR_IA32_DEBUGCTLMSR:
1061 case MSR_IA32_LASTBRANCHFROMIP:
1062 case MSR_IA32_LASTBRANCHTOIP:
1063 case MSR_IA32_LASTINTFROMIP:
1064 case MSR_IA32_LASTINTTOIP:
1065 case MSR_K8_SYSCFG:
1066 case MSR_K7_HWCR:
1067 case MSR_VM_HSAVE_PA:
1068 case MSR_P6_PERFCTR0:
1069 case MSR_P6_PERFCTR1:
1070 case MSR_P6_EVNTSEL0:
1071 case MSR_P6_EVNTSEL1:
1072 case MSR_K7_EVNTSEL0:
1073 case MSR_K7_PERFCTR0:
1074 case MSR_K8_INT_PENDING_MSG:
1075 case MSR_AMD64_NB_CFG:
1076 case MSR_FAM10H_MMIO_CONF_BASE:
1077 data = 0;
1078 break;
1079 case MSR_MTRRcap:
1080 data = 0x500 | KVM_NR_VAR_MTRR;
1081 break;
1082 case 0x200 ... 0x2ff:
1083 return get_msr_mtrr(vcpu, msr, pdata);
1084 case 0xcd: /* fsb frequency */
1085 data = 3;
1086 break;
1087 case MSR_IA32_APICBASE:
1088 data = kvm_get_apic_base(vcpu);
1089 break;
1090 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1091 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1092 break;
1093 case MSR_IA32_MISC_ENABLE:
1094 data = vcpu->arch.ia32_misc_enable_msr;
1095 break;
1096 case MSR_IA32_PERF_STATUS:
1097 /* TSC increment by tick */
1098 data = 1000ULL;
1099 /* CPU multiplier */
1100 data |= (((uint64_t)4ULL) << 40);
1101 break;
1102 case MSR_EFER:
1103 data = vcpu->arch.shadow_efer;
1104 break;
1105 case MSR_KVM_WALL_CLOCK:
1106 data = vcpu->kvm->arch.wall_clock;
1107 break;
1108 case MSR_KVM_SYSTEM_TIME:
1109 data = vcpu->arch.time;
1110 break;
1111 case MSR_IA32_P5_MC_ADDR:
1112 case MSR_IA32_P5_MC_TYPE:
1113 case MSR_IA32_MCG_CAP:
1114 case MSR_IA32_MCG_CTL:
1115 case MSR_IA32_MCG_STATUS:
1116 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1117 return get_msr_mce(vcpu, msr, pdata);
1118 default:
1119 if (!ignore_msrs) {
1120 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1121 return 1;
1122 } else {
1123 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1124 data = 0;
1125 }
1126 break;
1127 }
1128 *pdata = data;
1129 return 0;
1130 }
1131 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1132
1133 /*
1134 * Read or write a bunch of msrs. All parameters are kernel addresses.
1135 *
1136 * @return number of msrs set successfully.
1137 */
1138 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1139 struct kvm_msr_entry *entries,
1140 int (*do_msr)(struct kvm_vcpu *vcpu,
1141 unsigned index, u64 *data))
1142 {
1143 int i;
1144
1145 vcpu_load(vcpu);
1146
1147 down_read(&vcpu->kvm->slots_lock);
1148 for (i = 0; i < msrs->nmsrs; ++i)
1149 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1150 break;
1151 up_read(&vcpu->kvm->slots_lock);
1152
1153 vcpu_put(vcpu);
1154
1155 return i;
1156 }
1157
1158 /*
1159 * Read or write a bunch of msrs. Parameters are user addresses.
1160 *
1161 * @return number of msrs set successfully.
1162 */
1163 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1164 int (*do_msr)(struct kvm_vcpu *vcpu,
1165 unsigned index, u64 *data),
1166 int writeback)
1167 {
1168 struct kvm_msrs msrs;
1169 struct kvm_msr_entry *entries;
1170 int r, n;
1171 unsigned size;
1172
1173 r = -EFAULT;
1174 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1175 goto out;
1176
1177 r = -E2BIG;
1178 if (msrs.nmsrs >= MAX_IO_MSRS)
1179 goto out;
1180
1181 r = -ENOMEM;
1182 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1183 entries = vmalloc(size);
1184 if (!entries)
1185 goto out;
1186
1187 r = -EFAULT;
1188 if (copy_from_user(entries, user_msrs->entries, size))
1189 goto out_free;
1190
1191 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1192 if (r < 0)
1193 goto out_free;
1194
1195 r = -EFAULT;
1196 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1197 goto out_free;
1198
1199 r = n;
1200
1201 out_free:
1202 vfree(entries);
1203 out:
1204 return r;
1205 }
1206
1207 int kvm_dev_ioctl_check_extension(long ext)
1208 {
1209 int r;
1210
1211 switch (ext) {
1212 case KVM_CAP_IRQCHIP:
1213 case KVM_CAP_HLT:
1214 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1215 case KVM_CAP_SET_TSS_ADDR:
1216 case KVM_CAP_EXT_CPUID:
1217 case KVM_CAP_CLOCKSOURCE:
1218 case KVM_CAP_PIT:
1219 case KVM_CAP_NOP_IO_DELAY:
1220 case KVM_CAP_MP_STATE:
1221 case KVM_CAP_SYNC_MMU:
1222 case KVM_CAP_REINJECT_CONTROL:
1223 case KVM_CAP_IRQ_INJECT_STATUS:
1224 case KVM_CAP_ASSIGN_DEV_IRQ:
1225 case KVM_CAP_IRQFD:
1226 case KVM_CAP_IOEVENTFD:
1227 case KVM_CAP_PIT2:
1228 case KVM_CAP_PIT_STATE2:
1229 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
1230 r = 1;
1231 break;
1232 case KVM_CAP_COALESCED_MMIO:
1233 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1234 break;
1235 case KVM_CAP_VAPIC:
1236 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1237 break;
1238 case KVM_CAP_NR_VCPUS:
1239 r = KVM_MAX_VCPUS;
1240 break;
1241 case KVM_CAP_NR_MEMSLOTS:
1242 r = KVM_MEMORY_SLOTS;
1243 break;
1244 case KVM_CAP_PV_MMU:
1245 r = !tdp_enabled;
1246 break;
1247 case KVM_CAP_IOMMU:
1248 r = iommu_found();
1249 break;
1250 case KVM_CAP_MCE:
1251 r = KVM_MAX_MCE_BANKS;
1252 break;
1253 default:
1254 r = 0;
1255 break;
1256 }
1257 return r;
1258
1259 }
1260
1261 long kvm_arch_dev_ioctl(struct file *filp,
1262 unsigned int ioctl, unsigned long arg)
1263 {
1264 void __user *argp = (void __user *)arg;
1265 long r;
1266
1267 switch (ioctl) {
1268 case KVM_GET_MSR_INDEX_LIST: {
1269 struct kvm_msr_list __user *user_msr_list = argp;
1270 struct kvm_msr_list msr_list;
1271 unsigned n;
1272
1273 r = -EFAULT;
1274 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1275 goto out;
1276 n = msr_list.nmsrs;
1277 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1278 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1279 goto out;
1280 r = -E2BIG;
1281 if (n < msr_list.nmsrs)
1282 goto out;
1283 r = -EFAULT;
1284 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1285 num_msrs_to_save * sizeof(u32)))
1286 goto out;
1287 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
1288 &emulated_msrs,
1289 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1290 goto out;
1291 r = 0;
1292 break;
1293 }
1294 case KVM_GET_SUPPORTED_CPUID: {
1295 struct kvm_cpuid2 __user *cpuid_arg = argp;
1296 struct kvm_cpuid2 cpuid;
1297
1298 r = -EFAULT;
1299 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1300 goto out;
1301 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1302 cpuid_arg->entries);
1303 if (r)
1304 goto out;
1305
1306 r = -EFAULT;
1307 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1308 goto out;
1309 r = 0;
1310 break;
1311 }
1312 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1313 u64 mce_cap;
1314
1315 mce_cap = KVM_MCE_CAP_SUPPORTED;
1316 r = -EFAULT;
1317 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1318 goto out;
1319 r = 0;
1320 break;
1321 }
1322 default:
1323 r = -EINVAL;
1324 }
1325 out:
1326 return r;
1327 }
1328
1329 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1330 {
1331 kvm_x86_ops->vcpu_load(vcpu, cpu);
1332 kvm_request_guest_time_update(vcpu);
1333 }
1334
1335 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1336 {
1337 kvm_x86_ops->vcpu_put(vcpu);
1338 kvm_put_guest_fpu(vcpu);
1339 }
1340
1341 static int is_efer_nx(void)
1342 {
1343 unsigned long long efer = 0;
1344
1345 rdmsrl_safe(MSR_EFER, &efer);
1346 return efer & EFER_NX;
1347 }
1348
1349 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1350 {
1351 int i;
1352 struct kvm_cpuid_entry2 *e, *entry;
1353
1354 entry = NULL;
1355 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1356 e = &vcpu->arch.cpuid_entries[i];
1357 if (e->function == 0x80000001) {
1358 entry = e;
1359 break;
1360 }
1361 }
1362 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
1363 entry->edx &= ~(1 << 20);
1364 printk(KERN_INFO "kvm: guest NX capability removed\n");
1365 }
1366 }
1367
1368 /* when an old userspace process fills a new kernel module */
1369 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1370 struct kvm_cpuid *cpuid,
1371 struct kvm_cpuid_entry __user *entries)
1372 {
1373 int r, i;
1374 struct kvm_cpuid_entry *cpuid_entries;
1375
1376 r = -E2BIG;
1377 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1378 goto out;
1379 r = -ENOMEM;
1380 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1381 if (!cpuid_entries)
1382 goto out;
1383 r = -EFAULT;
1384 if (copy_from_user(cpuid_entries, entries,
1385 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1386 goto out_free;
1387 for (i = 0; i < cpuid->nent; i++) {
1388 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1389 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1390 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1391 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1392 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1393 vcpu->arch.cpuid_entries[i].index = 0;
1394 vcpu->arch.cpuid_entries[i].flags = 0;
1395 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1396 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1397 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1398 }
1399 vcpu->arch.cpuid_nent = cpuid->nent;
1400 cpuid_fix_nx_cap(vcpu);
1401 r = 0;
1402 kvm_apic_set_version(vcpu);
1403
1404 out_free:
1405 vfree(cpuid_entries);
1406 out:
1407 return r;
1408 }
1409
1410 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1411 struct kvm_cpuid2 *cpuid,
1412 struct kvm_cpuid_entry2 __user *entries)
1413 {
1414 int r;
1415
1416 r = -E2BIG;
1417 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1418 goto out;
1419 r = -EFAULT;
1420 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
1421 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
1422 goto out;
1423 vcpu->arch.cpuid_nent = cpuid->nent;
1424 kvm_apic_set_version(vcpu);
1425 return 0;
1426
1427 out:
1428 return r;
1429 }
1430
1431 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1432 struct kvm_cpuid2 *cpuid,
1433 struct kvm_cpuid_entry2 __user *entries)
1434 {
1435 int r;
1436
1437 r = -E2BIG;
1438 if (cpuid->nent < vcpu->arch.cpuid_nent)
1439 goto out;
1440 r = -EFAULT;
1441 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1442 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
1443 goto out;
1444 return 0;
1445
1446 out:
1447 cpuid->nent = vcpu->arch.cpuid_nent;
1448 return r;
1449 }
1450
1451 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1452 u32 index)
1453 {
1454 entry->function = function;
1455 entry->index = index;
1456 cpuid_count(entry->function, entry->index,
1457 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1458 entry->flags = 0;
1459 }
1460
1461 #define F(x) bit(X86_FEATURE_##x)
1462
1463 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1464 u32 index, int *nent, int maxnent)
1465 {
1466 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
1467 unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
1468 #ifdef CONFIG_X86_64
1469 unsigned f_lm = F(LM);
1470 #else
1471 unsigned f_lm = 0;
1472 #endif
1473
1474 /* cpuid 1.edx */
1475 const u32 kvm_supported_word0_x86_features =
1476 F(FPU) | F(VME) | F(DE) | F(PSE) |
1477 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1478 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1479 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1480 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1481 0 /* Reserved, DS, ACPI */ | F(MMX) |
1482 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1483 0 /* HTT, TM, Reserved, PBE */;
1484 /* cpuid 0x80000001.edx */
1485 const u32 kvm_supported_word1_x86_features =
1486 F(FPU) | F(VME) | F(DE) | F(PSE) |
1487 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1488 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1489 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1490 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1491 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1492 F(FXSR) | F(FXSR_OPT) | f_gbpages | 0 /* RDTSCP */ |
1493 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1494 /* cpuid 1.ecx */
1495 const u32 kvm_supported_word4_x86_features =
1496 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1497 0 /* DS-CPL, VMX, SMX, EST */ |
1498 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1499 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1500 0 /* Reserved, DCA */ | F(XMM4_1) |
1501 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
1502 0 /* Reserved, XSAVE, OSXSAVE */;
1503 /* cpuid 0x80000001.ecx */
1504 const u32 kvm_supported_word6_x86_features =
1505 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1506 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1507 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1508 0 /* SKINIT */ | 0 /* WDT */;
1509
1510 /* all calls to cpuid_count() should be made on the same cpu */
1511 get_cpu();
1512 do_cpuid_1_ent(entry, function, index);
1513 ++*nent;
1514
1515 switch (function) {
1516 case 0:
1517 entry->eax = min(entry->eax, (u32)0xb);
1518 break;
1519 case 1:
1520 entry->edx &= kvm_supported_word0_x86_features;
1521 entry->ecx &= kvm_supported_word4_x86_features;
1522 /* we support x2apic emulation even if host does not support
1523 * it since we emulate x2apic in software */
1524 entry->ecx |= F(X2APIC);
1525 break;
1526 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1527 * may return different values. This forces us to get_cpu() before
1528 * issuing the first command, and also to emulate this annoying behavior
1529 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1530 case 2: {
1531 int t, times = entry->eax & 0xff;
1532
1533 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1534 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
1535 for (t = 1; t < times && *nent < maxnent; ++t) {
1536 do_cpuid_1_ent(&entry[t], function, 0);
1537 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1538 ++*nent;
1539 }
1540 break;
1541 }
1542 /* function 4 and 0xb have additional index. */
1543 case 4: {
1544 int i, cache_type;
1545
1546 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1547 /* read more entries until cache_type is zero */
1548 for (i = 1; *nent < maxnent; ++i) {
1549 cache_type = entry[i - 1].eax & 0x1f;
1550 if (!cache_type)
1551 break;
1552 do_cpuid_1_ent(&entry[i], function, i);
1553 entry[i].flags |=
1554 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1555 ++*nent;
1556 }
1557 break;
1558 }
1559 case 0xb: {
1560 int i, level_type;
1561
1562 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1563 /* read more entries until level_type is zero */
1564 for (i = 1; *nent < maxnent; ++i) {
1565 level_type = entry[i - 1].ecx & 0xff00;
1566 if (!level_type)
1567 break;
1568 do_cpuid_1_ent(&entry[i], function, i);
1569 entry[i].flags |=
1570 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1571 ++*nent;
1572 }
1573 break;
1574 }
1575 case 0x80000000:
1576 entry->eax = min(entry->eax, 0x8000001a);
1577 break;
1578 case 0x80000001:
1579 entry->edx &= kvm_supported_word1_x86_features;
1580 entry->ecx &= kvm_supported_word6_x86_features;
1581 break;
1582 }
1583 put_cpu();
1584 }
1585
1586 #undef F
1587
1588 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
1589 struct kvm_cpuid_entry2 __user *entries)
1590 {
1591 struct kvm_cpuid_entry2 *cpuid_entries;
1592 int limit, nent = 0, r = -E2BIG;
1593 u32 func;
1594
1595 if (cpuid->nent < 1)
1596 goto out;
1597 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1598 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
1599 r = -ENOMEM;
1600 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1601 if (!cpuid_entries)
1602 goto out;
1603
1604 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1605 limit = cpuid_entries[0].eax;
1606 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1607 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1608 &nent, cpuid->nent);
1609 r = -E2BIG;
1610 if (nent >= cpuid->nent)
1611 goto out_free;
1612
1613 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1614 limit = cpuid_entries[nent - 1].eax;
1615 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1616 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1617 &nent, cpuid->nent);
1618 r = -E2BIG;
1619 if (nent >= cpuid->nent)
1620 goto out_free;
1621
1622 r = -EFAULT;
1623 if (copy_to_user(entries, cpuid_entries,
1624 nent * sizeof(struct kvm_cpuid_entry2)))
1625 goto out_free;
1626 cpuid->nent = nent;
1627 r = 0;
1628
1629 out_free:
1630 vfree(cpuid_entries);
1631 out:
1632 return r;
1633 }
1634
1635 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1636 struct kvm_lapic_state *s)
1637 {
1638 vcpu_load(vcpu);
1639 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
1640 vcpu_put(vcpu);
1641
1642 return 0;
1643 }
1644
1645 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1646 struct kvm_lapic_state *s)
1647 {
1648 vcpu_load(vcpu);
1649 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1650 kvm_apic_post_state_restore(vcpu);
1651 update_cr8_intercept(vcpu);
1652 vcpu_put(vcpu);
1653
1654 return 0;
1655 }
1656
1657 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1658 struct kvm_interrupt *irq)
1659 {
1660 if (irq->irq < 0 || irq->irq >= 256)
1661 return -EINVAL;
1662 if (irqchip_in_kernel(vcpu->kvm))
1663 return -ENXIO;
1664 vcpu_load(vcpu);
1665
1666 kvm_queue_interrupt(vcpu, irq->irq, false);
1667
1668 vcpu_put(vcpu);
1669
1670 return 0;
1671 }
1672
1673 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1674 {
1675 vcpu_load(vcpu);
1676 kvm_inject_nmi(vcpu);
1677 vcpu_put(vcpu);
1678
1679 return 0;
1680 }
1681
1682 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1683 struct kvm_tpr_access_ctl *tac)
1684 {
1685 if (tac->flags)
1686 return -EINVAL;
1687 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1688 return 0;
1689 }
1690
1691 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1692 u64 mcg_cap)
1693 {
1694 int r;
1695 unsigned bank_num = mcg_cap & 0xff, bank;
1696
1697 r = -EINVAL;
1698 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
1699 goto out;
1700 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1701 goto out;
1702 r = 0;
1703 vcpu->arch.mcg_cap = mcg_cap;
1704 /* Init IA32_MCG_CTL to all 1s */
1705 if (mcg_cap & MCG_CTL_P)
1706 vcpu->arch.mcg_ctl = ~(u64)0;
1707 /* Init IA32_MCi_CTL to all 1s */
1708 for (bank = 0; bank < bank_num; bank++)
1709 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1710 out:
1711 return r;
1712 }
1713
1714 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1715 struct kvm_x86_mce *mce)
1716 {
1717 u64 mcg_cap = vcpu->arch.mcg_cap;
1718 unsigned bank_num = mcg_cap & 0xff;
1719 u64 *banks = vcpu->arch.mce_banks;
1720
1721 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1722 return -EINVAL;
1723 /*
1724 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1725 * reporting is disabled
1726 */
1727 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1728 vcpu->arch.mcg_ctl != ~(u64)0)
1729 return 0;
1730 banks += 4 * mce->bank;
1731 /*
1732 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1733 * reporting is disabled for the bank
1734 */
1735 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1736 return 0;
1737 if (mce->status & MCI_STATUS_UC) {
1738 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1739 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1740 printk(KERN_DEBUG "kvm: set_mce: "
1741 "injects mce exception while "
1742 "previous one is in progress!\n");
1743 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1744 return 0;
1745 }
1746 if (banks[1] & MCI_STATUS_VAL)
1747 mce->status |= MCI_STATUS_OVER;
1748 banks[2] = mce->addr;
1749 banks[3] = mce->misc;
1750 vcpu->arch.mcg_status = mce->mcg_status;
1751 banks[1] = mce->status;
1752 kvm_queue_exception(vcpu, MC_VECTOR);
1753 } else if (!(banks[1] & MCI_STATUS_VAL)
1754 || !(banks[1] & MCI_STATUS_UC)) {
1755 if (banks[1] & MCI_STATUS_VAL)
1756 mce->status |= MCI_STATUS_OVER;
1757 banks[2] = mce->addr;
1758 banks[3] = mce->misc;
1759 banks[1] = mce->status;
1760 } else
1761 banks[1] |= MCI_STATUS_OVER;
1762 return 0;
1763 }
1764
1765 long kvm_arch_vcpu_ioctl(struct file *filp,
1766 unsigned int ioctl, unsigned long arg)
1767 {
1768 struct kvm_vcpu *vcpu = filp->private_data;
1769 void __user *argp = (void __user *)arg;
1770 int r;
1771 struct kvm_lapic_state *lapic = NULL;
1772
1773 switch (ioctl) {
1774 case KVM_GET_LAPIC: {
1775 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1776
1777 r = -ENOMEM;
1778 if (!lapic)
1779 goto out;
1780 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
1781 if (r)
1782 goto out;
1783 r = -EFAULT;
1784 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
1785 goto out;
1786 r = 0;
1787 break;
1788 }
1789 case KVM_SET_LAPIC: {
1790 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1791 r = -ENOMEM;
1792 if (!lapic)
1793 goto out;
1794 r = -EFAULT;
1795 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
1796 goto out;
1797 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
1798 if (r)
1799 goto out;
1800 r = 0;
1801 break;
1802 }
1803 case KVM_INTERRUPT: {
1804 struct kvm_interrupt irq;
1805
1806 r = -EFAULT;
1807 if (copy_from_user(&irq, argp, sizeof irq))
1808 goto out;
1809 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1810 if (r)
1811 goto out;
1812 r = 0;
1813 break;
1814 }
1815 case KVM_NMI: {
1816 r = kvm_vcpu_ioctl_nmi(vcpu);
1817 if (r)
1818 goto out;
1819 r = 0;
1820 break;
1821 }
1822 case KVM_SET_CPUID: {
1823 struct kvm_cpuid __user *cpuid_arg = argp;
1824 struct kvm_cpuid cpuid;
1825
1826 r = -EFAULT;
1827 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1828 goto out;
1829 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1830 if (r)
1831 goto out;
1832 break;
1833 }
1834 case KVM_SET_CPUID2: {
1835 struct kvm_cpuid2 __user *cpuid_arg = argp;
1836 struct kvm_cpuid2 cpuid;
1837
1838 r = -EFAULT;
1839 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1840 goto out;
1841 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1842 cpuid_arg->entries);
1843 if (r)
1844 goto out;
1845 break;
1846 }
1847 case KVM_GET_CPUID2: {
1848 struct kvm_cpuid2 __user *cpuid_arg = argp;
1849 struct kvm_cpuid2 cpuid;
1850
1851 r = -EFAULT;
1852 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1853 goto out;
1854 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1855 cpuid_arg->entries);
1856 if (r)
1857 goto out;
1858 r = -EFAULT;
1859 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1860 goto out;
1861 r = 0;
1862 break;
1863 }
1864 case KVM_GET_MSRS:
1865 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1866 break;
1867 case KVM_SET_MSRS:
1868 r = msr_io(vcpu, argp, do_set_msr, 0);
1869 break;
1870 case KVM_TPR_ACCESS_REPORTING: {
1871 struct kvm_tpr_access_ctl tac;
1872
1873 r = -EFAULT;
1874 if (copy_from_user(&tac, argp, sizeof tac))
1875 goto out;
1876 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1877 if (r)
1878 goto out;
1879 r = -EFAULT;
1880 if (copy_to_user(argp, &tac, sizeof tac))
1881 goto out;
1882 r = 0;
1883 break;
1884 };
1885 case KVM_SET_VAPIC_ADDR: {
1886 struct kvm_vapic_addr va;
1887
1888 r = -EINVAL;
1889 if (!irqchip_in_kernel(vcpu->kvm))
1890 goto out;
1891 r = -EFAULT;
1892 if (copy_from_user(&va, argp, sizeof va))
1893 goto out;
1894 r = 0;
1895 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1896 break;
1897 }
1898 case KVM_X86_SETUP_MCE: {
1899 u64 mcg_cap;
1900
1901 r = -EFAULT;
1902 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1903 goto out;
1904 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1905 break;
1906 }
1907 case KVM_X86_SET_MCE: {
1908 struct kvm_x86_mce mce;
1909
1910 r = -EFAULT;
1911 if (copy_from_user(&mce, argp, sizeof mce))
1912 goto out;
1913 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1914 break;
1915 }
1916 default:
1917 r = -EINVAL;
1918 }
1919 out:
1920 kfree(lapic);
1921 return r;
1922 }
1923
1924 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1925 {
1926 int ret;
1927
1928 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1929 return -1;
1930 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1931 return ret;
1932 }
1933
1934 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
1935 u64 ident_addr)
1936 {
1937 kvm->arch.ept_identity_map_addr = ident_addr;
1938 return 0;
1939 }
1940
1941 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1942 u32 kvm_nr_mmu_pages)
1943 {
1944 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1945 return -EINVAL;
1946
1947 down_write(&kvm->slots_lock);
1948 spin_lock(&kvm->mmu_lock);
1949
1950 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
1951 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1952
1953 spin_unlock(&kvm->mmu_lock);
1954 up_write(&kvm->slots_lock);
1955 return 0;
1956 }
1957
1958 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1959 {
1960 return kvm->arch.n_alloc_mmu_pages;
1961 }
1962
1963 gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1964 {
1965 int i;
1966 struct kvm_mem_alias *alias;
1967
1968 for (i = 0; i < kvm->arch.naliases; ++i) {
1969 alias = &kvm->arch.aliases[i];
1970 if (gfn >= alias->base_gfn
1971 && gfn < alias->base_gfn + alias->npages)
1972 return alias->target_gfn + gfn - alias->base_gfn;
1973 }
1974 return gfn;
1975 }
1976
1977 /*
1978 * Set a new alias region. Aliases map a portion of physical memory into
1979 * another portion. This is useful for memory windows, for example the PC
1980 * VGA region.
1981 */
1982 static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1983 struct kvm_memory_alias *alias)
1984 {
1985 int r, n;
1986 struct kvm_mem_alias *p;
1987
1988 r = -EINVAL;
1989 /* General sanity checks */
1990 if (alias->memory_size & (PAGE_SIZE - 1))
1991 goto out;
1992 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1993 goto out;
1994 if (alias->slot >= KVM_ALIAS_SLOTS)
1995 goto out;
1996 if (alias->guest_phys_addr + alias->memory_size
1997 < alias->guest_phys_addr)
1998 goto out;
1999 if (alias->target_phys_addr + alias->memory_size
2000 < alias->target_phys_addr)
2001 goto out;
2002
2003 down_write(&kvm->slots_lock);
2004 spin_lock(&kvm->mmu_lock);
2005
2006 p = &kvm->arch.aliases[alias->slot];
2007 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2008 p->npages = alias->memory_size >> PAGE_SHIFT;
2009 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
2010
2011 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
2012 if (kvm->arch.aliases[n - 1].npages)
2013 break;
2014 kvm->arch.naliases = n;
2015
2016 spin_unlock(&kvm->mmu_lock);
2017 kvm_mmu_zap_all(kvm);
2018
2019 up_write(&kvm->slots_lock);
2020
2021 return 0;
2022
2023 out:
2024 return r;
2025 }
2026
2027 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2028 {
2029 int r;
2030
2031 r = 0;
2032 switch (chip->chip_id) {
2033 case KVM_IRQCHIP_PIC_MASTER:
2034 memcpy(&chip->chip.pic,
2035 &pic_irqchip(kvm)->pics[0],
2036 sizeof(struct kvm_pic_state));
2037 break;
2038 case KVM_IRQCHIP_PIC_SLAVE:
2039 memcpy(&chip->chip.pic,
2040 &pic_irqchip(kvm)->pics[1],
2041 sizeof(struct kvm_pic_state));
2042 break;
2043 case KVM_IRQCHIP_IOAPIC:
2044 memcpy(&chip->chip.ioapic,
2045 ioapic_irqchip(kvm),
2046 sizeof(struct kvm_ioapic_state));
2047 break;
2048 default:
2049 r = -EINVAL;
2050 break;
2051 }
2052 return r;
2053 }
2054
2055 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2056 {
2057 int r;
2058
2059 r = 0;
2060 switch (chip->chip_id) {
2061 case KVM_IRQCHIP_PIC_MASTER:
2062 spin_lock(&pic_irqchip(kvm)->lock);
2063 memcpy(&pic_irqchip(kvm)->pics[0],
2064 &chip->chip.pic,
2065 sizeof(struct kvm_pic_state));
2066 spin_unlock(&pic_irqchip(kvm)->lock);
2067 break;
2068 case KVM_IRQCHIP_PIC_SLAVE:
2069 spin_lock(&pic_irqchip(kvm)->lock);
2070 memcpy(&pic_irqchip(kvm)->pics[1],
2071 &chip->chip.pic,
2072 sizeof(struct kvm_pic_state));
2073 spin_unlock(&pic_irqchip(kvm)->lock);
2074 break;
2075 case KVM_IRQCHIP_IOAPIC:
2076 mutex_lock(&kvm->irq_lock);
2077 memcpy(ioapic_irqchip(kvm),
2078 &chip->chip.ioapic,
2079 sizeof(struct kvm_ioapic_state));
2080 mutex_unlock(&kvm->irq_lock);
2081 break;
2082 default:
2083 r = -EINVAL;
2084 break;
2085 }
2086 kvm_pic_update_irq(pic_irqchip(kvm));
2087 return r;
2088 }
2089
2090 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2091 {
2092 int r = 0;
2093
2094 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2095 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2096 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2097 return r;
2098 }
2099
2100 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2101 {
2102 int r = 0;
2103
2104 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2105 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2106 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2107 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2108 return r;
2109 }
2110
2111 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2112 {
2113 int r = 0;
2114
2115 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2116 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2117 sizeof(ps->channels));
2118 ps->flags = kvm->arch.vpit->pit_state.flags;
2119 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2120 return r;
2121 }
2122
2123 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2124 {
2125 int r = 0, start = 0;
2126 u32 prev_legacy, cur_legacy;
2127 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2128 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2129 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2130 if (!prev_legacy && cur_legacy)
2131 start = 1;
2132 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2133 sizeof(kvm->arch.vpit->pit_state.channels));
2134 kvm->arch.vpit->pit_state.flags = ps->flags;
2135 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
2136 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2137 return r;
2138 }
2139
2140 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2141 struct kvm_reinject_control *control)
2142 {
2143 if (!kvm->arch.vpit)
2144 return -ENXIO;
2145 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2146 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
2147 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2148 return 0;
2149 }
2150
2151 /*
2152 * Get (and clear) the dirty memory log for a memory slot.
2153 */
2154 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2155 struct kvm_dirty_log *log)
2156 {
2157 int r;
2158 int n;
2159 struct kvm_memory_slot *memslot;
2160 int is_dirty = 0;
2161
2162 down_write(&kvm->slots_lock);
2163
2164 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2165 if (r)
2166 goto out;
2167
2168 /* If nothing is dirty, don't bother messing with page tables. */
2169 if (is_dirty) {
2170 spin_lock(&kvm->mmu_lock);
2171 kvm_mmu_slot_remove_write_access(kvm, log->slot);
2172 spin_unlock(&kvm->mmu_lock);
2173 memslot = &kvm->memslots[log->slot];
2174 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2175 memset(memslot->dirty_bitmap, 0, n);
2176 }
2177 r = 0;
2178 out:
2179 up_write(&kvm->slots_lock);
2180 return r;
2181 }
2182
2183 long kvm_arch_vm_ioctl(struct file *filp,
2184 unsigned int ioctl, unsigned long arg)
2185 {
2186 struct kvm *kvm = filp->private_data;
2187 void __user *argp = (void __user *)arg;
2188 int r = -EINVAL;
2189 /*
2190 * This union makes it completely explicit to gcc-3.x
2191 * that these two variables' stack usage should be
2192 * combined, not added together.
2193 */
2194 union {
2195 struct kvm_pit_state ps;
2196 struct kvm_pit_state2 ps2;
2197 struct kvm_memory_alias alias;
2198 struct kvm_pit_config pit_config;
2199 } u;
2200
2201 switch (ioctl) {
2202 case KVM_SET_TSS_ADDR:
2203 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2204 if (r < 0)
2205 goto out;
2206 break;
2207 case KVM_SET_IDENTITY_MAP_ADDR: {
2208 u64 ident_addr;
2209
2210 r = -EFAULT;
2211 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2212 goto out;
2213 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2214 if (r < 0)
2215 goto out;
2216 break;
2217 }
2218 case KVM_SET_MEMORY_REGION: {
2219 struct kvm_memory_region kvm_mem;
2220 struct kvm_userspace_memory_region kvm_userspace_mem;
2221
2222 r = -EFAULT;
2223 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2224 goto out;
2225 kvm_userspace_mem.slot = kvm_mem.slot;
2226 kvm_userspace_mem.flags = kvm_mem.flags;
2227 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2228 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2229 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2230 if (r)
2231 goto out;
2232 break;
2233 }
2234 case KVM_SET_NR_MMU_PAGES:
2235 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2236 if (r)
2237 goto out;
2238 break;
2239 case KVM_GET_NR_MMU_PAGES:
2240 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2241 break;
2242 case KVM_SET_MEMORY_ALIAS:
2243 r = -EFAULT;
2244 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
2245 goto out;
2246 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
2247 if (r)
2248 goto out;
2249 break;
2250 case KVM_CREATE_IRQCHIP:
2251 r = -ENOMEM;
2252 kvm->arch.vpic = kvm_create_pic(kvm);
2253 if (kvm->arch.vpic) {
2254 r = kvm_ioapic_init(kvm);
2255 if (r) {
2256 kfree(kvm->arch.vpic);
2257 kvm->arch.vpic = NULL;
2258 goto out;
2259 }
2260 } else
2261 goto out;
2262 r = kvm_setup_default_irq_routing(kvm);
2263 if (r) {
2264 kfree(kvm->arch.vpic);
2265 kfree(kvm->arch.vioapic);
2266 goto out;
2267 }
2268 break;
2269 case KVM_CREATE_PIT:
2270 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2271 goto create_pit;
2272 case KVM_CREATE_PIT2:
2273 r = -EFAULT;
2274 if (copy_from_user(&u.pit_config, argp,
2275 sizeof(struct kvm_pit_config)))
2276 goto out;
2277 create_pit:
2278 down_write(&kvm->slots_lock);
2279 r = -EEXIST;
2280 if (kvm->arch.vpit)
2281 goto create_pit_unlock;
2282 r = -ENOMEM;
2283 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
2284 if (kvm->arch.vpit)
2285 r = 0;
2286 create_pit_unlock:
2287 up_write(&kvm->slots_lock);
2288 break;
2289 case KVM_IRQ_LINE_STATUS:
2290 case KVM_IRQ_LINE: {
2291 struct kvm_irq_level irq_event;
2292
2293 r = -EFAULT;
2294 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2295 goto out;
2296 if (irqchip_in_kernel(kvm)) {
2297 __s32 status;
2298 mutex_lock(&kvm->irq_lock);
2299 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2300 irq_event.irq, irq_event.level);
2301 mutex_unlock(&kvm->irq_lock);
2302 if (ioctl == KVM_IRQ_LINE_STATUS) {
2303 irq_event.status = status;
2304 if (copy_to_user(argp, &irq_event,
2305 sizeof irq_event))
2306 goto out;
2307 }
2308 r = 0;
2309 }
2310 break;
2311 }
2312 case KVM_GET_IRQCHIP: {
2313 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2314 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2315
2316 r = -ENOMEM;
2317 if (!chip)
2318 goto out;
2319 r = -EFAULT;
2320 if (copy_from_user(chip, argp, sizeof *chip))
2321 goto get_irqchip_out;
2322 r = -ENXIO;
2323 if (!irqchip_in_kernel(kvm))
2324 goto get_irqchip_out;
2325 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
2326 if (r)
2327 goto get_irqchip_out;
2328 r = -EFAULT;
2329 if (copy_to_user(argp, chip, sizeof *chip))
2330 goto get_irqchip_out;
2331 r = 0;
2332 get_irqchip_out:
2333 kfree(chip);
2334 if (r)
2335 goto out;
2336 break;
2337 }
2338 case KVM_SET_IRQCHIP: {
2339 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2340 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2341
2342 r = -ENOMEM;
2343 if (!chip)
2344 goto out;
2345 r = -EFAULT;
2346 if (copy_from_user(chip, argp, sizeof *chip))
2347 goto set_irqchip_out;
2348 r = -ENXIO;
2349 if (!irqchip_in_kernel(kvm))
2350 goto set_irqchip_out;
2351 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
2352 if (r)
2353 goto set_irqchip_out;
2354 r = 0;
2355 set_irqchip_out:
2356 kfree(chip);
2357 if (r)
2358 goto out;
2359 break;
2360 }
2361 case KVM_GET_PIT: {
2362 r = -EFAULT;
2363 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
2364 goto out;
2365 r = -ENXIO;
2366 if (!kvm->arch.vpit)
2367 goto out;
2368 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
2369 if (r)
2370 goto out;
2371 r = -EFAULT;
2372 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
2373 goto out;
2374 r = 0;
2375 break;
2376 }
2377 case KVM_SET_PIT: {
2378 r = -EFAULT;
2379 if (copy_from_user(&u.ps, argp, sizeof u.ps))
2380 goto out;
2381 r = -ENXIO;
2382 if (!kvm->arch.vpit)
2383 goto out;
2384 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
2385 if (r)
2386 goto out;
2387 r = 0;
2388 break;
2389 }
2390 case KVM_GET_PIT2: {
2391 r = -ENXIO;
2392 if (!kvm->arch.vpit)
2393 goto out;
2394 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2395 if (r)
2396 goto out;
2397 r = -EFAULT;
2398 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2399 goto out;
2400 r = 0;
2401 break;
2402 }
2403 case KVM_SET_PIT2: {
2404 r = -EFAULT;
2405 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2406 goto out;
2407 r = -ENXIO;
2408 if (!kvm->arch.vpit)
2409 goto out;
2410 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2411 if (r)
2412 goto out;
2413 r = 0;
2414 break;
2415 }
2416 case KVM_REINJECT_CONTROL: {
2417 struct kvm_reinject_control control;
2418 r = -EFAULT;
2419 if (copy_from_user(&control, argp, sizeof(control)))
2420 goto out;
2421 r = kvm_vm_ioctl_reinject(kvm, &control);
2422 if (r)
2423 goto out;
2424 r = 0;
2425 break;
2426 }
2427 default:
2428 ;
2429 }
2430 out:
2431 return r;
2432 }
2433
2434 static void kvm_init_msr_list(void)
2435 {
2436 u32 dummy[2];
2437 unsigned i, j;
2438
2439 /* skip the first msrs in the list. KVM-specific */
2440 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
2441 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2442 continue;
2443 if (j < i)
2444 msrs_to_save[j] = msrs_to_save[i];
2445 j++;
2446 }
2447 num_msrs_to_save = j;
2448 }
2449
2450 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2451 const void *v)
2452 {
2453 if (vcpu->arch.apic &&
2454 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2455 return 0;
2456
2457 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
2458 }
2459
2460 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
2461 {
2462 if (vcpu->arch.apic &&
2463 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2464 return 0;
2465
2466 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
2467 }
2468
2469 static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2470 struct kvm_vcpu *vcpu)
2471 {
2472 void *data = val;
2473 int r = X86EMUL_CONTINUE;
2474
2475 while (bytes) {
2476 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2477 unsigned offset = addr & (PAGE_SIZE-1);
2478 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
2479 int ret;
2480
2481 if (gpa == UNMAPPED_GVA) {
2482 r = X86EMUL_PROPAGATE_FAULT;
2483 goto out;
2484 }
2485 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
2486 if (ret < 0) {
2487 r = X86EMUL_UNHANDLEABLE;
2488 goto out;
2489 }
2490
2491 bytes -= toread;
2492 data += toread;
2493 addr += toread;
2494 }
2495 out:
2496 return r;
2497 }
2498
2499 static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2500 struct kvm_vcpu *vcpu)
2501 {
2502 void *data = val;
2503 int r = X86EMUL_CONTINUE;
2504
2505 while (bytes) {
2506 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2507 unsigned offset = addr & (PAGE_SIZE-1);
2508 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2509 int ret;
2510
2511 if (gpa == UNMAPPED_GVA) {
2512 r = X86EMUL_PROPAGATE_FAULT;
2513 goto out;
2514 }
2515 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2516 if (ret < 0) {
2517 r = X86EMUL_UNHANDLEABLE;
2518 goto out;
2519 }
2520
2521 bytes -= towrite;
2522 data += towrite;
2523 addr += towrite;
2524 }
2525 out:
2526 return r;
2527 }
2528
2529
2530 static int emulator_read_emulated(unsigned long addr,
2531 void *val,
2532 unsigned int bytes,
2533 struct kvm_vcpu *vcpu)
2534 {
2535 gpa_t gpa;
2536
2537 if (vcpu->mmio_read_completed) {
2538 memcpy(val, vcpu->mmio_data, bytes);
2539 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2540 vcpu->mmio_phys_addr, *(u64 *)val);
2541 vcpu->mmio_read_completed = 0;
2542 return X86EMUL_CONTINUE;
2543 }
2544
2545 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2546
2547 /* For APIC access vmexit */
2548 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2549 goto mmio;
2550
2551 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2552 == X86EMUL_CONTINUE)
2553 return X86EMUL_CONTINUE;
2554 if (gpa == UNMAPPED_GVA)
2555 return X86EMUL_PROPAGATE_FAULT;
2556
2557 mmio:
2558 /*
2559 * Is this MMIO handled locally?
2560 */
2561 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2562 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
2563 return X86EMUL_CONTINUE;
2564 }
2565
2566 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
2567
2568 vcpu->mmio_needed = 1;
2569 vcpu->mmio_phys_addr = gpa;
2570 vcpu->mmio_size = bytes;
2571 vcpu->mmio_is_write = 0;
2572
2573 return X86EMUL_UNHANDLEABLE;
2574 }
2575
2576 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
2577 const void *val, int bytes)
2578 {
2579 int ret;
2580
2581 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
2582 if (ret < 0)
2583 return 0;
2584 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
2585 return 1;
2586 }
2587
2588 static int emulator_write_emulated_onepage(unsigned long addr,
2589 const void *val,
2590 unsigned int bytes,
2591 struct kvm_vcpu *vcpu)
2592 {
2593 gpa_t gpa;
2594
2595 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2596
2597 if (gpa == UNMAPPED_GVA) {
2598 kvm_inject_page_fault(vcpu, addr, 2);
2599 return X86EMUL_PROPAGATE_FAULT;
2600 }
2601
2602 /* For APIC access vmexit */
2603 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2604 goto mmio;
2605
2606 if (emulator_write_phys(vcpu, gpa, val, bytes))
2607 return X86EMUL_CONTINUE;
2608
2609 mmio:
2610 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
2611 /*
2612 * Is this MMIO handled locally?
2613 */
2614 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
2615 return X86EMUL_CONTINUE;
2616
2617 vcpu->mmio_needed = 1;
2618 vcpu->mmio_phys_addr = gpa;
2619 vcpu->mmio_size = bytes;
2620 vcpu->mmio_is_write = 1;
2621 memcpy(vcpu->mmio_data, val, bytes);
2622
2623 return X86EMUL_CONTINUE;
2624 }
2625
2626 int emulator_write_emulated(unsigned long addr,
2627 const void *val,
2628 unsigned int bytes,
2629 struct kvm_vcpu *vcpu)
2630 {
2631 /* Crossing a page boundary? */
2632 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2633 int rc, now;
2634
2635 now = -addr & ~PAGE_MASK;
2636 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2637 if (rc != X86EMUL_CONTINUE)
2638 return rc;
2639 addr += now;
2640 val += now;
2641 bytes -= now;
2642 }
2643 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2644 }
2645 EXPORT_SYMBOL_GPL(emulator_write_emulated);
2646
2647 static int emulator_cmpxchg_emulated(unsigned long addr,
2648 const void *old,
2649 const void *new,
2650 unsigned int bytes,
2651 struct kvm_vcpu *vcpu)
2652 {
2653 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2654 #ifndef CONFIG_X86_64
2655 /* guests cmpxchg8b have to be emulated atomically */
2656 if (bytes == 8) {
2657 gpa_t gpa;
2658 struct page *page;
2659 char *kaddr;
2660 u64 val;
2661
2662 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2663
2664 if (gpa == UNMAPPED_GVA ||
2665 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2666 goto emul_write;
2667
2668 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2669 goto emul_write;
2670
2671 val = *(u64 *)new;
2672
2673 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2674
2675 kaddr = kmap_atomic(page, KM_USER0);
2676 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2677 kunmap_atomic(kaddr, KM_USER0);
2678 kvm_release_page_dirty(page);
2679 }
2680 emul_write:
2681 #endif
2682
2683 return emulator_write_emulated(addr, new, bytes, vcpu);
2684 }
2685
2686 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2687 {
2688 return kvm_x86_ops->get_segment_base(vcpu, seg);
2689 }
2690
2691 int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2692 {
2693 kvm_mmu_invlpg(vcpu, address);
2694 return X86EMUL_CONTINUE;
2695 }
2696
2697 int emulate_clts(struct kvm_vcpu *vcpu)
2698 {
2699 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
2700 return X86EMUL_CONTINUE;
2701 }
2702
2703 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2704 {
2705 struct kvm_vcpu *vcpu = ctxt->vcpu;
2706
2707 switch (dr) {
2708 case 0 ... 3:
2709 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2710 return X86EMUL_CONTINUE;
2711 default:
2712 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
2713 return X86EMUL_UNHANDLEABLE;
2714 }
2715 }
2716
2717 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2718 {
2719 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2720 int exception;
2721
2722 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2723 if (exception) {
2724 /* FIXME: better handling */
2725 return X86EMUL_UNHANDLEABLE;
2726 }
2727 return X86EMUL_CONTINUE;
2728 }
2729
2730 void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2731 {
2732 u8 opcodes[4];
2733 unsigned long rip = kvm_rip_read(vcpu);
2734 unsigned long rip_linear;
2735
2736 if (!printk_ratelimit())
2737 return;
2738
2739 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2740
2741 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
2742
2743 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2744 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
2745 }
2746 EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2747
2748 static struct x86_emulate_ops emulate_ops = {
2749 .read_std = kvm_read_guest_virt,
2750 .read_emulated = emulator_read_emulated,
2751 .write_emulated = emulator_write_emulated,
2752 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2753 };
2754
2755 static void cache_all_regs(struct kvm_vcpu *vcpu)
2756 {
2757 kvm_register_read(vcpu, VCPU_REGS_RAX);
2758 kvm_register_read(vcpu, VCPU_REGS_RSP);
2759 kvm_register_read(vcpu, VCPU_REGS_RIP);
2760 vcpu->arch.regs_dirty = ~0;
2761 }
2762
2763 int emulate_instruction(struct kvm_vcpu *vcpu,
2764 struct kvm_run *run,
2765 unsigned long cr2,
2766 u16 error_code,
2767 int emulation_type)
2768 {
2769 int r, shadow_mask;
2770 struct decode_cache *c;
2771
2772 kvm_clear_exception_queue(vcpu);
2773 vcpu->arch.mmio_fault_cr2 = cr2;
2774 /*
2775 * TODO: fix emulate.c to use guest_read/write_register
2776 * instead of direct ->regs accesses, can save hundred cycles
2777 * on Intel for instructions that don't read/change RSP, for
2778 * for example.
2779 */
2780 cache_all_regs(vcpu);
2781
2782 vcpu->mmio_is_write = 0;
2783 vcpu->arch.pio.string = 0;
2784
2785 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
2786 int cs_db, cs_l;
2787 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2788
2789 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2790 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2791 vcpu->arch.emulate_ctxt.mode =
2792 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
2793 ? X86EMUL_MODE_REAL : cs_l
2794 ? X86EMUL_MODE_PROT64 : cs_db
2795 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2796
2797 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
2798
2799 /* Only allow emulation of specific instructions on #UD
2800 * (namely VMMCALL, sysenter, sysexit, syscall)*/
2801 c = &vcpu->arch.emulate_ctxt.decode;
2802 if (emulation_type & EMULTYPE_TRAP_UD) {
2803 if (!c->twobyte)
2804 return EMULATE_FAIL;
2805 switch (c->b) {
2806 case 0x01: /* VMMCALL */
2807 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2808 return EMULATE_FAIL;
2809 break;
2810 case 0x34: /* sysenter */
2811 case 0x35: /* sysexit */
2812 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2813 return EMULATE_FAIL;
2814 break;
2815 case 0x05: /* syscall */
2816 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2817 return EMULATE_FAIL;
2818 break;
2819 default:
2820 return EMULATE_FAIL;
2821 }
2822
2823 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2824 return EMULATE_FAIL;
2825 }
2826
2827 ++vcpu->stat.insn_emulation;
2828 if (r) {
2829 ++vcpu->stat.insn_emulation_fail;
2830 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2831 return EMULATE_DONE;
2832 return EMULATE_FAIL;
2833 }
2834 }
2835
2836 if (emulation_type & EMULTYPE_SKIP) {
2837 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2838 return EMULATE_DONE;
2839 }
2840
2841 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
2842 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2843
2844 if (r == 0)
2845 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
2846
2847 if (vcpu->arch.pio.string)
2848 return EMULATE_DO_MMIO;
2849
2850 if ((r || vcpu->mmio_is_write) && run) {
2851 run->exit_reason = KVM_EXIT_MMIO;
2852 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2853 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2854 run->mmio.len = vcpu->mmio_size;
2855 run->mmio.is_write = vcpu->mmio_is_write;
2856 }
2857
2858 if (r) {
2859 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2860 return EMULATE_DONE;
2861 if (!vcpu->mmio_needed) {
2862 kvm_report_emulation_failure(vcpu, "mmio");
2863 return EMULATE_FAIL;
2864 }
2865 return EMULATE_DO_MMIO;
2866 }
2867
2868 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
2869
2870 if (vcpu->mmio_is_write) {
2871 vcpu->mmio_needed = 0;
2872 return EMULATE_DO_MMIO;
2873 }
2874
2875 return EMULATE_DONE;
2876 }
2877 EXPORT_SYMBOL_GPL(emulate_instruction);
2878
2879 static int pio_copy_data(struct kvm_vcpu *vcpu)
2880 {
2881 void *p = vcpu->arch.pio_data;
2882 gva_t q = vcpu->arch.pio.guest_gva;
2883 unsigned bytes;
2884 int ret;
2885
2886 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2887 if (vcpu->arch.pio.in)
2888 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
2889 else
2890 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2891 return ret;
2892 }
2893
2894 int complete_pio(struct kvm_vcpu *vcpu)
2895 {
2896 struct kvm_pio_request *io = &vcpu->arch.pio;
2897 long delta;
2898 int r;
2899 unsigned long val;
2900
2901 if (!io->string) {
2902 if (io->in) {
2903 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2904 memcpy(&val, vcpu->arch.pio_data, io->size);
2905 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2906 }
2907 } else {
2908 if (io->in) {
2909 r = pio_copy_data(vcpu);
2910 if (r)
2911 return r;
2912 }
2913
2914 delta = 1;
2915 if (io->rep) {
2916 delta *= io->cur_count;
2917 /*
2918 * The size of the register should really depend on
2919 * current address size.
2920 */
2921 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2922 val -= delta;
2923 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
2924 }
2925 if (io->down)
2926 delta = -delta;
2927 delta *= io->size;
2928 if (io->in) {
2929 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2930 val += delta;
2931 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2932 } else {
2933 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2934 val += delta;
2935 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2936 }
2937 }
2938
2939 io->count -= io->cur_count;
2940 io->cur_count = 0;
2941
2942 return 0;
2943 }
2944
2945 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
2946 {
2947 /* TODO: String I/O for in kernel device */
2948 int r;
2949
2950 if (vcpu->arch.pio.in)
2951 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2952 vcpu->arch.pio.size, pd);
2953 else
2954 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2955 vcpu->arch.pio.size, pd);
2956 return r;
2957 }
2958
2959 static int pio_string_write(struct kvm_vcpu *vcpu)
2960 {
2961 struct kvm_pio_request *io = &vcpu->arch.pio;
2962 void *pd = vcpu->arch.pio_data;
2963 int i, r = 0;
2964
2965 for (i = 0; i < io->cur_count; i++) {
2966 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2967 io->port, io->size, pd)) {
2968 r = -EOPNOTSUPP;
2969 break;
2970 }
2971 pd += io->size;
2972 }
2973 return r;
2974 }
2975
2976 int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2977 int size, unsigned port)
2978 {
2979 unsigned long val;
2980
2981 vcpu->run->exit_reason = KVM_EXIT_IO;
2982 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
2983 vcpu->run->io.size = vcpu->arch.pio.size = size;
2984 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
2985 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2986 vcpu->run->io.port = vcpu->arch.pio.port = port;
2987 vcpu->arch.pio.in = in;
2988 vcpu->arch.pio.string = 0;
2989 vcpu->arch.pio.down = 0;
2990 vcpu->arch.pio.rep = 0;
2991
2992 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2993 size, 1);
2994
2995 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2996 memcpy(vcpu->arch.pio_data, &val, 4);
2997
2998 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
2999 complete_pio(vcpu);
3000 return 1;
3001 }
3002 return 0;
3003 }
3004 EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3005
3006 int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
3007 int size, unsigned long count, int down,
3008 gva_t address, int rep, unsigned port)
3009 {
3010 unsigned now, in_page;
3011 int ret = 0;
3012
3013 vcpu->run->exit_reason = KVM_EXIT_IO;
3014 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
3015 vcpu->run->io.size = vcpu->arch.pio.size = size;
3016 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3017 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3018 vcpu->run->io.port = vcpu->arch.pio.port = port;
3019 vcpu->arch.pio.in = in;
3020 vcpu->arch.pio.string = 1;
3021 vcpu->arch.pio.down = down;
3022 vcpu->arch.pio.rep = rep;
3023
3024 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3025 size, count);
3026
3027 if (!count) {
3028 kvm_x86_ops->skip_emulated_instruction(vcpu);
3029 return 1;
3030 }
3031
3032 if (!down)
3033 in_page = PAGE_SIZE - offset_in_page(address);
3034 else
3035 in_page = offset_in_page(address) + size;
3036 now = min(count, (unsigned long)in_page / size);
3037 if (!now)
3038 now = 1;
3039 if (down) {
3040 /*
3041 * String I/O in reverse. Yuck. Kill the guest, fix later.
3042 */
3043 pr_unimpl(vcpu, "guest string pio down\n");
3044 kvm_inject_gp(vcpu, 0);
3045 return 1;
3046 }
3047 vcpu->run->io.count = now;
3048 vcpu->arch.pio.cur_count = now;
3049
3050 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
3051 kvm_x86_ops->skip_emulated_instruction(vcpu);
3052
3053 vcpu->arch.pio.guest_gva = address;
3054
3055 if (!vcpu->arch.pio.in) {
3056 /* string PIO write */
3057 ret = pio_copy_data(vcpu);
3058 if (ret == X86EMUL_PROPAGATE_FAULT) {
3059 kvm_inject_gp(vcpu, 0);
3060 return 1;
3061 }
3062 if (ret == 0 && !pio_string_write(vcpu)) {
3063 complete_pio(vcpu);
3064 if (vcpu->arch.pio.count == 0)
3065 ret = 1;
3066 }
3067 }
3068 /* no string PIO read support yet */
3069
3070 return ret;
3071 }
3072 EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3073
3074 static void bounce_off(void *info)
3075 {
3076 /* nothing */
3077 }
3078
3079 static unsigned int ref_freq;
3080 static unsigned long tsc_khz_ref;
3081
3082 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3083 void *data)
3084 {
3085 struct cpufreq_freqs *freq = data;
3086 struct kvm *kvm;
3087 struct kvm_vcpu *vcpu;
3088 int i, send_ipi = 0;
3089
3090 if (!ref_freq)
3091 ref_freq = freq->old;
3092
3093 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3094 return 0;
3095 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3096 return 0;
3097 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3098
3099 spin_lock(&kvm_lock);
3100 list_for_each_entry(kvm, &vm_list, vm_list) {
3101 kvm_for_each_vcpu(i, vcpu, kvm) {
3102 if (vcpu->cpu != freq->cpu)
3103 continue;
3104 if (!kvm_request_guest_time_update(vcpu))
3105 continue;
3106 if (vcpu->cpu != smp_processor_id())
3107 send_ipi++;
3108 }
3109 }
3110 spin_unlock(&kvm_lock);
3111
3112 if (freq->old < freq->new && send_ipi) {
3113 /*
3114 * We upscale the frequency. Must make the guest
3115 * doesn't see old kvmclock values while running with
3116 * the new frequency, otherwise we risk the guest sees
3117 * time go backwards.
3118 *
3119 * In case we update the frequency for another cpu
3120 * (which might be in guest context) send an interrupt
3121 * to kick the cpu out of guest context. Next time
3122 * guest context is entered kvmclock will be updated,
3123 * so the guest will not see stale values.
3124 */
3125 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3126 }
3127 return 0;
3128 }
3129
3130 static struct notifier_block kvmclock_cpufreq_notifier_block = {
3131 .notifier_call = kvmclock_cpufreq_notifier
3132 };
3133
3134 int kvm_arch_init(void *opaque)
3135 {
3136 int r, cpu;
3137 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3138
3139 if (kvm_x86_ops) {
3140 printk(KERN_ERR "kvm: already loaded the other module\n");
3141 r = -EEXIST;
3142 goto out;
3143 }
3144
3145 if (!ops->cpu_has_kvm_support()) {
3146 printk(KERN_ERR "kvm: no hardware support\n");
3147 r = -EOPNOTSUPP;
3148 goto out;
3149 }
3150 if (ops->disabled_by_bios()) {
3151 printk(KERN_ERR "kvm: disabled by bios\n");
3152 r = -EOPNOTSUPP;
3153 goto out;
3154 }
3155
3156 r = kvm_mmu_module_init();
3157 if (r)
3158 goto out;
3159
3160 kvm_init_msr_list();
3161
3162 kvm_x86_ops = ops;
3163 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
3164 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3165 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
3166 PT_DIRTY_MASK, PT64_NX_MASK, 0);
3167
3168 for_each_possible_cpu(cpu)
3169 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3170 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3171 tsc_khz_ref = tsc_khz;
3172 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3173 CPUFREQ_TRANSITION_NOTIFIER);
3174 }
3175
3176 return 0;
3177
3178 out:
3179 return r;
3180 }
3181
3182 void kvm_arch_exit(void)
3183 {
3184 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3185 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3186 CPUFREQ_TRANSITION_NOTIFIER);
3187 kvm_x86_ops = NULL;
3188 kvm_mmu_module_exit();
3189 }
3190
3191 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3192 {
3193 ++vcpu->stat.halt_exits;
3194 if (irqchip_in_kernel(vcpu->kvm)) {
3195 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3196 return 1;
3197 } else {
3198 vcpu->run->exit_reason = KVM_EXIT_HLT;
3199 return 0;
3200 }
3201 }
3202 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3203
3204 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3205 unsigned long a1)
3206 {
3207 if (is_long_mode(vcpu))
3208 return a0;
3209 else
3210 return a0 | ((gpa_t)a1 << 32);
3211 }
3212
3213 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3214 {
3215 unsigned long nr, a0, a1, a2, a3, ret;
3216 int r = 1;
3217
3218 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3219 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3220 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3221 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3222 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
3223
3224 trace_kvm_hypercall(nr, a0, a1, a2, a3);
3225
3226 if (!is_long_mode(vcpu)) {
3227 nr &= 0xFFFFFFFF;
3228 a0 &= 0xFFFFFFFF;
3229 a1 &= 0xFFFFFFFF;
3230 a2 &= 0xFFFFFFFF;
3231 a3 &= 0xFFFFFFFF;
3232 }
3233
3234 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3235 ret = -KVM_EPERM;
3236 goto out;
3237 }
3238
3239 switch (nr) {
3240 case KVM_HC_VAPIC_POLL_IRQ:
3241 ret = 0;
3242 break;
3243 case KVM_HC_MMU_OP:
3244 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3245 break;
3246 default:
3247 ret = -KVM_ENOSYS;
3248 break;
3249 }
3250 out:
3251 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3252 ++vcpu->stat.hypercalls;
3253 return r;
3254 }
3255 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3256
3257 int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3258 {
3259 char instruction[3];
3260 int ret = 0;
3261 unsigned long rip = kvm_rip_read(vcpu);
3262
3263
3264 /*
3265 * Blow out the MMU to ensure that no other VCPU has an active mapping
3266 * to ensure that the updated hypercall appears atomically across all
3267 * VCPUs.
3268 */
3269 kvm_mmu_zap_all(vcpu->kvm);
3270
3271 kvm_x86_ops->patch_hypercall(vcpu, instruction);
3272 if (emulator_write_emulated(rip, instruction, 3, vcpu)
3273 != X86EMUL_CONTINUE)
3274 ret = -EFAULT;
3275
3276 return ret;
3277 }
3278
3279 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3280 {
3281 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3282 }
3283
3284 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3285 {
3286 struct descriptor_table dt = { limit, base };
3287
3288 kvm_x86_ops->set_gdt(vcpu, &dt);
3289 }
3290
3291 void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3292 {
3293 struct descriptor_table dt = { limit, base };
3294
3295 kvm_x86_ops->set_idt(vcpu, &dt);
3296 }
3297
3298 void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3299 unsigned long *rflags)
3300 {
3301 kvm_lmsw(vcpu, msw);
3302 *rflags = kvm_x86_ops->get_rflags(vcpu);
3303 }
3304
3305 unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3306 {
3307 unsigned long value;
3308
3309 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3310 switch (cr) {
3311 case 0:
3312 value = vcpu->arch.cr0;
3313 break;
3314 case 2:
3315 value = vcpu->arch.cr2;
3316 break;
3317 case 3:
3318 value = vcpu->arch.cr3;
3319 break;
3320 case 4:
3321 value = vcpu->arch.cr4;
3322 break;
3323 case 8:
3324 value = kvm_get_cr8(vcpu);
3325 break;
3326 default:
3327 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3328 return 0;
3329 }
3330
3331 return value;
3332 }
3333
3334 void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3335 unsigned long *rflags)
3336 {
3337 switch (cr) {
3338 case 0:
3339 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
3340 *rflags = kvm_x86_ops->get_rflags(vcpu);
3341 break;
3342 case 2:
3343 vcpu->arch.cr2 = val;
3344 break;
3345 case 3:
3346 kvm_set_cr3(vcpu, val);
3347 break;
3348 case 4:
3349 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
3350 break;
3351 case 8:
3352 kvm_set_cr8(vcpu, val & 0xfUL);
3353 break;
3354 default:
3355 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3356 }
3357 }
3358
3359 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3360 {
3361 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3362 int j, nent = vcpu->arch.cpuid_nent;
3363
3364 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3365 /* when no next entry is found, the current entry[i] is reselected */
3366 for (j = i + 1; ; j = (j + 1) % nent) {
3367 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
3368 if (ej->function == e->function) {
3369 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3370 return j;
3371 }
3372 }
3373 return 0; /* silence gcc, even though control never reaches here */
3374 }
3375
3376 /* find an entry with matching function, matching index (if needed), and that
3377 * should be read next (if it's stateful) */
3378 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3379 u32 function, u32 index)
3380 {
3381 if (e->function != function)
3382 return 0;
3383 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3384 return 0;
3385 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
3386 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
3387 return 0;
3388 return 1;
3389 }
3390
3391 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3392 u32 function, u32 index)
3393 {
3394 int i;
3395 struct kvm_cpuid_entry2 *best = NULL;
3396
3397 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
3398 struct kvm_cpuid_entry2 *e;
3399
3400 e = &vcpu->arch.cpuid_entries[i];
3401 if (is_matching_cpuid_entry(e, function, index)) {
3402 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3403 move_to_next_stateful_cpuid_entry(vcpu, i);
3404 best = e;
3405 break;
3406 }
3407 /*
3408 * Both basic or both extended?
3409 */
3410 if (((e->function ^ function) & 0x80000000) == 0)
3411 if (!best || e->function > best->function)
3412 best = e;
3413 }
3414 return best;
3415 }
3416
3417 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3418 {
3419 struct kvm_cpuid_entry2 *best;
3420
3421 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3422 if (best)
3423 return best->eax & 0xff;
3424 return 36;
3425 }
3426
3427 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3428 {
3429 u32 function, index;
3430 struct kvm_cpuid_entry2 *best;
3431
3432 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3433 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3434 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3435 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3436 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3437 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3438 best = kvm_find_cpuid_entry(vcpu, function, index);
3439 if (best) {
3440 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3441 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3442 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3443 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
3444 }
3445 kvm_x86_ops->skip_emulated_instruction(vcpu);
3446 trace_kvm_cpuid(function,
3447 kvm_register_read(vcpu, VCPU_REGS_RAX),
3448 kvm_register_read(vcpu, VCPU_REGS_RBX),
3449 kvm_register_read(vcpu, VCPU_REGS_RCX),
3450 kvm_register_read(vcpu, VCPU_REGS_RDX));
3451 }
3452 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
3453
3454 /*
3455 * Check if userspace requested an interrupt window, and that the
3456 * interrupt window is open.
3457 *
3458 * No need to exit to userspace if we already have an interrupt queued.
3459 */
3460 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3461 struct kvm_run *kvm_run)
3462 {
3463 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
3464 kvm_run->request_interrupt_window &&
3465 kvm_arch_interrupt_allowed(vcpu));
3466 }
3467
3468 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3469 struct kvm_run *kvm_run)
3470 {
3471 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
3472 kvm_run->cr8 = kvm_get_cr8(vcpu);
3473 kvm_run->apic_base = kvm_get_apic_base(vcpu);
3474 if (irqchip_in_kernel(vcpu->kvm))
3475 kvm_run->ready_for_interrupt_injection = 1;
3476 else
3477 kvm_run->ready_for_interrupt_injection =
3478 kvm_arch_interrupt_allowed(vcpu) &&
3479 !kvm_cpu_has_interrupt(vcpu) &&
3480 !kvm_event_needs_reinjection(vcpu);
3481 }
3482
3483 static void vapic_enter(struct kvm_vcpu *vcpu)
3484 {
3485 struct kvm_lapic *apic = vcpu->arch.apic;
3486 struct page *page;
3487
3488 if (!apic || !apic->vapic_addr)
3489 return;
3490
3491 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3492
3493 vcpu->arch.apic->vapic_page = page;
3494 }
3495
3496 static void vapic_exit(struct kvm_vcpu *vcpu)
3497 {
3498 struct kvm_lapic *apic = vcpu->arch.apic;
3499
3500 if (!apic || !apic->vapic_addr)
3501 return;
3502
3503 down_read(&vcpu->kvm->slots_lock);
3504 kvm_release_page_dirty(apic->vapic_page);
3505 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3506 up_read(&vcpu->kvm->slots_lock);
3507 }
3508
3509 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3510 {
3511 int max_irr, tpr;
3512
3513 if (!kvm_x86_ops->update_cr8_intercept)
3514 return;
3515
3516 if (!vcpu->arch.apic)
3517 return;
3518
3519 if (!vcpu->arch.apic->vapic_addr)
3520 max_irr = kvm_lapic_find_highest_irr(vcpu);
3521 else
3522 max_irr = -1;
3523
3524 if (max_irr != -1)
3525 max_irr >>= 4;
3526
3527 tpr = kvm_lapic_get_cr8(vcpu);
3528
3529 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3530 }
3531
3532 static void inject_pending_event(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3533 {
3534 /* try to reinject previous events if any */
3535 if (vcpu->arch.exception.pending) {
3536 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3537 vcpu->arch.exception.has_error_code,
3538 vcpu->arch.exception.error_code);
3539 return;
3540 }
3541
3542 if (vcpu->arch.nmi_injected) {
3543 kvm_x86_ops->set_nmi(vcpu);
3544 return;
3545 }
3546
3547 if (vcpu->arch.interrupt.pending) {
3548 kvm_x86_ops->set_irq(vcpu);
3549 return;
3550 }
3551
3552 /* try to inject new event if pending */
3553 if (vcpu->arch.nmi_pending) {
3554 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3555 vcpu->arch.nmi_pending = false;
3556 vcpu->arch.nmi_injected = true;
3557 kvm_x86_ops->set_nmi(vcpu);
3558 }
3559 } else if (kvm_cpu_has_interrupt(vcpu)) {
3560 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
3561 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3562 false);
3563 kvm_x86_ops->set_irq(vcpu);
3564 }
3565 }
3566 }
3567
3568 static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3569 {
3570 int r;
3571 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3572 kvm_run->request_interrupt_window;
3573
3574 if (vcpu->requests)
3575 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3576 kvm_mmu_unload(vcpu);
3577
3578 r = kvm_mmu_reload(vcpu);
3579 if (unlikely(r))
3580 goto out;
3581
3582 if (vcpu->requests) {
3583 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
3584 __kvm_migrate_timers(vcpu);
3585 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3586 kvm_write_guest_time(vcpu);
3587 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3588 kvm_mmu_sync_roots(vcpu);
3589 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3590 kvm_x86_ops->tlb_flush(vcpu);
3591 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3592 &vcpu->requests)) {
3593 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3594 r = 0;
3595 goto out;
3596 }
3597 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3598 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3599 r = 0;
3600 goto out;
3601 }
3602 }
3603
3604 preempt_disable();
3605
3606 kvm_x86_ops->prepare_guest_switch(vcpu);
3607 kvm_load_guest_fpu(vcpu);
3608
3609 local_irq_disable();
3610
3611 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3612 smp_mb__after_clear_bit();
3613
3614 if (vcpu->requests || need_resched() || signal_pending(current)) {
3615 set_bit(KVM_REQ_KICK, &vcpu->requests);
3616 local_irq_enable();
3617 preempt_enable();
3618 r = 1;
3619 goto out;
3620 }
3621
3622 inject_pending_event(vcpu, kvm_run);
3623
3624 /* enable NMI/IRQ window open exits if needed */
3625 if (vcpu->arch.nmi_pending)
3626 kvm_x86_ops->enable_nmi_window(vcpu);
3627 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3628 kvm_x86_ops->enable_irq_window(vcpu);
3629
3630 if (kvm_lapic_enabled(vcpu)) {
3631 update_cr8_intercept(vcpu);
3632 kvm_lapic_sync_to_vapic(vcpu);
3633 }
3634
3635 up_read(&vcpu->kvm->slots_lock);
3636
3637 kvm_guest_enter();
3638
3639 if (unlikely(vcpu->arch.switch_db_regs)) {
3640 set_debugreg(0, 7);
3641 set_debugreg(vcpu->arch.eff_db[0], 0);
3642 set_debugreg(vcpu->arch.eff_db[1], 1);
3643 set_debugreg(vcpu->arch.eff_db[2], 2);
3644 set_debugreg(vcpu->arch.eff_db[3], 3);
3645 }
3646
3647 trace_kvm_entry(vcpu->vcpu_id);
3648 kvm_x86_ops->run(vcpu, kvm_run);
3649
3650 if (unlikely(vcpu->arch.switch_db_regs || test_thread_flag(TIF_DEBUG))) {
3651 set_debugreg(current->thread.debugreg0, 0);
3652 set_debugreg(current->thread.debugreg1, 1);
3653 set_debugreg(current->thread.debugreg2, 2);
3654 set_debugreg(current->thread.debugreg3, 3);
3655 set_debugreg(current->thread.debugreg6, 6);
3656 set_debugreg(current->thread.debugreg7, 7);
3657 }
3658
3659 set_bit(KVM_REQ_KICK, &vcpu->requests);
3660 local_irq_enable();
3661
3662 ++vcpu->stat.exits;
3663
3664 /*
3665 * We must have an instruction between local_irq_enable() and
3666 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3667 * the interrupt shadow. The stat.exits increment will do nicely.
3668 * But we need to prevent reordering, hence this barrier():
3669 */
3670 barrier();
3671
3672 kvm_guest_exit();
3673
3674 preempt_enable();
3675
3676 down_read(&vcpu->kvm->slots_lock);
3677
3678 /*
3679 * Profile KVM exit RIPs:
3680 */
3681 if (unlikely(prof_on == KVM_PROFILING)) {
3682 unsigned long rip = kvm_rip_read(vcpu);
3683 profile_hit(KVM_PROFILING, (void *)rip);
3684 }
3685
3686
3687 kvm_lapic_sync_from_vapic(vcpu);
3688
3689 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
3690 out:
3691 return r;
3692 }
3693
3694
3695 static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3696 {
3697 int r;
3698
3699 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
3700 pr_debug("vcpu %d received sipi with vector # %x\n",
3701 vcpu->vcpu_id, vcpu->arch.sipi_vector);
3702 kvm_lapic_reset(vcpu);
3703 r = kvm_arch_vcpu_reset(vcpu);
3704 if (r)
3705 return r;
3706 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3707 }
3708
3709 down_read(&vcpu->kvm->slots_lock);
3710 vapic_enter(vcpu);
3711
3712 r = 1;
3713 while (r > 0) {
3714 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
3715 r = vcpu_enter_guest(vcpu, kvm_run);
3716 else {
3717 up_read(&vcpu->kvm->slots_lock);
3718 kvm_vcpu_block(vcpu);
3719 down_read(&vcpu->kvm->slots_lock);
3720 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3721 {
3722 switch(vcpu->arch.mp_state) {
3723 case KVM_MP_STATE_HALTED:
3724 vcpu->arch.mp_state =
3725 KVM_MP_STATE_RUNNABLE;
3726 case KVM_MP_STATE_RUNNABLE:
3727 break;
3728 case KVM_MP_STATE_SIPI_RECEIVED:
3729 default:
3730 r = -EINTR;
3731 break;
3732 }
3733 }
3734 }
3735
3736 if (r <= 0)
3737 break;
3738
3739 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3740 if (kvm_cpu_has_pending_timer(vcpu))
3741 kvm_inject_pending_timer_irqs(vcpu);
3742
3743 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3744 r = -EINTR;
3745 kvm_run->exit_reason = KVM_EXIT_INTR;
3746 ++vcpu->stat.request_irq_exits;
3747 }
3748 if (signal_pending(current)) {
3749 r = -EINTR;
3750 kvm_run->exit_reason = KVM_EXIT_INTR;
3751 ++vcpu->stat.signal_exits;
3752 }
3753 if (need_resched()) {
3754 up_read(&vcpu->kvm->slots_lock);
3755 kvm_resched(vcpu);
3756 down_read(&vcpu->kvm->slots_lock);
3757 }
3758 }
3759
3760 up_read(&vcpu->kvm->slots_lock);
3761 post_kvm_run_save(vcpu, kvm_run);
3762
3763 vapic_exit(vcpu);
3764
3765 return r;
3766 }
3767
3768 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3769 {
3770 int r;
3771 sigset_t sigsaved;
3772
3773 vcpu_load(vcpu);
3774
3775 if (vcpu->sigset_active)
3776 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3777
3778 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
3779 kvm_vcpu_block(vcpu);
3780 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
3781 r = -EAGAIN;
3782 goto out;
3783 }
3784
3785 /* re-sync apic's tpr */
3786 if (!irqchip_in_kernel(vcpu->kvm))
3787 kvm_set_cr8(vcpu, kvm_run->cr8);
3788
3789 if (vcpu->arch.pio.cur_count) {
3790 r = complete_pio(vcpu);
3791 if (r)
3792 goto out;
3793 }
3794 #if CONFIG_HAS_IOMEM
3795 if (vcpu->mmio_needed) {
3796 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3797 vcpu->mmio_read_completed = 1;
3798 vcpu->mmio_needed = 0;
3799
3800 down_read(&vcpu->kvm->slots_lock);
3801 r = emulate_instruction(vcpu, kvm_run,
3802 vcpu->arch.mmio_fault_cr2, 0,
3803 EMULTYPE_NO_DECODE);
3804 up_read(&vcpu->kvm->slots_lock);
3805 if (r == EMULATE_DO_MMIO) {
3806 /*
3807 * Read-modify-write. Back to userspace.
3808 */
3809 r = 0;
3810 goto out;
3811 }
3812 }
3813 #endif
3814 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3815 kvm_register_write(vcpu, VCPU_REGS_RAX,
3816 kvm_run->hypercall.ret);
3817
3818 r = __vcpu_run(vcpu, kvm_run);
3819
3820 out:
3821 if (vcpu->sigset_active)
3822 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3823
3824 vcpu_put(vcpu);
3825 return r;
3826 }
3827
3828 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3829 {
3830 vcpu_load(vcpu);
3831
3832 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3833 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3834 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3835 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3836 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3837 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3838 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3839 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3840 #ifdef CONFIG_X86_64
3841 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3842 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3843 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3844 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3845 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3846 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3847 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3848 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
3849 #endif
3850
3851 regs->rip = kvm_rip_read(vcpu);
3852 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3853
3854 /*
3855 * Don't leak debug flags in case they were set for guest debugging
3856 */
3857 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3858 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3859
3860 vcpu_put(vcpu);
3861
3862 return 0;
3863 }
3864
3865 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3866 {
3867 vcpu_load(vcpu);
3868
3869 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3870 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3871 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3872 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3873 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3874 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3875 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3876 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
3877 #ifdef CONFIG_X86_64
3878 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3879 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3880 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3881 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3882 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3883 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3884 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3885 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3886
3887 #endif
3888
3889 kvm_rip_write(vcpu, regs->rip);
3890 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3891
3892
3893 vcpu->arch.exception.pending = false;
3894
3895 vcpu_put(vcpu);
3896
3897 return 0;
3898 }
3899
3900 void kvm_get_segment(struct kvm_vcpu *vcpu,
3901 struct kvm_segment *var, int seg)
3902 {
3903 kvm_x86_ops->get_segment(vcpu, var, seg);
3904 }
3905
3906 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3907 {
3908 struct kvm_segment cs;
3909
3910 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
3911 *db = cs.db;
3912 *l = cs.l;
3913 }
3914 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3915
3916 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3917 struct kvm_sregs *sregs)
3918 {
3919 struct descriptor_table dt;
3920
3921 vcpu_load(vcpu);
3922
3923 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3924 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3925 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3926 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3927 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3928 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3929
3930 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3931 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3932
3933 kvm_x86_ops->get_idt(vcpu, &dt);
3934 sregs->idt.limit = dt.limit;
3935 sregs->idt.base = dt.base;
3936 kvm_x86_ops->get_gdt(vcpu, &dt);
3937 sregs->gdt.limit = dt.limit;
3938 sregs->gdt.base = dt.base;
3939
3940 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3941 sregs->cr0 = vcpu->arch.cr0;
3942 sregs->cr2 = vcpu->arch.cr2;
3943 sregs->cr3 = vcpu->arch.cr3;
3944 sregs->cr4 = vcpu->arch.cr4;
3945 sregs->cr8 = kvm_get_cr8(vcpu);
3946 sregs->efer = vcpu->arch.shadow_efer;
3947 sregs->apic_base = kvm_get_apic_base(vcpu);
3948
3949 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
3950
3951 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
3952 set_bit(vcpu->arch.interrupt.nr,
3953 (unsigned long *)sregs->interrupt_bitmap);
3954
3955 vcpu_put(vcpu);
3956
3957 return 0;
3958 }
3959
3960 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3961 struct kvm_mp_state *mp_state)
3962 {
3963 vcpu_load(vcpu);
3964 mp_state->mp_state = vcpu->arch.mp_state;
3965 vcpu_put(vcpu);
3966 return 0;
3967 }
3968
3969 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3970 struct kvm_mp_state *mp_state)
3971 {
3972 vcpu_load(vcpu);
3973 vcpu->arch.mp_state = mp_state->mp_state;
3974 vcpu_put(vcpu);
3975 return 0;
3976 }
3977
3978 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3979 struct kvm_segment *var, int seg)
3980 {
3981 kvm_x86_ops->set_segment(vcpu, var, seg);
3982 }
3983
3984 static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3985 struct kvm_segment *kvm_desct)
3986 {
3987 kvm_desct->base = get_desc_base(seg_desc);
3988 kvm_desct->limit = get_desc_limit(seg_desc);
3989 if (seg_desc->g) {
3990 kvm_desct->limit <<= 12;
3991 kvm_desct->limit |= 0xfff;
3992 }
3993 kvm_desct->selector = selector;
3994 kvm_desct->type = seg_desc->type;
3995 kvm_desct->present = seg_desc->p;
3996 kvm_desct->dpl = seg_desc->dpl;
3997 kvm_desct->db = seg_desc->d;
3998 kvm_desct->s = seg_desc->s;
3999 kvm_desct->l = seg_desc->l;
4000 kvm_desct->g = seg_desc->g;
4001 kvm_desct->avl = seg_desc->avl;
4002 if (!selector)
4003 kvm_desct->unusable = 1;
4004 else
4005 kvm_desct->unusable = 0;
4006 kvm_desct->padding = 0;
4007 }
4008
4009 static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4010 u16 selector,
4011 struct descriptor_table *dtable)
4012 {
4013 if (selector & 1 << 2) {
4014 struct kvm_segment kvm_seg;
4015
4016 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
4017
4018 if (kvm_seg.unusable)
4019 dtable->limit = 0;
4020 else
4021 dtable->limit = kvm_seg.limit;
4022 dtable->base = kvm_seg.base;
4023 }
4024 else
4025 kvm_x86_ops->get_gdt(vcpu, dtable);
4026 }
4027
4028 /* allowed just for 8 bytes segments */
4029 static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4030 struct desc_struct *seg_desc)
4031 {
4032 struct descriptor_table dtable;
4033 u16 index = selector >> 3;
4034
4035 get_segment_descriptor_dtable(vcpu, selector, &dtable);
4036
4037 if (dtable.limit < index * 8 + 7) {
4038 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4039 return 1;
4040 }
4041 return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
4042 }
4043
4044 /* allowed just for 8 bytes segments */
4045 static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4046 struct desc_struct *seg_desc)
4047 {
4048 struct descriptor_table dtable;
4049 u16 index = selector >> 3;
4050
4051 get_segment_descriptor_dtable(vcpu, selector, &dtable);
4052
4053 if (dtable.limit < index * 8 + 7)
4054 return 1;
4055 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
4056 }
4057
4058 static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
4059 struct desc_struct *seg_desc)
4060 {
4061 u32 base_addr = get_desc_base(seg_desc);
4062
4063 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
4064 }
4065
4066 static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4067 {
4068 struct kvm_segment kvm_seg;
4069
4070 kvm_get_segment(vcpu, &kvm_seg, seg);
4071 return kvm_seg.selector;
4072 }
4073
4074 static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4075 u16 selector,
4076 struct kvm_segment *kvm_seg)
4077 {
4078 struct desc_struct seg_desc;
4079
4080 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4081 return 1;
4082 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4083 return 0;
4084 }
4085
4086 static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
4087 {
4088 struct kvm_segment segvar = {
4089 .base = selector << 4,
4090 .limit = 0xffff,
4091 .selector = selector,
4092 .type = 3,
4093 .present = 1,
4094 .dpl = 3,
4095 .db = 0,
4096 .s = 1,
4097 .l = 0,
4098 .g = 0,
4099 .avl = 0,
4100 .unusable = 0,
4101 };
4102 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4103 return 0;
4104 }
4105
4106 static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4107 {
4108 return (seg != VCPU_SREG_LDTR) &&
4109 (seg != VCPU_SREG_TR) &&
4110 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_VM);
4111 }
4112
4113 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4114 int type_bits, int seg)
4115 {
4116 struct kvm_segment kvm_seg;
4117
4118 if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE))
4119 return kvm_load_realmode_segment(vcpu, selector, seg);
4120 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4121 return 1;
4122 kvm_seg.type |= type_bits;
4123
4124 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4125 seg != VCPU_SREG_LDTR)
4126 if (!kvm_seg.s)
4127 kvm_seg.unusable = 1;
4128
4129 kvm_set_segment(vcpu, &kvm_seg, seg);
4130 return 0;
4131 }
4132
4133 static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4134 struct tss_segment_32 *tss)
4135 {
4136 tss->cr3 = vcpu->arch.cr3;
4137 tss->eip = kvm_rip_read(vcpu);
4138 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
4139 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4140 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4141 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4142 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4143 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4144 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4145 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4146 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4147 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4148 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4149 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4150 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4151 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4152 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4153 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4154 }
4155
4156 static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4157 struct tss_segment_32 *tss)
4158 {
4159 kvm_set_cr3(vcpu, tss->cr3);
4160
4161 kvm_rip_write(vcpu, tss->eip);
4162 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4163
4164 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4165 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4166 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4167 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4168 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4169 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4170 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4171 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
4172
4173 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
4174 return 1;
4175
4176 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4177 return 1;
4178
4179 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4180 return 1;
4181
4182 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4183 return 1;
4184
4185 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4186 return 1;
4187
4188 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
4189 return 1;
4190
4191 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
4192 return 1;
4193 return 0;
4194 }
4195
4196 static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4197 struct tss_segment_16 *tss)
4198 {
4199 tss->ip = kvm_rip_read(vcpu);
4200 tss->flag = kvm_x86_ops->get_rflags(vcpu);
4201 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4202 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4203 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4204 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4205 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4206 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4207 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4208 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
4209
4210 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4211 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4212 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4213 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4214 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4215 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4216 }
4217
4218 static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4219 struct tss_segment_16 *tss)
4220 {
4221 kvm_rip_write(vcpu, tss->ip);
4222 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
4223 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4224 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4225 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4226 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4227 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4228 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4229 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4230 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
4231
4232 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
4233 return 1;
4234
4235 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4236 return 1;
4237
4238 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4239 return 1;
4240
4241 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4242 return 1;
4243
4244 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4245 return 1;
4246 return 0;
4247 }
4248
4249 static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
4250 u16 old_tss_sel, u32 old_tss_base,
4251 struct desc_struct *nseg_desc)
4252 {
4253 struct tss_segment_16 tss_segment_16;
4254 int ret = 0;
4255
4256 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4257 sizeof tss_segment_16))
4258 goto out;
4259
4260 save_state_to_tss16(vcpu, &tss_segment_16);
4261
4262 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4263 sizeof tss_segment_16))
4264 goto out;
4265
4266 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4267 &tss_segment_16, sizeof tss_segment_16))
4268 goto out;
4269
4270 if (old_tss_sel != 0xffff) {
4271 tss_segment_16.prev_task_link = old_tss_sel;
4272
4273 if (kvm_write_guest(vcpu->kvm,
4274 get_tss_base_addr(vcpu, nseg_desc),
4275 &tss_segment_16.prev_task_link,
4276 sizeof tss_segment_16.prev_task_link))
4277 goto out;
4278 }
4279
4280 if (load_state_from_tss16(vcpu, &tss_segment_16))
4281 goto out;
4282
4283 ret = 1;
4284 out:
4285 return ret;
4286 }
4287
4288 static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
4289 u16 old_tss_sel, u32 old_tss_base,
4290 struct desc_struct *nseg_desc)
4291 {
4292 struct tss_segment_32 tss_segment_32;
4293 int ret = 0;
4294
4295 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4296 sizeof tss_segment_32))
4297 goto out;
4298
4299 save_state_to_tss32(vcpu, &tss_segment_32);
4300
4301 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4302 sizeof tss_segment_32))
4303 goto out;
4304
4305 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4306 &tss_segment_32, sizeof tss_segment_32))
4307 goto out;
4308
4309 if (old_tss_sel != 0xffff) {
4310 tss_segment_32.prev_task_link = old_tss_sel;
4311
4312 if (kvm_write_guest(vcpu->kvm,
4313 get_tss_base_addr(vcpu, nseg_desc),
4314 &tss_segment_32.prev_task_link,
4315 sizeof tss_segment_32.prev_task_link))
4316 goto out;
4317 }
4318
4319 if (load_state_from_tss32(vcpu, &tss_segment_32))
4320 goto out;
4321
4322 ret = 1;
4323 out:
4324 return ret;
4325 }
4326
4327 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4328 {
4329 struct kvm_segment tr_seg;
4330 struct desc_struct cseg_desc;
4331 struct desc_struct nseg_desc;
4332 int ret = 0;
4333 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4334 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
4335
4336 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
4337
4338 /* FIXME: Handle errors. Failure to read either TSS or their
4339 * descriptors should generate a pagefault.
4340 */
4341 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4342 goto out;
4343
4344 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
4345 goto out;
4346
4347 if (reason != TASK_SWITCH_IRET) {
4348 int cpl;
4349
4350 cpl = kvm_x86_ops->get_cpl(vcpu);
4351 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4352 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4353 return 1;
4354 }
4355 }
4356
4357 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
4358 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4359 return 1;
4360 }
4361
4362 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
4363 cseg_desc.type &= ~(1 << 1); //clear the B flag
4364 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
4365 }
4366
4367 if (reason == TASK_SWITCH_IRET) {
4368 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4369 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4370 }
4371
4372 /* set back link to prev task only if NT bit is set in eflags
4373 note that old_tss_sel is not used afetr this point */
4374 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4375 old_tss_sel = 0xffff;
4376
4377 /* set back link to prev task only if NT bit is set in eflags
4378 note that old_tss_sel is not used afetr this point */
4379 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4380 old_tss_sel = 0xffff;
4381
4382 if (nseg_desc.type & 8)
4383 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4384 old_tss_base, &nseg_desc);
4385 else
4386 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4387 old_tss_base, &nseg_desc);
4388
4389 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4390 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4391 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4392 }
4393
4394 if (reason != TASK_SWITCH_IRET) {
4395 nseg_desc.type |= (1 << 1);
4396 save_guest_segment_descriptor(vcpu, tss_selector,
4397 &nseg_desc);
4398 }
4399
4400 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4401 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4402 tr_seg.type = 11;
4403 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
4404 out:
4405 return ret;
4406 }
4407 EXPORT_SYMBOL_GPL(kvm_task_switch);
4408
4409 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4410 struct kvm_sregs *sregs)
4411 {
4412 int mmu_reset_needed = 0;
4413 int pending_vec, max_bits;
4414 struct descriptor_table dt;
4415
4416 vcpu_load(vcpu);
4417
4418 dt.limit = sregs->idt.limit;
4419 dt.base = sregs->idt.base;
4420 kvm_x86_ops->set_idt(vcpu, &dt);
4421 dt.limit = sregs->gdt.limit;
4422 dt.base = sregs->gdt.base;
4423 kvm_x86_ops->set_gdt(vcpu, &dt);
4424
4425 vcpu->arch.cr2 = sregs->cr2;
4426 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
4427 vcpu->arch.cr3 = sregs->cr3;
4428
4429 kvm_set_cr8(vcpu, sregs->cr8);
4430
4431 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
4432 kvm_x86_ops->set_efer(vcpu, sregs->efer);
4433 kvm_set_apic_base(vcpu, sregs->apic_base);
4434
4435 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4436
4437 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
4438 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
4439 vcpu->arch.cr0 = sregs->cr0;
4440
4441 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
4442 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4443 if (!is_long_mode(vcpu) && is_pae(vcpu))
4444 load_pdptrs(vcpu, vcpu->arch.cr3);
4445
4446 if (mmu_reset_needed)
4447 kvm_mmu_reset_context(vcpu);
4448
4449 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4450 pending_vec = find_first_bit(
4451 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4452 if (pending_vec < max_bits) {
4453 kvm_queue_interrupt(vcpu, pending_vec, false);
4454 pr_debug("Set back pending irq %d\n", pending_vec);
4455 if (irqchip_in_kernel(vcpu->kvm))
4456 kvm_pic_clear_isr_ack(vcpu->kvm);
4457 }
4458
4459 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4460 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4461 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4462 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4463 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4464 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
4465
4466 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4467 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
4468
4469 update_cr8_intercept(vcpu);
4470
4471 /* Older userspace won't unhalt the vcpu on reset. */
4472 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
4473 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4474 !(vcpu->arch.cr0 & X86_CR0_PE))
4475 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4476
4477 vcpu_put(vcpu);
4478
4479 return 0;
4480 }
4481
4482 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4483 struct kvm_guest_debug *dbg)
4484 {
4485 int i, r;
4486
4487 vcpu_load(vcpu);
4488
4489 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4490 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4491 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4492 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4493 vcpu->arch.switch_db_regs =
4494 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4495 } else {
4496 for (i = 0; i < KVM_NR_DB_REGS; i++)
4497 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4498 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4499 }
4500
4501 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4502
4503 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4504 kvm_queue_exception(vcpu, DB_VECTOR);
4505 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4506 kvm_queue_exception(vcpu, BP_VECTOR);
4507
4508 vcpu_put(vcpu);
4509
4510 return r;
4511 }
4512
4513 /*
4514 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4515 * we have asm/x86/processor.h
4516 */
4517 struct fxsave {
4518 u16 cwd;
4519 u16 swd;
4520 u16 twd;
4521 u16 fop;
4522 u64 rip;
4523 u64 rdp;
4524 u32 mxcsr;
4525 u32 mxcsr_mask;
4526 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4527 #ifdef CONFIG_X86_64
4528 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4529 #else
4530 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4531 #endif
4532 };
4533
4534 /*
4535 * Translate a guest virtual address to a guest physical address.
4536 */
4537 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4538 struct kvm_translation *tr)
4539 {
4540 unsigned long vaddr = tr->linear_address;
4541 gpa_t gpa;
4542
4543 vcpu_load(vcpu);
4544 down_read(&vcpu->kvm->slots_lock);
4545 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
4546 up_read(&vcpu->kvm->slots_lock);
4547 tr->physical_address = gpa;
4548 tr->valid = gpa != UNMAPPED_GVA;
4549 tr->writeable = 1;
4550 tr->usermode = 0;
4551 vcpu_put(vcpu);
4552
4553 return 0;
4554 }
4555
4556 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4557 {
4558 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4559
4560 vcpu_load(vcpu);
4561
4562 memcpy(fpu->fpr, fxsave->st_space, 128);
4563 fpu->fcw = fxsave->cwd;
4564 fpu->fsw = fxsave->swd;
4565 fpu->ftwx = fxsave->twd;
4566 fpu->last_opcode = fxsave->fop;
4567 fpu->last_ip = fxsave->rip;
4568 fpu->last_dp = fxsave->rdp;
4569 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4570
4571 vcpu_put(vcpu);
4572
4573 return 0;
4574 }
4575
4576 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4577 {
4578 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4579
4580 vcpu_load(vcpu);
4581
4582 memcpy(fxsave->st_space, fpu->fpr, 128);
4583 fxsave->cwd = fpu->fcw;
4584 fxsave->swd = fpu->fsw;
4585 fxsave->twd = fpu->ftwx;
4586 fxsave->fop = fpu->last_opcode;
4587 fxsave->rip = fpu->last_ip;
4588 fxsave->rdp = fpu->last_dp;
4589 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4590
4591 vcpu_put(vcpu);
4592
4593 return 0;
4594 }
4595
4596 void fx_init(struct kvm_vcpu *vcpu)
4597 {
4598 unsigned after_mxcsr_mask;
4599
4600 /*
4601 * Touch the fpu the first time in non atomic context as if
4602 * this is the first fpu instruction the exception handler
4603 * will fire before the instruction returns and it'll have to
4604 * allocate ram with GFP_KERNEL.
4605 */
4606 if (!used_math())
4607 kvm_fx_save(&vcpu->arch.host_fx_image);
4608
4609 /* Initialize guest FPU by resetting ours and saving into guest's */
4610 preempt_disable();
4611 kvm_fx_save(&vcpu->arch.host_fx_image);
4612 kvm_fx_finit();
4613 kvm_fx_save(&vcpu->arch.guest_fx_image);
4614 kvm_fx_restore(&vcpu->arch.host_fx_image);
4615 preempt_enable();
4616
4617 vcpu->arch.cr0 |= X86_CR0_ET;
4618 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
4619 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4620 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
4621 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4622 }
4623 EXPORT_SYMBOL_GPL(fx_init);
4624
4625 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4626 {
4627 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4628 return;
4629
4630 vcpu->guest_fpu_loaded = 1;
4631 kvm_fx_save(&vcpu->arch.host_fx_image);
4632 kvm_fx_restore(&vcpu->arch.guest_fx_image);
4633 }
4634 EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4635
4636 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4637 {
4638 if (!vcpu->guest_fpu_loaded)
4639 return;
4640
4641 vcpu->guest_fpu_loaded = 0;
4642 kvm_fx_save(&vcpu->arch.guest_fx_image);
4643 kvm_fx_restore(&vcpu->arch.host_fx_image);
4644 ++vcpu->stat.fpu_reload;
4645 }
4646 EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
4647
4648 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4649 {
4650 if (vcpu->arch.time_page) {
4651 kvm_release_page_dirty(vcpu->arch.time_page);
4652 vcpu->arch.time_page = NULL;
4653 }
4654
4655 kvm_x86_ops->vcpu_free(vcpu);
4656 }
4657
4658 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4659 unsigned int id)
4660 {
4661 return kvm_x86_ops->vcpu_create(kvm, id);
4662 }
4663
4664 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4665 {
4666 int r;
4667
4668 /* We do fxsave: this must be aligned. */
4669 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
4670
4671 vcpu->arch.mtrr_state.have_fixed = 1;
4672 vcpu_load(vcpu);
4673 r = kvm_arch_vcpu_reset(vcpu);
4674 if (r == 0)
4675 r = kvm_mmu_setup(vcpu);
4676 vcpu_put(vcpu);
4677 if (r < 0)
4678 goto free_vcpu;
4679
4680 return 0;
4681 free_vcpu:
4682 kvm_x86_ops->vcpu_free(vcpu);
4683 return r;
4684 }
4685
4686 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
4687 {
4688 vcpu_load(vcpu);
4689 kvm_mmu_unload(vcpu);
4690 vcpu_put(vcpu);
4691
4692 kvm_x86_ops->vcpu_free(vcpu);
4693 }
4694
4695 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4696 {
4697 vcpu->arch.nmi_pending = false;
4698 vcpu->arch.nmi_injected = false;
4699
4700 vcpu->arch.switch_db_regs = 0;
4701 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4702 vcpu->arch.dr6 = DR6_FIXED_1;
4703 vcpu->arch.dr7 = DR7_FIXED_1;
4704
4705 return kvm_x86_ops->vcpu_reset(vcpu);
4706 }
4707
4708 void kvm_arch_hardware_enable(void *garbage)
4709 {
4710 kvm_x86_ops->hardware_enable(garbage);
4711 }
4712
4713 void kvm_arch_hardware_disable(void *garbage)
4714 {
4715 kvm_x86_ops->hardware_disable(garbage);
4716 }
4717
4718 int kvm_arch_hardware_setup(void)
4719 {
4720 return kvm_x86_ops->hardware_setup();
4721 }
4722
4723 void kvm_arch_hardware_unsetup(void)
4724 {
4725 kvm_x86_ops->hardware_unsetup();
4726 }
4727
4728 void kvm_arch_check_processor_compat(void *rtn)
4729 {
4730 kvm_x86_ops->check_processor_compatibility(rtn);
4731 }
4732
4733 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4734 {
4735 struct page *page;
4736 struct kvm *kvm;
4737 int r;
4738
4739 BUG_ON(vcpu->kvm == NULL);
4740 kvm = vcpu->kvm;
4741
4742 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4743 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
4744 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4745 else
4746 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
4747
4748 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4749 if (!page) {
4750 r = -ENOMEM;
4751 goto fail;
4752 }
4753 vcpu->arch.pio_data = page_address(page);
4754
4755 r = kvm_mmu_create(vcpu);
4756 if (r < 0)
4757 goto fail_free_pio_data;
4758
4759 if (irqchip_in_kernel(kvm)) {
4760 r = kvm_create_lapic(vcpu);
4761 if (r < 0)
4762 goto fail_mmu_destroy;
4763 }
4764
4765 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4766 GFP_KERNEL);
4767 if (!vcpu->arch.mce_banks) {
4768 r = -ENOMEM;
4769 goto fail_mmu_destroy;
4770 }
4771 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4772
4773 return 0;
4774
4775 fail_mmu_destroy:
4776 kvm_mmu_destroy(vcpu);
4777 fail_free_pio_data:
4778 free_page((unsigned long)vcpu->arch.pio_data);
4779 fail:
4780 return r;
4781 }
4782
4783 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4784 {
4785 kvm_free_lapic(vcpu);
4786 down_read(&vcpu->kvm->slots_lock);
4787 kvm_mmu_destroy(vcpu);
4788 up_read(&vcpu->kvm->slots_lock);
4789 free_page((unsigned long)vcpu->arch.pio_data);
4790 }
4791
4792 struct kvm *kvm_arch_create_vm(void)
4793 {
4794 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4795
4796 if (!kvm)
4797 return ERR_PTR(-ENOMEM);
4798
4799 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4800 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
4801
4802 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4803 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4804
4805 rdtscll(kvm->arch.vm_init_tsc);
4806
4807 return kvm;
4808 }
4809
4810 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4811 {
4812 vcpu_load(vcpu);
4813 kvm_mmu_unload(vcpu);
4814 vcpu_put(vcpu);
4815 }
4816
4817 static void kvm_free_vcpus(struct kvm *kvm)
4818 {
4819 unsigned int i;
4820 struct kvm_vcpu *vcpu;
4821
4822 /*
4823 * Unpin any mmu pages first.
4824 */
4825 kvm_for_each_vcpu(i, vcpu, kvm)
4826 kvm_unload_vcpu_mmu(vcpu);
4827 kvm_for_each_vcpu(i, vcpu, kvm)
4828 kvm_arch_vcpu_free(vcpu);
4829
4830 mutex_lock(&kvm->lock);
4831 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4832 kvm->vcpus[i] = NULL;
4833
4834 atomic_set(&kvm->online_vcpus, 0);
4835 mutex_unlock(&kvm->lock);
4836 }
4837
4838 void kvm_arch_sync_events(struct kvm *kvm)
4839 {
4840 kvm_free_all_assigned_devices(kvm);
4841 }
4842
4843 void kvm_arch_destroy_vm(struct kvm *kvm)
4844 {
4845 kvm_iommu_unmap_guest(kvm);
4846 kvm_free_pit(kvm);
4847 kfree(kvm->arch.vpic);
4848 kfree(kvm->arch.vioapic);
4849 kvm_free_vcpus(kvm);
4850 kvm_free_physmem(kvm);
4851 if (kvm->arch.apic_access_page)
4852 put_page(kvm->arch.apic_access_page);
4853 if (kvm->arch.ept_identity_pagetable)
4854 put_page(kvm->arch.ept_identity_pagetable);
4855 kfree(kvm);
4856 }
4857
4858 int kvm_arch_set_memory_region(struct kvm *kvm,
4859 struct kvm_userspace_memory_region *mem,
4860 struct kvm_memory_slot old,
4861 int user_alloc)
4862 {
4863 int npages = mem->memory_size >> PAGE_SHIFT;
4864 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4865
4866 /*To keep backward compatibility with older userspace,
4867 *x86 needs to hanlde !user_alloc case.
4868 */
4869 if (!user_alloc) {
4870 if (npages && !old.rmap) {
4871 unsigned long userspace_addr;
4872
4873 down_write(&current->mm->mmap_sem);
4874 userspace_addr = do_mmap(NULL, 0,
4875 npages * PAGE_SIZE,
4876 PROT_READ | PROT_WRITE,
4877 MAP_PRIVATE | MAP_ANONYMOUS,
4878 0);
4879 up_write(&current->mm->mmap_sem);
4880
4881 if (IS_ERR((void *)userspace_addr))
4882 return PTR_ERR((void *)userspace_addr);
4883
4884 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4885 spin_lock(&kvm->mmu_lock);
4886 memslot->userspace_addr = userspace_addr;
4887 spin_unlock(&kvm->mmu_lock);
4888 } else {
4889 if (!old.user_alloc && old.rmap) {
4890 int ret;
4891
4892 down_write(&current->mm->mmap_sem);
4893 ret = do_munmap(current->mm, old.userspace_addr,
4894 old.npages * PAGE_SIZE);
4895 up_write(&current->mm->mmap_sem);
4896 if (ret < 0)
4897 printk(KERN_WARNING
4898 "kvm_vm_ioctl_set_memory_region: "
4899 "failed to munmap memory\n");
4900 }
4901 }
4902 }
4903
4904 spin_lock(&kvm->mmu_lock);
4905 if (!kvm->arch.n_requested_mmu_pages) {
4906 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4907 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4908 }
4909
4910 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4911 spin_unlock(&kvm->mmu_lock);
4912
4913 return 0;
4914 }
4915
4916 void kvm_arch_flush_shadow(struct kvm *kvm)
4917 {
4918 kvm_mmu_zap_all(kvm);
4919 kvm_reload_remote_mmus(kvm);
4920 }
4921
4922 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4923 {
4924 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4925 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4926 || vcpu->arch.nmi_pending ||
4927 (kvm_arch_interrupt_allowed(vcpu) &&
4928 kvm_cpu_has_interrupt(vcpu));
4929 }
4930
4931 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4932 {
4933 int me;
4934 int cpu = vcpu->cpu;
4935
4936 if (waitqueue_active(&vcpu->wq)) {
4937 wake_up_interruptible(&vcpu->wq);
4938 ++vcpu->stat.halt_wakeup;
4939 }
4940
4941 me = get_cpu();
4942 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4943 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4944 smp_send_reschedule(cpu);
4945 put_cpu();
4946 }
4947
4948 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4949 {
4950 return kvm_x86_ops->interrupt_allowed(vcpu);
4951 }
4952
4953 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4954 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4955 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4956 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4957 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree