x86: replace is_buffer_dma_capable() with dma_capable
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kernel / pci-gart_64.c
blob98a827ee9ed7fc48d27b84dd16e43740cd77757f
1 /*
2 * Dynamic DMA mapping support for AMD Hammer.
4 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
5 * This allows to use PCI devices that only support 32bit addresses on systems
6 * with more than 4GB.
8 * See Documentation/PCI/PCI-DMA-mapping.txt for the interface specification.
10 * Copyright 2002 Andi Kleen, SuSE Labs.
11 * Subject to the GNU General Public License v2 only.
14 #include <linux/types.h>
15 #include <linux/ctype.h>
16 #include <linux/agp_backend.h>
17 #include <linux/init.h>
18 #include <linux/mm.h>
19 #include <linux/string.h>
20 #include <linux/spinlock.h>
21 #include <linux/pci.h>
22 #include <linux/module.h>
23 #include <linux/topology.h>
24 #include <linux/interrupt.h>
25 #include <linux/bitops.h>
26 #include <linux/kdebug.h>
27 #include <linux/scatterlist.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/sysdev.h>
30 #include <linux/io.h>
31 #include <asm/atomic.h>
32 #include <asm/mtrr.h>
33 #include <asm/pgtable.h>
34 #include <asm/proto.h>
35 #include <asm/iommu.h>
36 #include <asm/gart.h>
37 #include <asm/cacheflush.h>
38 #include <asm/swiotlb.h>
39 #include <asm/dma.h>
40 #include <asm/k8.h>
42 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
43 static unsigned long iommu_size; /* size of remapping area bytes */
44 static unsigned long iommu_pages; /* .. and in pages */
46 static u32 *iommu_gatt_base; /* Remapping table */
49 * If this is disabled the IOMMU will use an optimized flushing strategy
50 * of only flushing when an mapping is reused. With it true the GART is
51 * flushed for every mapping. Problem is that doing the lazy flush seems
52 * to trigger bugs with some popular PCI cards, in particular 3ware (but
53 * has been also also seen with Qlogic at least).
55 static int iommu_fullflush = 1;
57 /* Allocation bitmap for the remapping area: */
58 static DEFINE_SPINLOCK(iommu_bitmap_lock);
59 /* Guarded by iommu_bitmap_lock: */
60 static unsigned long *iommu_gart_bitmap;
62 static u32 gart_unmapped_entry;
64 #define GPTE_VALID 1
65 #define GPTE_COHERENT 2
66 #define GPTE_ENCODE(x) \
67 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
68 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
70 #define EMERGENCY_PAGES 32 /* = 128KB */
72 #ifdef CONFIG_AGP
73 #define AGPEXTERN extern
74 #else
75 #define AGPEXTERN
76 #endif
78 /* backdoor interface to AGP driver */
79 AGPEXTERN int agp_memory_reserved;
80 AGPEXTERN __u32 *agp_gatt_table;
82 static unsigned long next_bit; /* protected by iommu_bitmap_lock */
83 static bool need_flush; /* global flush state. set for each gart wrap */
85 static unsigned long alloc_iommu(struct device *dev, int size,
86 unsigned long align_mask)
88 unsigned long offset, flags;
89 unsigned long boundary_size;
90 unsigned long base_index;
92 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
93 PAGE_SIZE) >> PAGE_SHIFT;
94 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
95 PAGE_SIZE) >> PAGE_SHIFT;
97 spin_lock_irqsave(&iommu_bitmap_lock, flags);
98 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
99 size, base_index, boundary_size, align_mask);
100 if (offset == -1) {
101 need_flush = true;
102 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
103 size, base_index, boundary_size,
104 align_mask);
106 if (offset != -1) {
107 next_bit = offset+size;
108 if (next_bit >= iommu_pages) {
109 next_bit = 0;
110 need_flush = true;
113 if (iommu_fullflush)
114 need_flush = true;
115 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
117 return offset;
120 static void free_iommu(unsigned long offset, int size)
122 unsigned long flags;
124 spin_lock_irqsave(&iommu_bitmap_lock, flags);
125 iommu_area_free(iommu_gart_bitmap, offset, size);
126 if (offset >= next_bit)
127 next_bit = offset + size;
128 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
132 * Use global flush state to avoid races with multiple flushers.
134 static void flush_gart(void)
136 unsigned long flags;
138 spin_lock_irqsave(&iommu_bitmap_lock, flags);
139 if (need_flush) {
140 k8_flush_garts();
141 need_flush = false;
143 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
146 #ifdef CONFIG_IOMMU_LEAK
147 /* Debugging aid for drivers that don't free their IOMMU tables */
148 static int leak_trace;
149 static int iommu_leak_pages = 20;
151 static void dump_leak(void)
153 static int dump;
155 if (dump)
156 return;
157 dump = 1;
159 show_stack(NULL, NULL);
160 debug_dma_dump_mappings(NULL);
162 #endif
164 static void iommu_full(struct device *dev, size_t size, int dir)
167 * Ran out of IOMMU space for this operation. This is very bad.
168 * Unfortunately the drivers cannot handle this operation properly.
169 * Return some non mapped prereserved space in the aperture and
170 * let the Northbridge deal with it. This will result in garbage
171 * in the IO operation. When the size exceeds the prereserved space
172 * memory corruption will occur or random memory will be DMAed
173 * out. Hopefully no network devices use single mappings that big.
176 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
178 if (size > PAGE_SIZE*EMERGENCY_PAGES) {
179 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
180 panic("PCI-DMA: Memory would be corrupted\n");
181 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
182 panic(KERN_ERR
183 "PCI-DMA: Random memory would be DMAed\n");
185 #ifdef CONFIG_IOMMU_LEAK
186 dump_leak();
187 #endif
190 static inline int
191 need_iommu(struct device *dev, unsigned long addr, size_t size)
193 return force_iommu || !dma_capable(dev, addr, size);
196 static inline int
197 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
199 return !dma_capable(dev, addr, size);
202 /* Map a single continuous physical area into the IOMMU.
203 * Caller needs to check if the iommu is needed and flush.
205 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
206 size_t size, int dir, unsigned long align_mask)
208 unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE);
209 unsigned long iommu_page = alloc_iommu(dev, npages, align_mask);
210 int i;
212 if (iommu_page == -1) {
213 if (!nonforced_iommu(dev, phys_mem, size))
214 return phys_mem;
215 if (panic_on_overflow)
216 panic("dma_map_area overflow %lu bytes\n", size);
217 iommu_full(dev, size, dir);
218 return bad_dma_address;
221 for (i = 0; i < npages; i++) {
222 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
223 phys_mem += PAGE_SIZE;
225 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
228 /* Map a single area into the IOMMU */
229 static dma_addr_t gart_map_page(struct device *dev, struct page *page,
230 unsigned long offset, size_t size,
231 enum dma_data_direction dir,
232 struct dma_attrs *attrs)
234 unsigned long bus;
235 phys_addr_t paddr = page_to_phys(page) + offset;
237 if (!dev)
238 dev = &x86_dma_fallback_dev;
240 if (!need_iommu(dev, paddr, size))
241 return paddr;
243 bus = dma_map_area(dev, paddr, size, dir, 0);
244 flush_gart();
246 return bus;
250 * Free a DMA mapping.
252 static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr,
253 size_t size, enum dma_data_direction dir,
254 struct dma_attrs *attrs)
256 unsigned long iommu_page;
257 int npages;
258 int i;
260 if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
261 dma_addr >= iommu_bus_base + iommu_size)
262 return;
264 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
265 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
266 for (i = 0; i < npages; i++) {
267 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
269 free_iommu(iommu_page, npages);
273 * Wrapper for pci_unmap_single working with scatterlists.
275 static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
276 enum dma_data_direction dir, struct dma_attrs *attrs)
278 struct scatterlist *s;
279 int i;
281 for_each_sg(sg, s, nents, i) {
282 if (!s->dma_length || !s->length)
283 break;
284 gart_unmap_page(dev, s->dma_address, s->dma_length, dir, NULL);
288 /* Fallback for dma_map_sg in case of overflow */
289 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
290 int nents, int dir)
292 struct scatterlist *s;
293 int i;
295 #ifdef CONFIG_IOMMU_DEBUG
296 printk(KERN_DEBUG "dma_map_sg overflow\n");
297 #endif
299 for_each_sg(sg, s, nents, i) {
300 unsigned long addr = sg_phys(s);
302 if (nonforced_iommu(dev, addr, s->length)) {
303 addr = dma_map_area(dev, addr, s->length, dir, 0);
304 if (addr == bad_dma_address) {
305 if (i > 0)
306 gart_unmap_sg(dev, sg, i, dir, NULL);
307 nents = 0;
308 sg[0].dma_length = 0;
309 break;
312 s->dma_address = addr;
313 s->dma_length = s->length;
315 flush_gart();
317 return nents;
320 /* Map multiple scatterlist entries continuous into the first. */
321 static int __dma_map_cont(struct device *dev, struct scatterlist *start,
322 int nelems, struct scatterlist *sout,
323 unsigned long pages)
325 unsigned long iommu_start = alloc_iommu(dev, pages, 0);
326 unsigned long iommu_page = iommu_start;
327 struct scatterlist *s;
328 int i;
330 if (iommu_start == -1)
331 return -1;
333 for_each_sg(start, s, nelems, i) {
334 unsigned long pages, addr;
335 unsigned long phys_addr = s->dma_address;
337 BUG_ON(s != start && s->offset);
338 if (s == start) {
339 sout->dma_address = iommu_bus_base;
340 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
341 sout->dma_length = s->length;
342 } else {
343 sout->dma_length += s->length;
346 addr = phys_addr;
347 pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE);
348 while (pages--) {
349 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
350 addr += PAGE_SIZE;
351 iommu_page++;
354 BUG_ON(iommu_page - iommu_start != pages);
356 return 0;
359 static inline int
360 dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
361 struct scatterlist *sout, unsigned long pages, int need)
363 if (!need) {
364 BUG_ON(nelems != 1);
365 sout->dma_address = start->dma_address;
366 sout->dma_length = start->length;
367 return 0;
369 return __dma_map_cont(dev, start, nelems, sout, pages);
373 * DMA map all entries in a scatterlist.
374 * Merge chunks that have page aligned sizes into a continuous mapping.
376 static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
377 enum dma_data_direction dir, struct dma_attrs *attrs)
379 struct scatterlist *s, *ps, *start_sg, *sgmap;
380 int need = 0, nextneed, i, out, start;
381 unsigned long pages = 0;
382 unsigned int seg_size;
383 unsigned int max_seg_size;
385 if (nents == 0)
386 return 0;
388 if (!dev)
389 dev = &x86_dma_fallback_dev;
391 out = 0;
392 start = 0;
393 start_sg = sgmap = sg;
394 seg_size = 0;
395 max_seg_size = dma_get_max_seg_size(dev);
396 ps = NULL; /* shut up gcc */
397 for_each_sg(sg, s, nents, i) {
398 dma_addr_t addr = sg_phys(s);
400 s->dma_address = addr;
401 BUG_ON(s->length == 0);
403 nextneed = need_iommu(dev, addr, s->length);
405 /* Handle the previous not yet processed entries */
406 if (i > start) {
408 * Can only merge when the last chunk ends on a
409 * page boundary and the new one doesn't have an
410 * offset.
412 if (!iommu_merge || !nextneed || !need || s->offset ||
413 (s->length + seg_size > max_seg_size) ||
414 (ps->offset + ps->length) % PAGE_SIZE) {
415 if (dma_map_cont(dev, start_sg, i - start,
416 sgmap, pages, need) < 0)
417 goto error;
418 out++;
419 seg_size = 0;
420 sgmap = sg_next(sgmap);
421 pages = 0;
422 start = i;
423 start_sg = s;
427 seg_size += s->length;
428 need = nextneed;
429 pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE);
430 ps = s;
432 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
433 goto error;
434 out++;
435 flush_gart();
436 if (out < nents) {
437 sgmap = sg_next(sgmap);
438 sgmap->dma_length = 0;
440 return out;
442 error:
443 flush_gart();
444 gart_unmap_sg(dev, sg, out, dir, NULL);
446 /* When it was forced or merged try again in a dumb way */
447 if (force_iommu || iommu_merge) {
448 out = dma_map_sg_nonforce(dev, sg, nents, dir);
449 if (out > 0)
450 return out;
452 if (panic_on_overflow)
453 panic("dma_map_sg: overflow on %lu pages\n", pages);
455 iommu_full(dev, pages << PAGE_SHIFT, dir);
456 for_each_sg(sg, s, nents, i)
457 s->dma_address = bad_dma_address;
458 return 0;
461 /* allocate and map a coherent mapping */
462 static void *
463 gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
464 gfp_t flag)
466 dma_addr_t paddr;
467 unsigned long align_mask;
468 struct page *page;
470 if (force_iommu && !(flag & GFP_DMA)) {
471 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
472 page = alloc_pages(flag | __GFP_ZERO, get_order(size));
473 if (!page)
474 return NULL;
476 align_mask = (1UL << get_order(size)) - 1;
477 paddr = dma_map_area(dev, page_to_phys(page), size,
478 DMA_BIDIRECTIONAL, align_mask);
480 flush_gart();
481 if (paddr != bad_dma_address) {
482 *dma_addr = paddr;
483 return page_address(page);
485 __free_pages(page, get_order(size));
486 } else
487 return dma_generic_alloc_coherent(dev, size, dma_addr, flag);
489 return NULL;
492 /* free a coherent mapping */
493 static void
494 gart_free_coherent(struct device *dev, size_t size, void *vaddr,
495 dma_addr_t dma_addr)
497 gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, NULL);
498 free_pages((unsigned long)vaddr, get_order(size));
501 static int no_agp;
503 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
505 unsigned long a;
507 if (!iommu_size) {
508 iommu_size = aper_size;
509 if (!no_agp)
510 iommu_size /= 2;
513 a = aper + iommu_size;
514 iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
516 if (iommu_size < 64*1024*1024) {
517 printk(KERN_WARNING
518 "PCI-DMA: Warning: Small IOMMU %luMB."
519 " Consider increasing the AGP aperture in BIOS\n",
520 iommu_size >> 20);
523 return iommu_size;
526 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
528 unsigned aper_size = 0, aper_base_32, aper_order;
529 u64 aper_base;
531 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
532 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
533 aper_order = (aper_order >> 1) & 7;
535 aper_base = aper_base_32 & 0x7fff;
536 aper_base <<= 25;
538 aper_size = (32 * 1024 * 1024) << aper_order;
539 if (aper_base + aper_size > 0x100000000UL || !aper_size)
540 aper_base = 0;
542 *size = aper_size;
543 return aper_base;
546 static void enable_gart_translations(void)
548 int i;
550 for (i = 0; i < num_k8_northbridges; i++) {
551 struct pci_dev *dev = k8_northbridges[i];
553 enable_gart_translation(dev, __pa(agp_gatt_table));
558 * If fix_up_north_bridges is set, the north bridges have to be fixed up on
559 * resume in the same way as they are handled in gart_iommu_hole_init().
561 static bool fix_up_north_bridges;
562 static u32 aperture_order;
563 static u32 aperture_alloc;
565 void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
567 fix_up_north_bridges = true;
568 aperture_order = aper_order;
569 aperture_alloc = aper_alloc;
572 static int gart_resume(struct sys_device *dev)
574 printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
576 if (fix_up_north_bridges) {
577 int i;
579 printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
581 for (i = 0; i < num_k8_northbridges; i++) {
582 struct pci_dev *dev = k8_northbridges[i];
585 * Don't enable translations just yet. That is the next
586 * step. Restore the pre-suspend aperture settings.
588 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
589 aperture_order << 1);
590 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
591 aperture_alloc >> 25);
595 enable_gart_translations();
597 return 0;
600 static int gart_suspend(struct sys_device *dev, pm_message_t state)
602 return 0;
605 static struct sysdev_class gart_sysdev_class = {
606 .name = "gart",
607 .suspend = gart_suspend,
608 .resume = gart_resume,
612 static struct sys_device device_gart = {
613 .id = 0,
614 .cls = &gart_sysdev_class,
618 * Private Northbridge GATT initialization in case we cannot use the
619 * AGP driver for some reason.
621 static __init int init_k8_gatt(struct agp_kern_info *info)
623 unsigned aper_size, gatt_size, new_aper_size;
624 unsigned aper_base, new_aper_base;
625 struct pci_dev *dev;
626 void *gatt;
627 int i, error;
629 printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
630 aper_size = aper_base = info->aper_size = 0;
631 dev = NULL;
632 for (i = 0; i < num_k8_northbridges; i++) {
633 dev = k8_northbridges[i];
634 new_aper_base = read_aperture(dev, &new_aper_size);
635 if (!new_aper_base)
636 goto nommu;
638 if (!aper_base) {
639 aper_size = new_aper_size;
640 aper_base = new_aper_base;
642 if (aper_size != new_aper_size || aper_base != new_aper_base)
643 goto nommu;
645 if (!aper_base)
646 goto nommu;
647 info->aper_base = aper_base;
648 info->aper_size = aper_size >> 20;
650 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
651 gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
652 get_order(gatt_size));
653 if (!gatt)
654 panic("Cannot allocate GATT table");
655 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
656 panic("Could not set GART PTEs to uncacheable pages");
658 agp_gatt_table = gatt;
660 error = sysdev_class_register(&gart_sysdev_class);
661 if (!error)
662 error = sysdev_register(&device_gart);
663 if (error)
664 panic("Could not register gart_sysdev -- "
665 "would corrupt data on next suspend");
667 flush_gart();
669 printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
670 aper_base, aper_size>>10);
672 return 0;
674 nommu:
675 /* Should not happen anymore */
676 printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
677 "falling back to iommu=soft.\n");
678 return -1;
681 static struct dma_map_ops gart_dma_ops = {
682 .map_sg = gart_map_sg,
683 .unmap_sg = gart_unmap_sg,
684 .map_page = gart_map_page,
685 .unmap_page = gart_unmap_page,
686 .alloc_coherent = gart_alloc_coherent,
687 .free_coherent = gart_free_coherent,
690 void gart_iommu_shutdown(void)
692 struct pci_dev *dev;
693 int i;
695 if (no_agp && (dma_ops != &gart_dma_ops))
696 return;
698 for (i = 0; i < num_k8_northbridges; i++) {
699 u32 ctl;
701 dev = k8_northbridges[i];
702 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
704 ctl &= ~GARTEN;
706 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
710 void __init gart_iommu_init(void)
712 struct agp_kern_info info;
713 unsigned long iommu_start;
714 unsigned long aper_base, aper_size;
715 unsigned long start_pfn, end_pfn;
716 unsigned long scratch;
717 long i;
719 if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0)
720 return;
722 #ifndef CONFIG_AGP_AMD64
723 no_agp = 1;
724 #else
725 /* Makefile puts PCI initialization via subsys_initcall first. */
726 /* Add other K8 AGP bridge drivers here */
727 no_agp = no_agp ||
728 (agp_amd64_init() < 0) ||
729 (agp_copy_info(agp_bridge, &info) < 0);
730 #endif
732 if (swiotlb)
733 return;
735 /* Did we detect a different HW IOMMU? */
736 if (iommu_detected && !gart_iommu_aperture)
737 return;
739 if (no_iommu ||
740 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
741 !gart_iommu_aperture ||
742 (no_agp && init_k8_gatt(&info) < 0)) {
743 if (max_pfn > MAX_DMA32_PFN) {
744 printk(KERN_WARNING "More than 4GB of memory "
745 "but GART IOMMU not available.\n");
746 printk(KERN_WARNING "falling back to iommu=soft.\n");
748 return;
751 /* need to map that range */
752 aper_size = info.aper_size << 20;
753 aper_base = info.aper_base;
754 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
755 if (end_pfn > max_low_pfn_mapped) {
756 start_pfn = (aper_base>>PAGE_SHIFT);
757 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
760 printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
761 iommu_size = check_iommu_size(info.aper_base, aper_size);
762 iommu_pages = iommu_size >> PAGE_SHIFT;
764 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
765 get_order(iommu_pages/8));
766 if (!iommu_gart_bitmap)
767 panic("Cannot allocate iommu bitmap\n");
769 #ifdef CONFIG_IOMMU_LEAK
770 if (leak_trace) {
771 int ret;
773 ret = dma_debug_resize_entries(iommu_pages);
774 if (ret)
775 printk(KERN_DEBUG
776 "PCI-DMA: Cannot trace all the entries\n");
778 #endif
781 * Out of IOMMU space handling.
782 * Reserve some invalid pages at the beginning of the GART.
784 iommu_area_reserve(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
786 agp_memory_reserved = iommu_size;
787 printk(KERN_INFO
788 "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
789 iommu_size >> 20);
791 iommu_start = aper_size - iommu_size;
792 iommu_bus_base = info.aper_base + iommu_start;
793 bad_dma_address = iommu_bus_base;
794 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
797 * Unmap the IOMMU part of the GART. The alias of the page is
798 * always mapped with cache enabled and there is no full cache
799 * coherency across the GART remapping. The unmapping avoids
800 * automatic prefetches from the CPU allocating cache lines in
801 * there. All CPU accesses are done via the direct mapping to
802 * the backing memory. The GART address is only used by PCI
803 * devices.
805 set_memory_np((unsigned long)__va(iommu_bus_base),
806 iommu_size >> PAGE_SHIFT);
808 * Tricky. The GART table remaps the physical memory range,
809 * so the CPU wont notice potential aliases and if the memory
810 * is remapped to UC later on, we might surprise the PCI devices
811 * with a stray writeout of a cacheline. So play it sure and
812 * do an explicit, full-scale wbinvd() _after_ having marked all
813 * the pages as Not-Present:
815 wbinvd();
818 * Now all caches are flushed and we can safely enable
819 * GART hardware. Doing it early leaves the possibility
820 * of stale cache entries that can lead to GART PTE
821 * errors.
823 enable_gart_translations();
826 * Try to workaround a bug (thanks to BenH):
827 * Set unmapped entries to a scratch page instead of 0.
828 * Any prefetches that hit unmapped entries won't get an bus abort
829 * then. (P2P bridge may be prefetching on DMA reads).
831 scratch = get_zeroed_page(GFP_KERNEL);
832 if (!scratch)
833 panic("Cannot allocate iommu scratch page");
834 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
835 for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
836 iommu_gatt_base[i] = gart_unmapped_entry;
838 flush_gart();
839 dma_ops = &gart_dma_ops;
842 void __init gart_parse_options(char *p)
844 int arg;
846 #ifdef CONFIG_IOMMU_LEAK
847 if (!strncmp(p, "leak", 4)) {
848 leak_trace = 1;
849 p += 4;
850 if (*p == '=')
851 ++p;
852 if (isdigit(*p) && get_option(&p, &arg))
853 iommu_leak_pages = arg;
855 #endif
856 if (isdigit(*p) && get_option(&p, &arg))
857 iommu_size = arg;
858 if (!strncmp(p, "fullflush", 8))
859 iommu_fullflush = 1;
860 if (!strncmp(p, "nofullflush", 11))
861 iommu_fullflush = 0;
862 if (!strncmp(p, "noagp", 5))
863 no_agp = 1;
864 if (!strncmp(p, "noaperture", 10))
865 fix_aperture = 0;
866 /* duplicated from pci-dma.c */
867 if (!strncmp(p, "force", 5))
868 gart_iommu_aperture_allowed = 1;
869 if (!strncmp(p, "allowed", 7))
870 gart_iommu_aperture_allowed = 1;
871 if (!strncmp(p, "memaper", 7)) {
872 fallback_aper_force = 1;
873 p += 7;
874 if (*p == '=') {
875 ++p;
876 if (get_option(&p, &arg))
877 fallback_aper_order = arg;