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ahci: AHCI mode SATA patch for Intel DH89xxCC DeviceIDs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / ahci.c
blob3a43b116783e54828bf32ca090c813422a2cdddc
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 };
57
58 enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
63 board_ahci_yes_fbs,
64
65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
67 board_ahci_mcp77,
68 board_ahci_mcp89,
69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
79 };
80
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 #ifdef CONFIG_PM
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
91 #endif
92
93 static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95 };
96
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
100 };
101
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
105 };
106
107 static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
111 };
112
113 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114
115 static const struct ata_port_info ahci_port_info[] = {
116 /* by features */
117 [board_ahci] =
118 {
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_ign_iferr] =
125 {
126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_nosntf] =
133 {
134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 [board_ahci_yes_fbs] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
148 /* by chipsets */
149 [board_ahci_mcp65] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
152 AHCI_HFLAG_YES_NCQ),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp77] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_mcp89] =
167 {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_mv] =
175 {
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
183 },
184 [board_ahci_sb600] =
185 {
186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
187 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
188 AHCI_HFLAG_32BIT_ONLY),
189 .flags = AHCI_FLAG_COMMON,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_sb600_ops,
193 },
194 [board_ahci_sb700] = /* for SB700 and SB800 */
195 {
196 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_sb600_ops,
201 },
202 [board_ahci_vt8251] =
203 {
204 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
205 .flags = AHCI_FLAG_COMMON,
206 .pio_mask = ATA_PIO4,
207 .udma_mask = ATA_UDMA6,
208 .port_ops = &ahci_vt8251_ops,
209 },
210 };
211
212 static const struct pci_device_id ahci_pci_tbl[] = {
213 /* Intel */
214 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
215 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
216 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
217 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
218 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
219 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
220 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
223 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
224 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
225 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
227 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
228 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
229 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
234 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
239 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
240 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
241 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
242 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
243 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
244 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
245 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
246 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
248 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
250 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
251 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
252 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
253 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
256 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
259 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
260 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
261 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
262 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
263 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
264
265 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
266 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
267 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
268
269 /* ATI */
270 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
271 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
276 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
277
278 /* AMD */
279 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
280 /* AMD is using RAID class only for ahci controllers */
281 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
282 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
283
284 /* VIA */
285 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
286 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
287
288 /* NVIDIA */
289 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
373
374 /* SiS */
375 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
376 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
377 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
378
379 /* Marvell */
380 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
381 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
382 { PCI_DEVICE(0x1b4b, 0x9123),
383 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
384
385 /* Promise */
386 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
387
388 /* Generic, PCI class code for AHCI */
389 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
390 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
391
392 { } /* terminate list */
393 };
394
395
396 static struct pci_driver ahci_pci_driver = {
397 .name = DRV_NAME,
398 .id_table = ahci_pci_tbl,
399 .probe = ahci_init_one,
400 .remove = ata_pci_remove_one,
401 #ifdef CONFIG_PM
402 .suspend = ahci_pci_device_suspend,
403 .resume = ahci_pci_device_resume,
404 #endif
405 };
406
407 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
408 static int marvell_enable;
409 #else
410 static int marvell_enable = 1;
411 #endif
412 module_param(marvell_enable, int, 0644);
413 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
414
415
416 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
417 struct ahci_host_priv *hpriv)
418 {
419 unsigned int force_port_map = 0;
420 unsigned int mask_port_map = 0;
421
422 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
423 dev_info(&pdev->dev, "JMB361 has only one port\n");
424 force_port_map = 1;
425 }
426
427 /*
428 * Temporary Marvell 6145 hack: PATA port presence
429 * is asserted through the standard AHCI port
430 * presence register, as bit 4 (counting from 0)
431 */
432 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
433 if (pdev->device == 0x6121)
434 mask_port_map = 0x3;
435 else
436 mask_port_map = 0xf;
437 dev_info(&pdev->dev,
438 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
439 }
440
441 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
442 mask_port_map);
443 }
444
445 static int ahci_pci_reset_controller(struct ata_host *host)
446 {
447 struct pci_dev *pdev = to_pci_dev(host->dev);
448
449 ahci_reset_controller(host);
450
451 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
452 struct ahci_host_priv *hpriv = host->private_data;
453 u16 tmp16;
454
455 /* configure PCS */
456 pci_read_config_word(pdev, 0x92, &tmp16);
457 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
458 tmp16 |= hpriv->port_map;
459 pci_write_config_word(pdev, 0x92, tmp16);
460 }
461 }
462
463 return 0;
464 }
465
466 static void ahci_pci_init_controller(struct ata_host *host)
467 {
468 struct ahci_host_priv *hpriv = host->private_data;
469 struct pci_dev *pdev = to_pci_dev(host->dev);
470 void __iomem *port_mmio;
471 u32 tmp;
472 int mv;
473
474 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
475 if (pdev->device == 0x6121)
476 mv = 2;
477 else
478 mv = 4;
479 port_mmio = __ahci_port_base(host, mv);
480
481 writel(0, port_mmio + PORT_IRQ_MASK);
482
483 /* clear port IRQ */
484 tmp = readl(port_mmio + PORT_IRQ_STAT);
485 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
486 if (tmp)
487 writel(tmp, port_mmio + PORT_IRQ_STAT);
488 }
489
490 ahci_init_controller(host);
491 }
492
493 static int ahci_sb600_check_ready(struct ata_link *link)
494 {
495 void __iomem *port_mmio = ahci_port_base(link->ap);
496 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
497 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
498
499 /*
500 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
501 * which can save timeout delay.
502 */
503 if (irq_status & PORT_IRQ_BAD_PMP)
504 return -EIO;
505
506 return ata_check_ready(status);
507 }
508
509 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
510 unsigned long deadline)
511 {
512 struct ata_port *ap = link->ap;
513 void __iomem *port_mmio = ahci_port_base(ap);
514 int pmp = sata_srst_pmp(link);
515 int rc;
516 u32 irq_sts;
517
518 DPRINTK("ENTER\n");
519
520 rc = ahci_do_softreset(link, class, pmp, deadline,
521 ahci_sb600_check_ready);
522
523 /*
524 * Soft reset fails on some ATI chips with IPMS set when PMP
525 * is enabled but SATA HDD/ODD is connected to SATA port,
526 * do soft reset again to port 0.
527 */
528 if (rc == -EIO) {
529 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
530 if (irq_sts & PORT_IRQ_BAD_PMP) {
531 ata_link_printk(link, KERN_WARNING,
532 "applying SB600 PMP SRST workaround "
533 "and retrying\n");
534 rc = ahci_do_softreset(link, class, 0, deadline,
535 ahci_check_ready);
536 }
537 }
538
539 return rc;
540 }
541
542 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
543 unsigned long deadline)
544 {
545 struct ata_port *ap = link->ap;
546 bool online;
547 int rc;
548
549 DPRINTK("ENTER\n");
550
551 ahci_stop_engine(ap);
552
553 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
554 deadline, &online, NULL);
555
556 ahci_start_engine(ap);
557
558 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
559
560 /* vt8251 doesn't clear BSY on signature FIS reception,
561 * request follow-up softreset.
562 */
563 return online ? -EAGAIN : rc;
564 }
565
566 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
567 unsigned long deadline)
568 {
569 struct ata_port *ap = link->ap;
570 struct ahci_port_priv *pp = ap->private_data;
571 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
572 struct ata_taskfile tf;
573 bool online;
574 int rc;
575
576 ahci_stop_engine(ap);
577
578 /* clear D2H reception area to properly wait for D2H FIS */
579 ata_tf_init(link->device, &tf);
580 tf.command = 0x80;
581 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
582
583 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
584 deadline, &online, NULL);
585
586 ahci_start_engine(ap);
587
588 /* The pseudo configuration device on SIMG4726 attached to
589 * ASUS P5W-DH Deluxe doesn't send signature FIS after
590 * hardreset if no device is attached to the first downstream
591 * port && the pseudo device locks up on SRST w/ PMP==0. To
592 * work around this, wait for !BSY only briefly. If BSY isn't
593 * cleared, perform CLO and proceed to IDENTIFY (achieved by
594 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
595 *
596 * Wait for two seconds. Devices attached to downstream port
597 * which can't process the following IDENTIFY after this will
598 * have to be reset again. For most cases, this should
599 * suffice while making probing snappish enough.
600 */
601 if (online) {
602 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
603 ahci_check_ready);
604 if (rc)
605 ahci_kick_engine(ap);
606 }
607 return rc;
608 }
609
610 #ifdef CONFIG_PM
611 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
612 {
613 struct ata_host *host = dev_get_drvdata(&pdev->dev);
614 struct ahci_host_priv *hpriv = host->private_data;
615 void __iomem *mmio = hpriv->mmio;
616 u32 ctl;
617
618 if (mesg.event & PM_EVENT_SUSPEND &&
619 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
620 dev_printk(KERN_ERR, &pdev->dev,
621 "BIOS update required for suspend/resume\n");
622 return -EIO;
623 }
624
625 if (mesg.event & PM_EVENT_SLEEP) {
626 /* AHCI spec rev1.1 section 8.3.3:
627 * Software must disable interrupts prior to requesting a
628 * transition of the HBA to D3 state.
629 */
630 ctl = readl(mmio + HOST_CTL);
631 ctl &= ~HOST_IRQ_EN;
632 writel(ctl, mmio + HOST_CTL);
633 readl(mmio + HOST_CTL); /* flush */
634 }
635
636 return ata_pci_device_suspend(pdev, mesg);
637 }
638
639 static int ahci_pci_device_resume(struct pci_dev *pdev)
640 {
641 struct ata_host *host = dev_get_drvdata(&pdev->dev);
642 int rc;
643
644 rc = ata_pci_device_do_resume(pdev);
645 if (rc)
646 return rc;
647
648 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
649 rc = ahci_pci_reset_controller(host);
650 if (rc)
651 return rc;
652
653 ahci_pci_init_controller(host);
654 }
655
656 ata_host_resume(host);
657
658 return 0;
659 }
660 #endif
661
662 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
663 {
664 int rc;
665
666 if (using_dac &&
667 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
668 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
669 if (rc) {
670 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
671 if (rc) {
672 dev_printk(KERN_ERR, &pdev->dev,
673 "64-bit DMA enable failed\n");
674 return rc;
675 }
676 }
677 } else {
678 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
679 if (rc) {
680 dev_printk(KERN_ERR, &pdev->dev,
681 "32-bit DMA enable failed\n");
682 return rc;
683 }
684 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
685 if (rc) {
686 dev_printk(KERN_ERR, &pdev->dev,
687 "32-bit consistent DMA enable failed\n");
688 return rc;
689 }
690 }
691 return 0;
692 }
693
694 static void ahci_pci_print_info(struct ata_host *host)
695 {
696 struct pci_dev *pdev = to_pci_dev(host->dev);
697 u16 cc;
698 const char *scc_s;
699
700 pci_read_config_word(pdev, 0x0a, &cc);
701 if (cc == PCI_CLASS_STORAGE_IDE)
702 scc_s = "IDE";
703 else if (cc == PCI_CLASS_STORAGE_SATA)
704 scc_s = "SATA";
705 else if (cc == PCI_CLASS_STORAGE_RAID)
706 scc_s = "RAID";
707 else
708 scc_s = "unknown";
709
710 ahci_print_info(host, scc_s);
711 }
712
713 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
714 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
715 * support PMP and the 4726 either directly exports the device
716 * attached to the first downstream port or acts as a hardware storage
717 * controller and emulate a single ATA device (can be RAID 0/1 or some
718 * other configuration).
719 *
720 * When there's no device attached to the first downstream port of the
721 * 4726, "Config Disk" appears, which is a pseudo ATA device to
722 * configure the 4726. However, ATA emulation of the device is very
723 * lame. It doesn't send signature D2H Reg FIS after the initial
724 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
725 *
726 * The following function works around the problem by always using
727 * hardreset on the port and not depending on receiving signature FIS
728 * afterward. If signature FIS isn't received soon, ATA class is
729 * assumed without follow-up softreset.
730 */
731 static void ahci_p5wdh_workaround(struct ata_host *host)
732 {
733 static struct dmi_system_id sysids[] = {
734 {
735 .ident = "P5W DH Deluxe",
736 .matches = {
737 DMI_MATCH(DMI_SYS_VENDOR,
738 "ASUSTEK COMPUTER INC"),
739 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
740 },
741 },
742 { }
743 };
744 struct pci_dev *pdev = to_pci_dev(host->dev);
745
746 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
747 dmi_check_system(sysids)) {
748 struct ata_port *ap = host->ports[1];
749
750 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
751 "Deluxe on-board SIMG4726 workaround\n");
752
753 ap->ops = &ahci_p5wdh_ops;
754 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
755 }
756 }
757
758 /* only some SB600 ahci controllers can do 64bit DMA */
759 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
760 {
761 static const struct dmi_system_id sysids[] = {
762 /*
763 * The oldest version known to be broken is 0901 and
764 * working is 1501 which was released on 2007-10-26.
765 * Enable 64bit DMA on 1501 and anything newer.
766 *
767 * Please read bko#9412 for more info.
768 */
769 {
770 .ident = "ASUS M2A-VM",
771 .matches = {
772 DMI_MATCH(DMI_BOARD_VENDOR,
773 "ASUSTeK Computer INC."),
774 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
775 },
776 .driver_data = "20071026", /* yyyymmdd */
777 },
778 /*
779 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
780 * support 64bit DMA.
781 *
782 * BIOS versions earlier than 1.5 had the Manufacturer DMI
783 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
784 * This spelling mistake was fixed in BIOS version 1.5, so
785 * 1.5 and later have the Manufacturer as
786 * "MICRO-STAR INTERNATIONAL CO.,LTD".
787 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
788 *
789 * BIOS versions earlier than 1.9 had a Board Product Name
790 * DMI field of "MS-7376". This was changed to be
791 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
792 * match on DMI_BOARD_NAME of "MS-7376".
793 */
794 {
795 .ident = "MSI K9A2 Platinum",
796 .matches = {
797 DMI_MATCH(DMI_BOARD_VENDOR,
798 "MICRO-STAR INTER"),
799 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
800 },
801 },
802 { }
803 };
804 const struct dmi_system_id *match;
805 int year, month, date;
806 char buf[9];
807
808 match = dmi_first_match(sysids);
809 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
810 !match)
811 return false;
812
813 if (!match->driver_data)
814 goto enable_64bit;
815
816 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
817 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
818
819 if (strcmp(buf, match->driver_data) >= 0)
820 goto enable_64bit;
821 else {
822 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
823 "forcing 32bit DMA, update BIOS\n", match->ident);
824 return false;
825 }
826
827 enable_64bit:
828 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
829 match->ident);
830 return true;
831 }
832
833 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
834 {
835 static const struct dmi_system_id broken_systems[] = {
836 {
837 .ident = "HP Compaq nx6310",
838 .matches = {
839 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
840 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
841 },
842 /* PCI slot number of the controller */
843 .driver_data = (void *)0x1FUL,
844 },
845 {
846 .ident = "HP Compaq 6720s",
847 .matches = {
848 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
849 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
850 },
851 /* PCI slot number of the controller */
852 .driver_data = (void *)0x1FUL,
853 },
854
855 { } /* terminate list */
856 };
857 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
858
859 if (dmi) {
860 unsigned long slot = (unsigned long)dmi->driver_data;
861 /* apply the quirk only to on-board controllers */
862 return slot == PCI_SLOT(pdev->devfn);
863 }
864
865 return false;
866 }
867
868 static bool ahci_broken_suspend(struct pci_dev *pdev)
869 {
870 static const struct dmi_system_id sysids[] = {
871 /*
872 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
873 * to the harddisk doesn't become online after
874 * resuming from STR. Warn and fail suspend.
875 *
876 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
877 *
878 * Use dates instead of versions to match as HP is
879 * apparently recycling both product and version
880 * strings.
881 *
882 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
883 */
884 {
885 .ident = "dv4",
886 .matches = {
887 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
888 DMI_MATCH(DMI_PRODUCT_NAME,
889 "HP Pavilion dv4 Notebook PC"),
890 },
891 .driver_data = "20090105", /* F.30 */
892 },
893 {
894 .ident = "dv5",
895 .matches = {
896 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
897 DMI_MATCH(DMI_PRODUCT_NAME,
898 "HP Pavilion dv5 Notebook PC"),
899 },
900 .driver_data = "20090506", /* F.16 */
901 },
902 {
903 .ident = "dv6",
904 .matches = {
905 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
906 DMI_MATCH(DMI_PRODUCT_NAME,
907 "HP Pavilion dv6 Notebook PC"),
908 },
909 .driver_data = "20090423", /* F.21 */
910 },
911 {
912 .ident = "HDX18",
913 .matches = {
914 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
915 DMI_MATCH(DMI_PRODUCT_NAME,
916 "HP HDX18 Notebook PC"),
917 },
918 .driver_data = "20090430", /* F.23 */
919 },
920 /*
921 * Acer eMachines G725 has the same problem. BIOS
922 * V1.03 is known to be broken. V3.04 is known to
923 * work. Inbetween, there are V1.06, V2.06 and V3.03
924 * that we don't have much idea about. For now,
925 * blacklist anything older than V3.04.
926 *
927 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
928 */
929 {
930 .ident = "G725",
931 .matches = {
932 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
933 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
934 },
935 .driver_data = "20091216", /* V3.04 */
936 },
937 { } /* terminate list */
938 };
939 const struct dmi_system_id *dmi = dmi_first_match(sysids);
940 int year, month, date;
941 char buf[9];
942
943 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
944 return false;
945
946 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
947 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
948
949 return strcmp(buf, dmi->driver_data) < 0;
950 }
951
952 static bool ahci_broken_online(struct pci_dev *pdev)
953 {
954 #define ENCODE_BUSDEVFN(bus, slot, func) \
955 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
956 static const struct dmi_system_id sysids[] = {
957 /*
958 * There are several gigabyte boards which use
959 * SIMG5723s configured as hardware RAID. Certain
960 * 5723 firmware revisions shipped there keep the link
961 * online but fail to answer properly to SRST or
962 * IDENTIFY when no device is attached downstream
963 * causing libata to retry quite a few times leading
964 * to excessive detection delay.
965 *
966 * As these firmwares respond to the second reset try
967 * with invalid device signature, considering unknown
968 * sig as offline works around the problem acceptably.
969 */
970 {
971 .ident = "EP45-DQ6",
972 .matches = {
973 DMI_MATCH(DMI_BOARD_VENDOR,
974 "Gigabyte Technology Co., Ltd."),
975 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
976 },
977 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
978 },
979 {
980 .ident = "EP45-DS5",
981 .matches = {
982 DMI_MATCH(DMI_BOARD_VENDOR,
983 "Gigabyte Technology Co., Ltd."),
984 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
985 },
986 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
987 },
988 { } /* terminate list */
989 };
990 #undef ENCODE_BUSDEVFN
991 const struct dmi_system_id *dmi = dmi_first_match(sysids);
992 unsigned int val;
993
994 if (!dmi)
995 return false;
996
997 val = (unsigned long)dmi->driver_data;
998
999 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1000 }
1001
1002 #ifdef CONFIG_ATA_ACPI
1003 static void ahci_gtf_filter_workaround(struct ata_host *host)
1004 {
1005 static const struct dmi_system_id sysids[] = {
1006 /*
1007 * Aspire 3810T issues a bunch of SATA enable commands
1008 * via _GTF including an invalid one and one which is
1009 * rejected by the device. Among the successful ones
1010 * is FPDMA non-zero offset enable which when enabled
1011 * only on the drive side leads to NCQ command
1012 * failures. Filter it out.
1013 */
1014 {
1015 .ident = "Aspire 3810T",
1016 .matches = {
1017 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1018 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1019 },
1020 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1021 },
1022 { }
1023 };
1024 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1025 unsigned int filter;
1026 int i;
1027
1028 if (!dmi)
1029 return;
1030
1031 filter = (unsigned long)dmi->driver_data;
1032 dev_printk(KERN_INFO, host->dev,
1033 "applying extra ACPI _GTF filter 0x%x for %s\n",
1034 filter, dmi->ident);
1035
1036 for (i = 0; i < host->n_ports; i++) {
1037 struct ata_port *ap = host->ports[i];
1038 struct ata_link *link;
1039 struct ata_device *dev;
1040
1041 ata_for_each_link(link, ap, EDGE)
1042 ata_for_each_dev(dev, link, ALL)
1043 dev->gtf_filter |= filter;
1044 }
1045 }
1046 #else
1047 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1048 {}
1049 #endif
1050
1051 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1052 {
1053 static int printed_version;
1054 unsigned int board_id = ent->driver_data;
1055 struct ata_port_info pi = ahci_port_info[board_id];
1056 const struct ata_port_info *ppi[] = { &pi, NULL };
1057 struct device *dev = &pdev->dev;
1058 struct ahci_host_priv *hpriv;
1059 struct ata_host *host;
1060 int n_ports, i, rc;
1061
1062 VPRINTK("ENTER\n");
1063
1064 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1065
1066 if (!printed_version++)
1067 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1068
1069 /* The AHCI driver can only drive the SATA ports, the PATA driver
1070 can drive them all so if both drivers are selected make sure
1071 AHCI stays out of the way */
1072 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1073 return -ENODEV;
1074
1075 /*
1076 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1077 * ahci, use ata_generic instead.
1078 */
1079 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1080 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1081 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1082 pdev->subsystem_device == 0xcb89)
1083 return -ENODEV;
1084
1085 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1086 * At the moment, we can only use the AHCI mode. Let the users know
1087 * that for SAS drives they're out of luck.
1088 */
1089 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1090 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1091 "can only drive SATA devices with this driver\n");
1092
1093 /* acquire resources */
1094 rc = pcim_enable_device(pdev);
1095 if (rc)
1096 return rc;
1097
1098 /* AHCI controllers often implement SFF compatible interface.
1099 * Grab all PCI BARs just in case.
1100 */
1101 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1102 if (rc == -EBUSY)
1103 pcim_pin_device(pdev);
1104 if (rc)
1105 return rc;
1106
1107 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1108 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1109 u8 map;
1110
1111 /* ICH6s share the same PCI ID for both piix and ahci
1112 * modes. Enabling ahci mode while MAP indicates
1113 * combined mode is a bad idea. Yield to ata_piix.
1114 */
1115 pci_read_config_byte(pdev, ICH_MAP, &map);
1116 if (map & 0x3) {
1117 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1118 "combined mode, can't enable AHCI mode\n");
1119 return -ENODEV;
1120 }
1121 }
1122
1123 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1124 if (!hpriv)
1125 return -ENOMEM;
1126 hpriv->flags |= (unsigned long)pi.private_data;
1127
1128 /* MCP65 revision A1 and A2 can't do MSI */
1129 if (board_id == board_ahci_mcp65 &&
1130 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1131 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1132
1133 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1134 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1135 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1136
1137 /* only some SB600s can do 64bit DMA */
1138 if (ahci_sb600_enable_64bit(pdev))
1139 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1140
1141 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1142 pci_intx(pdev, 1);
1143
1144 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1145
1146 /* save initial config */
1147 ahci_pci_save_initial_config(pdev, hpriv);
1148
1149 /* prepare host */
1150 if (hpriv->cap & HOST_CAP_NCQ) {
1151 pi.flags |= ATA_FLAG_NCQ;
1152 /*
1153 * Auto-activate optimization is supposed to be
1154 * supported on all AHCI controllers indicating NCQ
1155 * capability, but it seems to be broken on some
1156 * chipsets including NVIDIAs.
1157 */
1158 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1159 pi.flags |= ATA_FLAG_FPDMA_AA;
1160 }
1161
1162 if (hpriv->cap & HOST_CAP_PMP)
1163 pi.flags |= ATA_FLAG_PMP;
1164
1165 ahci_set_em_messages(hpriv, &pi);
1166
1167 if (ahci_broken_system_poweroff(pdev)) {
1168 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1169 dev_info(&pdev->dev,
1170 "quirky BIOS, skipping spindown on poweroff\n");
1171 }
1172
1173 if (ahci_broken_suspend(pdev)) {
1174 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1175 dev_printk(KERN_WARNING, &pdev->dev,
1176 "BIOS update required for suspend/resume\n");
1177 }
1178
1179 if (ahci_broken_online(pdev)) {
1180 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1181 dev_info(&pdev->dev,
1182 "online status unreliable, applying workaround\n");
1183 }
1184
1185 /* CAP.NP sometimes indicate the index of the last enabled
1186 * port, at other times, that of the last possible port, so
1187 * determining the maximum port number requires looking at
1188 * both CAP.NP and port_map.
1189 */
1190 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1191
1192 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1193 if (!host)
1194 return -ENOMEM;
1195 host->private_data = hpriv;
1196
1197 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1198 host->flags |= ATA_HOST_PARALLEL_SCAN;
1199 else
1200 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1201
1202 if (pi.flags & ATA_FLAG_EM)
1203 ahci_reset_em(host);
1204
1205 for (i = 0; i < host->n_ports; i++) {
1206 struct ata_port *ap = host->ports[i];
1207
1208 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1209 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1210 0x100 + ap->port_no * 0x80, "port");
1211
1212 /* set enclosure management message type */
1213 if (ap->flags & ATA_FLAG_EM)
1214 ap->em_message_type = hpriv->em_msg_type;
1215
1216
1217 /* disabled/not-implemented port */
1218 if (!(hpriv->port_map & (1 << i)))
1219 ap->ops = &ata_dummy_port_ops;
1220 }
1221
1222 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1223 ahci_p5wdh_workaround(host);
1224
1225 /* apply gtf filter quirk */
1226 ahci_gtf_filter_workaround(host);
1227
1228 /* initialize adapter */
1229 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1230 if (rc)
1231 return rc;
1232
1233 rc = ahci_pci_reset_controller(host);
1234 if (rc)
1235 return rc;
1236
1237 ahci_pci_init_controller(host);
1238 ahci_pci_print_info(host);
1239
1240 pci_set_master(pdev);
1241 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1242 &ahci_sht);
1243 }
1244
1245 static int __init ahci_init(void)
1246 {
1247 return pci_register_driver(&ahci_pci_driver);
1248 }
1249
1250 static void __exit ahci_exit(void)
1251 {
1252 pci_unregister_driver(&ahci_pci_driver);
1253 }
1254
1255
1256 MODULE_AUTHOR("Jeff Garzik");
1257 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1258 MODULE_LICENSE("GPL");
1259 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1260 MODULE_VERSION(DRV_VERSION);
1261
1262 module_init(ahci_init);
1263 module_exit(ahci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree