2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
58 #include <asm/msidef.h>
59 #include <asm/hypertransport.h>
60 #include <asm/setup.h>
61 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
72 * Is the SiS APIC rmw bug present ?
73 * -1 = don't know, 0 = no, 1 = yes
75 int sis_apic_bug
= -1;
77 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
78 static DEFINE_RAW_SPINLOCK(vector_lock
);
81 * # of IRQ routing registers
83 int nr_ioapic_registers
[MAX_IO_APICS
];
85 /* I/O APIC entries */
86 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
89 /* IO APIC gsi routing info */
90 struct mp_ioapic_gsi mp_gsi_routing
[MAX_IO_APICS
];
92 /* The one past the highest gsi number used */
95 /* MP IRQ source entries */
96 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
98 /* # of MP IRQ source entries */
102 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
104 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
105 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
108 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
110 int skip_ioapic_setup
;
112 void arch_disable_smp_support(void)
116 noioapicreroute
= -1;
118 skip_ioapic_setup
= 1;
121 static int __init
parse_noapic(char *str
)
123 /* disable IO-APIC */
124 arch_disable_smp_support();
127 early_param("noapic", parse_noapic
);
129 struct irq_pin_list
{
131 struct irq_pin_list
*next
;
134 static struct irq_pin_list
*get_one_free_irq_2_pin(int node
)
136 struct irq_pin_list
*pin
;
138 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
143 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
144 #ifdef CONFIG_SPARSE_IRQ
145 static struct irq_cfg irq_cfgx
[NR_IRQS_LEGACY
];
147 static struct irq_cfg irq_cfgx
[NR_IRQS
];
150 int __init
arch_early_irq_init(void)
153 struct irq_desc
*desc
;
158 if (!legacy_pic
->nr_legacy_irqs
) {
164 count
= ARRAY_SIZE(irq_cfgx
);
165 node
= cpu_to_node(boot_cpu_id
);
167 for (i
= 0; i
< count
; i
++) {
168 desc
= irq_to_desc(i
);
169 desc
->chip_data
= &cfg
[i
];
170 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_NOWAIT
, node
);
171 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_NOWAIT
, node
);
173 * For legacy IRQ's, start with assigning irq0 to irq15 to
174 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
176 if (i
< legacy_pic
->nr_legacy_irqs
) {
177 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
178 cpumask_set_cpu(0, cfg
[i
].domain
);
185 #ifdef CONFIG_SPARSE_IRQ
186 struct irq_cfg
*irq_cfg(unsigned int irq
)
188 struct irq_cfg
*cfg
= NULL
;
189 struct irq_desc
*desc
;
191 desc
= irq_to_desc(irq
);
193 cfg
= desc
->chip_data
;
198 static struct irq_cfg
*get_one_free_irq_cfg(int node
)
202 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
204 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
207 } else if (!zalloc_cpumask_var_node(&cfg
->old_domain
,
209 free_cpumask_var(cfg
->domain
);
218 int arch_init_chip_data(struct irq_desc
*desc
, int node
)
222 cfg
= desc
->chip_data
;
224 desc
->chip_data
= get_one_free_irq_cfg(node
);
225 if (!desc
->chip_data
) {
226 printk(KERN_ERR
"can not alloc irq_cfg\n");
234 /* for move_irq_desc */
236 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int node
)
238 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
240 cfg
->irq_2_pin
= NULL
;
241 old_entry
= old_cfg
->irq_2_pin
;
245 entry
= get_one_free_irq_2_pin(node
);
249 entry
->apic
= old_entry
->apic
;
250 entry
->pin
= old_entry
->pin
;
253 old_entry
= old_entry
->next
;
255 entry
= get_one_free_irq_2_pin(node
);
263 /* still use the old one */
266 entry
->apic
= old_entry
->apic
;
267 entry
->pin
= old_entry
->pin
;
270 old_entry
= old_entry
->next
;
274 cfg
->irq_2_pin
= head
;
277 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
279 struct irq_pin_list
*entry
, *next
;
281 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
284 entry
= old_cfg
->irq_2_pin
;
291 old_cfg
->irq_2_pin
= NULL
;
294 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
295 struct irq_desc
*desc
, int node
)
298 struct irq_cfg
*old_cfg
;
300 cfg
= get_one_free_irq_cfg(node
);
305 desc
->chip_data
= cfg
;
307 old_cfg
= old_desc
->chip_data
;
309 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
311 init_copy_irq_2_pin(old_cfg
, cfg
, node
);
314 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
319 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
321 struct irq_cfg
*old_cfg
, *cfg
;
323 old_cfg
= old_desc
->chip_data
;
324 cfg
= desc
->chip_data
;
330 free_irq_2_pin(old_cfg
, cfg
);
331 free_irq_cfg(old_cfg
);
332 old_desc
->chip_data
= NULL
;
335 /* end for move_irq_desc */
338 struct irq_cfg
*irq_cfg(unsigned int irq
)
340 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
347 unsigned int unused
[3];
349 unsigned int unused2
[11];
353 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
355 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
356 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
359 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
361 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
362 writel(vector
, &io_apic
->eoi
);
365 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
367 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
368 writel(reg
, &io_apic
->index
);
369 return readl(&io_apic
->data
);
372 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
374 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
375 writel(reg
, &io_apic
->index
);
376 writel(value
, &io_apic
->data
);
380 * Re-write a value: to be used for read-modify-write
381 * cycles where the read already set up the index register.
383 * Older SiS APIC requires we rewrite the index register
385 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
387 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
390 writel(reg
, &io_apic
->index
);
391 writel(value
, &io_apic
->data
);
394 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
396 struct irq_pin_list
*entry
;
399 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
400 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
405 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
406 /* Is the remote IRR bit set? */
407 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
408 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
412 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
418 struct { u32 w1
, w2
; };
419 struct IO_APIC_route_entry entry
;
422 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
424 union entry_union eu
;
426 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
427 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
428 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
429 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
434 * When we write a new IO APIC routing entry, we need to write the high
435 * word first! If the mask bit in the low word is clear, we will enable
436 * the interrupt, and we need to make sure the entry is fully populated
437 * before that happens.
440 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
442 union entry_union eu
= {{0, 0}};
445 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
446 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
449 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
452 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
453 __ioapic_write_entry(apic
, pin
, e
);
454 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
458 * When we mask an IO APIC routing entry, we need to write the low
459 * word first, in order to set the mask bit before we change the
462 static void ioapic_mask_entry(int apic
, int pin
)
465 union entry_union eu
= { .entry
.mask
= 1 };
467 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
468 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
469 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
470 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
474 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
475 * shared ISA-space IRQs, so we have to support them. We are super
476 * fast in the common case, and fast for shared ISA-space IRQs.
479 add_pin_to_irq_node_nopanic(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
481 struct irq_pin_list
**last
, *entry
;
483 /* don't allow duplicates */
484 last
= &cfg
->irq_2_pin
;
485 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
486 if (entry
->apic
== apic
&& entry
->pin
== pin
)
491 entry
= get_one_free_irq_2_pin(node
);
493 printk(KERN_ERR
"can not alloc irq_pin_list (%d,%d,%d)\n",
504 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
506 if (add_pin_to_irq_node_nopanic(cfg
, node
, apic
, pin
))
507 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
511 * Reroute an IRQ to a different pin.
513 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
514 int oldapic
, int oldpin
,
515 int newapic
, int newpin
)
517 struct irq_pin_list
*entry
;
519 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
520 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
521 entry
->apic
= newapic
;
523 /* every one is different, right? */
528 /* old apic/pin didn't exist, so just add new ones */
529 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
532 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
533 int mask_and
, int mask_or
,
534 void (*final
)(struct irq_pin_list
*entry
))
536 unsigned int reg
, pin
;
539 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
542 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
547 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
548 int mask_and
, int mask_or
,
549 void (*final
)(struct irq_pin_list
*entry
))
551 struct irq_pin_list
*entry
;
553 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
554 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
557 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list
*entry
)
559 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
560 IO_APIC_REDIR_MASKED
, NULL
);
563 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list
*entry
)
565 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_MASKED
,
566 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
569 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
571 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
574 static void io_apic_sync(struct irq_pin_list
*entry
)
577 * Synchronize the IO-APIC and the CPU by doing
578 * a dummy read from the IO-APIC
580 struct io_apic __iomem
*io_apic
;
581 io_apic
= io_apic_base(entry
->apic
);
582 readl(&io_apic
->data
);
585 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
587 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
590 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
592 struct irq_cfg
*cfg
= desc
->chip_data
;
597 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
598 __mask_IO_APIC_irq(cfg
);
599 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
602 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
604 struct irq_cfg
*cfg
= desc
->chip_data
;
607 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
608 __unmask_IO_APIC_irq(cfg
);
609 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
612 static void mask_IO_APIC_irq(unsigned int irq
)
614 struct irq_desc
*desc
= irq_to_desc(irq
);
616 mask_IO_APIC_irq_desc(desc
);
618 static void unmask_IO_APIC_irq(unsigned int irq
)
620 struct irq_desc
*desc
= irq_to_desc(irq
);
622 unmask_IO_APIC_irq_desc(desc
);
625 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
627 struct IO_APIC_route_entry entry
;
629 /* Check delivery_mode to be sure we're not clearing an SMI pin */
630 entry
= ioapic_read_entry(apic
, pin
);
631 if (entry
.delivery_mode
== dest_SMI
)
634 * Disable it in the IO-APIC irq-routing table:
636 ioapic_mask_entry(apic
, pin
);
639 static void clear_IO_APIC (void)
643 for (apic
= 0; apic
< nr_ioapics
; apic
++)
644 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
645 clear_IO_APIC_pin(apic
, pin
);
650 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
651 * specific CPU-side IRQs.
655 static int pirq_entries
[MAX_PIRQS
] = {
656 [0 ... MAX_PIRQS
- 1] = -1
659 static int __init
ioapic_pirq_setup(char *str
)
662 int ints
[MAX_PIRQS
+1];
664 get_options(str
, ARRAY_SIZE(ints
), ints
);
666 apic_printk(APIC_VERBOSE
, KERN_INFO
667 "PIRQ redirection, working around broken MP-BIOS.\n");
669 if (ints
[0] < MAX_PIRQS
)
672 for (i
= 0; i
< max
; i
++) {
673 apic_printk(APIC_VERBOSE
, KERN_DEBUG
674 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
676 * PIRQs are mapped upside down, usually.
678 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
683 __setup("pirq=", ioapic_pirq_setup
);
684 #endif /* CONFIG_X86_32 */
686 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
689 struct IO_APIC_route_entry
**ioapic_entries
;
691 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
696 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
697 ioapic_entries
[apic
] =
698 kzalloc(sizeof(struct IO_APIC_route_entry
) *
699 nr_ioapic_registers
[apic
], GFP_ATOMIC
);
700 if (!ioapic_entries
[apic
])
704 return ioapic_entries
;
708 kfree(ioapic_entries
[apic
]);
709 kfree(ioapic_entries
);
715 * Saves all the IO-APIC RTE's
717 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
724 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
725 if (!ioapic_entries
[apic
])
728 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
729 ioapic_entries
[apic
][pin
] =
730 ioapic_read_entry(apic
, pin
);
737 * Mask all IO APIC entries.
739 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
746 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
747 if (!ioapic_entries
[apic
])
750 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
751 struct IO_APIC_route_entry entry
;
753 entry
= ioapic_entries
[apic
][pin
];
756 ioapic_write_entry(apic
, pin
, entry
);
763 * Restore IO APIC entries which was saved in ioapic_entries.
765 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
772 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
773 if (!ioapic_entries
[apic
])
776 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
777 ioapic_write_entry(apic
, pin
,
778 ioapic_entries
[apic
][pin
]);
783 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
787 for (apic
= 0; apic
< nr_ioapics
; apic
++)
788 kfree(ioapic_entries
[apic
]);
790 kfree(ioapic_entries
);
794 * Find the IRQ entry number of a certain pin.
796 static int find_irq_entry(int apic
, int pin
, int type
)
800 for (i
= 0; i
< mp_irq_entries
; i
++)
801 if (mp_irqs
[i
].irqtype
== type
&&
802 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
803 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
804 mp_irqs
[i
].dstirq
== pin
)
811 * Find the pin to which IRQ[irq] (ISA) is connected
813 static int __init
find_isa_irq_pin(int irq
, int type
)
817 for (i
= 0; i
< mp_irq_entries
; i
++) {
818 int lbus
= mp_irqs
[i
].srcbus
;
820 if (test_bit(lbus
, mp_bus_not_pci
) &&
821 (mp_irqs
[i
].irqtype
== type
) &&
822 (mp_irqs
[i
].srcbusirq
== irq
))
824 return mp_irqs
[i
].dstirq
;
829 static int __init
find_isa_irq_apic(int irq
, int type
)
833 for (i
= 0; i
< mp_irq_entries
; i
++) {
834 int lbus
= mp_irqs
[i
].srcbus
;
836 if (test_bit(lbus
, mp_bus_not_pci
) &&
837 (mp_irqs
[i
].irqtype
== type
) &&
838 (mp_irqs
[i
].srcbusirq
== irq
))
841 if (i
< mp_irq_entries
) {
843 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
844 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
852 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
854 * EISA Edge/Level control register, ELCR
856 static int EISA_ELCR(unsigned int irq
)
858 if (irq
< legacy_pic
->nr_legacy_irqs
) {
859 unsigned int port
= 0x4d0 + (irq
>> 3);
860 return (inb(port
) >> (irq
& 7)) & 1;
862 apic_printk(APIC_VERBOSE
, KERN_INFO
863 "Broken MPtable reports ISA irq %d\n", irq
);
869 /* ISA interrupts are always polarity zero edge triggered,
870 * when listed as conforming in the MP table. */
872 #define default_ISA_trigger(idx) (0)
873 #define default_ISA_polarity(idx) (0)
875 /* EISA interrupts are always polarity zero and can be edge or level
876 * trigger depending on the ELCR value. If an interrupt is listed as
877 * EISA conforming in the MP table, that means its trigger type must
878 * be read in from the ELCR */
880 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
881 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
883 /* PCI interrupts are always polarity one level triggered,
884 * when listed as conforming in the MP table. */
886 #define default_PCI_trigger(idx) (1)
887 #define default_PCI_polarity(idx) (1)
889 /* MCA interrupts are always polarity zero level triggered,
890 * when listed as conforming in the MP table. */
892 #define default_MCA_trigger(idx) (1)
893 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
895 static int MPBIOS_polarity(int idx
)
897 int bus
= mp_irqs
[idx
].srcbus
;
901 * Determine IRQ line polarity (high active or low active):
903 switch (mp_irqs
[idx
].irqflag
& 3)
905 case 0: /* conforms, ie. bus-type dependent polarity */
906 if (test_bit(bus
, mp_bus_not_pci
))
907 polarity
= default_ISA_polarity(idx
);
909 polarity
= default_PCI_polarity(idx
);
911 case 1: /* high active */
916 case 2: /* reserved */
918 printk(KERN_WARNING
"broken BIOS!!\n");
922 case 3: /* low active */
927 default: /* invalid */
929 printk(KERN_WARNING
"broken BIOS!!\n");
937 static int MPBIOS_trigger(int idx
)
939 int bus
= mp_irqs
[idx
].srcbus
;
943 * Determine IRQ trigger mode (edge or level sensitive):
945 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
947 case 0: /* conforms, ie. bus-type dependent */
948 if (test_bit(bus
, mp_bus_not_pci
))
949 trigger
= default_ISA_trigger(idx
);
951 trigger
= default_PCI_trigger(idx
);
952 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
953 switch (mp_bus_id_to_type
[bus
]) {
954 case MP_BUS_ISA
: /* ISA pin */
956 /* set before the switch */
959 case MP_BUS_EISA
: /* EISA pin */
961 trigger
= default_EISA_trigger(idx
);
964 case MP_BUS_PCI
: /* PCI pin */
966 /* set before the switch */
969 case MP_BUS_MCA
: /* MCA pin */
971 trigger
= default_MCA_trigger(idx
);
976 printk(KERN_WARNING
"broken BIOS!!\n");
988 case 2: /* reserved */
990 printk(KERN_WARNING
"broken BIOS!!\n");
999 default: /* invalid */
1001 printk(KERN_WARNING
"broken BIOS!!\n");
1009 static inline int irq_polarity(int idx
)
1011 return MPBIOS_polarity(idx
);
1014 static inline int irq_trigger(int idx
)
1016 return MPBIOS_trigger(idx
);
1019 static int pin_2_irq(int idx
, int apic
, int pin
)
1022 int bus
= mp_irqs
[idx
].srcbus
;
1025 * Debugging check, we are in big trouble if this message pops up!
1027 if (mp_irqs
[idx
].dstirq
!= pin
)
1028 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1030 if (test_bit(bus
, mp_bus_not_pci
)) {
1031 irq
= mp_irqs
[idx
].srcbusirq
;
1033 u32 gsi
= mp_gsi_routing
[apic
].gsi_base
+ pin
;
1035 if (gsi
>= NR_IRQS_LEGACY
)
1038 irq
= gsi_top
+ gsi
;
1041 #ifdef CONFIG_X86_32
1043 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1045 if ((pin
>= 16) && (pin
<= 23)) {
1046 if (pirq_entries
[pin
-16] != -1) {
1047 if (!pirq_entries
[pin
-16]) {
1048 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1049 "disabling PIRQ%d\n", pin
-16);
1051 irq
= pirq_entries
[pin
-16];
1052 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1053 "using PIRQ%d -> IRQ %d\n",
1064 * Find a specific PCI IRQ entry.
1065 * Not an __init, possibly needed by modules
1067 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1068 struct io_apic_irq_attr
*irq_attr
)
1070 int apic
, i
, best_guess
= -1;
1072 apic_printk(APIC_DEBUG
,
1073 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1075 if (test_bit(bus
, mp_bus_not_pci
)) {
1076 apic_printk(APIC_VERBOSE
,
1077 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1080 for (i
= 0; i
< mp_irq_entries
; i
++) {
1081 int lbus
= mp_irqs
[i
].srcbus
;
1083 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1084 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1085 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1088 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1089 !mp_irqs
[i
].irqtype
&&
1091 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1092 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1094 if (!(apic
|| IO_APIC_IRQ(irq
)))
1097 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1098 set_io_apic_irq_attr(irq_attr
, apic
,
1105 * Use the first all-but-pin matching entry as a
1106 * best-guess fuzzy result for broken mptables.
1108 if (best_guess
< 0) {
1109 set_io_apic_irq_attr(irq_attr
, apic
,
1119 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1121 void lock_vector_lock(void)
1123 /* Used to the online set of cpus does not change
1124 * during assign_irq_vector.
1126 raw_spin_lock(&vector_lock
);
1129 void unlock_vector_lock(void)
1131 raw_spin_unlock(&vector_lock
);
1135 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1138 * NOTE! The local APIC isn't very good at handling
1139 * multiple interrupts at the same interrupt level.
1140 * As the interrupt level is determined by taking the
1141 * vector number and shifting that right by 4, we
1142 * want to spread these out a bit so that they don't
1143 * all fall in the same interrupt level.
1145 * Also, we've got to be careful not to trash gate
1146 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1148 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1149 static int current_offset
= VECTOR_OFFSET_START
% 8;
1150 unsigned int old_vector
;
1152 cpumask_var_t tmp_mask
;
1154 if (cfg
->move_in_progress
)
1157 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1160 old_vector
= cfg
->vector
;
1162 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1163 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1164 if (!cpumask_empty(tmp_mask
)) {
1165 free_cpumask_var(tmp_mask
);
1170 /* Only try and allocate irqs on cpus that are present */
1172 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1176 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1178 vector
= current_vector
;
1179 offset
= current_offset
;
1182 if (vector
>= first_system_vector
) {
1183 /* If out of vectors on large boxen, must share them. */
1184 offset
= (offset
+ 1) % 8;
1185 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1187 if (unlikely(current_vector
== vector
))
1190 if (test_bit(vector
, used_vectors
))
1193 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1194 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1197 current_vector
= vector
;
1198 current_offset
= offset
;
1200 cfg
->move_in_progress
= 1;
1201 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1203 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1204 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1205 cfg
->vector
= vector
;
1206 cpumask_copy(cfg
->domain
, tmp_mask
);
1210 free_cpumask_var(tmp_mask
);
1214 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1217 unsigned long flags
;
1219 raw_spin_lock_irqsave(&vector_lock
, flags
);
1220 err
= __assign_irq_vector(irq
, cfg
, mask
);
1221 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1225 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1229 BUG_ON(!cfg
->vector
);
1231 vector
= cfg
->vector
;
1232 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1233 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1236 cpumask_clear(cfg
->domain
);
1238 if (likely(!cfg
->move_in_progress
))
1240 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1241 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1243 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1245 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1249 cfg
->move_in_progress
= 0;
1252 void __setup_vector_irq(int cpu
)
1254 /* Initialize vector_irq on a new cpu */
1256 struct irq_cfg
*cfg
;
1257 struct irq_desc
*desc
;
1260 * vector_lock will make sure that we don't run into irq vector
1261 * assignments that might be happening on another cpu in parallel,
1262 * while we setup our initial vector to irq mappings.
1264 raw_spin_lock(&vector_lock
);
1265 /* Mark the inuse vectors */
1266 for_each_irq_desc(irq
, desc
) {
1267 cfg
= desc
->chip_data
;
1270 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1271 * will be part of the irq_cfg's domain.
1273 if (irq
< legacy_pic
->nr_legacy_irqs
&& !IO_APIC_IRQ(irq
))
1274 cpumask_set_cpu(cpu
, cfg
->domain
);
1276 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1278 vector
= cfg
->vector
;
1279 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1281 /* Mark the free vectors */
1282 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1283 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1288 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1289 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1291 raw_spin_unlock(&vector_lock
);
1294 static struct irq_chip ioapic_chip
;
1295 static struct irq_chip ir_ioapic_chip
;
1297 #define IOAPIC_AUTO -1
1298 #define IOAPIC_EDGE 0
1299 #define IOAPIC_LEVEL 1
1301 #ifdef CONFIG_X86_32
1302 static inline int IO_APIC_irq_trigger(int irq
)
1306 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1307 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1308 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1309 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1310 return irq_trigger(idx
);
1314 * nonexistent IRQs are edge default
1319 static inline int IO_APIC_irq_trigger(int irq
)
1325 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1328 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1329 trigger
== IOAPIC_LEVEL
)
1330 desc
->status
|= IRQ_LEVEL
;
1332 desc
->status
&= ~IRQ_LEVEL
;
1334 if (irq_remapped(irq
)) {
1335 desc
->status
|= IRQ_MOVE_PCNTXT
;
1337 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1341 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1342 handle_edge_irq
, "edge");
1346 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1347 trigger
== IOAPIC_LEVEL
)
1348 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1352 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1353 handle_edge_irq
, "edge");
1356 int setup_ioapic_entry(int apic_id
, int irq
,
1357 struct IO_APIC_route_entry
*entry
,
1358 unsigned int destination
, int trigger
,
1359 int polarity
, int vector
, int pin
)
1362 * add it to the IO-APIC irq-routing table:
1364 memset(entry
,0,sizeof(*entry
));
1366 if (intr_remapping_enabled
) {
1367 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1369 struct IR_IO_APIC_route_entry
*ir_entry
=
1370 (struct IR_IO_APIC_route_entry
*) entry
;
1374 panic("No mapping iommu for ioapic %d\n", apic_id
);
1376 index
= alloc_irte(iommu
, irq
, 1);
1378 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1380 memset(&irte
, 0, sizeof(irte
));
1383 irte
.dst_mode
= apic
->irq_dest_mode
;
1385 * Trigger mode in the IRTE will always be edge, and the
1386 * actual level or edge trigger will be setup in the IO-APIC
1387 * RTE. This will help simplify level triggered irq migration.
1388 * For more details, see the comments above explainig IO-APIC
1389 * irq migration in the presence of interrupt-remapping.
1391 irte
.trigger_mode
= 0;
1392 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
1393 irte
.vector
= vector
;
1394 irte
.dest_id
= IRTE_DEST(destination
);
1396 /* Set source-id of interrupt request */
1397 set_ioapic_sid(&irte
, apic_id
);
1399 modify_irte(irq
, &irte
);
1401 ir_entry
->index2
= (index
>> 15) & 0x1;
1403 ir_entry
->format
= 1;
1404 ir_entry
->index
= (index
& 0x7fff);
1406 * IO-APIC RTE will be configured with virtual vector.
1407 * irq handler will do the explicit EOI to the io-apic.
1409 ir_entry
->vector
= pin
;
1411 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1412 entry
->dest_mode
= apic
->irq_dest_mode
;
1413 entry
->dest
= destination
;
1414 entry
->vector
= vector
;
1417 entry
->mask
= 0; /* enable IRQ */
1418 entry
->trigger
= trigger
;
1419 entry
->polarity
= polarity
;
1421 /* Mask level triggered irqs.
1422 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1429 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1430 int trigger
, int polarity
)
1432 struct irq_cfg
*cfg
;
1433 struct IO_APIC_route_entry entry
;
1436 if (!IO_APIC_IRQ(irq
))
1439 cfg
= desc
->chip_data
;
1442 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1443 * controllers like 8259. Now that IO-APIC can handle this irq, update
1446 if (irq
< legacy_pic
->nr_legacy_irqs
&& cpumask_test_cpu(0, cfg
->domain
))
1447 apic
->vector_allocation_domain(0, cfg
->domain
);
1449 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1452 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1454 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1455 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1456 "IRQ %d Mode:%i Active:%i)\n",
1457 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1458 irq
, trigger
, polarity
);
1461 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1462 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1463 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1464 mp_ioapics
[apic_id
].apicid
, pin
);
1465 __clear_irq_vector(irq
, cfg
);
1469 ioapic_register_intr(irq
, desc
, trigger
);
1470 if (irq
< legacy_pic
->nr_legacy_irqs
)
1471 legacy_pic
->chip
->mask(irq
);
1473 ioapic_write_entry(apic_id
, pin
, entry
);
1477 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1478 } mp_ioapic_routing
[MAX_IO_APICS
];
1480 static void __init
setup_IO_APIC_irqs(void)
1482 int apic_id
, pin
, idx
, irq
;
1484 struct irq_desc
*desc
;
1485 struct irq_cfg
*cfg
;
1486 int node
= cpu_to_node(boot_cpu_id
);
1488 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1490 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++)
1491 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1492 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1496 apic_printk(APIC_VERBOSE
,
1497 KERN_DEBUG
" %d-%d",
1498 mp_ioapics
[apic_id
].apicid
, pin
);
1500 apic_printk(APIC_VERBOSE
, " %d-%d",
1501 mp_ioapics
[apic_id
].apicid
, pin
);
1505 apic_printk(APIC_VERBOSE
,
1506 " (apicid-pin) not connected\n");
1510 irq
= pin_2_irq(idx
, apic_id
, pin
);
1512 if ((apic_id
> 0) && (irq
> 16))
1516 * Skip the timer IRQ if there's a quirk handler
1517 * installed and if it returns 1:
1519 if (apic
->multi_timer_check
&&
1520 apic
->multi_timer_check(apic_id
, irq
))
1523 desc
= irq_to_desc_alloc_node(irq
, node
);
1525 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1528 cfg
= desc
->chip_data
;
1529 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1531 * don't mark it in pin_programmed, so later acpi could
1532 * set it correctly when irq < 16
1534 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1535 irq_trigger(idx
), irq_polarity(idx
));
1539 apic_printk(APIC_VERBOSE
,
1540 " (apicid-pin) not connected\n");
1544 * for the gsit that is not in first ioapic
1545 * but could not use acpi_register_gsi()
1546 * like some special sci in IBM x3330
1548 void setup_IO_APIC_irq_extra(u32 gsi
)
1550 int apic_id
= 0, pin
, idx
, irq
;
1551 int node
= cpu_to_node(boot_cpu_id
);
1552 struct irq_desc
*desc
;
1553 struct irq_cfg
*cfg
;
1556 * Convert 'gsi' to 'ioapic.pin'.
1558 apic_id
= mp_find_ioapic(gsi
);
1562 pin
= mp_find_ioapic_pin(apic_id
, gsi
);
1563 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1567 irq
= pin_2_irq(idx
, apic_id
, pin
);
1568 #ifdef CONFIG_SPARSE_IRQ
1569 desc
= irq_to_desc(irq
);
1573 desc
= irq_to_desc_alloc_node(irq
, node
);
1575 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1579 cfg
= desc
->chip_data
;
1580 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1582 if (test_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
)) {
1583 pr_debug("Pin %d-%d already programmed\n",
1584 mp_ioapics
[apic_id
].apicid
, pin
);
1587 set_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
);
1589 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1590 irq_trigger(idx
), irq_polarity(idx
));
1594 * Set up the timer pin, possibly with the 8259A-master behind.
1596 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1599 struct IO_APIC_route_entry entry
;
1601 if (intr_remapping_enabled
)
1604 memset(&entry
, 0, sizeof(entry
));
1607 * We use logical delivery to get the timer IRQ
1610 entry
.dest_mode
= apic
->irq_dest_mode
;
1611 entry
.mask
= 0; /* don't mask IRQ for edge */
1612 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1613 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1616 entry
.vector
= vector
;
1619 * The timer IRQ doesn't have to know that behind the
1620 * scene we may have a 8259A-master in AEOI mode ...
1622 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1625 * Add it to the IO-APIC irq-routing table:
1627 ioapic_write_entry(apic_id
, pin
, entry
);
1631 __apicdebuginit(void) print_IO_APIC(void)
1634 union IO_APIC_reg_00 reg_00
;
1635 union IO_APIC_reg_01 reg_01
;
1636 union IO_APIC_reg_02 reg_02
;
1637 union IO_APIC_reg_03 reg_03
;
1638 unsigned long flags
;
1639 struct irq_cfg
*cfg
;
1640 struct irq_desc
*desc
;
1643 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1644 for (i
= 0; i
< nr_ioapics
; i
++)
1645 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1646 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1649 * We are a bit conservative about what we expect. We have to
1650 * know about every hardware change ASAP.
1652 printk(KERN_INFO
"testing the IO APIC.......................\n");
1654 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1656 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1657 reg_00
.raw
= io_apic_read(apic
, 0);
1658 reg_01
.raw
= io_apic_read(apic
, 1);
1659 if (reg_01
.bits
.version
>= 0x10)
1660 reg_02
.raw
= io_apic_read(apic
, 2);
1661 if (reg_01
.bits
.version
>= 0x20)
1662 reg_03
.raw
= io_apic_read(apic
, 3);
1663 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1666 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1667 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1668 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1669 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1670 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1672 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1673 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1675 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1676 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1679 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1680 * but the value of reg_02 is read as the previous read register
1681 * value, so ignore it if reg_02 == reg_01.
1683 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1684 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1685 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1689 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1690 * or reg_03, but the value of reg_0[23] is read as the previous read
1691 * register value, so ignore it if reg_03 == reg_0[12].
1693 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1694 reg_03
.raw
!= reg_01
.raw
) {
1695 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1696 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1699 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1701 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1702 " Stat Dmod Deli Vect:\n");
1704 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1705 struct IO_APIC_route_entry entry
;
1707 entry
= ioapic_read_entry(apic
, i
);
1709 printk(KERN_DEBUG
" %02x %03X ",
1714 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1719 entry
.delivery_status
,
1721 entry
.delivery_mode
,
1726 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1727 for_each_irq_desc(irq
, desc
) {
1728 struct irq_pin_list
*entry
;
1730 cfg
= desc
->chip_data
;
1731 entry
= cfg
->irq_2_pin
;
1734 printk(KERN_DEBUG
"IRQ%d ", irq
);
1735 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1736 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1740 printk(KERN_INFO
".................................... done.\n");
1745 __apicdebuginit(void) print_APIC_field(int base
)
1751 for (i
= 0; i
< 8; i
++)
1752 printk(KERN_CONT
"%08x", apic_read(base
+ i
*0x10));
1754 printk(KERN_CONT
"\n");
1757 __apicdebuginit(void) print_local_APIC(void *dummy
)
1759 unsigned int i
, v
, ver
, maxlvt
;
1762 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1763 smp_processor_id(), hard_smp_processor_id());
1764 v
= apic_read(APIC_ID
);
1765 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1766 v
= apic_read(APIC_LVR
);
1767 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1768 ver
= GET_APIC_VERSION(v
);
1769 maxlvt
= lapic_get_maxlvt();
1771 v
= apic_read(APIC_TASKPRI
);
1772 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1774 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1775 if (!APIC_XAPIC(ver
)) {
1776 v
= apic_read(APIC_ARBPRI
);
1777 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1778 v
& APIC_ARBPRI_MASK
);
1780 v
= apic_read(APIC_PROCPRI
);
1781 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1785 * Remote read supported only in the 82489DX and local APIC for
1786 * Pentium processors.
1788 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1789 v
= apic_read(APIC_RRR
);
1790 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1793 v
= apic_read(APIC_LDR
);
1794 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1795 if (!x2apic_enabled()) {
1796 v
= apic_read(APIC_DFR
);
1797 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1799 v
= apic_read(APIC_SPIV
);
1800 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1802 printk(KERN_DEBUG
"... APIC ISR field:\n");
1803 print_APIC_field(APIC_ISR
);
1804 printk(KERN_DEBUG
"... APIC TMR field:\n");
1805 print_APIC_field(APIC_TMR
);
1806 printk(KERN_DEBUG
"... APIC IRR field:\n");
1807 print_APIC_field(APIC_IRR
);
1809 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1810 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1811 apic_write(APIC_ESR
, 0);
1813 v
= apic_read(APIC_ESR
);
1814 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1817 icr
= apic_icr_read();
1818 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1819 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1821 v
= apic_read(APIC_LVTT
);
1822 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1824 if (maxlvt
> 3) { /* PC is LVT#4. */
1825 v
= apic_read(APIC_LVTPC
);
1826 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1828 v
= apic_read(APIC_LVT0
);
1829 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1830 v
= apic_read(APIC_LVT1
);
1831 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1833 if (maxlvt
> 2) { /* ERR is LVT#3. */
1834 v
= apic_read(APIC_LVTERR
);
1835 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1838 v
= apic_read(APIC_TMICT
);
1839 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1840 v
= apic_read(APIC_TMCCT
);
1841 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1842 v
= apic_read(APIC_TDCR
);
1843 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1845 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1846 v
= apic_read(APIC_EFEAT
);
1847 maxlvt
= (v
>> 16) & 0xff;
1848 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1849 v
= apic_read(APIC_ECTRL
);
1850 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1851 for (i
= 0; i
< maxlvt
; i
++) {
1852 v
= apic_read(APIC_EILVTn(i
));
1853 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1859 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1867 for_each_online_cpu(cpu
) {
1870 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1875 __apicdebuginit(void) print_PIC(void)
1878 unsigned long flags
;
1880 if (!legacy_pic
->nr_legacy_irqs
)
1883 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1885 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1887 v
= inb(0xa1) << 8 | inb(0x21);
1888 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1890 v
= inb(0xa0) << 8 | inb(0x20);
1891 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1895 v
= inb(0xa0) << 8 | inb(0x20);
1899 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1901 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1903 v
= inb(0x4d1) << 8 | inb(0x4d0);
1904 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1907 static int __initdata show_lapic
= 1;
1908 static __init
int setup_show_lapic(char *arg
)
1912 if (strcmp(arg
, "all") == 0) {
1913 show_lapic
= CONFIG_NR_CPUS
;
1915 get_option(&arg
, &num
);
1922 __setup("show_lapic=", setup_show_lapic
);
1924 __apicdebuginit(int) print_ICs(void)
1926 if (apic_verbosity
== APIC_QUIET
)
1931 /* don't print out if apic is not there */
1932 if (!cpu_has_apic
&& !apic_from_smp_config())
1935 print_local_APICs(show_lapic
);
1941 fs_initcall(print_ICs
);
1944 /* Where if anywhere is the i8259 connect in external int mode */
1945 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1947 void __init
enable_IO_APIC(void)
1949 int i8259_apic
, i8259_pin
;
1952 if (!legacy_pic
->nr_legacy_irqs
)
1955 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1957 /* See if any of the pins is in ExtINT mode */
1958 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1959 struct IO_APIC_route_entry entry
;
1960 entry
= ioapic_read_entry(apic
, pin
);
1962 /* If the interrupt line is enabled and in ExtInt mode
1963 * I have found the pin where the i8259 is connected.
1965 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1966 ioapic_i8259
.apic
= apic
;
1967 ioapic_i8259
.pin
= pin
;
1973 /* Look to see what if the MP table has reported the ExtINT */
1974 /* If we could not find the appropriate pin by looking at the ioapic
1975 * the i8259 probably is not connected the ioapic but give the
1976 * mptable a chance anyway.
1978 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1979 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1980 /* Trust the MP table if nothing is setup in the hardware */
1981 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1982 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1983 ioapic_i8259
.pin
= i8259_pin
;
1984 ioapic_i8259
.apic
= i8259_apic
;
1986 /* Complain if the MP table and the hardware disagree */
1987 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1988 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1990 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1994 * Do not trust the IO-APIC being empty at bootup
2000 * Not an __init, needed by the reboot code
2002 void disable_IO_APIC(void)
2005 * Clear the IO-APIC before rebooting:
2009 if (!legacy_pic
->nr_legacy_irqs
)
2013 * If the i8259 is routed through an IOAPIC
2014 * Put that IOAPIC in virtual wire mode
2015 * so legacy interrupts can be delivered.
2017 * With interrupt-remapping, for now we will use virtual wire A mode,
2018 * as virtual wire B is little complex (need to configure both
2019 * IOAPIC RTE aswell as interrupt-remapping table entry).
2020 * As this gets called during crash dump, keep this simple for now.
2022 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
2023 struct IO_APIC_route_entry entry
;
2025 memset(&entry
, 0, sizeof(entry
));
2026 entry
.mask
= 0; /* Enabled */
2027 entry
.trigger
= 0; /* Edge */
2029 entry
.polarity
= 0; /* High */
2030 entry
.delivery_status
= 0;
2031 entry
.dest_mode
= 0; /* Physical */
2032 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2034 entry
.dest
= read_apic_id();
2037 * Add it to the IO-APIC irq-routing table:
2039 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2043 * Use virtual wire A mode when interrupt remapping is enabled.
2045 if (cpu_has_apic
|| apic_from_smp_config())
2046 disconnect_bsp_APIC(!intr_remapping_enabled
&&
2047 ioapic_i8259
.pin
!= -1);
2050 #ifdef CONFIG_X86_32
2052 * function to set the IO-APIC physical IDs based on the
2053 * values stored in the MPC table.
2055 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2058 void __init
setup_ioapic_ids_from_mpc(void)
2060 union IO_APIC_reg_00 reg_00
;
2061 physid_mask_t phys_id_present_map
;
2064 unsigned char old_id
;
2065 unsigned long flags
;
2070 * Don't check I/O APIC IDs for xAPIC systems. They have
2071 * no meaning without the serial APIC bus.
2073 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2074 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2077 * This is broken; anything with a real cpu count has to
2078 * circumvent this idiocy regardless.
2080 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
2083 * Set the IOAPIC ID to the value stored in the MPC table.
2085 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2087 /* Read the register 0 value */
2088 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2089 reg_00
.raw
= io_apic_read(apic_id
, 0);
2090 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2092 old_id
= mp_ioapics
[apic_id
].apicid
;
2094 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2095 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2096 apic_id
, mp_ioapics
[apic_id
].apicid
);
2097 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2099 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2103 * Sanity check, is the ID really free? Every APIC in a
2104 * system must have a unique ID or we get lots of nice
2105 * 'stuck on smp_invalidate_needed IPI wait' messages.
2107 if (apic
->check_apicid_used(&phys_id_present_map
,
2108 mp_ioapics
[apic_id
].apicid
)) {
2109 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2110 apic_id
, mp_ioapics
[apic_id
].apicid
);
2111 for (i
= 0; i
< get_physical_broadcast(); i
++)
2112 if (!physid_isset(i
, phys_id_present_map
))
2114 if (i
>= get_physical_broadcast())
2115 panic("Max APIC ID exceeded!\n");
2116 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2118 physid_set(i
, phys_id_present_map
);
2119 mp_ioapics
[apic_id
].apicid
= i
;
2122 apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
, &tmp
);
2123 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2124 "phys_id_present_map\n",
2125 mp_ioapics
[apic_id
].apicid
);
2126 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2131 * We need to adjust the IRQ routing table
2132 * if the ID changed.
2134 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2135 for (i
= 0; i
< mp_irq_entries
; i
++)
2136 if (mp_irqs
[i
].dstapic
== old_id
)
2138 = mp_ioapics
[apic_id
].apicid
;
2141 * Read the right value from the MPC table and
2142 * write it into the ID register.
2144 apic_printk(APIC_VERBOSE
, KERN_INFO
2145 "...changing IO-APIC physical APIC ID to %d ...",
2146 mp_ioapics
[apic_id
].apicid
);
2148 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2149 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2150 io_apic_write(apic_id
, 0, reg_00
.raw
);
2151 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2156 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2157 reg_00
.raw
= io_apic_read(apic_id
, 0);
2158 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2159 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2160 printk("could not set ID!\n");
2162 apic_printk(APIC_VERBOSE
, " ok.\n");
2167 int no_timer_check __initdata
;
2169 static int __init
notimercheck(char *s
)
2174 __setup("no_timer_check", notimercheck
);
2177 * There is a nasty bug in some older SMP boards, their mptable lies
2178 * about the timer IRQ. We do the following to work around the situation:
2180 * - timer IRQ defaults to IO-APIC IRQ
2181 * - if this function detects that timer IRQs are defunct, then we fall
2182 * back to ISA timer IRQs
2184 static int __init
timer_irq_works(void)
2186 unsigned long t1
= jiffies
;
2187 unsigned long flags
;
2192 local_save_flags(flags
);
2194 /* Let ten ticks pass... */
2195 mdelay((10 * 1000) / HZ
);
2196 local_irq_restore(flags
);
2199 * Expect a few ticks at least, to be sure some possible
2200 * glue logic does not lock up after one or two first
2201 * ticks in a non-ExtINT mode. Also the local APIC
2202 * might have cached one ExtINT interrupt. Finally, at
2203 * least one tick may be lost due to delays.
2207 if (time_after(jiffies
, t1
+ 4))
2213 * In the SMP+IOAPIC case it might happen that there are an unspecified
2214 * number of pending IRQ events unhandled. These cases are very rare,
2215 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2216 * better to do it this way as thus we do not have to be aware of
2217 * 'pending' interrupts in the IRQ path, except at this point.
2220 * Edge triggered needs to resend any interrupt
2221 * that was delayed but this is now handled in the device
2226 * Starting up a edge-triggered IO-APIC interrupt is
2227 * nasty - we need to make sure that we get the edge.
2228 * If it is already asserted for some reason, we need
2229 * return 1 to indicate that is was pending.
2231 * This is not complete - we should be able to fake
2232 * an edge even if it isn't on the 8259A...
2235 static unsigned int startup_ioapic_irq(unsigned int irq
)
2237 int was_pending
= 0;
2238 unsigned long flags
;
2239 struct irq_cfg
*cfg
;
2241 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2242 if (irq
< legacy_pic
->nr_legacy_irqs
) {
2243 legacy_pic
->chip
->mask(irq
);
2244 if (legacy_pic
->irq_pending(irq
))
2248 __unmask_IO_APIC_irq(cfg
);
2249 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2254 static int ioapic_retrigger_irq(unsigned int irq
)
2257 struct irq_cfg
*cfg
= irq_cfg(irq
);
2258 unsigned long flags
;
2260 raw_spin_lock_irqsave(&vector_lock
, flags
);
2261 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2262 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2268 * Level and edge triggered IO-APIC interrupts need different handling,
2269 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2270 * handled with the level-triggered descriptor, but that one has slightly
2271 * more overhead. Level-triggered interrupts cannot be handled with the
2272 * edge-triggered handler, without risking IRQ storms and other ugly
2277 void send_cleanup_vector(struct irq_cfg
*cfg
)
2279 cpumask_var_t cleanup_mask
;
2281 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2283 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2284 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2286 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2287 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2288 free_cpumask_var(cleanup_mask
);
2290 cfg
->move_in_progress
= 0;
2293 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2296 struct irq_pin_list
*entry
;
2297 u8 vector
= cfg
->vector
;
2299 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2305 * With interrupt-remapping, destination information comes
2306 * from interrupt-remapping table entry.
2308 if (!irq_remapped(irq
))
2309 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2310 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2311 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2313 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2318 * Either sets desc->affinity to a valid value, and returns
2319 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2320 * leaves desc->affinity untouched.
2323 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
,
2324 unsigned int *dest_id
)
2326 struct irq_cfg
*cfg
;
2329 if (!cpumask_intersects(mask
, cpu_online_mask
))
2333 cfg
= desc
->chip_data
;
2334 if (assign_irq_vector(irq
, cfg
, mask
))
2337 cpumask_copy(desc
->affinity
, mask
);
2339 *dest_id
= apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
2344 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2346 struct irq_cfg
*cfg
;
2347 unsigned long flags
;
2353 cfg
= desc
->chip_data
;
2355 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2356 ret
= set_desc_affinity(desc
, mask
, &dest
);
2358 /* Only the high 8 bits are valid. */
2359 dest
= SET_APIC_LOGICAL_ID(dest
);
2360 __target_IO_APIC_irq(irq
, dest
, cfg
);
2362 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2368 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
2370 struct irq_desc
*desc
;
2372 desc
= irq_to_desc(irq
);
2374 return set_ioapic_affinity_irq_desc(desc
, mask
);
2377 #ifdef CONFIG_INTR_REMAP
2380 * Migrate the IO-APIC irq in the presence of intr-remapping.
2382 * For both level and edge triggered, irq migration is a simple atomic
2383 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2385 * For level triggered, we eliminate the io-apic RTE modification (with the
2386 * updated vector information), by using a virtual vector (io-apic pin number).
2387 * Real vector that is used for interrupting cpu will be coming from
2388 * the interrupt-remapping table entry.
2391 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2393 struct irq_cfg
*cfg
;
2399 if (!cpumask_intersects(mask
, cpu_online_mask
))
2403 if (get_irte(irq
, &irte
))
2406 cfg
= desc
->chip_data
;
2407 if (assign_irq_vector(irq
, cfg
, mask
))
2410 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2412 irte
.vector
= cfg
->vector
;
2413 irte
.dest_id
= IRTE_DEST(dest
);
2416 * Modified the IRTE and flushes the Interrupt entry cache.
2418 modify_irte(irq
, &irte
);
2420 if (cfg
->move_in_progress
)
2421 send_cleanup_vector(cfg
);
2423 cpumask_copy(desc
->affinity
, mask
);
2429 * Migrates the IRQ destination in the process context.
2431 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2432 const struct cpumask
*mask
)
2434 return migrate_ioapic_irq_desc(desc
, mask
);
2436 static int set_ir_ioapic_affinity_irq(unsigned int irq
,
2437 const struct cpumask
*mask
)
2439 struct irq_desc
*desc
= irq_to_desc(irq
);
2441 return set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2444 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2445 const struct cpumask
*mask
)
2451 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2453 unsigned vector
, me
;
2459 me
= smp_processor_id();
2460 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2463 struct irq_desc
*desc
;
2464 struct irq_cfg
*cfg
;
2465 irq
= __get_cpu_var(vector_irq
)[vector
];
2470 desc
= irq_to_desc(irq
);
2475 raw_spin_lock(&desc
->lock
);
2478 * Check if the irq migration is in progress. If so, we
2479 * haven't received the cleanup request yet for this irq.
2481 if (cfg
->move_in_progress
)
2484 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2487 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2489 * Check if the vector that needs to be cleanedup is
2490 * registered at the cpu's IRR. If so, then this is not
2491 * the best time to clean it up. Lets clean it up in the
2492 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2495 if (irr
& (1 << (vector
% 32))) {
2496 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2499 __get_cpu_var(vector_irq
)[vector
] = -1;
2501 raw_spin_unlock(&desc
->lock
);
2507 static void __irq_complete_move(struct irq_desc
**descp
, unsigned vector
)
2509 struct irq_desc
*desc
= *descp
;
2510 struct irq_cfg
*cfg
= desc
->chip_data
;
2513 if (likely(!cfg
->move_in_progress
))
2516 me
= smp_processor_id();
2518 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2519 send_cleanup_vector(cfg
);
2522 static void irq_complete_move(struct irq_desc
**descp
)
2524 __irq_complete_move(descp
, ~get_irq_regs()->orig_ax
);
2527 void irq_force_complete_move(int irq
)
2529 struct irq_desc
*desc
= irq_to_desc(irq
);
2530 struct irq_cfg
*cfg
= desc
->chip_data
;
2535 __irq_complete_move(&desc
, cfg
->vector
);
2538 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2541 static void ack_apic_edge(unsigned int irq
)
2543 struct irq_desc
*desc
= irq_to_desc(irq
);
2545 irq_complete_move(&desc
);
2546 move_native_irq(irq
);
2550 atomic_t irq_mis_count
;
2553 * IO-APIC versions below 0x20 don't support EOI register.
2554 * For the record, here is the information about various versions:
2556 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2557 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2560 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2561 * version as 0x2. This is an error with documentation and these ICH chips
2562 * use io-apic's of version 0x20.
2564 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2565 * Otherwise, we simulate the EOI message manually by changing the trigger
2566 * mode to edge and then back to level, with RTE being masked during this.
2568 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2570 struct irq_pin_list
*entry
;
2572 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2573 if (mp_ioapics
[entry
->apic
].apicver
>= 0x20) {
2575 * Intr-remapping uses pin number as the virtual vector
2576 * in the RTE. Actual vector is programmed in
2577 * intr-remapping table entry. Hence for the io-apic
2578 * EOI we use the pin number.
2580 if (irq_remapped(irq
))
2581 io_apic_eoi(entry
->apic
, entry
->pin
);
2583 io_apic_eoi(entry
->apic
, cfg
->vector
);
2585 __mask_and_edge_IO_APIC_irq(entry
);
2586 __unmask_and_level_IO_APIC_irq(entry
);
2591 static void eoi_ioapic_irq(struct irq_desc
*desc
)
2593 struct irq_cfg
*cfg
;
2594 unsigned long flags
;
2598 cfg
= desc
->chip_data
;
2600 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2601 __eoi_ioapic_irq(irq
, cfg
);
2602 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2605 static void ack_apic_level(unsigned int irq
)
2607 struct irq_desc
*desc
= irq_to_desc(irq
);
2610 struct irq_cfg
*cfg
;
2611 int do_unmask_irq
= 0;
2613 irq_complete_move(&desc
);
2614 #ifdef CONFIG_GENERIC_PENDING_IRQ
2615 /* If we are moving the irq we need to mask it */
2616 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2618 mask_IO_APIC_irq_desc(desc
);
2623 * It appears there is an erratum which affects at least version 0x11
2624 * of I/O APIC (that's the 82093AA and cores integrated into various
2625 * chipsets). Under certain conditions a level-triggered interrupt is
2626 * erroneously delivered as edge-triggered one but the respective IRR
2627 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2628 * message but it will never arrive and further interrupts are blocked
2629 * from the source. The exact reason is so far unknown, but the
2630 * phenomenon was observed when two consecutive interrupt requests
2631 * from a given source get delivered to the same CPU and the source is
2632 * temporarily disabled in between.
2634 * A workaround is to simulate an EOI message manually. We achieve it
2635 * by setting the trigger mode to edge and then to level when the edge
2636 * trigger mode gets detected in the TMR of a local APIC for a
2637 * level-triggered interrupt. We mask the source for the time of the
2638 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2639 * The idea is from Manfred Spraul. --macro
2641 * Also in the case when cpu goes offline, fixup_irqs() will forward
2642 * any unhandled interrupt on the offlined cpu to the new cpu
2643 * destination that is handling the corresponding interrupt. This
2644 * interrupt forwarding is done via IPI's. Hence, in this case also
2645 * level-triggered io-apic interrupt will be seen as an edge
2646 * interrupt in the IRR. And we can't rely on the cpu's EOI
2647 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2648 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2649 * supporting EOI register, we do an explicit EOI to clear the
2650 * remote IRR and on IO-APIC's which don't have an EOI register,
2651 * we use the above logic (mask+edge followed by unmask+level) from
2652 * Manfred Spraul to clear the remote IRR.
2654 cfg
= desc
->chip_data
;
2656 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2659 * We must acknowledge the irq before we move it or the acknowledge will
2660 * not propagate properly.
2665 * Tail end of clearing remote IRR bit (either by delivering the EOI
2666 * message via io-apic EOI register write or simulating it using
2667 * mask+edge followed by unnask+level logic) manually when the
2668 * level triggered interrupt is seen as the edge triggered interrupt
2671 if (!(v
& (1 << (i
& 0x1f)))) {
2672 atomic_inc(&irq_mis_count
);
2674 eoi_ioapic_irq(desc
);
2677 /* Now we can move and renable the irq */
2678 if (unlikely(do_unmask_irq
)) {
2679 /* Only migrate the irq if the ack has been received.
2681 * On rare occasions the broadcast level triggered ack gets
2682 * delayed going to ioapics, and if we reprogram the
2683 * vector while Remote IRR is still set the irq will never
2686 * To prevent this scenario we read the Remote IRR bit
2687 * of the ioapic. This has two effects.
2688 * - On any sane system the read of the ioapic will
2689 * flush writes (and acks) going to the ioapic from
2691 * - We get to see if the ACK has actually been delivered.
2693 * Based on failed experiments of reprogramming the
2694 * ioapic entry from outside of irq context starting
2695 * with masking the ioapic entry and then polling until
2696 * Remote IRR was clear before reprogramming the
2697 * ioapic I don't trust the Remote IRR bit to be
2698 * completey accurate.
2700 * However there appears to be no other way to plug
2701 * this race, so if the Remote IRR bit is not
2702 * accurate and is causing problems then it is a hardware bug
2703 * and you can go talk to the chipset vendor about it.
2705 cfg
= desc
->chip_data
;
2706 if (!io_apic_level_ack_pending(cfg
))
2707 move_masked_irq(irq
);
2708 unmask_IO_APIC_irq_desc(desc
);
2712 #ifdef CONFIG_INTR_REMAP
2713 static void ir_ack_apic_edge(unsigned int irq
)
2718 static void ir_ack_apic_level(unsigned int irq
)
2720 struct irq_desc
*desc
= irq_to_desc(irq
);
2723 eoi_ioapic_irq(desc
);
2725 #endif /* CONFIG_INTR_REMAP */
2727 static struct irq_chip ioapic_chip __read_mostly
= {
2729 .startup
= startup_ioapic_irq
,
2730 .mask
= mask_IO_APIC_irq
,
2731 .unmask
= unmask_IO_APIC_irq
,
2732 .ack
= ack_apic_edge
,
2733 .eoi
= ack_apic_level
,
2735 .set_affinity
= set_ioapic_affinity_irq
,
2737 .retrigger
= ioapic_retrigger_irq
,
2740 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2741 .name
= "IR-IO-APIC",
2742 .startup
= startup_ioapic_irq
,
2743 .mask
= mask_IO_APIC_irq
,
2744 .unmask
= unmask_IO_APIC_irq
,
2745 #ifdef CONFIG_INTR_REMAP
2746 .ack
= ir_ack_apic_edge
,
2747 .eoi
= ir_ack_apic_level
,
2749 .set_affinity
= set_ir_ioapic_affinity_irq
,
2752 .retrigger
= ioapic_retrigger_irq
,
2755 static inline void init_IO_APIC_traps(void)
2758 struct irq_desc
*desc
;
2759 struct irq_cfg
*cfg
;
2762 * NOTE! The local APIC isn't very good at handling
2763 * multiple interrupts at the same interrupt level.
2764 * As the interrupt level is determined by taking the
2765 * vector number and shifting that right by 4, we
2766 * want to spread these out a bit so that they don't
2767 * all fall in the same interrupt level.
2769 * Also, we've got to be careful not to trash gate
2770 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2772 for_each_irq_desc(irq
, desc
) {
2773 cfg
= desc
->chip_data
;
2774 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2776 * Hmm.. We don't have an entry for this,
2777 * so default to an old-fashioned 8259
2778 * interrupt if we can..
2780 if (irq
< legacy_pic
->nr_legacy_irqs
)
2781 legacy_pic
->make_irq(irq
);
2783 /* Strange. Oh, well.. */
2784 desc
->chip
= &no_irq_chip
;
2790 * The local APIC irq-chip implementation:
2793 static void mask_lapic_irq(unsigned int irq
)
2797 v
= apic_read(APIC_LVT0
);
2798 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2801 static void unmask_lapic_irq(unsigned int irq
)
2805 v
= apic_read(APIC_LVT0
);
2806 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2809 static void ack_lapic_irq(unsigned int irq
)
2814 static struct irq_chip lapic_chip __read_mostly
= {
2815 .name
= "local-APIC",
2816 .mask
= mask_lapic_irq
,
2817 .unmask
= unmask_lapic_irq
,
2818 .ack
= ack_lapic_irq
,
2821 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2823 desc
->status
&= ~IRQ_LEVEL
;
2824 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2828 static void __init
setup_nmi(void)
2831 * Dirty trick to enable the NMI watchdog ...
2832 * We put the 8259A master into AEOI mode and
2833 * unmask on all local APICs LVT0 as NMI.
2835 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2836 * is from Maciej W. Rozycki - so we do not have to EOI from
2837 * the NMI handler or the timer interrupt.
2839 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2841 enable_NMI_through_LVT0();
2843 apic_printk(APIC_VERBOSE
, " done.\n");
2847 * This looks a bit hackish but it's about the only one way of sending
2848 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2849 * not support the ExtINT mode, unfortunately. We need to send these
2850 * cycles as some i82489DX-based boards have glue logic that keeps the
2851 * 8259A interrupt line asserted until INTA. --macro
2853 static inline void __init
unlock_ExtINT_logic(void)
2856 struct IO_APIC_route_entry entry0
, entry1
;
2857 unsigned char save_control
, save_freq_select
;
2859 pin
= find_isa_irq_pin(8, mp_INT
);
2864 apic
= find_isa_irq_apic(8, mp_INT
);
2870 entry0
= ioapic_read_entry(apic
, pin
);
2871 clear_IO_APIC_pin(apic
, pin
);
2873 memset(&entry1
, 0, sizeof(entry1
));
2875 entry1
.dest_mode
= 0; /* physical delivery */
2876 entry1
.mask
= 0; /* unmask IRQ now */
2877 entry1
.dest
= hard_smp_processor_id();
2878 entry1
.delivery_mode
= dest_ExtINT
;
2879 entry1
.polarity
= entry0
.polarity
;
2883 ioapic_write_entry(apic
, pin
, entry1
);
2885 save_control
= CMOS_READ(RTC_CONTROL
);
2886 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2887 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2889 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2894 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2898 CMOS_WRITE(save_control
, RTC_CONTROL
);
2899 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2900 clear_IO_APIC_pin(apic
, pin
);
2902 ioapic_write_entry(apic
, pin
, entry0
);
2905 static int disable_timer_pin_1 __initdata
;
2906 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2907 static int __init
disable_timer_pin_setup(char *arg
)
2909 disable_timer_pin_1
= 1;
2912 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2914 int timer_through_8259 __initdata
;
2917 * This code may look a bit paranoid, but it's supposed to cooperate with
2918 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2919 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2920 * fanatically on his truly buggy board.
2922 * FIXME: really need to revamp this for all platforms.
2924 static inline void __init
check_timer(void)
2926 struct irq_desc
*desc
= irq_to_desc(0);
2927 struct irq_cfg
*cfg
= desc
->chip_data
;
2928 int node
= cpu_to_node(boot_cpu_id
);
2929 int apic1
, pin1
, apic2
, pin2
;
2930 unsigned long flags
;
2933 local_irq_save(flags
);
2936 * get/set the timer IRQ vector:
2938 legacy_pic
->chip
->mask(0);
2939 assign_irq_vector(0, cfg
, apic
->target_cpus());
2942 * As IRQ0 is to be enabled in the 8259A, the virtual
2943 * wire has to be disabled in the local APIC. Also
2944 * timer interrupts need to be acknowledged manually in
2945 * the 8259A for the i82489DX when using the NMI
2946 * watchdog as that APIC treats NMIs as level-triggered.
2947 * The AEOI mode will finish them in the 8259A
2950 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2951 legacy_pic
->init(1);
2952 #ifdef CONFIG_X86_32
2956 ver
= apic_read(APIC_LVR
);
2957 ver
= GET_APIC_VERSION(ver
);
2958 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2962 pin1
= find_isa_irq_pin(0, mp_INT
);
2963 apic1
= find_isa_irq_apic(0, mp_INT
);
2964 pin2
= ioapic_i8259
.pin
;
2965 apic2
= ioapic_i8259
.apic
;
2967 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2968 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2969 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2972 * Some BIOS writers are clueless and report the ExtINTA
2973 * I/O APIC input from the cascaded 8259A as the timer
2974 * interrupt input. So just in case, if only one pin
2975 * was found above, try it both directly and through the
2979 if (intr_remapping_enabled
)
2980 panic("BIOS bug: timer not connected to IO-APIC");
2984 } else if (pin2
== -1) {
2991 * Ok, does IRQ0 through the IOAPIC work?
2994 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2995 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2997 /* for edge trigger, setup_IO_APIC_irq already
2998 * leave it unmasked.
2999 * so only need to unmask if it is level-trigger
3000 * do we really have level trigger timer?
3003 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
3004 if (idx
!= -1 && irq_trigger(idx
))
3005 unmask_IO_APIC_irq_desc(desc
);
3007 if (timer_irq_works()) {
3008 if (nmi_watchdog
== NMI_IO_APIC
) {
3010 legacy_pic
->chip
->unmask(0);
3012 if (disable_timer_pin_1
> 0)
3013 clear_IO_APIC_pin(0, pin1
);
3016 if (intr_remapping_enabled
)
3017 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3018 local_irq_disable();
3019 clear_IO_APIC_pin(apic1
, pin1
);
3021 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
3022 "8254 timer not connected to IO-APIC\n");
3024 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
3025 "(IRQ0) through the 8259A ...\n");
3026 apic_printk(APIC_QUIET
, KERN_INFO
3027 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
3029 * legacy devices should be connected to IO APIC #0
3031 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
3032 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
3033 legacy_pic
->chip
->unmask(0);
3034 if (timer_irq_works()) {
3035 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
3036 timer_through_8259
= 1;
3037 if (nmi_watchdog
== NMI_IO_APIC
) {
3038 legacy_pic
->chip
->mask(0);
3040 legacy_pic
->chip
->unmask(0);
3045 * Cleanup, just in case ...
3047 local_irq_disable();
3048 legacy_pic
->chip
->mask(0);
3049 clear_IO_APIC_pin(apic2
, pin2
);
3050 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
3053 if (nmi_watchdog
== NMI_IO_APIC
) {
3054 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
3055 "through the IO-APIC - disabling NMI Watchdog!\n");
3056 nmi_watchdog
= NMI_NONE
;
3058 #ifdef CONFIG_X86_32
3062 apic_printk(APIC_QUIET
, KERN_INFO
3063 "...trying to set up timer as Virtual Wire IRQ...\n");
3065 lapic_register_intr(0, desc
);
3066 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
3067 legacy_pic
->chip
->unmask(0);
3069 if (timer_irq_works()) {
3070 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3073 local_irq_disable();
3074 legacy_pic
->chip
->mask(0);
3075 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3076 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3078 apic_printk(APIC_QUIET
, KERN_INFO
3079 "...trying to set up timer as ExtINT IRQ...\n");
3081 legacy_pic
->init(0);
3082 legacy_pic
->make_irq(0);
3083 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3085 unlock_ExtINT_logic();
3087 if (timer_irq_works()) {
3088 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3091 local_irq_disable();
3092 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3093 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3094 "report. Then try booting with the 'noapic' option.\n");
3096 local_irq_restore(flags
);
3100 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3101 * to devices. However there may be an I/O APIC pin available for
3102 * this interrupt regardless. The pin may be left unconnected, but
3103 * typically it will be reused as an ExtINT cascade interrupt for
3104 * the master 8259A. In the MPS case such a pin will normally be
3105 * reported as an ExtINT interrupt in the MP table. With ACPI
3106 * there is no provision for ExtINT interrupts, and in the absence
3107 * of an override it would be treated as an ordinary ISA I/O APIC
3108 * interrupt, that is edge-triggered and unmasked by default. We
3109 * used to do this, but it caused problems on some systems because
3110 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3111 * the same ExtINT cascade interrupt to drive the local APIC of the
3112 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3113 * the I/O APIC in all cases now. No actual device should request
3114 * it anyway. --macro
3116 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3118 void __init
setup_IO_APIC(void)
3122 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3124 io_apic_irqs
= legacy_pic
->nr_legacy_irqs
? ~PIC_IRQS
: ~0UL;
3126 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3128 * Set up IO-APIC IRQ routing.
3130 x86_init
.mpparse
.setup_ioapic_ids();
3133 setup_IO_APIC_irqs();
3134 init_IO_APIC_traps();
3135 if (legacy_pic
->nr_legacy_irqs
)
3140 * Called after all the initialization is done. If we didnt find any
3141 * APIC bugs then we can allow the modify fast path
3144 static int __init
io_apic_bug_finalize(void)
3146 if (sis_apic_bug
== -1)
3151 late_initcall(io_apic_bug_finalize
);
3153 struct sysfs_ioapic_data
{
3154 struct sys_device dev
;
3155 struct IO_APIC_route_entry entry
[0];
3157 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3159 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3161 struct IO_APIC_route_entry
*entry
;
3162 struct sysfs_ioapic_data
*data
;
3165 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3166 entry
= data
->entry
;
3167 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3168 *entry
= ioapic_read_entry(dev
->id
, i
);
3173 static int ioapic_resume(struct sys_device
*dev
)
3175 struct IO_APIC_route_entry
*entry
;
3176 struct sysfs_ioapic_data
*data
;
3177 unsigned long flags
;
3178 union IO_APIC_reg_00 reg_00
;
3181 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3182 entry
= data
->entry
;
3184 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3185 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3186 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3187 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3188 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3190 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3191 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3192 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3197 static struct sysdev_class ioapic_sysdev_class
= {
3199 .suspend
= ioapic_suspend
,
3200 .resume
= ioapic_resume
,
3203 static int __init
ioapic_init_sysfs(void)
3205 struct sys_device
* dev
;
3208 error
= sysdev_class_register(&ioapic_sysdev_class
);
3212 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3213 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3214 * sizeof(struct IO_APIC_route_entry
);
3215 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3216 if (!mp_ioapic_data
[i
]) {
3217 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3220 dev
= &mp_ioapic_data
[i
]->dev
;
3222 dev
->cls
= &ioapic_sysdev_class
;
3223 error
= sysdev_register(dev
);
3225 kfree(mp_ioapic_data
[i
]);
3226 mp_ioapic_data
[i
] = NULL
;
3227 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3235 device_initcall(ioapic_init_sysfs
);
3238 * Dynamic irq allocate and deallocation
3240 unsigned int create_irq_nr(unsigned int irq_want
, int node
)
3242 /* Allocate an unused irq */
3245 unsigned long flags
;
3246 struct irq_cfg
*cfg_new
= NULL
;
3247 struct irq_desc
*desc_new
= NULL
;
3250 if (irq_want
< nr_irqs_gsi
)
3251 irq_want
= nr_irqs_gsi
;
3253 raw_spin_lock_irqsave(&vector_lock
, flags
);
3254 for (new = irq_want
; new < nr_irqs
; new++) {
3255 desc_new
= irq_to_desc_alloc_node(new, node
);
3257 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3260 cfg_new
= desc_new
->chip_data
;
3262 if (cfg_new
->vector
!= 0)
3265 desc_new
= move_irq_desc(desc_new
, node
);
3266 cfg_new
= desc_new
->chip_data
;
3268 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3272 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3275 dynamic_irq_init_keep_chip_data(irq
);
3280 int create_irq(void)
3282 int node
= cpu_to_node(boot_cpu_id
);
3283 unsigned int irq_want
;
3286 irq_want
= nr_irqs_gsi
;
3287 irq
= create_irq_nr(irq_want
, node
);
3295 void destroy_irq(unsigned int irq
)
3297 unsigned long flags
;
3299 dynamic_irq_cleanup_keep_chip_data(irq
);
3302 raw_spin_lock_irqsave(&vector_lock
, flags
);
3303 __clear_irq_vector(irq
, get_irq_chip_data(irq
));
3304 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3308 * MSI message composition
3310 #ifdef CONFIG_PCI_MSI
3311 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
3312 struct msi_msg
*msg
, u8 hpet_id
)
3314 struct irq_cfg
*cfg
;
3322 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3326 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3328 if (irq_remapped(irq
)) {
3333 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3334 BUG_ON(ir_index
== -1);
3336 memset (&irte
, 0, sizeof(irte
));
3339 irte
.dst_mode
= apic
->irq_dest_mode
;
3340 irte
.trigger_mode
= 0; /* edge */
3341 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
3342 irte
.vector
= cfg
->vector
;
3343 irte
.dest_id
= IRTE_DEST(dest
);
3345 /* Set source-id of interrupt request */
3347 set_msi_sid(&irte
, pdev
);
3349 set_hpet_sid(&irte
, hpet_id
);
3351 modify_irte(irq
, &irte
);
3353 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3354 msg
->data
= sub_handle
;
3355 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3357 MSI_ADDR_IR_INDEX1(ir_index
) |
3358 MSI_ADDR_IR_INDEX2(ir_index
);
3360 if (x2apic_enabled())
3361 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3362 MSI_ADDR_EXT_DEST_ID(dest
);
3364 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3368 ((apic
->irq_dest_mode
== 0) ?
3369 MSI_ADDR_DEST_MODE_PHYSICAL
:
3370 MSI_ADDR_DEST_MODE_LOGICAL
) |
3371 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3372 MSI_ADDR_REDIRECTION_CPU
:
3373 MSI_ADDR_REDIRECTION_LOWPRI
) |
3374 MSI_ADDR_DEST_ID(dest
);
3377 MSI_DATA_TRIGGER_EDGE
|
3378 MSI_DATA_LEVEL_ASSERT
|
3379 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3380 MSI_DATA_DELIVERY_FIXED
:
3381 MSI_DATA_DELIVERY_LOWPRI
) |
3382 MSI_DATA_VECTOR(cfg
->vector
);
3388 static int set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3390 struct irq_desc
*desc
= irq_to_desc(irq
);
3391 struct irq_cfg
*cfg
;
3395 if (set_desc_affinity(desc
, mask
, &dest
))
3398 cfg
= desc
->chip_data
;
3400 read_msi_msg_desc(desc
, &msg
);
3402 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3403 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3404 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3405 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3407 write_msi_msg_desc(desc
, &msg
);
3411 #ifdef CONFIG_INTR_REMAP
3413 * Migrate the MSI irq to another cpumask. This migration is
3414 * done in the process context using interrupt-remapping hardware.
3417 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3419 struct irq_desc
*desc
= irq_to_desc(irq
);
3420 struct irq_cfg
*cfg
= desc
->chip_data
;
3424 if (get_irte(irq
, &irte
))
3427 if (set_desc_affinity(desc
, mask
, &dest
))
3430 irte
.vector
= cfg
->vector
;
3431 irte
.dest_id
= IRTE_DEST(dest
);
3434 * atomically update the IRTE with the new destination and vector.
3436 modify_irte(irq
, &irte
);
3439 * After this point, all the interrupts will start arriving
3440 * at the new destination. So, time to cleanup the previous
3441 * vector allocation.
3443 if (cfg
->move_in_progress
)
3444 send_cleanup_vector(cfg
);
3450 #endif /* CONFIG_SMP */
3453 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3454 * which implement the MSI or MSI-X Capability Structure.
3456 static struct irq_chip msi_chip
= {
3458 .unmask
= unmask_msi_irq
,
3459 .mask
= mask_msi_irq
,
3460 .ack
= ack_apic_edge
,
3462 .set_affinity
= set_msi_irq_affinity
,
3464 .retrigger
= ioapic_retrigger_irq
,
3467 static struct irq_chip msi_ir_chip
= {
3468 .name
= "IR-PCI-MSI",
3469 .unmask
= unmask_msi_irq
,
3470 .mask
= mask_msi_irq
,
3471 #ifdef CONFIG_INTR_REMAP
3472 .ack
= ir_ack_apic_edge
,
3474 .set_affinity
= ir_set_msi_irq_affinity
,
3477 .retrigger
= ioapic_retrigger_irq
,
3481 * Map the PCI dev to the corresponding remapping hardware unit
3482 * and allocate 'nvec' consecutive interrupt-remapping table entries
3485 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3487 struct intel_iommu
*iommu
;
3490 iommu
= map_dev_to_ir(dev
);
3493 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3497 index
= alloc_irte(iommu
, irq
, nvec
);
3500 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3507 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3512 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3516 set_irq_msi(irq
, msidesc
);
3517 write_msi_msg(irq
, &msg
);
3519 if (irq_remapped(irq
)) {
3520 struct irq_desc
*desc
= irq_to_desc(irq
);
3522 * irq migration in process context
3524 desc
->status
|= IRQ_MOVE_PCNTXT
;
3525 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3527 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3529 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3534 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3537 int ret
, sub_handle
;
3538 struct msi_desc
*msidesc
;
3539 unsigned int irq_want
;
3540 struct intel_iommu
*iommu
= NULL
;
3544 /* x86 doesn't support multiple MSI yet */
3545 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3548 node
= dev_to_node(&dev
->dev
);
3549 irq_want
= nr_irqs_gsi
;
3551 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3552 irq
= create_irq_nr(irq_want
, node
);
3556 if (!intr_remapping_enabled
)
3561 * allocate the consecutive block of IRTE's
3564 index
= msi_alloc_irte(dev
, irq
, nvec
);
3570 iommu
= map_dev_to_ir(dev
);
3576 * setup the mapping between the irq and the IRTE
3577 * base index, the sub_handle pointing to the
3578 * appropriate interrupt remap table entry.
3580 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3583 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3595 void arch_teardown_msi_irq(unsigned int irq
)
3600 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3602 static int dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3604 struct irq_desc
*desc
= irq_to_desc(irq
);
3605 struct irq_cfg
*cfg
;
3609 if (set_desc_affinity(desc
, mask
, &dest
))
3612 cfg
= desc
->chip_data
;
3614 dmar_msi_read(irq
, &msg
);
3616 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3617 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3618 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3619 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3621 dmar_msi_write(irq
, &msg
);
3626 #endif /* CONFIG_SMP */
3628 static struct irq_chip dmar_msi_type
= {
3630 .unmask
= dmar_msi_unmask
,
3631 .mask
= dmar_msi_mask
,
3632 .ack
= ack_apic_edge
,
3634 .set_affinity
= dmar_msi_set_affinity
,
3636 .retrigger
= ioapic_retrigger_irq
,
3639 int arch_setup_dmar_msi(unsigned int irq
)
3644 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3647 dmar_msi_write(irq
, &msg
);
3648 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3654 #ifdef CONFIG_HPET_TIMER
3657 static int hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3659 struct irq_desc
*desc
= irq_to_desc(irq
);
3660 struct irq_cfg
*cfg
;
3664 if (set_desc_affinity(desc
, mask
, &dest
))
3667 cfg
= desc
->chip_data
;
3669 hpet_msi_read(irq
, &msg
);
3671 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3672 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3673 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3674 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3676 hpet_msi_write(irq
, &msg
);
3681 #endif /* CONFIG_SMP */
3683 static struct irq_chip ir_hpet_msi_type
= {
3684 .name
= "IR-HPET_MSI",
3685 .unmask
= hpet_msi_unmask
,
3686 .mask
= hpet_msi_mask
,
3687 #ifdef CONFIG_INTR_REMAP
3688 .ack
= ir_ack_apic_edge
,
3690 .set_affinity
= ir_set_msi_irq_affinity
,
3693 .retrigger
= ioapic_retrigger_irq
,
3696 static struct irq_chip hpet_msi_type
= {
3698 .unmask
= hpet_msi_unmask
,
3699 .mask
= hpet_msi_mask
,
3700 .ack
= ack_apic_edge
,
3702 .set_affinity
= hpet_msi_set_affinity
,
3704 .retrigger
= ioapic_retrigger_irq
,
3707 int arch_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3711 struct irq_desc
*desc
= irq_to_desc(irq
);
3713 if (intr_remapping_enabled
) {
3714 struct intel_iommu
*iommu
= map_hpet_to_ir(id
);
3720 index
= alloc_irte(iommu
, irq
, 1);
3725 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3729 hpet_msi_write(irq
, &msg
);
3730 desc
->status
|= IRQ_MOVE_PCNTXT
;
3731 if (irq_remapped(irq
))
3732 set_irq_chip_and_handler_name(irq
, &ir_hpet_msi_type
,
3733 handle_edge_irq
, "edge");
3735 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
,
3736 handle_edge_irq
, "edge");
3742 #endif /* CONFIG_PCI_MSI */
3744 * Hypertransport interrupt support
3746 #ifdef CONFIG_HT_IRQ
3750 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3752 struct ht_irq_msg msg
;
3753 fetch_ht_irq_msg(irq
, &msg
);
3755 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3756 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3758 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3759 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3761 write_ht_irq_msg(irq
, &msg
);
3764 static int set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3766 struct irq_desc
*desc
= irq_to_desc(irq
);
3767 struct irq_cfg
*cfg
;
3770 if (set_desc_affinity(desc
, mask
, &dest
))
3773 cfg
= desc
->chip_data
;
3775 target_ht_irq(irq
, dest
, cfg
->vector
);
3782 static struct irq_chip ht_irq_chip
= {
3784 .mask
= mask_ht_irq
,
3785 .unmask
= unmask_ht_irq
,
3786 .ack
= ack_apic_edge
,
3788 .set_affinity
= set_ht_irq_affinity
,
3790 .retrigger
= ioapic_retrigger_irq
,
3793 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3795 struct irq_cfg
*cfg
;
3802 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3804 struct ht_irq_msg msg
;
3807 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3808 apic
->target_cpus());
3810 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3814 HT_IRQ_LOW_DEST_ID(dest
) |
3815 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3816 ((apic
->irq_dest_mode
== 0) ?
3817 HT_IRQ_LOW_DM_PHYSICAL
:
3818 HT_IRQ_LOW_DM_LOGICAL
) |
3819 HT_IRQ_LOW_RQEOI_EDGE
|
3820 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3821 HT_IRQ_LOW_MT_FIXED
:
3822 HT_IRQ_LOW_MT_ARBITRATED
) |
3823 HT_IRQ_LOW_IRQ_MASKED
;
3825 write_ht_irq_msg(irq
, &msg
);
3827 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3828 handle_edge_irq
, "edge");
3830 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3834 #endif /* CONFIG_HT_IRQ */
3836 int __init
io_apic_get_redir_entries (int ioapic
)
3838 union IO_APIC_reg_01 reg_01
;
3839 unsigned long flags
;
3841 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3842 reg_01
.raw
= io_apic_read(ioapic
, 1);
3843 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3845 /* The register returns the maximum index redir index
3846 * supported, which is one less than the total number of redir
3849 return reg_01
.bits
.entries
+ 1;
3852 void __init
probe_nr_irqs_gsi(void)
3856 nr
= gsi_top
+ NR_IRQS_LEGACY
;
3857 if (nr
> nr_irqs_gsi
)
3860 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3863 #ifdef CONFIG_SPARSE_IRQ
3864 int __init
arch_probe_nr_irqs(void)
3868 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3869 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3871 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3872 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3874 * for MSI and HT dyn irq
3876 nr
+= nr_irqs_gsi
* 16;
3885 static int __io_apic_set_pci_routing(struct device
*dev
, int irq
,
3886 struct io_apic_irq_attr
*irq_attr
)
3888 struct irq_desc
*desc
;
3889 struct irq_cfg
*cfg
;
3892 int trigger
, polarity
;
3894 ioapic
= irq_attr
->ioapic
;
3895 if (!IO_APIC_IRQ(irq
)) {
3896 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3902 node
= dev_to_node(dev
);
3904 node
= cpu_to_node(boot_cpu_id
);
3906 desc
= irq_to_desc_alloc_node(irq
, node
);
3908 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3912 pin
= irq_attr
->ioapic_pin
;
3913 trigger
= irq_attr
->trigger
;
3914 polarity
= irq_attr
->polarity
;
3917 * IRQs < 16 are already in the irq_2_pin[] map
3919 if (irq
>= legacy_pic
->nr_legacy_irqs
) {
3920 cfg
= desc
->chip_data
;
3921 if (add_pin_to_irq_node_nopanic(cfg
, node
, ioapic
, pin
)) {
3922 printk(KERN_INFO
"can not add pin %d for irq %d\n",
3928 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, trigger
, polarity
);
3933 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3934 struct io_apic_irq_attr
*irq_attr
)
3938 * Avoid pin reprogramming. PRTs typically include entries
3939 * with redundant pin->gsi mappings (but unique PCI devices);
3940 * we only program the IOAPIC on the first.
3942 ioapic
= irq_attr
->ioapic
;
3943 pin
= irq_attr
->ioapic_pin
;
3944 if (test_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
)) {
3945 pr_debug("Pin %d-%d already programmed\n",
3946 mp_ioapics
[ioapic
].apicid
, pin
);
3949 set_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
);
3951 return __io_apic_set_pci_routing(dev
, irq
, irq_attr
);
3954 u8 __init
io_apic_unique_id(u8 id
)
3956 #ifdef CONFIG_X86_32
3957 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3958 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3959 return io_apic_get_unique_id(nr_ioapics
, id
);
3964 DECLARE_BITMAP(used
, 256);
3966 bitmap_zero(used
, 256);
3967 for (i
= 0; i
< nr_ioapics
; i
++) {
3968 struct mpc_ioapic
*ia
= &mp_ioapics
[i
];
3969 __set_bit(ia
->apicid
, used
);
3971 if (!test_bit(id
, used
))
3973 return find_first_zero_bit(used
, 256);
3977 #ifdef CONFIG_X86_32
3978 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3980 union IO_APIC_reg_00 reg_00
;
3981 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3983 unsigned long flags
;
3987 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3988 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3989 * supports up to 16 on one shared APIC bus.
3991 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3992 * advantage of new APIC bus architecture.
3995 if (physids_empty(apic_id_map
))
3996 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
3998 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3999 reg_00
.raw
= io_apic_read(ioapic
, 0);
4000 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
4002 if (apic_id
>= get_physical_broadcast()) {
4003 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
4004 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
4005 apic_id
= reg_00
.bits
.ID
;
4009 * Every APIC in a system must have a unique ID or we get lots of nice
4010 * 'stuck on smp_invalidate_needed IPI wait' messages.
4012 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
4014 for (i
= 0; i
< get_physical_broadcast(); i
++) {
4015 if (!apic
->check_apicid_used(&apic_id_map
, i
))
4019 if (i
== get_physical_broadcast())
4020 panic("Max apic_id exceeded!\n");
4022 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
4023 "trying %d\n", ioapic
, apic_id
, i
);
4028 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
4029 physids_or(apic_id_map
, apic_id_map
, tmp
);
4031 if (reg_00
.bits
.ID
!= apic_id
) {
4032 reg_00
.bits
.ID
= apic_id
;
4034 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
4035 io_apic_write(ioapic
, 0, reg_00
.raw
);
4036 reg_00
.raw
= io_apic_read(ioapic
, 0);
4037 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
4040 if (reg_00
.bits
.ID
!= apic_id
) {
4041 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
4046 apic_printk(APIC_VERBOSE
, KERN_INFO
4047 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
4053 int __init
io_apic_get_version(int ioapic
)
4055 union IO_APIC_reg_01 reg_01
;
4056 unsigned long flags
;
4058 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
4059 reg_01
.raw
= io_apic_read(ioapic
, 1);
4060 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
4062 return reg_01
.bits
.version
;
4065 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
4067 int ioapic
, pin
, idx
;
4069 if (skip_ioapic_setup
)
4072 ioapic
= mp_find_ioapic(gsi
);
4076 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
4080 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
4084 *trigger
= irq_trigger(idx
);
4085 *polarity
= irq_polarity(idx
);
4090 * This function currently is only a helper for the i386 smp boot process where
4091 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4092 * so mask in all cases should simply be apic->target_cpus()
4095 void __init
setup_ioapic_dest(void)
4097 int pin
, ioapic
, irq
, irq_entry
;
4098 struct irq_desc
*desc
;
4099 const struct cpumask
*mask
;
4101 if (skip_ioapic_setup
== 1)
4104 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++)
4105 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4106 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4107 if (irq_entry
== -1)
4109 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4111 if ((ioapic
> 0) && (irq
> 16))
4114 desc
= irq_to_desc(irq
);
4117 * Honour affinities which have been set in early boot
4120 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4121 mask
= desc
->affinity
;
4123 mask
= apic
->target_cpus();
4125 if (intr_remapping_enabled
)
4126 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4128 set_ioapic_affinity_irq_desc(desc
, mask
);
4134 #define IOAPIC_RESOURCE_NAME_SIZE 11
4136 static struct resource
*ioapic_resources
;
4138 static struct resource
* __init
ioapic_setup_resources(int nr_ioapics
)
4141 struct resource
*res
;
4145 if (nr_ioapics
<= 0)
4148 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4151 mem
= alloc_bootmem(n
);
4154 mem
+= sizeof(struct resource
) * nr_ioapics
;
4156 for (i
= 0; i
< nr_ioapics
; i
++) {
4158 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4159 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
4160 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4163 ioapic_resources
= res
;
4168 void __init
ioapic_init_mappings(void)
4170 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4171 struct resource
*ioapic_res
;
4174 ioapic_res
= ioapic_setup_resources(nr_ioapics
);
4175 for (i
= 0; i
< nr_ioapics
; i
++) {
4176 if (smp_found_config
) {
4177 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4178 #ifdef CONFIG_X86_32
4181 "WARNING: bogus zero IO-APIC "
4182 "address found in MPTABLE, "
4183 "disabling IO/APIC support!\n");
4184 smp_found_config
= 0;
4185 skip_ioapic_setup
= 1;
4186 goto fake_ioapic_page
;
4190 #ifdef CONFIG_X86_32
4193 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
4194 ioapic_phys
= __pa(ioapic_phys
);
4196 set_fixmap_nocache(idx
, ioapic_phys
);
4197 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
4198 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
4202 ioapic_res
->start
= ioapic_phys
;
4203 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
4208 void __init
ioapic_insert_resources(void)
4211 struct resource
*r
= ioapic_resources
;
4216 "IO APIC resources couldn't be allocated.\n");
4220 for (i
= 0; i
< nr_ioapics
; i
++) {
4221 insert_resource(&iomem_resource
, r
);
4226 int mp_find_ioapic(u32 gsi
)
4230 /* Find the IOAPIC that manages this GSI. */
4231 for (i
= 0; i
< nr_ioapics
; i
++) {
4232 if ((gsi
>= mp_gsi_routing
[i
].gsi_base
)
4233 && (gsi
<= mp_gsi_routing
[i
].gsi_end
))
4237 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
4241 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
4243 if (WARN_ON(ioapic
== -1))
4245 if (WARN_ON(gsi
> mp_gsi_routing
[ioapic
].gsi_end
))
4248 return gsi
- mp_gsi_routing
[ioapic
].gsi_base
;
4251 static int bad_ioapic(unsigned long address
)
4253 if (nr_ioapics
>= MAX_IO_APICS
) {
4254 printk(KERN_WARNING
"WARING: Max # of I/O APICs (%d) exceeded "
4255 "(found %d), skipping\n", MAX_IO_APICS
, nr_ioapics
);
4259 printk(KERN_WARNING
"WARNING: Bogus (zero) I/O APIC address"
4260 " found in table, skipping!\n");
4266 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
4271 if (bad_ioapic(address
))
4276 mp_ioapics
[idx
].type
= MP_IOAPIC
;
4277 mp_ioapics
[idx
].flags
= MPC_APIC_USABLE
;
4278 mp_ioapics
[idx
].apicaddr
= address
;
4280 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
4281 mp_ioapics
[idx
].apicid
= io_apic_unique_id(id
);
4282 mp_ioapics
[idx
].apicver
= io_apic_get_version(idx
);
4285 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4286 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4288 entries
= io_apic_get_redir_entries(idx
);
4289 mp_gsi_routing
[idx
].gsi_base
= gsi_base
;
4290 mp_gsi_routing
[idx
].gsi_end
= gsi_base
+ entries
- 1;
4293 * The number of IO-APIC IRQ registers (== #pins):
4295 nr_ioapic_registers
[idx
] = entries
;
4297 if (mp_gsi_routing
[idx
].gsi_end
>= gsi_top
)
4298 gsi_top
= mp_gsi_routing
[idx
].gsi_end
+ 1;
4300 printk(KERN_INFO
"IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4301 "GSI %d-%d\n", idx
, mp_ioapics
[idx
].apicid
,
4302 mp_ioapics
[idx
].apicver
, mp_ioapics
[idx
].apicaddr
,
4303 mp_gsi_routing
[idx
].gsi_base
, mp_gsi_routing
[idx
].gsi_end
);
4308 /* Enable IOAPIC early just for system timer */
4309 void __init
pre_init_apic_IRQ0(void)
4311 struct irq_cfg
*cfg
;
4312 struct irq_desc
*desc
;
4314 printk(KERN_INFO
"Early APIC setup for system timer0\n");
4316 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
4318 desc
= irq_to_desc_alloc_node(0, 0);
4323 add_pin_to_irq_node(cfg
, 0, 0, 0);
4324 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
4326 setup_IO_APIC_irq(0, 0, 0, desc
, 0, 0);