drivers/staging/gma500/psb_drv.h

   1 /**************************************************************************
   2  * Copyright (c) 2007-2008, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #ifndef _PSB_DRV_H_
  21 #define _PSB_DRV_H_
  22
  23 #include <linux/version.h>
  24
  25 #include <drm/drmP.h>
  26 #include "drm_global.h"
  27 #include "psb_drm.h"
  28 #include "psb_reg.h"
  29 #include "psb_intel_drv.h"
  30 #include "psb_gtt.h"
  31 #include "psb_powermgmt.h"
  32 #include "mrst.h"
  33
  34 /*Append new drm mode definition here, align with libdrm definition*/
  35 #define DRM_MODE_SCALE_NO_SCALE   2
  36
  37 extern struct ttm_bo_driver psb_ttm_bo_driver;
  38
  39 enum {
  40         CHIP_PSB_8108 = 0,
  41         CHIP_PSB_8109 = 1,
  42         CHIP_MRST_4100 = 2,
  43 };
  44
  45 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
  46
  47 /*
  48  *Hardware bugfixes
  49  */
  50
  51 #define DRIVER_NAME "pvrsrvkm"
  52 #define DRIVER_DESC "drm driver for the Intel GMA500"
  53 #define DRIVER_AUTHOR "Intel Corporation"
  54
  55 #define PSB_DRM_DRIVER_DATE "2009-03-10"
  56 #define PSB_DRM_DRIVER_MAJOR 8
  57 #define PSB_DRM_DRIVER_MINOR 1
  58 #define PSB_DRM_DRIVER_PATCHLEVEL 0
  59
  60 /*
  61  *TTM driver private offsets.
  62  */
  63
  64 #define DRM_PSB_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  65
  66 #define PSB_OBJECT_HASH_ORDER 13
  67 #define PSB_FILE_OBJECT_HASH_ORDER 12
  68 #define PSB_BO_HASH_ORDER 12
  69
  70 #define PSB_VDC_OFFSET           0x00000000
  71 #define PSB_VDC_SIZE             0x000080000
  72 #define MRST_MMIO_SIZE           0x0000C0000
  73 #define MDFLD_MMIO_SIZE          0x000100000
  74 #define PSB_SGX_SIZE             0x8000
  75 #define PSB_SGX_OFFSET           0x00040000
  76 #define MRST_SGX_OFFSET          0x00080000
  77 #define PSB_MMIO_RESOURCE        0
  78 #define PSB_GATT_RESOURCE        2
  79 #define PSB_GTT_RESOURCE         3
  80 #define PSB_GMCH_CTRL            0x52
  81 #define PSB_BSM                  0x5C
  82 #define _PSB_GMCH_ENABLED        0x4
  83 #define PSB_PGETBL_CTL           0x2020
  84 #define _PSB_PGETBL_ENABLED      0x00000001
  85 #define PSB_SGX_2D_SLAVE_PORT    0x4000
  86 #define PSB_TT_PRIV0_LIMIT       (256*1024*1024)
  87 #define PSB_TT_PRIV0_PLIMIT      (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
  88 #define PSB_NUM_VALIDATE_BUFFERS 2048
  89
  90 /*
  91  *Flags for external memory type field.
  92  */
  93
  94 #define PSB_MMU_CACHED_MEMORY     0x0001        /* Bind to MMU only */
  95 #define PSB_MMU_RO_MEMORY         0x0002        /* MMU RO memory */
  96 #define PSB_MMU_WO_MEMORY         0x0004        /* MMU WO memory */
  97
  98 /*
  99  *PTE's and PDE's
 100  */
 101
 102 #define PSB_PDE_MASK              0x003FFFFF
 103 #define PSB_PDE_SHIFT             22
 104 #define PSB_PTE_SHIFT             12
 105
 106 #define PSB_PTE_VALID             0x0001        /* PTE / PDE valid */
 107 #define PSB_PTE_WO                0x0002        /* Write only */
 108 #define PSB_PTE_RO                0x0004        /* Read only */
 109 #define PSB_PTE_CACHED            0x0008        /* CPU cache coherent */
 110
 111 /*
 112  *VDC registers and bits
 113  */
 114 #define PSB_MSVDX_CLOCKGATING     0x2064
 115 #define PSB_TOPAZ_CLOCKGATING     0x2068
 116 #define PSB_HWSTAM                0x2098
 117 #define PSB_INSTPM                0x20C0
 118 #define PSB_INT_IDENTITY_R        0x20A4
 119 #define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
 120 #define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
 121 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
 122 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
 123 #define _PSB_VSYNC_PIPEB_FLAG     (1<<5)
 124 #define _PSB_DPST_PIPEA_FLAG      (1<<6)
 125 #define _PSB_PIPEA_EVENT_FLAG     (1<<6)
 126 #define _PSB_VSYNC_PIPEA_FLAG     (1<<7)
 127 #define _MDFLD_MIPIA_FLAG         (1<<16)
 128 #define _MDFLD_MIPIC_FLAG         (1<<17)
 129 #define _PSB_IRQ_SGX_FLAG         (1<<18)
 130 #define _PSB_IRQ_MSVDX_FLAG       (1<<19)
 131 #define _LNC_IRQ_TOPAZ_FLAG       (1<<20)
 132
 133 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
 134 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | _MDFLD_PIPEB_EVENT_FLAG | \
 135         _PSB_PIPEA_EVENT_FLAG | _PSB_VSYNC_PIPEA_FLAG | _MDFLD_MIPIA_FLAG | _MDFLD_MIPIC_FLAG)
 136 #define PSB_INT_IDENTITY_R        0x20A4
 137 #define PSB_INT_MASK_R            0x20A8
 138 #define PSB_INT_ENABLE_R          0x20A0
 139
 140 #define _PSB_MMU_ER_MASK      0x0001FF00
 141 #define _PSB_MMU_ER_HOST      (1 << 16)
 142 #define GPIOA                   0x5010
 143 #define GPIOB                   0x5014
 144 #define GPIOC                   0x5018
 145 #define GPIOD                   0x501c
 146 #define GPIOE                   0x5020
 147 #define GPIOF                   0x5024
 148 #define GPIOG                   0x5028
 149 #define GPIOH                   0x502c
 150 #define GPIO_CLOCK_DIR_MASK             (1 << 0)
 151 #define GPIO_CLOCK_DIR_IN               (0 << 1)
 152 #define GPIO_CLOCK_DIR_OUT              (1 << 1)
 153 #define GPIO_CLOCK_VAL_MASK             (1 << 2)
 154 #define GPIO_CLOCK_VAL_OUT              (1 << 3)
 155 #define GPIO_CLOCK_VAL_IN               (1 << 4)
 156 #define GPIO_CLOCK_PULLUP_DISABLE       (1 << 5)
 157 #define GPIO_DATA_DIR_MASK              (1 << 8)
 158 #define GPIO_DATA_DIR_IN                (0 << 9)
 159 #define GPIO_DATA_DIR_OUT               (1 << 9)
 160 #define GPIO_DATA_VAL_MASK              (1 << 10)
 161 #define GPIO_DATA_VAL_OUT               (1 << 11)
 162 #define GPIO_DATA_VAL_IN                (1 << 12)
 163 #define GPIO_DATA_PULLUP_DISABLE        (1 << 13)
 164
 165 #define VCLK_DIVISOR_VGA0   0x6000
 166 #define VCLK_DIVISOR_VGA1   0x6004
 167 #define VCLK_POST_DIV       0x6010
 168
 169 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
 170 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
 171 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
 172 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
 173 #define PSB_COMM_USER_IRQ (1024 >> 2)
 174 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
 175 #define PSB_COMM_FW (2048 >> 2)
 176
 177 #define PSB_UIRQ_VISTEST               1
 178 #define PSB_UIRQ_OOM_REPLY             2
 179 #define PSB_UIRQ_FIRE_TA_REPLY         3
 180 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
 181
 182 #define PSB_2D_SIZE (256*1024*1024)
 183 #define PSB_MAX_RELOC_PAGES 1024
 184
 185 #define PSB_LOW_REG_OFFS 0x0204
 186 #define PSB_HIGH_REG_OFFS 0x0600
 187
 188 #define PSB_NUM_VBLANKS 2
 189
 190
 191 #define PSB_2D_SIZE (256*1024*1024)
 192 #define PSB_MAX_RELOC_PAGES 1024
 193
 194 #define PSB_LOW_REG_OFFS 0x0204
 195 #define PSB_HIGH_REG_OFFS 0x0600
 196
 197 #define PSB_NUM_VBLANKS 2
 198 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
 199 #define PSB_LID_DELAY (DRM_HZ / 10)
 200
 201 #define MDFLD_PNW_A0 0x00
 202 #define MDFLD_PNW_B0 0x04
 203 #define MDFLD_PNW_C0 0x08
 204
 205 #define PSB_PWR_STATE_ON                1
 206 #define PSB_PWR_STATE_OFF               2
 207
 208 #define PSB_PMPOLICY_NOPM               0
 209 #define PSB_PMPOLICY_CLOCKGATING        1
 210 #define PSB_PMPOLICY_POWERDOWN          2
 211
 212 #define PSB_PMSTATE_POWERUP             0
 213 #define PSB_PMSTATE_CLOCKGATED          1
 214 #define PSB_PMSTATE_POWERDOWN           2
 215 #define PSB_PCIx_MSI_ADDR_LOC           0x94
 216 #define PSB_PCIx_MSI_DATA_LOC           0x98
 217
 218 struct opregion_header;
 219 struct opregion_acpi;
 220 struct opregion_swsci;
 221 struct opregion_asle;
 222
 223 struct psb_intel_opregion {
 224         struct opregion_header *header;
 225         struct opregion_acpi *acpi;
 226         struct opregion_swsci *swsci;
 227         struct opregion_asle *asle;
 228         int enabled;
 229 };
 230
 231 struct drm_psb_private {
 232         struct drm_device *dev;
 233
 234         unsigned long chipset;
 235
 236         struct psb_gtt *pg;
 237
 238         /*GTT Memory manager*/
 239         struct psb_gtt_mm *gtt_mm;
 240         struct page *scratch_page;
 241
 242         struct psb_mmu_driver *mmu;
 243         struct psb_mmu_pd *pf_pd;
 244
 245         uint8_t *sgx_reg;
 246         uint8_t *vdc_reg;
 247         uint32_t gatt_free_offset;
 248
 249
 250         /*
 251          *Fencing / irq.
 252          */
 253
 254         uint32_t vdc_irq_mask;
 255         uint32_t pipestat[PSB_NUM_PIPE];
 256
 257         spinlock_t irqmask_lock;
 258
 259         /*
 260          *Modesetting
 261          */
 262         struct psb_intel_mode_device mode_dev;
 263
 264         struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
 265         struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
 266         uint32_t num_pipe;
 267
 268         /*
 269          *Memory managers
 270          */
 271
 272         /*
 273         *OSPM info
 274         */
 275         uint32_t ospm_base;
 276
 277         /*
 278          * Sizes info
 279          */
 280
 281         struct drm_psb_sizes_arg sizes;
 282
 283         u32 fuse_reg_value;
 284         u32 video_device_fuse;
 285
 286         /* pci revision id for B0:D2:F0 */
 287         uint8_t platform_rev_id;
 288
 289         /*
 290          *LVDS info
 291          */
 292         int backlight_duty_cycle;       /* restore backlight to this value */
 293         bool panel_wants_dither;
 294         struct drm_display_mode *panel_fixed_mode;
 295         struct drm_display_mode *lfp_lvds_vbt_mode;
 296         struct drm_display_mode *sdvo_lvds_vbt_mode;
 297
 298         struct bdb_lvds_backlight *lvds_bl; /*LVDS backlight info from VBT*/
 299         struct psb_intel_i2c_chan *lvds_i2c_bus;
 300
 301         /* Feature bits from the VBIOS*/
 302         unsigned int int_tv_support:1;
 303         unsigned int lvds_dither:1;
 304         unsigned int lvds_vbt:1;
 305         unsigned int int_crt_support:1;
 306         unsigned int lvds_use_ssc:1;
 307         int lvds_ssc_freq;
 308         bool is_lvds_on;
 309         bool is_mipi_on;
 310
 311         unsigned int core_freq;
 312         uint32_t iLVDS_enable;
 313
 314         /*runtime PM state*/
 315         int rpm_enabled;
 316
 317         /* Moorestown specific */
 318         struct mrst_vbt vbt_data;
 319         struct mrst_gct_data gct_data;
 320
 321         /* Moorestown pipe config register value cache */
 322         uint32_t pipeconf;
 323         uint32_t pipeconf1;
 324         uint32_t pipeconf2;
 325
 326         /* Moorestown plane control register value cache */
 327         uint32_t dspcntr;
 328         uint32_t dspcntr1;
 329         uint32_t dspcntr2;
 330
 331         /*
 332          *Register state
 333          */
 334         uint32_t saveDSPACNTR;
 335         uint32_t saveDSPBCNTR;
 336         uint32_t savePIPEACONF;
 337         uint32_t savePIPEBCONF;
 338         uint32_t savePIPEASRC;
 339         uint32_t savePIPEBSRC;
 340         uint32_t saveFPA0;
 341         uint32_t saveFPA1;
 342         uint32_t saveDPLL_A;
 343         uint32_t saveDPLL_A_MD;
 344         uint32_t saveHTOTAL_A;
 345         uint32_t saveHBLANK_A;
 346         uint32_t saveHSYNC_A;
 347         uint32_t saveVTOTAL_A;
 348         uint32_t saveVBLANK_A;
 349         uint32_t saveVSYNC_A;
 350         uint32_t saveDSPASTRIDE;
 351         uint32_t saveDSPASIZE;
 352         uint32_t saveDSPAPOS;
 353         uint32_t saveDSPABASE;
 354         uint32_t saveDSPASURF;
 355         uint32_t saveFPB0;
 356         uint32_t saveFPB1;
 357         uint32_t saveDPLL_B;
 358         uint32_t saveDPLL_B_MD;
 359         uint32_t saveHTOTAL_B;
 360         uint32_t saveHBLANK_B;
 361         uint32_t saveHSYNC_B;
 362         uint32_t saveVTOTAL_B;
 363         uint32_t saveVBLANK_B;
 364         uint32_t saveVSYNC_B;
 365         uint32_t saveDSPBSTRIDE;
 366         uint32_t saveDSPBSIZE;
 367         uint32_t saveDSPBPOS;
 368         uint32_t saveDSPBBASE;
 369         uint32_t saveDSPBSURF;
 370         uint32_t saveVCLK_DIVISOR_VGA0;
 371         uint32_t saveVCLK_DIVISOR_VGA1;
 372         uint32_t saveVCLK_POST_DIV;
 373         uint32_t saveVGACNTRL;
 374         uint32_t saveADPA;
 375         uint32_t saveLVDS;
 376         uint32_t saveDVOA;
 377         uint32_t saveDVOB;
 378         uint32_t saveDVOC;
 379         uint32_t savePP_ON;
 380         uint32_t savePP_OFF;
 381         uint32_t savePP_CONTROL;
 382         uint32_t savePP_CYCLE;
 383         uint32_t savePFIT_CONTROL;
 384         uint32_t savePaletteA[256];
 385         uint32_t savePaletteB[256];
 386         uint32_t saveBLC_PWM_CTL2;
 387         uint32_t saveBLC_PWM_CTL;
 388         uint32_t saveCLOCKGATING;
 389         uint32_t saveDSPARB;
 390         uint32_t saveDSPATILEOFF;
 391         uint32_t saveDSPBTILEOFF;
 392         uint32_t saveDSPAADDR;
 393         uint32_t saveDSPBADDR;
 394         uint32_t savePFIT_AUTO_RATIOS;
 395         uint32_t savePFIT_PGM_RATIOS;
 396         uint32_t savePP_ON_DELAYS;
 397         uint32_t savePP_OFF_DELAYS;
 398         uint32_t savePP_DIVISOR;
 399         uint32_t saveBSM;
 400         uint32_t saveVBT;
 401         uint32_t saveBCLRPAT_A;
 402         uint32_t saveBCLRPAT_B;
 403         uint32_t saveDSPALINOFF;
 404         uint32_t saveDSPBLINOFF;
 405         uint32_t savePERF_MODE;
 406         uint32_t saveDSPFW1;
 407         uint32_t saveDSPFW2;
 408         uint32_t saveDSPFW3;
 409         uint32_t saveDSPFW4;
 410         uint32_t saveDSPFW5;
 411         uint32_t saveDSPFW6;
 412         uint32_t saveCHICKENBIT;
 413         uint32_t saveDSPACURSOR_CTRL;
 414         uint32_t saveDSPBCURSOR_CTRL;
 415         uint32_t saveDSPACURSOR_BASE;
 416         uint32_t saveDSPBCURSOR_BASE;
 417         uint32_t saveDSPACURSOR_POS;
 418         uint32_t saveDSPBCURSOR_POS;
 419         uint32_t save_palette_a[256];
 420         uint32_t save_palette_b[256];
 421         uint32_t saveOV_OVADD;
 422         uint32_t saveOV_OGAMC0;
 423         uint32_t saveOV_OGAMC1;
 424         uint32_t saveOV_OGAMC2;
 425         uint32_t saveOV_OGAMC3;
 426         uint32_t saveOV_OGAMC4;
 427         uint32_t saveOV_OGAMC5;
 428         uint32_t saveOVC_OVADD;
 429         uint32_t saveOVC_OGAMC0;
 430         uint32_t saveOVC_OGAMC1;
 431         uint32_t saveOVC_OGAMC2;
 432         uint32_t saveOVC_OGAMC3;
 433         uint32_t saveOVC_OGAMC4;
 434         uint32_t saveOVC_OGAMC5;
 435
 436         /* MSI reg save */
 437         uint32_t msi_addr;
 438         uint32_t msi_data;
 439
 440         /*
 441          * LID-Switch
 442          */
 443         spinlock_t lid_lock;
 444         struct timer_list lid_timer;
 445         struct psb_intel_opregion opregion;
 446         u32 *lid_state;
 447         u32 lid_last_state;
 448
 449         /*
 450          *Watchdog
 451          */
 452
 453         uint32_t apm_reg;
 454         uint16_t apm_base;
 455
 456         /*
 457          * Used for modifying backlight from
 458          * xrandr -- consider removing and using HAL instead
 459          */
 460         struct drm_property *backlight_property;
 461         uint32_t blc_adj1;
 462         uint32_t blc_adj2;
 463
 464         void * fbdev;
 465 };
 466
 467
 468 struct psb_mmu_driver;
 469
 470 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
 471 extern int drm_pick_crtcs(struct drm_device *dev);
 472
 473 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
 474 {
 475         return (struct drm_psb_private *) dev->dev_private;
 476 }
 477
 478 /*
 479  *MMU stuff.
 480  */
 481
 482 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
 483                                         int trap_pagefaults,
 484                                         int invalid_type,
 485                                         struct drm_psb_private *dev_priv);
 486 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
 487 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
 488                                                  *driver);
 489 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
 490                                uint32_t gtt_start, uint32_t gtt_pages);
 491 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
 492                                            int trap_pagefaults,
 493                                            int invalid_type);
 494 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
 495 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
 496 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
 497                                         unsigned long address,
 498                                         uint32_t num_pages);
 499 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
 500                                        uint32_t start_pfn,
 501                                        unsigned long address,
 502                                        uint32_t num_pages, int type);
 503 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
 504                                   unsigned long *pfn);
 505
 506 /*
 507  *Enable / disable MMU for different requestors.
 508  */
 509
 510
 511 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
 512 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
 513                                 unsigned long address, uint32_t num_pages,
 514                                 uint32_t desired_tile_stride,
 515                                 uint32_t hw_tile_stride, int type);
 516 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
 517                                  unsigned long address, uint32_t num_pages,
 518                                  uint32_t desired_tile_stride,
 519                                  uint32_t hw_tile_stride);
 520 /*
 521  *psb_irq.c
 522  */
 523
 524 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
 525 extern int psb_irq_enable_dpst(struct drm_device *dev);
 526 extern int psb_irq_disable_dpst(struct drm_device *dev);
 527 extern void psb_irq_preinstall(struct drm_device *dev);
 528 extern int psb_irq_postinstall(struct drm_device *dev);
 529 extern void psb_irq_uninstall(struct drm_device *dev);
 530 extern void psb_irq_preinstall_islands(struct drm_device *dev, int hw_islands);
 531 extern int psb_irq_postinstall_islands(struct drm_device *dev, int hw_islands);
 532 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
 533 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
 534
 535 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
 536 extern int psb_vblank_wait2(struct drm_device *dev,unsigned int *sequence);
 537 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
 538 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
 539 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
 540 void
 541 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 542
 543 void
 544 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 545
 546 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
 547
 548 /*
 549  * psb_opregion.c
 550  */
 551 extern int psb_intel_opregion_init(struct drm_device *dev);
 552
 553 /*
 554  *psb_fb.c
 555  */
 556 extern int psbfb_probed(struct drm_device *dev);
 557 extern int psbfb_remove(struct drm_device *dev,
 558                         struct drm_framebuffer *fb);
 559 extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
 560                                struct drm_file *file_priv);
 561 extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
 562                               struct drm_file *file_priv);
 563 extern void *psbfb_vdc_reg(struct drm_device* dev);
 564
 565 /*
 566  * psb_2d.c
 567  */
 568 extern void psbfb_fillrect(struct fb_info *info,
 569                                         const struct fb_fillrect *rect);
 570 extern void psbfb_copyarea(struct fb_info *info,
 571                                         const struct fb_copyarea *region);
 572 extern void psbfb_imageblit(struct fb_info *info,
 573                                         const struct fb_image *image);
 574 extern int psbfb_sync(struct fb_info *info);
 575
 576 extern void psb_spank(struct drm_psb_private *dev_priv);
 577
 578 extern int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
 579                            unsigned size);
 580
 581 /*
 582  *psb_reset.c
 583  */
 584
 585 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
 586 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
 587 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
 588
 589 /* modesetting */
 590 extern void psb_modeset_init(struct drm_device *dev);
 591 extern void psb_modeset_cleanup(struct drm_device *dev);
 592 extern int psb_fbdev_init(struct drm_device * dev);
 593
 594 /* psb_bl.c */
 595 int psb_backlight_init(struct drm_device *dev);
 596 void psb_backlight_exit(void);
 597 int psb_set_brightness(struct backlight_device *bd);
 598 int psb_get_brightness(struct backlight_device *bd);
 599 struct backlight_device * psb_get_backlight_device(void);
 600
 601 /* mrst_crtc.c */
 602 extern const struct drm_crtc_helper_funcs mrst_helper_funcs;
 603
 604 /* mrst_lvds.c */
 605 extern void mrst_lvds_init(struct drm_device *dev,
 606                     struct psb_intel_mode_device *mode_dev);
 607
 608 /* psb_intel_lvds.c */
 609 extern void psb_intel_lvds_prepare(struct drm_encoder *encoder);
 610 extern void psb_intel_lvds_commit(struct drm_encoder *encoder);
 611 extern const struct drm_connector_helper_funcs
 612                                         psb_intel_lvds_connector_helper_funcs;
 613 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
 614
 615
 616 /*
 617  *Debug print bits setting
 618  */
 619 #define PSB_D_GENERAL (1 << 0)
 620 #define PSB_D_INIT    (1 << 1)
 621 #define PSB_D_IRQ     (1 << 2)
 622 #define PSB_D_ENTRY   (1 << 3)
 623 /* debug the get H/V BP/FP count */
 624 #define PSB_D_HV      (1 << 4)
 625 #define PSB_D_DBI_BF  (1 << 5)
 626 #define PSB_D_PM      (1 << 6)
 627 #define PSB_D_RENDER  (1 << 7)
 628 #define PSB_D_REG     (1 << 8)
 629 #define PSB_D_MSVDX   (1 << 9)
 630 #define PSB_D_TOPAZ   (1 << 10)
 631
 632 #ifndef DRM_DEBUG_CODE
 633 /* To enable debug printout, set drm_psb_debug in psb_drv.c
 634  * to any combination of above print flags.
 635  */
 636 /* #define DRM_DEBUG_CODE 2 */
 637 #endif
 638
 639 extern int drm_psb_debug;
 640 extern int drm_psb_no_fb;
 641 extern int drm_idle_check_interval;
 642
 643 #define PSB_DEBUG_GENERAL(_fmt, _arg...) \
 644         PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
 645 #define PSB_DEBUG_INIT(_fmt, _arg...) \
 646         PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
 647 #define PSB_DEBUG_IRQ(_fmt, _arg...) \
 648         PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
 649 #define PSB_DEBUG_ENTRY(_fmt, _arg...) \
 650         PSB_DEBUG(PSB_D_ENTRY, _fmt, ##_arg)
 651 #define PSB_DEBUG_HV(_fmt, _arg...) \
 652         PSB_DEBUG(PSB_D_HV, _fmt, ##_arg)
 653 #define PSB_DEBUG_DBI_BF(_fmt, _arg...) \
 654         PSB_DEBUG(PSB_D_DBI_BF, _fmt, ##_arg)
 655 #define PSB_DEBUG_PM(_fmt, _arg...) \
 656         PSB_DEBUG(PSB_D_PM, _fmt, ##_arg)
 657 #define PSB_DEBUG_RENDER(_fmt, _arg...) \
 658         PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
 659 #define PSB_DEBUG_REG(_fmt, _arg...) \
 660         PSB_DEBUG(PSB_D_REG, _fmt, ##_arg)
 661 #define PSB_DEBUG_MSVDX(_fmt, _arg...) \
 662         PSB_DEBUG(PSB_D_MSVDX, _fmt, ##_arg)
 663 #define PSB_DEBUG_TOPAZ(_fmt, _arg...) \
 664         PSB_DEBUG(PSB_D_TOPAZ, _fmt, ##_arg)
 665
 666 #if DRM_DEBUG_CODE
 667 #define PSB_DEBUG(_flag, _fmt, _arg...)                                 \
 668         do {                                                            \
 669                 if (unlikely((_flag) & drm_psb_debug))                  \
 670                         printk(KERN_DEBUG                               \
 671                                "[psb:0x%02x:%s] " _fmt , _flag,         \
 672                                __func__ , ##_arg);                      \
 673         } while (0)
 674 #else
 675 #define PSB_DEBUG(_fmt, _arg...)     do { } while (0)
 676 #endif
 677
 678 /*
 679  *Utilities
 680  */
 681 #define DRM_DRIVER_PRIVATE_T struct drm_psb_private
 682
 683 static inline u32 MRST_MSG_READ32(uint port, uint offset)
 684 {
 685         int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
 686         uint32_t ret_val = 0;
 687         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
 688         pci_write_config_dword (pci_root, 0xD0, mcr);
 689         pci_read_config_dword (pci_root, 0xD4, &ret_val);
 690         pci_dev_put(pci_root);
 691         return ret_val;
 692 }
 693 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
 694 {
 695         int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
 696         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
 697         pci_write_config_dword (pci_root, 0xD4, value);
 698         pci_write_config_dword (pci_root, 0xD0, mcr);
 699         pci_dev_put(pci_root);
 700 }
 701 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
 702 {
 703         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 704         uint32_t ret_val = 0;
 705         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
 706         pci_write_config_dword (pci_root, 0xD0, mcr);
 707         pci_read_config_dword (pci_root, 0xD4, &ret_val);
 708         pci_dev_put(pci_root);
 709         return ret_val;
 710 }
 711 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
 712 {
 713         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 714         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
 715         pci_write_config_dword (pci_root, 0xD4, value);
 716         pci_write_config_dword (pci_root, 0xD0, mcr);
 717         pci_dev_put(pci_root);
 718 }
 719
 720 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
 721 {
 722         struct drm_psb_private *dev_priv = dev->dev_private;
 723         int reg_val = ioread32(dev_priv->vdc_reg + (reg));
 724         PSB_DEBUG_REG("reg = 0x%x. reg_val = 0x%x. \n", reg, reg_val);
 725         return reg_val;
 726 }
 727
 728 #define REG_READ(reg)          REGISTER_READ(dev, (reg))
 729 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
 730                                       uint32_t val)
 731 {
 732         struct drm_psb_private *dev_priv = dev->dev_private;
 733         if ((reg < 0x70084 || reg >0x70088) && (reg < 0xa000 || reg >0xa3ff))
 734                 PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
 735
 736         iowrite32((val), dev_priv->vdc_reg + (reg));
 737 }
 738
 739 #define REG_WRITE(reg, val)     REGISTER_WRITE(dev, (reg), (val))
 740
 741 static inline void REGISTER_WRITE16(struct drm_device *dev,
 742                                         uint32_t reg, uint32_t val)
 743 {
 744         struct drm_psb_private *dev_priv = dev->dev_private;
 745
 746         PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
 747
 748         iowrite16((val), dev_priv->vdc_reg + (reg));
 749 }
 750
 751 #define REG_WRITE16(reg, val)     REGISTER_WRITE16(dev, (reg), (val))
 752
 753 static inline void REGISTER_WRITE8(struct drm_device *dev,
 754                                        uint32_t reg, uint32_t val)
 755 {
 756         struct drm_psb_private *dev_priv = dev->dev_private;
 757
 758         PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
 759
 760         iowrite8((val), dev_priv->vdc_reg + (reg));
 761 }
 762
 763 #define REG_WRITE8(reg, val)     REGISTER_WRITE8(dev, (reg), (val))
 764
 765 #define PSB_ALIGN_TO(_val, _align) \
 766   (((_val) + ((_align) - 1)) & ~((_align) - 1))
 767 #define PSB_WVDC32(_val, _offs) \
 768   iowrite32(_val, dev_priv->vdc_reg + (_offs))
 769 #define PSB_RVDC32(_offs) \
 770   ioread32(dev_priv->vdc_reg + (_offs))
 771
 772 /* #define TRAP_SGX_PM_FAULT 1 */
 773 #ifdef TRAP_SGX_PM_FAULT
 774 #define PSB_RSGX32(_offs)                                       \
 775 ({                                                              \
 776     if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) {          \
 777         printk(KERN_ERR "access sgx when it's off!! (READ) %s, %d\n", \
 778                __FILE__, __LINE__);                             \
 779         mdelay(1000);                                           \
 780     }                                                           \
 781     ioread32(dev_priv->sgx_reg + (_offs));                      \
 782 })
 783 #else
 784 #define PSB_RSGX32(_offs)                                       \
 785   ioread32(dev_priv->sgx_reg + (_offs))
 786 #endif
 787 #define PSB_WSGX32(_val, _offs) \
 788   iowrite32(_val, dev_priv->sgx_reg + (_offs))
 789
 790 #define MSVDX_REG_DUMP 0
 791 #if MSVDX_REG_DUMP
 792
 793 #define PSB_WMSVDX32(_val, _offs) \
 794   printk("MSVDX: write %08x to reg 0x%08x\n", (unsigned int)(_val), (unsigned int)(_offs));\
 795   iowrite32(_val, dev_priv->msvdx_reg + (_offs))
 796 #define PSB_RMSVDX32(_offs) \
 797   ioread32(dev_priv->msvdx_reg + (_offs))
 798
 799 #else
 800
 801 #define PSB_WMSVDX32(_val, _offs) \
 802   iowrite32(_val, dev_priv->msvdx_reg + (_offs))
 803 #define PSB_RMSVDX32(_offs) \
 804   ioread32(dev_priv->msvdx_reg + (_offs))
 805
 806 #endif
 807
 808 #define PSB_ALPL(_val, _base)                   \
 809   (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
 810 #define PSB_ALPLM(_val, _base)                  \
 811   ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
 812
 813 #endif