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e1000e: move settting of flow control refresh timer to link setup code
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / e1000e / ich8lan.c
blob2b2cffc017be4ec6309107a980be803646ce4bea
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 */
56
57 #include "e1000.h"
58
59 #define ICH_FLASH_GFPREG 0x0000
60 #define ICH_FLASH_HSFSTS 0x0004
61 #define ICH_FLASH_HSFCTL 0x0006
62 #define ICH_FLASH_FADDR 0x0008
63 #define ICH_FLASH_FDATA0 0x0010
64 #define ICH_FLASH_PR0 0x0074
65
66 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
70 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
71
72 #define ICH_CYCLE_READ 0
73 #define ICH_CYCLE_WRITE 2
74 #define ICH_CYCLE_ERASE 3
75
76 #define FLASH_GFPREG_BASE_MASK 0x1FFF
77 #define FLASH_SECTOR_ADDR_SHIFT 12
78
79 #define ICH_FLASH_SEG_SIZE_256 256
80 #define ICH_FLASH_SEG_SIZE_4K 4096
81 #define ICH_FLASH_SEG_SIZE_8K 8192
82 #define ICH_FLASH_SEG_SIZE_64K 65536
83
84
85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
86 /* FW established a valid mode */
87 #define E1000_ICH_FWSM_FW_VALID 0x00008000
88
89 #define E1000_ICH_MNG_IAMT_MODE 0x2
90
91 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
92 (ID_LED_DEF1_OFF2 << 8) | \
93 (ID_LED_DEF1_ON2 << 4) | \
94 (ID_LED_DEF1_DEF2))
95
96 #define E1000_ICH_NVM_SIG_WORD 0x13
97 #define E1000_ICH_NVM_SIG_MASK 0xC000
98 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
99 #define E1000_ICH_NVM_SIG_VALUE 0x80
100
101 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
102
103 #define E1000_FEXTNVM_SW_CONFIG 1
104 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
105
106 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
107
108 #define E1000_ICH_RAR_ENTRIES 7
109
110 #define PHY_PAGE_SHIFT 5
111 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
112 ((reg) & MAX_PHY_REG_ADDRESS))
113 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
114 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
115
116 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
117 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
118 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
119
120 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
121
122 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
123
124 /* SMBus Address Phy Register */
125 #define HV_SMB_ADDR PHY_REG(768, 26)
126 #define HV_SMB_ADDR_PEC_EN 0x0200
127 #define HV_SMB_ADDR_VALID 0x0080
128
129 /* Strapping Option Register - RO */
130 #define E1000_STRAP 0x0000C
131 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
132 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
133
134 /* OEM Bits Phy Register */
135 #define HV_OEM_BITS PHY_REG(768, 25)
136 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
137 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
138 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
139
140 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
141 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
142
143 /* KMRN Mode Control */
144 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
145 #define HV_KMRN_MDIO_SLOW 0x0400
146
147 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
148 /* Offset 04h HSFSTS */
149 union ich8_hws_flash_status {
150 struct ich8_hsfsts {
151 u16 flcdone :1; /* bit 0 Flash Cycle Done */
152 u16 flcerr :1; /* bit 1 Flash Cycle Error */
153 u16 dael :1; /* bit 2 Direct Access error Log */
154 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
155 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
156 u16 reserved1 :2; /* bit 13:6 Reserved */
157 u16 reserved2 :6; /* bit 13:6 Reserved */
158 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
159 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
160 } hsf_status;
161 u16 regval;
162 };
163
164 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
165 /* Offset 06h FLCTL */
166 union ich8_hws_flash_ctrl {
167 struct ich8_hsflctl {
168 u16 flcgo :1; /* 0 Flash Cycle Go */
169 u16 flcycle :2; /* 2:1 Flash Cycle */
170 u16 reserved :5; /* 7:3 Reserved */
171 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
172 u16 flockdn :6; /* 15:10 Reserved */
173 } hsf_ctrl;
174 u16 regval;
175 };
176
177 /* ICH Flash Region Access Permissions */
178 union ich8_hws_flash_regacc {
179 struct ich8_flracc {
180 u32 grra :8; /* 0:7 GbE region Read Access */
181 u32 grwa :8; /* 8:15 GbE region Write Access */
182 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
183 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
184 } hsf_flregacc;
185 u16 regval;
186 };
187
188 /* ICH Flash Protected Region */
189 union ich8_flash_protected_range {
190 struct ich8_pr {
191 u32 base:13; /* 0:12 Protected Range Base */
192 u32 reserved1:2; /* 13:14 Reserved */
193 u32 rpe:1; /* 15 Read Protection Enable */
194 u32 limit:13; /* 16:28 Protected Range Limit */
195 u32 reserved2:2; /* 29:30 Reserved */
196 u32 wpe:1; /* 31 Write Protection Enable */
197 } range;
198 u32 regval;
199 };
200
201 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
202 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
203 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
204 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
205 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
206 u32 offset, u8 byte);
207 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
208 u8 *data);
209 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
210 u16 *data);
211 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
212 u8 size, u16 *data);
213 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
214 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
215 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
216 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
217 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
218 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
219 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
220 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
221 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
222 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
223 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
224 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
225 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
226 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
227 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
228 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
229
230 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
231 {
232 return readw(hw->flash_address + reg);
233 }
234
235 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
236 {
237 return readl(hw->flash_address + reg);
238 }
239
240 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
241 {
242 writew(val, hw->flash_address + reg);
243 }
244
245 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
246 {
247 writel(val, hw->flash_address + reg);
248 }
249
250 #define er16flash(reg) __er16flash(hw, (reg))
251 #define er32flash(reg) __er32flash(hw, (reg))
252 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
253 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
254
255 /**
256 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
257 * @hw: pointer to the HW structure
258 *
259 * Initialize family-specific PHY parameters and function pointers.
260 **/
261 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
262 {
263 struct e1000_phy_info *phy = &hw->phy;
264 u32 ctrl;
265 s32 ret_val = 0;
266
267 phy->addr = 1;
268 phy->reset_delay_us = 100;
269
270 phy->ops.read_reg = e1000_read_phy_reg_hv;
271 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
272 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
273 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
274 phy->ops.write_reg = e1000_write_phy_reg_hv;
275 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
276 phy->ops.power_up = e1000_power_up_phy_copper;
277 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
278 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
279
280 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
281 /*
282 * The MAC-PHY interconnect may still be in SMBus mode
283 * after Sx->S0. Toggle the LANPHYPC Value bit to force
284 * the interconnect to PCIe mode, but only if there is no
285 * firmware present otherwise firmware will have done it.
286 */
287 ctrl = er32(CTRL);
288 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
289 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
290 ew32(CTRL, ctrl);
291 udelay(10);
292 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
293 ew32(CTRL, ctrl);
294 msleep(50);
295 }
296
297 /*
298 * Reset the PHY before any acccess to it. Doing so, ensures that
299 * the PHY is in a known good state before we read/write PHY registers.
300 * The generic reset is sufficient here, because we haven't determined
301 * the PHY type yet.
302 */
303 ret_val = e1000e_phy_hw_reset_generic(hw);
304 if (ret_val)
305 goto out;
306
307 phy->id = e1000_phy_unknown;
308 ret_val = e1000e_get_phy_id(hw);
309 if (ret_val)
310 goto out;
311 if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
312 /*
313 * In case the PHY needs to be in mdio slow mode (eg. 82577),
314 * set slow mode and try to get the PHY id again.
315 */
316 ret_val = e1000_set_mdio_slow_mode_hv(hw);
317 if (ret_val)
318 goto out;
319 ret_val = e1000e_get_phy_id(hw);
320 if (ret_val)
321 goto out;
322 }
323 phy->type = e1000e_get_phy_type_from_id(phy->id);
324
325 switch (phy->type) {
326 case e1000_phy_82577:
327 phy->ops.check_polarity = e1000_check_polarity_82577;
328 phy->ops.force_speed_duplex =
329 e1000_phy_force_speed_duplex_82577;
330 phy->ops.get_cable_length = e1000_get_cable_length_82577;
331 phy->ops.get_info = e1000_get_phy_info_82577;
332 phy->ops.commit = e1000e_phy_sw_reset;
333 break;
334 case e1000_phy_82578:
335 phy->ops.check_polarity = e1000_check_polarity_m88;
336 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
337 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
338 phy->ops.get_info = e1000e_get_phy_info_m88;
339 break;
340 default:
341 ret_val = -E1000_ERR_PHY;
342 break;
343 }
344
345 out:
346 return ret_val;
347 }
348
349 /**
350 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
351 * @hw: pointer to the HW structure
352 *
353 * Initialize family-specific PHY parameters and function pointers.
354 **/
355 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
356 {
357 struct e1000_phy_info *phy = &hw->phy;
358 s32 ret_val;
359 u16 i = 0;
360
361 phy->addr = 1;
362 phy->reset_delay_us = 100;
363
364 phy->ops.power_up = e1000_power_up_phy_copper;
365 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
366
367 /*
368 * We may need to do this twice - once for IGP and if that fails,
369 * we'll set BM func pointers and try again
370 */
371 ret_val = e1000e_determine_phy_address(hw);
372 if (ret_val) {
373 phy->ops.write_reg = e1000e_write_phy_reg_bm;
374 phy->ops.read_reg = e1000e_read_phy_reg_bm;
375 ret_val = e1000e_determine_phy_address(hw);
376 if (ret_val) {
377 e_dbg("Cannot determine PHY addr. Erroring out\n");
378 return ret_val;
379 }
380 }
381
382 phy->id = 0;
383 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
384 (i++ < 100)) {
385 msleep(1);
386 ret_val = e1000e_get_phy_id(hw);
387 if (ret_val)
388 return ret_val;
389 }
390
391 /* Verify phy id */
392 switch (phy->id) {
393 case IGP03E1000_E_PHY_ID:
394 phy->type = e1000_phy_igp_3;
395 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
396 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
397 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
398 phy->ops.get_info = e1000e_get_phy_info_igp;
399 phy->ops.check_polarity = e1000_check_polarity_igp;
400 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
401 break;
402 case IFE_E_PHY_ID:
403 case IFE_PLUS_E_PHY_ID:
404 case IFE_C_E_PHY_ID:
405 phy->type = e1000_phy_ife;
406 phy->autoneg_mask = E1000_ALL_NOT_GIG;
407 phy->ops.get_info = e1000_get_phy_info_ife;
408 phy->ops.check_polarity = e1000_check_polarity_ife;
409 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
410 break;
411 case BME1000_E_PHY_ID:
412 phy->type = e1000_phy_bm;
413 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
414 phy->ops.read_reg = e1000e_read_phy_reg_bm;
415 phy->ops.write_reg = e1000e_write_phy_reg_bm;
416 phy->ops.commit = e1000e_phy_sw_reset;
417 phy->ops.get_info = e1000e_get_phy_info_m88;
418 phy->ops.check_polarity = e1000_check_polarity_m88;
419 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
420 break;
421 default:
422 return -E1000_ERR_PHY;
423 break;
424 }
425
426 return 0;
427 }
428
429 /**
430 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
431 * @hw: pointer to the HW structure
432 *
433 * Initialize family-specific NVM parameters and function
434 * pointers.
435 **/
436 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
437 {
438 struct e1000_nvm_info *nvm = &hw->nvm;
439 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
440 u32 gfpreg, sector_base_addr, sector_end_addr;
441 u16 i;
442
443 /* Can't read flash registers if the register set isn't mapped. */
444 if (!hw->flash_address) {
445 e_dbg("ERROR: Flash registers not mapped\n");
446 return -E1000_ERR_CONFIG;
447 }
448
449 nvm->type = e1000_nvm_flash_sw;
450
451 gfpreg = er32flash(ICH_FLASH_GFPREG);
452
453 /*
454 * sector_X_addr is a "sector"-aligned address (4096 bytes)
455 * Add 1 to sector_end_addr since this sector is included in
456 * the overall size.
457 */
458 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
459 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
460
461 /* flash_base_addr is byte-aligned */
462 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
463
464 /*
465 * find total size of the NVM, then cut in half since the total
466 * size represents two separate NVM banks.
467 */
468 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
469 << FLASH_SECTOR_ADDR_SHIFT;
470 nvm->flash_bank_size /= 2;
471 /* Adjust to word count */
472 nvm->flash_bank_size /= sizeof(u16);
473
474 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
475
476 /* Clear shadow ram */
477 for (i = 0; i < nvm->word_size; i++) {
478 dev_spec->shadow_ram[i].modified = false;
479 dev_spec->shadow_ram[i].value = 0xFFFF;
480 }
481
482 return 0;
483 }
484
485 /**
486 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
487 * @hw: pointer to the HW structure
488 *
489 * Initialize family-specific MAC parameters and function
490 * pointers.
491 **/
492 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
493 {
494 struct e1000_hw *hw = &adapter->hw;
495 struct e1000_mac_info *mac = &hw->mac;
496
497 /* Set media type function pointer */
498 hw->phy.media_type = e1000_media_type_copper;
499
500 /* Set mta register count */
501 mac->mta_reg_count = 32;
502 /* Set rar entry count */
503 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
504 if (mac->type == e1000_ich8lan)
505 mac->rar_entry_count--;
506 /* FWSM register */
507 mac->has_fwsm = true;
508 /* ARC subsystem not supported */
509 mac->arc_subsystem_valid = false;
510 /* Adaptive IFS supported */
511 mac->adaptive_ifs = true;
512
513 /* LED operations */
514 switch (mac->type) {
515 case e1000_ich8lan:
516 case e1000_ich9lan:
517 case e1000_ich10lan:
518 /* ID LED init */
519 mac->ops.id_led_init = e1000e_id_led_init;
520 /* setup LED */
521 mac->ops.setup_led = e1000e_setup_led_generic;
522 /* cleanup LED */
523 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
524 /* turn on/off LED */
525 mac->ops.led_on = e1000_led_on_ich8lan;
526 mac->ops.led_off = e1000_led_off_ich8lan;
527 break;
528 case e1000_pchlan:
529 /* ID LED init */
530 mac->ops.id_led_init = e1000_id_led_init_pchlan;
531 /* setup LED */
532 mac->ops.setup_led = e1000_setup_led_pchlan;
533 /* cleanup LED */
534 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
535 /* turn on/off LED */
536 mac->ops.led_on = e1000_led_on_pchlan;
537 mac->ops.led_off = e1000_led_off_pchlan;
538 break;
539 default:
540 break;
541 }
542
543 /* Enable PCS Lock-loss workaround for ICH8 */
544 if (mac->type == e1000_ich8lan)
545 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
546
547 return 0;
548 }
549
550 /**
551 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
552 * @hw: pointer to the HW structure
553 *
554 * Checks to see of the link status of the hardware has changed. If a
555 * change in link status has been detected, then we read the PHY registers
556 * to get the current speed/duplex if link exists.
557 **/
558 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
559 {
560 struct e1000_mac_info *mac = &hw->mac;
561 s32 ret_val;
562 bool link;
563
564 /*
565 * We only want to go out to the PHY registers to see if Auto-Neg
566 * has completed and/or if our link status has changed. The
567 * get_link_status flag is set upon receiving a Link Status
568 * Change or Rx Sequence Error interrupt.
569 */
570 if (!mac->get_link_status) {
571 ret_val = 0;
572 goto out;
573 }
574
575 /*
576 * First we want to see if the MII Status Register reports
577 * link. If so, then we want to get the current speed/duplex
578 * of the PHY.
579 */
580 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
581 if (ret_val)
582 goto out;
583
584 if (hw->mac.type == e1000_pchlan) {
585 ret_val = e1000_k1_gig_workaround_hv(hw, link);
586 if (ret_val)
587 goto out;
588 }
589
590 if (!link)
591 goto out; /* No link detected */
592
593 mac->get_link_status = false;
594
595 if (hw->phy.type == e1000_phy_82578) {
596 ret_val = e1000_link_stall_workaround_hv(hw);
597 if (ret_val)
598 goto out;
599 }
600
601 /*
602 * Check if there was DownShift, must be checked
603 * immediately after link-up
604 */
605 e1000e_check_downshift(hw);
606
607 /*
608 * If we are forcing speed/duplex, then we simply return since
609 * we have already determined whether we have link or not.
610 */
611 if (!mac->autoneg) {
612 ret_val = -E1000_ERR_CONFIG;
613 goto out;
614 }
615
616 /*
617 * Auto-Neg is enabled. Auto Speed Detection takes care
618 * of MAC speed/duplex configuration. So we only need to
619 * configure Collision Distance in the MAC.
620 */
621 e1000e_config_collision_dist(hw);
622
623 /*
624 * Configure Flow Control now that Auto-Neg has completed.
625 * First, we need to restore the desired flow control
626 * settings because we may have had to re-autoneg with a
627 * different link partner.
628 */
629 ret_val = e1000e_config_fc_after_link_up(hw);
630 if (ret_val)
631 e_dbg("Error configuring flow control\n");
632
633 out:
634 return ret_val;
635 }
636
637 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
638 {
639 struct e1000_hw *hw = &adapter->hw;
640 s32 rc;
641
642 rc = e1000_init_mac_params_ich8lan(adapter);
643 if (rc)
644 return rc;
645
646 rc = e1000_init_nvm_params_ich8lan(hw);
647 if (rc)
648 return rc;
649
650 if (hw->mac.type == e1000_pchlan)
651 rc = e1000_init_phy_params_pchlan(hw);
652 else
653 rc = e1000_init_phy_params_ich8lan(hw);
654 if (rc)
655 return rc;
656
657 if (adapter->hw.phy.type == e1000_phy_ife) {
658 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
659 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
660 }
661
662 if ((adapter->hw.mac.type == e1000_ich8lan) &&
663 (adapter->hw.phy.type == e1000_phy_igp_3))
664 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
665
666 return 0;
667 }
668
669 static DEFINE_MUTEX(nvm_mutex);
670
671 /**
672 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
673 * @hw: pointer to the HW structure
674 *
675 * Acquires the mutex for performing NVM operations.
676 **/
677 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
678 {
679 mutex_lock(&nvm_mutex);
680
681 return 0;
682 }
683
684 /**
685 * e1000_release_nvm_ich8lan - Release NVM mutex
686 * @hw: pointer to the HW structure
687 *
688 * Releases the mutex used while performing NVM operations.
689 **/
690 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
691 {
692 mutex_unlock(&nvm_mutex);
693
694 return;
695 }
696
697 static DEFINE_MUTEX(swflag_mutex);
698
699 /**
700 * e1000_acquire_swflag_ich8lan - Acquire software control flag
701 * @hw: pointer to the HW structure
702 *
703 * Acquires the software control flag for performing PHY and select
704 * MAC CSR accesses.
705 **/
706 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
707 {
708 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
709 s32 ret_val = 0;
710
711 mutex_lock(&swflag_mutex);
712
713 while (timeout) {
714 extcnf_ctrl = er32(EXTCNF_CTRL);
715 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
716 break;
717
718 mdelay(1);
719 timeout--;
720 }
721
722 if (!timeout) {
723 e_dbg("SW/FW/HW has locked the resource for too long.\n");
724 ret_val = -E1000_ERR_CONFIG;
725 goto out;
726 }
727
728 timeout = SW_FLAG_TIMEOUT;
729
730 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
731 ew32(EXTCNF_CTRL, extcnf_ctrl);
732
733 while (timeout) {
734 extcnf_ctrl = er32(EXTCNF_CTRL);
735 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
736 break;
737
738 mdelay(1);
739 timeout--;
740 }
741
742 if (!timeout) {
743 e_dbg("Failed to acquire the semaphore.\n");
744 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
745 ew32(EXTCNF_CTRL, extcnf_ctrl);
746 ret_val = -E1000_ERR_CONFIG;
747 goto out;
748 }
749
750 out:
751 if (ret_val)
752 mutex_unlock(&swflag_mutex);
753
754 return ret_val;
755 }
756
757 /**
758 * e1000_release_swflag_ich8lan - Release software control flag
759 * @hw: pointer to the HW structure
760 *
761 * Releases the software control flag for performing PHY and select
762 * MAC CSR accesses.
763 **/
764 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
765 {
766 u32 extcnf_ctrl;
767
768 extcnf_ctrl = er32(EXTCNF_CTRL);
769 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
770 ew32(EXTCNF_CTRL, extcnf_ctrl);
771
772 mutex_unlock(&swflag_mutex);
773
774 return;
775 }
776
777 /**
778 * e1000_check_mng_mode_ich8lan - Checks management mode
779 * @hw: pointer to the HW structure
780 *
781 * This checks if the adapter has manageability enabled.
782 * This is a function pointer entry point only called by read/write
783 * routines for the PHY and NVM parts.
784 **/
785 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
786 {
787 u32 fwsm;
788
789 fwsm = er32(FWSM);
790
791 return (fwsm & E1000_FWSM_MODE_MASK) ==
792 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
793 }
794
795 /**
796 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
797 * @hw: pointer to the HW structure
798 *
799 * Checks if firmware is blocking the reset of the PHY.
800 * This is a function pointer entry point only called by
801 * reset routines.
802 **/
803 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
804 {
805 u32 fwsm;
806
807 fwsm = er32(FWSM);
808
809 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
810 }
811
812 /**
813 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
814 * @hw: pointer to the HW structure
815 *
816 * SW should configure the LCD from the NVM extended configuration region
817 * as a workaround for certain parts.
818 **/
819 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
820 {
821 struct e1000_adapter *adapter = hw->adapter;
822 struct e1000_phy_info *phy = &hw->phy;
823 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
824 s32 ret_val = 0;
825 u16 word_addr, reg_data, reg_addr, phy_page = 0;
826
827 if (!(hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) &&
828 !(hw->mac.type == e1000_pchlan))
829 return ret_val;
830
831 ret_val = hw->phy.ops.acquire(hw);
832 if (ret_val)
833 return ret_val;
834
835 /*
836 * Initialize the PHY from the NVM on ICH platforms. This
837 * is needed due to an issue where the NVM configuration is
838 * not properly autoloaded after power transitions.
839 * Therefore, after each PHY reset, we will load the
840 * configuration data out of the NVM manually.
841 */
842 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
843 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
844 (hw->mac.type == e1000_pchlan))
845 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
846 else
847 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
848
849 data = er32(FEXTNVM);
850 if (!(data & sw_cfg_mask))
851 goto out;
852
853 /* Wait for basic configuration completes before proceeding */
854 e1000_lan_init_done_ich8lan(hw);
855
856 /*
857 * Make sure HW does not configure LCD from PHY
858 * extended configuration before SW configuration
859 */
860 data = er32(EXTCNF_CTRL);
861 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
862 goto out;
863
864 cnf_size = er32(EXTCNF_SIZE);
865 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
866 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
867 if (!cnf_size)
868 goto out;
869
870 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
871 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
872
873 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
874 (hw->mac.type == e1000_pchlan)) {
875 /*
876 * HW configures the SMBus address and LEDs when the
877 * OEM and LCD Write Enable bits are set in the NVM.
878 * When both NVM bits are cleared, SW will configure
879 * them instead.
880 */
881 data = er32(STRAP);
882 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
883 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
884 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
885 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
886 reg_data);
887 if (ret_val)
888 goto out;
889
890 data = er32(LEDCTL);
891 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
892 (u16)data);
893 if (ret_val)
894 goto out;
895 }
896
897 /* Configure LCD from extended configuration region. */
898
899 /* cnf_base_addr is in DWORD */
900 word_addr = (u16)(cnf_base_addr << 1);
901
902 for (i = 0; i < cnf_size; i++) {
903 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
904 &reg_data);
905 if (ret_val)
906 goto out;
907
908 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
909 1, &reg_addr);
910 if (ret_val)
911 goto out;
912
913 /* Save off the PHY page for future writes. */
914 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
915 phy_page = reg_data;
916 continue;
917 }
918
919 reg_addr &= PHY_REG_MASK;
920 reg_addr |= phy_page;
921
922 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
923 reg_data);
924 if (ret_val)
925 goto out;
926 }
927
928 out:
929 hw->phy.ops.release(hw);
930 return ret_val;
931 }
932
933 /**
934 * e1000_k1_gig_workaround_hv - K1 Si workaround
935 * @hw: pointer to the HW structure
936 * @link: link up bool flag
937 *
938 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
939 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
940 * If link is down, the function will restore the default K1 setting located
941 * in the NVM.
942 **/
943 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
944 {
945 s32 ret_val = 0;
946 u16 status_reg = 0;
947 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
948
949 if (hw->mac.type != e1000_pchlan)
950 goto out;
951
952 /* Wrap the whole flow with the sw flag */
953 ret_val = hw->phy.ops.acquire(hw);
954 if (ret_val)
955 goto out;
956
957 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
958 if (link) {
959 if (hw->phy.type == e1000_phy_82578) {
960 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
961 &status_reg);
962 if (ret_val)
963 goto release;
964
965 status_reg &= BM_CS_STATUS_LINK_UP |
966 BM_CS_STATUS_RESOLVED |
967 BM_CS_STATUS_SPEED_MASK;
968
969 if (status_reg == (BM_CS_STATUS_LINK_UP |
970 BM_CS_STATUS_RESOLVED |
971 BM_CS_STATUS_SPEED_1000))
972 k1_enable = false;
973 }
974
975 if (hw->phy.type == e1000_phy_82577) {
976 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
977 &status_reg);
978 if (ret_val)
979 goto release;
980
981 status_reg &= HV_M_STATUS_LINK_UP |
982 HV_M_STATUS_AUTONEG_COMPLETE |
983 HV_M_STATUS_SPEED_MASK;
984
985 if (status_reg == (HV_M_STATUS_LINK_UP |
986 HV_M_STATUS_AUTONEG_COMPLETE |
987 HV_M_STATUS_SPEED_1000))
988 k1_enable = false;
989 }
990
991 /* Link stall fix for link up */
992 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
993 0x0100);
994 if (ret_val)
995 goto release;
996
997 } else {
998 /* Link stall fix for link down */
999 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1000 0x4100);
1001 if (ret_val)
1002 goto release;
1003 }
1004
1005 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1006
1007 release:
1008 hw->phy.ops.release(hw);
1009 out:
1010 return ret_val;
1011 }
1012
1013 /**
1014 * e1000_configure_k1_ich8lan - Configure K1 power state
1015 * @hw: pointer to the HW structure
1016 * @enable: K1 state to configure
1017 *
1018 * Configure the K1 power state based on the provided parameter.
1019 * Assumes semaphore already acquired.
1020 *
1021 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1022 **/
1023 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1024 {
1025 s32 ret_val = 0;
1026 u32 ctrl_reg = 0;
1027 u32 ctrl_ext = 0;
1028 u32 reg = 0;
1029 u16 kmrn_reg = 0;
1030
1031 ret_val = e1000e_read_kmrn_reg_locked(hw,
1032 E1000_KMRNCTRLSTA_K1_CONFIG,
1033 &kmrn_reg);
1034 if (ret_val)
1035 goto out;
1036
1037 if (k1_enable)
1038 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1039 else
1040 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1041
1042 ret_val = e1000e_write_kmrn_reg_locked(hw,
1043 E1000_KMRNCTRLSTA_K1_CONFIG,
1044 kmrn_reg);
1045 if (ret_val)
1046 goto out;
1047
1048 udelay(20);
1049 ctrl_ext = er32(CTRL_EXT);
1050 ctrl_reg = er32(CTRL);
1051
1052 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1053 reg |= E1000_CTRL_FRCSPD;
1054 ew32(CTRL, reg);
1055
1056 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1057 udelay(20);
1058 ew32(CTRL, ctrl_reg);
1059 ew32(CTRL_EXT, ctrl_ext);
1060 udelay(20);
1061
1062 out:
1063 return ret_val;
1064 }
1065
1066 /**
1067 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1068 * @hw: pointer to the HW structure
1069 * @d0_state: boolean if entering d0 or d3 device state
1070 *
1071 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1072 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1073 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1074 **/
1075 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1076 {
1077 s32 ret_val = 0;
1078 u32 mac_reg;
1079 u16 oem_reg;
1080
1081 if (hw->mac.type != e1000_pchlan)
1082 return ret_val;
1083
1084 ret_val = hw->phy.ops.acquire(hw);
1085 if (ret_val)
1086 return ret_val;
1087
1088 mac_reg = er32(EXTCNF_CTRL);
1089 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1090 goto out;
1091
1092 mac_reg = er32(FEXTNVM);
1093 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1094 goto out;
1095
1096 mac_reg = er32(PHY_CTRL);
1097
1098 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1099 if (ret_val)
1100 goto out;
1101
1102 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1103
1104 if (d0_state) {
1105 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1106 oem_reg |= HV_OEM_BITS_GBE_DIS;
1107
1108 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1109 oem_reg |= HV_OEM_BITS_LPLU;
1110 } else {
1111 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1112 oem_reg |= HV_OEM_BITS_GBE_DIS;
1113
1114 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1115 oem_reg |= HV_OEM_BITS_LPLU;
1116 }
1117 /* Restart auto-neg to activate the bits */
1118 if (!e1000_check_reset_block(hw))
1119 oem_reg |= HV_OEM_BITS_RESTART_AN;
1120 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1121
1122 out:
1123 hw->phy.ops.release(hw);
1124
1125 return ret_val;
1126 }
1127
1128
1129 /**
1130 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1131 * @hw: pointer to the HW structure
1132 **/
1133 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1134 {
1135 s32 ret_val;
1136 u16 data;
1137
1138 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1139 if (ret_val)
1140 return ret_val;
1141
1142 data |= HV_KMRN_MDIO_SLOW;
1143
1144 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1145
1146 return ret_val;
1147 }
1148
1149 /**
1150 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1151 * done after every PHY reset.
1152 **/
1153 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1154 {
1155 s32 ret_val = 0;
1156 u16 phy_data;
1157
1158 if (hw->mac.type != e1000_pchlan)
1159 return ret_val;
1160
1161 /* Set MDIO slow mode before any other MDIO access */
1162 if (hw->phy.type == e1000_phy_82577) {
1163 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1164 if (ret_val)
1165 goto out;
1166 }
1167
1168 if (((hw->phy.type == e1000_phy_82577) &&
1169 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1170 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1171 /* Disable generation of early preamble */
1172 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1173 if (ret_val)
1174 return ret_val;
1175
1176 /* Preamble tuning for SSC */
1177 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1178 if (ret_val)
1179 return ret_val;
1180 }
1181
1182 if (hw->phy.type == e1000_phy_82578) {
1183 /*
1184 * Return registers to default by doing a soft reset then
1185 * writing 0x3140 to the control register.
1186 */
1187 if (hw->phy.revision < 2) {
1188 e1000e_phy_sw_reset(hw);
1189 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1190 }
1191 }
1192
1193 /* Select page 0 */
1194 ret_val = hw->phy.ops.acquire(hw);
1195 if (ret_val)
1196 return ret_val;
1197
1198 hw->phy.addr = 1;
1199 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1200 hw->phy.ops.release(hw);
1201 if (ret_val)
1202 goto out;
1203
1204 /*
1205 * Configure the K1 Si workaround during phy reset assuming there is
1206 * link so that it disables K1 if link is in 1Gbps.
1207 */
1208 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1209 if (ret_val)
1210 goto out;
1211
1212 /* Workaround for link disconnects on a busy hub in half duplex */
1213 ret_val = hw->phy.ops.acquire(hw);
1214 if (ret_val)
1215 goto out;
1216 ret_val = hw->phy.ops.read_reg_locked(hw,
1217 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1218 &phy_data);
1219 if (ret_val)
1220 goto release;
1221 ret_val = hw->phy.ops.write_reg_locked(hw,
1222 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1223 phy_data & 0x00FF);
1224 release:
1225 hw->phy.ops.release(hw);
1226 out:
1227 return ret_val;
1228 }
1229
1230 /**
1231 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1232 * @hw: pointer to the HW structure
1233 *
1234 * Check the appropriate indication the MAC has finished configuring the
1235 * PHY after a software reset.
1236 **/
1237 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1238 {
1239 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1240
1241 /* Wait for basic configuration completes before proceeding */
1242 do {
1243 data = er32(STATUS);
1244 data &= E1000_STATUS_LAN_INIT_DONE;
1245 udelay(100);
1246 } while ((!data) && --loop);
1247
1248 /*
1249 * If basic configuration is incomplete before the above loop
1250 * count reaches 0, loading the configuration from NVM will
1251 * leave the PHY in a bad state possibly resulting in no link.
1252 */
1253 if (loop == 0)
1254 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1255
1256 /* Clear the Init Done bit for the next init event */
1257 data = er32(STATUS);
1258 data &= ~E1000_STATUS_LAN_INIT_DONE;
1259 ew32(STATUS, data);
1260 }
1261
1262 /**
1263 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1264 * @hw: pointer to the HW structure
1265 *
1266 * Resets the PHY
1267 * This is a function pointer entry point called by drivers
1268 * or other shared routines.
1269 **/
1270 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1271 {
1272 s32 ret_val = 0;
1273 u16 reg;
1274
1275 ret_val = e1000e_phy_hw_reset_generic(hw);
1276 if (ret_val)
1277 return ret_val;
1278
1279 /* Allow time for h/w to get to a quiescent state after reset */
1280 mdelay(10);
1281
1282 /* Perform any necessary post-reset workarounds */
1283 if (hw->mac.type == e1000_pchlan) {
1284 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1285 if (ret_val)
1286 return ret_val;
1287 }
1288
1289 /* Dummy read to clear the phy wakeup bit after lcd reset */
1290 if (hw->mac.type == e1000_pchlan)
1291 e1e_rphy(hw, BM_WUC, &reg);
1292
1293 /* Configure the LCD with the extended configuration region in NVM */
1294 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1295 if (ret_val)
1296 goto out;
1297
1298 /* Configure the LCD with the OEM bits in NVM */
1299 if (hw->mac.type == e1000_pchlan)
1300 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1301
1302 out:
1303 return 0;
1304 }
1305
1306 /**
1307 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1308 * @hw: pointer to the HW structure
1309 * @active: true to enable LPLU, false to disable
1310 *
1311 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1312 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1313 * the phy speed. This function will manually set the LPLU bit and restart
1314 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1315 * since it configures the same bit.
1316 **/
1317 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1318 {
1319 s32 ret_val = 0;
1320 u16 oem_reg;
1321
1322 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1323 if (ret_val)
1324 goto out;
1325
1326 if (active)
1327 oem_reg |= HV_OEM_BITS_LPLU;
1328 else
1329 oem_reg &= ~HV_OEM_BITS_LPLU;
1330
1331 oem_reg |= HV_OEM_BITS_RESTART_AN;
1332 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1333
1334 out:
1335 return ret_val;
1336 }
1337
1338 /**
1339 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1340 * @hw: pointer to the HW structure
1341 * @active: true to enable LPLU, false to disable
1342 *
1343 * Sets the LPLU D0 state according to the active flag. When
1344 * activating LPLU this function also disables smart speed
1345 * and vice versa. LPLU will not be activated unless the
1346 * device autonegotiation advertisement meets standards of
1347 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1348 * This is a function pointer entry point only called by
1349 * PHY setup routines.
1350 **/
1351 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1352 {
1353 struct e1000_phy_info *phy = &hw->phy;
1354 u32 phy_ctrl;
1355 s32 ret_val = 0;
1356 u16 data;
1357
1358 if (phy->type == e1000_phy_ife)
1359 return ret_val;
1360
1361 phy_ctrl = er32(PHY_CTRL);
1362
1363 if (active) {
1364 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1365 ew32(PHY_CTRL, phy_ctrl);
1366
1367 if (phy->type != e1000_phy_igp_3)
1368 return 0;
1369
1370 /*
1371 * Call gig speed drop workaround on LPLU before accessing
1372 * any PHY registers
1373 */
1374 if (hw->mac.type == e1000_ich8lan)
1375 e1000e_gig_downshift_workaround_ich8lan(hw);
1376
1377 /* When LPLU is enabled, we should disable SmartSpeed */
1378 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1379 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1380 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1381 if (ret_val)
1382 return ret_val;
1383 } else {
1384 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1385 ew32(PHY_CTRL, phy_ctrl);
1386
1387 if (phy->type != e1000_phy_igp_3)
1388 return 0;
1389
1390 /*
1391 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1392 * during Dx states where the power conservation is most
1393 * important. During driver activity we should enable
1394 * SmartSpeed, so performance is maintained.
1395 */
1396 if (phy->smart_speed == e1000_smart_speed_on) {
1397 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1398 &data);
1399 if (ret_val)
1400 return ret_val;
1401
1402 data |= IGP01E1000_PSCFR_SMART_SPEED;
1403 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1404 data);
1405 if (ret_val)
1406 return ret_val;
1407 } else if (phy->smart_speed == e1000_smart_speed_off) {
1408 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1409 &data);
1410 if (ret_val)
1411 return ret_val;
1412
1413 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1414 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1415 data);
1416 if (ret_val)
1417 return ret_val;
1418 }
1419 }
1420
1421 return 0;
1422 }
1423
1424 /**
1425 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1426 * @hw: pointer to the HW structure
1427 * @active: true to enable LPLU, false to disable
1428 *
1429 * Sets the LPLU D3 state according to the active flag. When
1430 * activating LPLU this function also disables smart speed
1431 * and vice versa. LPLU will not be activated unless the
1432 * device autonegotiation advertisement meets standards of
1433 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1434 * This is a function pointer entry point only called by
1435 * PHY setup routines.
1436 **/
1437 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1438 {
1439 struct e1000_phy_info *phy = &hw->phy;
1440 u32 phy_ctrl;
1441 s32 ret_val;
1442 u16 data;
1443
1444 phy_ctrl = er32(PHY_CTRL);
1445
1446 if (!active) {
1447 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1448 ew32(PHY_CTRL, phy_ctrl);
1449
1450 if (phy->type != e1000_phy_igp_3)
1451 return 0;
1452
1453 /*
1454 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1455 * during Dx states where the power conservation is most
1456 * important. During driver activity we should enable
1457 * SmartSpeed, so performance is maintained.
1458 */
1459 if (phy->smart_speed == e1000_smart_speed_on) {
1460 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1461 &data);
1462 if (ret_val)
1463 return ret_val;
1464
1465 data |= IGP01E1000_PSCFR_SMART_SPEED;
1466 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1467 data);
1468 if (ret_val)
1469 return ret_val;
1470 } else if (phy->smart_speed == e1000_smart_speed_off) {
1471 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1472 &data);
1473 if (ret_val)
1474 return ret_val;
1475
1476 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1477 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1478 data);
1479 if (ret_val)
1480 return ret_val;
1481 }
1482 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1483 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1484 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1485 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1486 ew32(PHY_CTRL, phy_ctrl);
1487
1488 if (phy->type != e1000_phy_igp_3)
1489 return 0;
1490
1491 /*
1492 * Call gig speed drop workaround on LPLU before accessing
1493 * any PHY registers
1494 */
1495 if (hw->mac.type == e1000_ich8lan)
1496 e1000e_gig_downshift_workaround_ich8lan(hw);
1497
1498 /* When LPLU is enabled, we should disable SmartSpeed */
1499 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1500 if (ret_val)
1501 return ret_val;
1502
1503 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1504 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1505 }
1506
1507 return 0;
1508 }
1509
1510 /**
1511 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1512 * @hw: pointer to the HW structure
1513 * @bank: pointer to the variable that returns the active bank
1514 *
1515 * Reads signature byte from the NVM using the flash access registers.
1516 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1517 **/
1518 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1519 {
1520 u32 eecd;
1521 struct e1000_nvm_info *nvm = &hw->nvm;
1522 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1523 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1524 u8 sig_byte = 0;
1525 s32 ret_val = 0;
1526
1527 switch (hw->mac.type) {
1528 case e1000_ich8lan:
1529 case e1000_ich9lan:
1530 eecd = er32(EECD);
1531 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1532 E1000_EECD_SEC1VAL_VALID_MASK) {
1533 if (eecd & E1000_EECD_SEC1VAL)
1534 *bank = 1;
1535 else
1536 *bank = 0;
1537
1538 return 0;
1539 }
1540 e_dbg("Unable to determine valid NVM bank via EEC - "
1541 "reading flash signature\n");
1542 /* fall-thru */
1543 default:
1544 /* set bank to 0 in case flash read fails */
1545 *bank = 0;
1546
1547 /* Check bank 0 */
1548 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1549 &sig_byte);
1550 if (ret_val)
1551 return ret_val;
1552 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1553 E1000_ICH_NVM_SIG_VALUE) {
1554 *bank = 0;
1555 return 0;
1556 }
1557
1558 /* Check bank 1 */
1559 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1560 bank1_offset,
1561 &sig_byte);
1562 if (ret_val)
1563 return ret_val;
1564 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1565 E1000_ICH_NVM_SIG_VALUE) {
1566 *bank = 1;
1567 return 0;
1568 }
1569
1570 e_dbg("ERROR: No valid NVM bank present\n");
1571 return -E1000_ERR_NVM;
1572 }
1573
1574 return 0;
1575 }
1576
1577 /**
1578 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1579 * @hw: pointer to the HW structure
1580 * @offset: The offset (in bytes) of the word(s) to read.
1581 * @words: Size of data to read in words
1582 * @data: Pointer to the word(s) to read at offset.
1583 *
1584 * Reads a word(s) from the NVM using the flash access registers.
1585 **/
1586 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1587 u16 *data)
1588 {
1589 struct e1000_nvm_info *nvm = &hw->nvm;
1590 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1591 u32 act_offset;
1592 s32 ret_val = 0;
1593 u32 bank = 0;
1594 u16 i, word;
1595
1596 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1597 (words == 0)) {
1598 e_dbg("nvm parameter(s) out of bounds\n");
1599 ret_val = -E1000_ERR_NVM;
1600 goto out;
1601 }
1602
1603 nvm->ops.acquire(hw);
1604
1605 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1606 if (ret_val) {
1607 e_dbg("Could not detect valid bank, assuming bank 0\n");
1608 bank = 0;
1609 }
1610
1611 act_offset = (bank) ? nvm->flash_bank_size : 0;
1612 act_offset += offset;
1613
1614 ret_val = 0;
1615 for (i = 0; i < words; i++) {
1616 if ((dev_spec->shadow_ram) &&
1617 (dev_spec->shadow_ram[offset+i].modified)) {
1618 data[i] = dev_spec->shadow_ram[offset+i].value;
1619 } else {
1620 ret_val = e1000_read_flash_word_ich8lan(hw,
1621 act_offset + i,
1622 &word);
1623 if (ret_val)
1624 break;
1625 data[i] = word;
1626 }
1627 }
1628
1629 nvm->ops.release(hw);
1630
1631 out:
1632 if (ret_val)
1633 e_dbg("NVM read error: %d\n", ret_val);
1634
1635 return ret_val;
1636 }
1637
1638 /**
1639 * e1000_flash_cycle_init_ich8lan - Initialize flash
1640 * @hw: pointer to the HW structure
1641 *
1642 * This function does initial flash setup so that a new read/write/erase cycle
1643 * can be started.
1644 **/
1645 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1646 {
1647 union ich8_hws_flash_status hsfsts;
1648 s32 ret_val = -E1000_ERR_NVM;
1649 s32 i = 0;
1650
1651 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1652
1653 /* Check if the flash descriptor is valid */
1654 if (hsfsts.hsf_status.fldesvalid == 0) {
1655 e_dbg("Flash descriptor invalid. "
1656 "SW Sequencing must be used.\n");
1657 return -E1000_ERR_NVM;
1658 }
1659
1660 /* Clear FCERR and DAEL in hw status by writing 1 */
1661 hsfsts.hsf_status.flcerr = 1;
1662 hsfsts.hsf_status.dael = 1;
1663
1664 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1665
1666 /*
1667 * Either we should have a hardware SPI cycle in progress
1668 * bit to check against, in order to start a new cycle or
1669 * FDONE bit should be changed in the hardware so that it
1670 * is 1 after hardware reset, which can then be used as an
1671 * indication whether a cycle is in progress or has been
1672 * completed.
1673 */
1674
1675 if (hsfsts.hsf_status.flcinprog == 0) {
1676 /*
1677 * There is no cycle running at present,
1678 * so we can start a cycle.
1679 * Begin by setting Flash Cycle Done.
1680 */
1681 hsfsts.hsf_status.flcdone = 1;
1682 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1683 ret_val = 0;
1684 } else {
1685 /*
1686 * Otherwise poll for sometime so the current
1687 * cycle has a chance to end before giving up.
1688 */
1689 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1690 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1691 if (hsfsts.hsf_status.flcinprog == 0) {
1692 ret_val = 0;
1693 break;
1694 }
1695 udelay(1);
1696 }
1697 if (ret_val == 0) {
1698 /*
1699 * Successful in waiting for previous cycle to timeout,
1700 * now set the Flash Cycle Done.
1701 */
1702 hsfsts.hsf_status.flcdone = 1;
1703 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1704 } else {
1705 e_dbg("Flash controller busy, cannot get access\n");
1706 }
1707 }
1708
1709 return ret_val;
1710 }
1711
1712 /**
1713 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1714 * @hw: pointer to the HW structure
1715 * @timeout: maximum time to wait for completion
1716 *
1717 * This function starts a flash cycle and waits for its completion.
1718 **/
1719 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1720 {
1721 union ich8_hws_flash_ctrl hsflctl;
1722 union ich8_hws_flash_status hsfsts;
1723 s32 ret_val = -E1000_ERR_NVM;
1724 u32 i = 0;
1725
1726 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1727 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1728 hsflctl.hsf_ctrl.flcgo = 1;
1729 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1730
1731 /* wait till FDONE bit is set to 1 */
1732 do {
1733 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1734 if (hsfsts.hsf_status.flcdone == 1)
1735 break;
1736 udelay(1);
1737 } while (i++ < timeout);
1738
1739 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1740 return 0;
1741
1742 return ret_val;
1743 }
1744
1745 /**
1746 * e1000_read_flash_word_ich8lan - Read word from flash
1747 * @hw: pointer to the HW structure
1748 * @offset: offset to data location
1749 * @data: pointer to the location for storing the data
1750 *
1751 * Reads the flash word at offset into data. Offset is converted
1752 * to bytes before read.
1753 **/
1754 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1755 u16 *data)
1756 {
1757 /* Must convert offset into bytes. */
1758 offset <<= 1;
1759
1760 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1761 }
1762
1763 /**
1764 * e1000_read_flash_byte_ich8lan - Read byte from flash
1765 * @hw: pointer to the HW structure
1766 * @offset: The offset of the byte to read.
1767 * @data: Pointer to a byte to store the value read.
1768 *
1769 * Reads a single byte from the NVM using the flash access registers.
1770 **/
1771 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1772 u8 *data)
1773 {
1774 s32 ret_val;
1775 u16 word = 0;
1776
1777 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1778 if (ret_val)
1779 return ret_val;
1780
1781 *data = (u8)word;
1782
1783 return 0;
1784 }
1785
1786 /**
1787 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1788 * @hw: pointer to the HW structure
1789 * @offset: The offset (in bytes) of the byte or word to read.
1790 * @size: Size of data to read, 1=byte 2=word
1791 * @data: Pointer to the word to store the value read.
1792 *
1793 * Reads a byte or word from the NVM using the flash access registers.
1794 **/
1795 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1796 u8 size, u16 *data)
1797 {
1798 union ich8_hws_flash_status hsfsts;
1799 union ich8_hws_flash_ctrl hsflctl;
1800 u32 flash_linear_addr;
1801 u32 flash_data = 0;
1802 s32 ret_val = -E1000_ERR_NVM;
1803 u8 count = 0;
1804
1805 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1806 return -E1000_ERR_NVM;
1807
1808 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1809 hw->nvm.flash_base_addr;
1810
1811 do {
1812 udelay(1);
1813 /* Steps */
1814 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1815 if (ret_val != 0)
1816 break;
1817
1818 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1819 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1820 hsflctl.hsf_ctrl.fldbcount = size - 1;
1821 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1822 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1823
1824 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1825
1826 ret_val = e1000_flash_cycle_ich8lan(hw,
1827 ICH_FLASH_READ_COMMAND_TIMEOUT);
1828
1829 /*
1830 * Check if FCERR is set to 1, if set to 1, clear it
1831 * and try the whole sequence a few more times, else
1832 * read in (shift in) the Flash Data0, the order is
1833 * least significant byte first msb to lsb
1834 */
1835 if (ret_val == 0) {
1836 flash_data = er32flash(ICH_FLASH_FDATA0);
1837 if (size == 1) {
1838 *data = (u8)(flash_data & 0x000000FF);
1839 } else if (size == 2) {
1840 *data = (u16)(flash_data & 0x0000FFFF);
1841 }
1842 break;
1843 } else {
1844 /*
1845 * If we've gotten here, then things are probably
1846 * completely hosed, but if the error condition is
1847 * detected, it won't hurt to give it another try...
1848 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1849 */
1850 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1851 if (hsfsts.hsf_status.flcerr == 1) {
1852 /* Repeat for some time before giving up. */
1853 continue;
1854 } else if (hsfsts.hsf_status.flcdone == 0) {
1855 e_dbg("Timeout error - flash cycle "
1856 "did not complete.\n");
1857 break;
1858 }
1859 }
1860 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1861
1862 return ret_val;
1863 }
1864
1865 /**
1866 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1867 * @hw: pointer to the HW structure
1868 * @offset: The offset (in bytes) of the word(s) to write.
1869 * @words: Size of data to write in words
1870 * @data: Pointer to the word(s) to write at offset.
1871 *
1872 * Writes a byte or word to the NVM using the flash access registers.
1873 **/
1874 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1875 u16 *data)
1876 {
1877 struct e1000_nvm_info *nvm = &hw->nvm;
1878 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1879 u16 i;
1880
1881 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1882 (words == 0)) {
1883 e_dbg("nvm parameter(s) out of bounds\n");
1884 return -E1000_ERR_NVM;
1885 }
1886
1887 nvm->ops.acquire(hw);
1888
1889 for (i = 0; i < words; i++) {
1890 dev_spec->shadow_ram[offset+i].modified = true;
1891 dev_spec->shadow_ram[offset+i].value = data[i];
1892 }
1893
1894 nvm->ops.release(hw);
1895
1896 return 0;
1897 }
1898
1899 /**
1900 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1901 * @hw: pointer to the HW structure
1902 *
1903 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1904 * which writes the checksum to the shadow ram. The changes in the shadow
1905 * ram are then committed to the EEPROM by processing each bank at a time
1906 * checking for the modified bit and writing only the pending changes.
1907 * After a successful commit, the shadow ram is cleared and is ready for
1908 * future writes.
1909 **/
1910 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1911 {
1912 struct e1000_nvm_info *nvm = &hw->nvm;
1913 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1914 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1915 s32 ret_val;
1916 u16 data;
1917
1918 ret_val = e1000e_update_nvm_checksum_generic(hw);
1919 if (ret_val)
1920 goto out;
1921
1922 if (nvm->type != e1000_nvm_flash_sw)
1923 goto out;
1924
1925 nvm->ops.acquire(hw);
1926
1927 /*
1928 * We're writing to the opposite bank so if we're on bank 1,
1929 * write to bank 0 etc. We also need to erase the segment that
1930 * is going to be written
1931 */
1932 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1933 if (ret_val) {
1934 e_dbg("Could not detect valid bank, assuming bank 0\n");
1935 bank = 0;
1936 }
1937
1938 if (bank == 0) {
1939 new_bank_offset = nvm->flash_bank_size;
1940 old_bank_offset = 0;
1941 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1942 if (ret_val)
1943 goto release;
1944 } else {
1945 old_bank_offset = nvm->flash_bank_size;
1946 new_bank_offset = 0;
1947 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1948 if (ret_val)
1949 goto release;
1950 }
1951
1952 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1953 /*
1954 * Determine whether to write the value stored
1955 * in the other NVM bank or a modified value stored
1956 * in the shadow RAM
1957 */
1958 if (dev_spec->shadow_ram[i].modified) {
1959 data = dev_spec->shadow_ram[i].value;
1960 } else {
1961 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1962 old_bank_offset,
1963 &data);
1964 if (ret_val)
1965 break;
1966 }
1967
1968 /*
1969 * If the word is 0x13, then make sure the signature bits
1970 * (15:14) are 11b until the commit has completed.
1971 * This will allow us to write 10b which indicates the
1972 * signature is valid. We want to do this after the write
1973 * has completed so that we don't mark the segment valid
1974 * while the write is still in progress
1975 */
1976 if (i == E1000_ICH_NVM_SIG_WORD)
1977 data |= E1000_ICH_NVM_SIG_MASK;
1978
1979 /* Convert offset to bytes. */
1980 act_offset = (i + new_bank_offset) << 1;
1981
1982 udelay(100);
1983 /* Write the bytes to the new bank. */
1984 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1985 act_offset,
1986 (u8)data);
1987 if (ret_val)
1988 break;
1989
1990 udelay(100);
1991 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1992 act_offset + 1,
1993 (u8)(data >> 8));
1994 if (ret_val)
1995 break;
1996 }
1997
1998 /*
1999 * Don't bother writing the segment valid bits if sector
2000 * programming failed.
2001 */
2002 if (ret_val) {
2003 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2004 e_dbg("Flash commit failed.\n");
2005 goto release;
2006 }
2007
2008 /*
2009 * Finally validate the new segment by setting bit 15:14
2010 * to 10b in word 0x13 , this can be done without an
2011 * erase as well since these bits are 11 to start with
2012 * and we need to change bit 14 to 0b
2013 */
2014 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2015 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2016 if (ret_val)
2017 goto release;
2018
2019 data &= 0xBFFF;
2020 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2021 act_offset * 2 + 1,
2022 (u8)(data >> 8));
2023 if (ret_val)
2024 goto release;
2025
2026 /*
2027 * And invalidate the previously valid segment by setting
2028 * its signature word (0x13) high_byte to 0b. This can be
2029 * done without an erase because flash erase sets all bits
2030 * to 1's. We can write 1's to 0's without an erase
2031 */
2032 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2033 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2034 if (ret_val)
2035 goto release;
2036
2037 /* Great! Everything worked, we can now clear the cached entries. */
2038 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2039 dev_spec->shadow_ram[i].modified = false;
2040 dev_spec->shadow_ram[i].value = 0xFFFF;
2041 }
2042
2043 release:
2044 nvm->ops.release(hw);
2045
2046 /*
2047 * Reload the EEPROM, or else modifications will not appear
2048 * until after the next adapter reset.
2049 */
2050 if (!ret_val) {
2051 e1000e_reload_nvm(hw);
2052 msleep(10);
2053 }
2054
2055 out:
2056 if (ret_val)
2057 e_dbg("NVM update error: %d\n", ret_val);
2058
2059 return ret_val;
2060 }
2061
2062 /**
2063 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2064 * @hw: pointer to the HW structure
2065 *
2066 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2067 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2068 * calculated, in which case we need to calculate the checksum and set bit 6.
2069 **/
2070 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2071 {
2072 s32 ret_val;
2073 u16 data;
2074
2075 /*
2076 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2077 * needs to be fixed. This bit is an indication that the NVM
2078 * was prepared by OEM software and did not calculate the
2079 * checksum...a likely scenario.
2080 */
2081 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2082 if (ret_val)
2083 return ret_val;
2084
2085 if ((data & 0x40) == 0) {
2086 data |= 0x40;
2087 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2088 if (ret_val)
2089 return ret_val;
2090 ret_val = e1000e_update_nvm_checksum(hw);
2091 if (ret_val)
2092 return ret_val;
2093 }
2094
2095 return e1000e_validate_nvm_checksum_generic(hw);
2096 }
2097
2098 /**
2099 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2100 * @hw: pointer to the HW structure
2101 *
2102 * To prevent malicious write/erase of the NVM, set it to be read-only
2103 * so that the hardware ignores all write/erase cycles of the NVM via
2104 * the flash control registers. The shadow-ram copy of the NVM will
2105 * still be updated, however any updates to this copy will not stick
2106 * across driver reloads.
2107 **/
2108 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2109 {
2110 struct e1000_nvm_info *nvm = &hw->nvm;
2111 union ich8_flash_protected_range pr0;
2112 union ich8_hws_flash_status hsfsts;
2113 u32 gfpreg;
2114
2115 nvm->ops.acquire(hw);
2116
2117 gfpreg = er32flash(ICH_FLASH_GFPREG);
2118
2119 /* Write-protect GbE Sector of NVM */
2120 pr0.regval = er32flash(ICH_FLASH_PR0);
2121 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2122 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2123 pr0.range.wpe = true;
2124 ew32flash(ICH_FLASH_PR0, pr0.regval);
2125
2126 /*
2127 * Lock down a subset of GbE Flash Control Registers, e.g.
2128 * PR0 to prevent the write-protection from being lifted.
2129 * Once FLOCKDN is set, the registers protected by it cannot
2130 * be written until FLOCKDN is cleared by a hardware reset.
2131 */
2132 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2133 hsfsts.hsf_status.flockdn = true;
2134 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2135
2136 nvm->ops.release(hw);
2137 }
2138
2139 /**
2140 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2141 * @hw: pointer to the HW structure
2142 * @offset: The offset (in bytes) of the byte/word to read.
2143 * @size: Size of data to read, 1=byte 2=word
2144 * @data: The byte(s) to write to the NVM.
2145 *
2146 * Writes one/two bytes to the NVM using the flash access registers.
2147 **/
2148 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2149 u8 size, u16 data)
2150 {
2151 union ich8_hws_flash_status hsfsts;
2152 union ich8_hws_flash_ctrl hsflctl;
2153 u32 flash_linear_addr;
2154 u32 flash_data = 0;
2155 s32 ret_val;
2156 u8 count = 0;
2157
2158 if (size < 1 || size > 2 || data > size * 0xff ||
2159 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2160 return -E1000_ERR_NVM;
2161
2162 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2163 hw->nvm.flash_base_addr;
2164
2165 do {
2166 udelay(1);
2167 /* Steps */
2168 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2169 if (ret_val)
2170 break;
2171
2172 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2173 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2174 hsflctl.hsf_ctrl.fldbcount = size -1;
2175 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2176 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2177
2178 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2179
2180 if (size == 1)
2181 flash_data = (u32)data & 0x00FF;
2182 else
2183 flash_data = (u32)data;
2184
2185 ew32flash(ICH_FLASH_FDATA0, flash_data);
2186
2187 /*
2188 * check if FCERR is set to 1 , if set to 1, clear it
2189 * and try the whole sequence a few more times else done
2190 */
2191 ret_val = e1000_flash_cycle_ich8lan(hw,
2192 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2193 if (!ret_val)
2194 break;
2195
2196 /*
2197 * If we're here, then things are most likely
2198 * completely hosed, but if the error condition
2199 * is detected, it won't hurt to give it another
2200 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2201 */
2202 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2203 if (hsfsts.hsf_status.flcerr == 1)
2204 /* Repeat for some time before giving up. */
2205 continue;
2206 if (hsfsts.hsf_status.flcdone == 0) {
2207 e_dbg("Timeout error - flash cycle "
2208 "did not complete.");
2209 break;
2210 }
2211 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2212
2213 return ret_val;
2214 }
2215
2216 /**
2217 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2218 * @hw: pointer to the HW structure
2219 * @offset: The index of the byte to read.
2220 * @data: The byte to write to the NVM.
2221 *
2222 * Writes a single byte to the NVM using the flash access registers.
2223 **/
2224 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2225 u8 data)
2226 {
2227 u16 word = (u16)data;
2228
2229 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2230 }
2231
2232 /**
2233 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2234 * @hw: pointer to the HW structure
2235 * @offset: The offset of the byte to write.
2236 * @byte: The byte to write to the NVM.
2237 *
2238 * Writes a single byte to the NVM using the flash access registers.
2239 * Goes through a retry algorithm before giving up.
2240 **/
2241 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2242 u32 offset, u8 byte)
2243 {
2244 s32 ret_val;
2245 u16 program_retries;
2246
2247 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2248 if (!ret_val)
2249 return ret_val;
2250
2251 for (program_retries = 0; program_retries < 100; program_retries++) {
2252 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2253 udelay(100);
2254 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2255 if (!ret_val)
2256 break;
2257 }
2258 if (program_retries == 100)
2259 return -E1000_ERR_NVM;
2260
2261 return 0;
2262 }
2263
2264 /**
2265 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2266 * @hw: pointer to the HW structure
2267 * @bank: 0 for first bank, 1 for second bank, etc.
2268 *
2269 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2270 * bank N is 4096 * N + flash_reg_addr.
2271 **/
2272 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2273 {
2274 struct e1000_nvm_info *nvm = &hw->nvm;
2275 union ich8_hws_flash_status hsfsts;
2276 union ich8_hws_flash_ctrl hsflctl;
2277 u32 flash_linear_addr;
2278 /* bank size is in 16bit words - adjust to bytes */
2279 u32 flash_bank_size = nvm->flash_bank_size * 2;
2280 s32 ret_val;
2281 s32 count = 0;
2282 s32 j, iteration, sector_size;
2283
2284 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2285
2286 /*
2287 * Determine HW Sector size: Read BERASE bits of hw flash status
2288 * register
2289 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2290 * consecutive sectors. The start index for the nth Hw sector
2291 * can be calculated as = bank * 4096 + n * 256
2292 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2293 * The start index for the nth Hw sector can be calculated
2294 * as = bank * 4096
2295 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2296 * (ich9 only, otherwise error condition)
2297 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2298 */
2299 switch (hsfsts.hsf_status.berasesz) {
2300 case 0:
2301 /* Hw sector size 256 */
2302 sector_size = ICH_FLASH_SEG_SIZE_256;
2303 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2304 break;
2305 case 1:
2306 sector_size = ICH_FLASH_SEG_SIZE_4K;
2307 iteration = 1;
2308 break;
2309 case 2:
2310 sector_size = ICH_FLASH_SEG_SIZE_8K;
2311 iteration = 1;
2312 break;
2313 case 3:
2314 sector_size = ICH_FLASH_SEG_SIZE_64K;
2315 iteration = 1;
2316 break;
2317 default:
2318 return -E1000_ERR_NVM;
2319 }
2320
2321 /* Start with the base address, then add the sector offset. */
2322 flash_linear_addr = hw->nvm.flash_base_addr;
2323 flash_linear_addr += (bank) ? flash_bank_size : 0;
2324
2325 for (j = 0; j < iteration ; j++) {
2326 do {
2327 /* Steps */
2328 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2329 if (ret_val)
2330 return ret_val;
2331
2332 /*
2333 * Write a value 11 (block Erase) in Flash
2334 * Cycle field in hw flash control
2335 */
2336 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2337 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2338 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2339
2340 /*
2341 * Write the last 24 bits of an index within the
2342 * block into Flash Linear address field in Flash
2343 * Address.
2344 */
2345 flash_linear_addr += (j * sector_size);
2346 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2347
2348 ret_val = e1000_flash_cycle_ich8lan(hw,
2349 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2350 if (ret_val == 0)
2351 break;
2352
2353 /*
2354 * Check if FCERR is set to 1. If 1,
2355 * clear it and try the whole sequence
2356 * a few more times else Done
2357 */
2358 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2359 if (hsfsts.hsf_status.flcerr == 1)
2360 /* repeat for some time before giving up */
2361 continue;
2362 else if (hsfsts.hsf_status.flcdone == 0)
2363 return ret_val;
2364 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2365 }
2366
2367 return 0;
2368 }
2369
2370 /**
2371 * e1000_valid_led_default_ich8lan - Set the default LED settings
2372 * @hw: pointer to the HW structure
2373 * @data: Pointer to the LED settings
2374 *
2375 * Reads the LED default settings from the NVM to data. If the NVM LED
2376 * settings is all 0's or F's, set the LED default to a valid LED default
2377 * setting.
2378 **/
2379 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2380 {
2381 s32 ret_val;
2382
2383 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2384 if (ret_val) {
2385 e_dbg("NVM Read Error\n");
2386 return ret_val;
2387 }
2388
2389 if (*data == ID_LED_RESERVED_0000 ||
2390 *data == ID_LED_RESERVED_FFFF)
2391 *data = ID_LED_DEFAULT_ICH8LAN;
2392
2393 return 0;
2394 }
2395
2396 /**
2397 * e1000_id_led_init_pchlan - store LED configurations
2398 * @hw: pointer to the HW structure
2399 *
2400 * PCH does not control LEDs via the LEDCTL register, rather it uses
2401 * the PHY LED configuration register.
2402 *
2403 * PCH also does not have an "always on" or "always off" mode which
2404 * complicates the ID feature. Instead of using the "on" mode to indicate
2405 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2406 * use "link_up" mode. The LEDs will still ID on request if there is no
2407 * link based on logic in e1000_led_[on|off]_pchlan().
2408 **/
2409 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2410 {
2411 struct e1000_mac_info *mac = &hw->mac;
2412 s32 ret_val;
2413 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2414 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2415 u16 data, i, temp, shift;
2416
2417 /* Get default ID LED modes */
2418 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2419 if (ret_val)
2420 goto out;
2421
2422 mac->ledctl_default = er32(LEDCTL);
2423 mac->ledctl_mode1 = mac->ledctl_default;
2424 mac->ledctl_mode2 = mac->ledctl_default;
2425
2426 for (i = 0; i < 4; i++) {
2427 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2428 shift = (i * 5);
2429 switch (temp) {
2430 case ID_LED_ON1_DEF2:
2431 case ID_LED_ON1_ON2:
2432 case ID_LED_ON1_OFF2:
2433 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2434 mac->ledctl_mode1 |= (ledctl_on << shift);
2435 break;
2436 case ID_LED_OFF1_DEF2:
2437 case ID_LED_OFF1_ON2:
2438 case ID_LED_OFF1_OFF2:
2439 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2440 mac->ledctl_mode1 |= (ledctl_off << shift);
2441 break;
2442 default:
2443 /* Do nothing */
2444 break;
2445 }
2446 switch (temp) {
2447 case ID_LED_DEF1_ON2:
2448 case ID_LED_ON1_ON2:
2449 case ID_LED_OFF1_ON2:
2450 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2451 mac->ledctl_mode2 |= (ledctl_on << shift);
2452 break;
2453 case ID_LED_DEF1_OFF2:
2454 case ID_LED_ON1_OFF2:
2455 case ID_LED_OFF1_OFF2:
2456 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2457 mac->ledctl_mode2 |= (ledctl_off << shift);
2458 break;
2459 default:
2460 /* Do nothing */
2461 break;
2462 }
2463 }
2464
2465 out:
2466 return ret_val;
2467 }
2468
2469 /**
2470 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2471 * @hw: pointer to the HW structure
2472 *
2473 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2474 * register, so the the bus width is hard coded.
2475 **/
2476 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2477 {
2478 struct e1000_bus_info *bus = &hw->bus;
2479 s32 ret_val;
2480
2481 ret_val = e1000e_get_bus_info_pcie(hw);
2482
2483 /*
2484 * ICH devices are "PCI Express"-ish. They have
2485 * a configuration space, but do not contain
2486 * PCI Express Capability registers, so bus width
2487 * must be hardcoded.
2488 */
2489 if (bus->width == e1000_bus_width_unknown)
2490 bus->width = e1000_bus_width_pcie_x1;
2491
2492 return ret_val;
2493 }
2494
2495 /**
2496 * e1000_reset_hw_ich8lan - Reset the hardware
2497 * @hw: pointer to the HW structure
2498 *
2499 * Does a full reset of the hardware which includes a reset of the PHY and
2500 * MAC.
2501 **/
2502 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2503 {
2504 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2505 u16 reg;
2506 u32 ctrl, icr, kab;
2507 s32 ret_val;
2508
2509 /*
2510 * Prevent the PCI-E bus from sticking if there is no TLP connection
2511 * on the last TLP read/write transaction when MAC is reset.
2512 */
2513 ret_val = e1000e_disable_pcie_master(hw);
2514 if (ret_val) {
2515 e_dbg("PCI-E Master disable polling has failed.\n");
2516 }
2517
2518 e_dbg("Masking off all interrupts\n");
2519 ew32(IMC, 0xffffffff);
2520
2521 /*
2522 * Disable the Transmit and Receive units. Then delay to allow
2523 * any pending transactions to complete before we hit the MAC
2524 * with the global reset.
2525 */
2526 ew32(RCTL, 0);
2527 ew32(TCTL, E1000_TCTL_PSP);
2528 e1e_flush();
2529
2530 msleep(10);
2531
2532 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2533 if (hw->mac.type == e1000_ich8lan) {
2534 /* Set Tx and Rx buffer allocation to 8k apiece. */
2535 ew32(PBA, E1000_PBA_8K);
2536 /* Set Packet Buffer Size to 16k. */
2537 ew32(PBS, E1000_PBS_16K);
2538 }
2539
2540 if (hw->mac.type == e1000_pchlan) {
2541 /* Save the NVM K1 bit setting*/
2542 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2543 if (ret_val)
2544 return ret_val;
2545
2546 if (reg & E1000_NVM_K1_ENABLE)
2547 dev_spec->nvm_k1_enabled = true;
2548 else
2549 dev_spec->nvm_k1_enabled = false;
2550 }
2551
2552 ctrl = er32(CTRL);
2553
2554 if (!e1000_check_reset_block(hw)) {
2555 /* Clear PHY Reset Asserted bit */
2556 if (hw->mac.type >= e1000_pchlan) {
2557 u32 status = er32(STATUS);
2558 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2559 }
2560
2561 /*
2562 * PHY HW reset requires MAC CORE reset at the same
2563 * time to make sure the interface between MAC and the
2564 * external PHY is reset.
2565 */
2566 ctrl |= E1000_CTRL_PHY_RST;
2567 }
2568 ret_val = e1000_acquire_swflag_ich8lan(hw);
2569 e_dbg("Issuing a global reset to ich8lan\n");
2570 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2571 msleep(20);
2572
2573 if (!ret_val)
2574 e1000_release_swflag_ich8lan(hw);
2575
2576 /* Perform any necessary post-reset workarounds */
2577 if (hw->mac.type == e1000_pchlan)
2578 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2579
2580 if (ctrl & E1000_CTRL_PHY_RST)
2581 ret_val = hw->phy.ops.get_cfg_done(hw);
2582
2583 if (hw->mac.type >= e1000_ich10lan) {
2584 e1000_lan_init_done_ich8lan(hw);
2585 } else {
2586 ret_val = e1000e_get_auto_rd_done(hw);
2587 if (ret_val) {
2588 /*
2589 * When auto config read does not complete, do not
2590 * return with an error. This can happen in situations
2591 * where there is no eeprom and prevents getting link.
2592 */
2593 e_dbg("Auto Read Done did not complete\n");
2594 }
2595 }
2596 /* Dummy read to clear the phy wakeup bit after lcd reset */
2597 if (hw->mac.type == e1000_pchlan)
2598 e1e_rphy(hw, BM_WUC, &reg);
2599
2600 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2601 if (ret_val)
2602 goto out;
2603
2604 if (hw->mac.type == e1000_pchlan) {
2605 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2606 if (ret_val)
2607 goto out;
2608 }
2609 /*
2610 * For PCH, this write will make sure that any noise
2611 * will be detected as a CRC error and be dropped rather than show up
2612 * as a bad packet to the DMA engine.
2613 */
2614 if (hw->mac.type == e1000_pchlan)
2615 ew32(CRC_OFFSET, 0x65656565);
2616
2617 ew32(IMC, 0xffffffff);
2618 icr = er32(ICR);
2619
2620 kab = er32(KABGTXD);
2621 kab |= E1000_KABGTXD_BGSQLBIAS;
2622 ew32(KABGTXD, kab);
2623
2624 out:
2625 return ret_val;
2626 }
2627
2628 /**
2629 * e1000_init_hw_ich8lan - Initialize the hardware
2630 * @hw: pointer to the HW structure
2631 *
2632 * Prepares the hardware for transmit and receive by doing the following:
2633 * - initialize hardware bits
2634 * - initialize LED identification
2635 * - setup receive address registers
2636 * - setup flow control
2637 * - setup transmit descriptors
2638 * - clear statistics
2639 **/
2640 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2641 {
2642 struct e1000_mac_info *mac = &hw->mac;
2643 u32 ctrl_ext, txdctl, snoop;
2644 s32 ret_val;
2645 u16 i;
2646
2647 e1000_initialize_hw_bits_ich8lan(hw);
2648
2649 /* Initialize identification LED */
2650 ret_val = mac->ops.id_led_init(hw);
2651 if (ret_val)
2652 e_dbg("Error initializing identification LED\n");
2653 /* This is not fatal and we should not stop init due to this */
2654
2655 /* Setup the receive address. */
2656 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2657
2658 /* Zero out the Multicast HASH table */
2659 e_dbg("Zeroing the MTA\n");
2660 for (i = 0; i < mac->mta_reg_count; i++)
2661 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2662
2663 /*
2664 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2665 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2666 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2667 */
2668 if (hw->phy.type == e1000_phy_82578) {
2669 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2670 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2671 if (ret_val)
2672 return ret_val;
2673 }
2674
2675 /* Setup link and flow control */
2676 ret_val = e1000_setup_link_ich8lan(hw);
2677
2678 /* Set the transmit descriptor write-back policy for both queues */
2679 txdctl = er32(TXDCTL(0));
2680 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2681 E1000_TXDCTL_FULL_TX_DESC_WB;
2682 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2683 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2684 ew32(TXDCTL(0), txdctl);
2685 txdctl = er32(TXDCTL(1));
2686 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2687 E1000_TXDCTL_FULL_TX_DESC_WB;
2688 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2689 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2690 ew32(TXDCTL(1), txdctl);
2691
2692 /*
2693 * ICH8 has opposite polarity of no_snoop bits.
2694 * By default, we should use snoop behavior.
2695 */
2696 if (mac->type == e1000_ich8lan)
2697 snoop = PCIE_ICH8_SNOOP_ALL;
2698 else
2699 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2700 e1000e_set_pcie_no_snoop(hw, snoop);
2701
2702 ctrl_ext = er32(CTRL_EXT);
2703 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2704 ew32(CTRL_EXT, ctrl_ext);
2705
2706 /*
2707 * Clear all of the statistics registers (clear on read). It is
2708 * important that we do this after we have tried to establish link
2709 * because the symbol error count will increment wildly if there
2710 * is no link.
2711 */
2712 e1000_clear_hw_cntrs_ich8lan(hw);
2713
2714 return 0;
2715 }
2716 /**
2717 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2718 * @hw: pointer to the HW structure
2719 *
2720 * Sets/Clears required hardware bits necessary for correctly setting up the
2721 * hardware for transmit and receive.
2722 **/
2723 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2724 {
2725 u32 reg;
2726
2727 /* Extended Device Control */
2728 reg = er32(CTRL_EXT);
2729 reg |= (1 << 22);
2730 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2731 if (hw->mac.type >= e1000_pchlan)
2732 reg |= E1000_CTRL_EXT_PHYPDEN;
2733 ew32(CTRL_EXT, reg);
2734
2735 /* Transmit Descriptor Control 0 */
2736 reg = er32(TXDCTL(0));
2737 reg |= (1 << 22);
2738 ew32(TXDCTL(0), reg);
2739
2740 /* Transmit Descriptor Control 1 */
2741 reg = er32(TXDCTL(1));
2742 reg |= (1 << 22);
2743 ew32(TXDCTL(1), reg);
2744
2745 /* Transmit Arbitration Control 0 */
2746 reg = er32(TARC(0));
2747 if (hw->mac.type == e1000_ich8lan)
2748 reg |= (1 << 28) | (1 << 29);
2749 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2750 ew32(TARC(0), reg);
2751
2752 /* Transmit Arbitration Control 1 */
2753 reg = er32(TARC(1));
2754 if (er32(TCTL) & E1000_TCTL_MULR)
2755 reg &= ~(1 << 28);
2756 else
2757 reg |= (1 << 28);
2758 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2759 ew32(TARC(1), reg);
2760
2761 /* Device Status */
2762 if (hw->mac.type == e1000_ich8lan) {
2763 reg = er32(STATUS);
2764 reg &= ~(1 << 31);
2765 ew32(STATUS, reg);
2766 }
2767
2768 /*
2769 * work-around descriptor data corruption issue during nfs v2 udp
2770 * traffic, just disable the nfs filtering capability
2771 */
2772 reg = er32(RFCTL);
2773 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
2774 ew32(RFCTL, reg);
2775
2776 return;
2777 }
2778
2779 /**
2780 * e1000_setup_link_ich8lan - Setup flow control and link settings
2781 * @hw: pointer to the HW structure
2782 *
2783 * Determines which flow control settings to use, then configures flow
2784 * control. Calls the appropriate media-specific link configuration
2785 * function. Assuming the adapter has a valid link partner, a valid link
2786 * should be established. Assumes the hardware has previously been reset
2787 * and the transmitter and receiver are not enabled.
2788 **/
2789 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2790 {
2791 s32 ret_val;
2792
2793 if (e1000_check_reset_block(hw))
2794 return 0;
2795
2796 /*
2797 * ICH parts do not have a word in the NVM to determine
2798 * the default flow control setting, so we explicitly
2799 * set it to full.
2800 */
2801 if (hw->fc.requested_mode == e1000_fc_default) {
2802 /* Workaround h/w hang when Tx flow control enabled */
2803 if (hw->mac.type == e1000_pchlan)
2804 hw->fc.requested_mode = e1000_fc_rx_pause;
2805 else
2806 hw->fc.requested_mode = e1000_fc_full;
2807 }
2808
2809 /*
2810 * Save off the requested flow control mode for use later. Depending
2811 * on the link partner's capabilities, we may or may not use this mode.
2812 */
2813 hw->fc.current_mode = hw->fc.requested_mode;
2814
2815 e_dbg("After fix-ups FlowControl is now = %x\n",
2816 hw->fc.current_mode);
2817
2818 /* Continue to configure the copper link. */
2819 ret_val = e1000_setup_copper_link_ich8lan(hw);
2820 if (ret_val)
2821 return ret_val;
2822
2823 ew32(FCTTV, hw->fc.pause_time);
2824 if ((hw->phy.type == e1000_phy_82578) ||
2825 (hw->phy.type == e1000_phy_82577)) {
2826 ew32(FCRTV_PCH, hw->fc.refresh_time);
2827
2828 ret_val = hw->phy.ops.write_reg(hw,
2829 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2830 hw->fc.pause_time);
2831 if (ret_val)
2832 return ret_val;
2833 }
2834
2835 return e1000e_set_fc_watermarks(hw);
2836 }
2837
2838 /**
2839 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2840 * @hw: pointer to the HW structure
2841 *
2842 * Configures the kumeran interface to the PHY to wait the appropriate time
2843 * when polling the PHY, then call the generic setup_copper_link to finish
2844 * configuring the copper link.
2845 **/
2846 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2847 {
2848 u32 ctrl;
2849 s32 ret_val;
2850 u16 reg_data;
2851
2852 ctrl = er32(CTRL);
2853 ctrl |= E1000_CTRL_SLU;
2854 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2855 ew32(CTRL, ctrl);
2856
2857 /*
2858 * Set the mac to wait the maximum time between each iteration
2859 * and increase the max iterations when polling the phy;
2860 * this fixes erroneous timeouts at 10Mbps.
2861 */
2862 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
2863 if (ret_val)
2864 return ret_val;
2865 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2866 &reg_data);
2867 if (ret_val)
2868 return ret_val;
2869 reg_data |= 0x3F;
2870 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2871 reg_data);
2872 if (ret_val)
2873 return ret_val;
2874
2875 switch (hw->phy.type) {
2876 case e1000_phy_igp_3:
2877 ret_val = e1000e_copper_link_setup_igp(hw);
2878 if (ret_val)
2879 return ret_val;
2880 break;
2881 case e1000_phy_bm:
2882 case e1000_phy_82578:
2883 ret_val = e1000e_copper_link_setup_m88(hw);
2884 if (ret_val)
2885 return ret_val;
2886 break;
2887 case e1000_phy_82577:
2888 ret_val = e1000_copper_link_setup_82577(hw);
2889 if (ret_val)
2890 return ret_val;
2891 break;
2892 case e1000_phy_ife:
2893 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2894 &reg_data);
2895 if (ret_val)
2896 return ret_val;
2897
2898 reg_data &= ~IFE_PMC_AUTO_MDIX;
2899
2900 switch (hw->phy.mdix) {
2901 case 1:
2902 reg_data &= ~IFE_PMC_FORCE_MDIX;
2903 break;
2904 case 2:
2905 reg_data |= IFE_PMC_FORCE_MDIX;
2906 break;
2907 case 0:
2908 default:
2909 reg_data |= IFE_PMC_AUTO_MDIX;
2910 break;
2911 }
2912 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2913 reg_data);
2914 if (ret_val)
2915 return ret_val;
2916 break;
2917 default:
2918 break;
2919 }
2920 return e1000e_setup_copper_link(hw);
2921 }
2922
2923 /**
2924 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2925 * @hw: pointer to the HW structure
2926 * @speed: pointer to store current link speed
2927 * @duplex: pointer to store the current link duplex
2928 *
2929 * Calls the generic get_speed_and_duplex to retrieve the current link
2930 * information and then calls the Kumeran lock loss workaround for links at
2931 * gigabit speeds.
2932 **/
2933 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2934 u16 *duplex)
2935 {
2936 s32 ret_val;
2937
2938 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2939 if (ret_val)
2940 return ret_val;
2941
2942 if ((hw->mac.type == e1000_ich8lan) &&
2943 (hw->phy.type == e1000_phy_igp_3) &&
2944 (*speed == SPEED_1000)) {
2945 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2946 }
2947
2948 return ret_val;
2949 }
2950
2951 /**
2952 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2953 * @hw: pointer to the HW structure
2954 *
2955 * Work-around for 82566 Kumeran PCS lock loss:
2956 * On link status change (i.e. PCI reset, speed change) and link is up and
2957 * speed is gigabit-
2958 * 0) if workaround is optionally disabled do nothing
2959 * 1) wait 1ms for Kumeran link to come up
2960 * 2) check Kumeran Diagnostic register PCS lock loss bit
2961 * 3) if not set the link is locked (all is good), otherwise...
2962 * 4) reset the PHY
2963 * 5) repeat up to 10 times
2964 * Note: this is only called for IGP3 copper when speed is 1gb.
2965 **/
2966 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2967 {
2968 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2969 u32 phy_ctrl;
2970 s32 ret_val;
2971 u16 i, data;
2972 bool link;
2973
2974 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2975 return 0;
2976
2977 /*
2978 * Make sure link is up before proceeding. If not just return.
2979 * Attempting this while link is negotiating fouled up link
2980 * stability
2981 */
2982 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2983 if (!link)
2984 return 0;
2985
2986 for (i = 0; i < 10; i++) {
2987 /* read once to clear */
2988 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2989 if (ret_val)
2990 return ret_val;
2991 /* and again to get new status */
2992 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2993 if (ret_val)
2994 return ret_val;
2995
2996 /* check for PCS lock */
2997 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2998 return 0;
2999
3000 /* Issue PHY reset */
3001 e1000_phy_hw_reset(hw);
3002 mdelay(5);
3003 }
3004 /* Disable GigE link negotiation */
3005 phy_ctrl = er32(PHY_CTRL);
3006 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3007 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3008 ew32(PHY_CTRL, phy_ctrl);
3009
3010 /*
3011 * Call gig speed drop workaround on Gig disable before accessing
3012 * any PHY registers
3013 */
3014 e1000e_gig_downshift_workaround_ich8lan(hw);
3015
3016 /* unable to acquire PCS lock */
3017 return -E1000_ERR_PHY;
3018 }
3019
3020 /**
3021 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3022 * @hw: pointer to the HW structure
3023 * @state: boolean value used to set the current Kumeran workaround state
3024 *
3025 * If ICH8, set the current Kumeran workaround state (enabled - true
3026 * /disabled - false).
3027 **/
3028 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3029 bool state)
3030 {
3031 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3032
3033 if (hw->mac.type != e1000_ich8lan) {
3034 e_dbg("Workaround applies to ICH8 only.\n");
3035 return;
3036 }
3037
3038 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3039 }
3040
3041 /**
3042 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3043 * @hw: pointer to the HW structure
3044 *
3045 * Workaround for 82566 power-down on D3 entry:
3046 * 1) disable gigabit link
3047 * 2) write VR power-down enable
3048 * 3) read it back
3049 * Continue if successful, else issue LCD reset and repeat
3050 **/
3051 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3052 {
3053 u32 reg;
3054 u16 data;
3055 u8 retry = 0;
3056
3057 if (hw->phy.type != e1000_phy_igp_3)
3058 return;
3059
3060 /* Try the workaround twice (if needed) */
3061 do {
3062 /* Disable link */
3063 reg = er32(PHY_CTRL);
3064 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3065 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3066 ew32(PHY_CTRL, reg);
3067
3068 /*
3069 * Call gig speed drop workaround on Gig disable before
3070 * accessing any PHY registers
3071 */
3072 if (hw->mac.type == e1000_ich8lan)
3073 e1000e_gig_downshift_workaround_ich8lan(hw);
3074
3075 /* Write VR power-down enable */
3076 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3077 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3078 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3079
3080 /* Read it back and test */
3081 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3082 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3083 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3084 break;
3085
3086 /* Issue PHY reset and repeat at most one more time */
3087 reg = er32(CTRL);
3088 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3089 retry++;
3090 } while (retry);
3091 }
3092
3093 /**
3094 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3095 * @hw: pointer to the HW structure
3096 *
3097 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3098 * LPLU, Gig disable, MDIC PHY reset):
3099 * 1) Set Kumeran Near-end loopback
3100 * 2) Clear Kumeran Near-end loopback
3101 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3102 **/
3103 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3104 {
3105 s32 ret_val;
3106 u16 reg_data;
3107
3108 if ((hw->mac.type != e1000_ich8lan) ||
3109 (hw->phy.type != e1000_phy_igp_3))
3110 return;
3111
3112 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3113 &reg_data);
3114 if (ret_val)
3115 return;
3116 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3117 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3118 reg_data);
3119 if (ret_val)
3120 return;
3121 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3122 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3123 reg_data);
3124 }
3125
3126 /**
3127 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3128 * @hw: pointer to the HW structure
3129 *
3130 * During S0 to Sx transition, it is possible the link remains at gig
3131 * instead of negotiating to a lower speed. Before going to Sx, set
3132 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3133 * to a lower speed.
3134 *
3135 * Should only be called for applicable parts.
3136 **/
3137 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3138 {
3139 u32 phy_ctrl;
3140
3141 switch (hw->mac.type) {
3142 case e1000_ich8lan:
3143 case e1000_ich9lan:
3144 case e1000_ich10lan:
3145 case e1000_pchlan:
3146 phy_ctrl = er32(PHY_CTRL);
3147 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3148 E1000_PHY_CTRL_GBE_DISABLE;
3149 ew32(PHY_CTRL, phy_ctrl);
3150
3151 if (hw->mac.type == e1000_pchlan)
3152 e1000_phy_hw_reset_ich8lan(hw);
3153 default:
3154 break;
3155 }
3156
3157 return;
3158 }
3159
3160 /**
3161 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3162 * @hw: pointer to the HW structure
3163 *
3164 * Return the LED back to the default configuration.
3165 **/
3166 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3167 {
3168 if (hw->phy.type == e1000_phy_ife)
3169 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3170
3171 ew32(LEDCTL, hw->mac.ledctl_default);
3172 return 0;
3173 }
3174
3175 /**
3176 * e1000_led_on_ich8lan - Turn LEDs on
3177 * @hw: pointer to the HW structure
3178 *
3179 * Turn on the LEDs.
3180 **/
3181 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3182 {
3183 if (hw->phy.type == e1000_phy_ife)
3184 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3185 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3186
3187 ew32(LEDCTL, hw->mac.ledctl_mode2);
3188 return 0;
3189 }
3190
3191 /**
3192 * e1000_led_off_ich8lan - Turn LEDs off
3193 * @hw: pointer to the HW structure
3194 *
3195 * Turn off the LEDs.
3196 **/
3197 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3198 {
3199 if (hw->phy.type == e1000_phy_ife)
3200 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3201 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3202
3203 ew32(LEDCTL, hw->mac.ledctl_mode1);
3204 return 0;
3205 }
3206
3207 /**
3208 * e1000_setup_led_pchlan - Configures SW controllable LED
3209 * @hw: pointer to the HW structure
3210 *
3211 * This prepares the SW controllable LED for use.
3212 **/
3213 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3214 {
3215 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3216 (u16)hw->mac.ledctl_mode1);
3217 }
3218
3219 /**
3220 * e1000_cleanup_led_pchlan - Restore the default LED operation
3221 * @hw: pointer to the HW structure
3222 *
3223 * Return the LED back to the default configuration.
3224 **/
3225 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3226 {
3227 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3228 (u16)hw->mac.ledctl_default);
3229 }
3230
3231 /**
3232 * e1000_led_on_pchlan - Turn LEDs on
3233 * @hw: pointer to the HW structure
3234 *
3235 * Turn on the LEDs.
3236 **/
3237 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3238 {
3239 u16 data = (u16)hw->mac.ledctl_mode2;
3240 u32 i, led;
3241
3242 /*
3243 * If no link, then turn LED on by setting the invert bit
3244 * for each LED that's mode is "link_up" in ledctl_mode2.
3245 */
3246 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3247 for (i = 0; i < 3; i++) {
3248 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3249 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3250 E1000_LEDCTL_MODE_LINK_UP)
3251 continue;
3252 if (led & E1000_PHY_LED0_IVRT)
3253 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3254 else
3255 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3256 }
3257 }
3258
3259 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3260 }
3261
3262 /**
3263 * e1000_led_off_pchlan - Turn LEDs off
3264 * @hw: pointer to the HW structure
3265 *
3266 * Turn off the LEDs.
3267 **/
3268 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3269 {
3270 u16 data = (u16)hw->mac.ledctl_mode1;
3271 u32 i, led;
3272
3273 /*
3274 * If no link, then turn LED off by clearing the invert bit
3275 * for each LED that's mode is "link_up" in ledctl_mode1.
3276 */
3277 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3278 for (i = 0; i < 3; i++) {
3279 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3280 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3281 E1000_LEDCTL_MODE_LINK_UP)
3282 continue;
3283 if (led & E1000_PHY_LED0_IVRT)
3284 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3285 else
3286 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3287 }
3288 }
3289
3290 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3291 }
3292
3293 /**
3294 * e1000_get_cfg_done_ich8lan - Read config done bit
3295 * @hw: pointer to the HW structure
3296 *
3297 * Read the management control register for the config done bit for
3298 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3299 * to read the config done bit, so an error is *ONLY* logged and returns
3300 * 0. If we were to return with error, EEPROM-less silicon
3301 * would not be able to be reset or change link.
3302 **/
3303 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3304 {
3305 u32 bank = 0;
3306
3307 if (hw->mac.type >= e1000_pchlan) {
3308 u32 status = er32(STATUS);
3309
3310 if (status & E1000_STATUS_PHYRA)
3311 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3312 else
3313 e_dbg("PHY Reset Asserted not set - needs delay\n");
3314 }
3315
3316 e1000e_get_cfg_done(hw);
3317
3318 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3319 if ((hw->mac.type != e1000_ich10lan) &&
3320 (hw->mac.type != e1000_pchlan)) {
3321 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3322 (hw->phy.type == e1000_phy_igp_3)) {
3323 e1000e_phy_init_script_igp3(hw);
3324 }
3325 } else {
3326 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3327 /* Maybe we should do a basic PHY config */
3328 e_dbg("EEPROM not present\n");
3329 return -E1000_ERR_CONFIG;
3330 }
3331 }
3332
3333 return 0;
3334 }
3335
3336 /**
3337 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3338 * @hw: pointer to the HW structure
3339 *
3340 * In the case of a PHY power down to save power, or to turn off link during a
3341 * driver unload, or wake on lan is not enabled, remove the link.
3342 **/
3343 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3344 {
3345 /* If the management interface is not enabled, then power down */
3346 if (!(hw->mac.ops.check_mng_mode(hw) ||
3347 hw->phy.ops.check_reset_block(hw)))
3348 e1000_power_down_phy_copper(hw);
3349
3350 return;
3351 }
3352
3353 /**
3354 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3355 * @hw: pointer to the HW structure
3356 *
3357 * Clears hardware counters specific to the silicon family and calls
3358 * clear_hw_cntrs_generic to clear all general purpose counters.
3359 **/
3360 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3361 {
3362 u16 phy_data;
3363
3364 e1000e_clear_hw_cntrs_base(hw);
3365
3366 er32(ALGNERRC);
3367 er32(RXERRC);
3368 er32(TNCRS);
3369 er32(CEXTERR);
3370 er32(TSCTC);
3371 er32(TSCTFC);
3372
3373 er32(MGTPRC);
3374 er32(MGTPDC);
3375 er32(MGTPTC);
3376
3377 er32(IAC);
3378 er32(ICRXOC);
3379
3380 /* Clear PHY statistics registers */
3381 if ((hw->phy.type == e1000_phy_82578) ||
3382 (hw->phy.type == e1000_phy_82577)) {
3383 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3384 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3385 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3386 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3387 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3388 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3389 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3390 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3391 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3392 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3393 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3394 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3395 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3396 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3397 }
3398 }
3399
3400 static struct e1000_mac_operations ich8_mac_ops = {
3401 .id_led_init = e1000e_id_led_init,
3402 .check_mng_mode = e1000_check_mng_mode_ich8lan,
3403 .check_for_link = e1000_check_for_copper_link_ich8lan,
3404 /* cleanup_led dependent on mac type */
3405 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3406 .get_bus_info = e1000_get_bus_info_ich8lan,
3407 .set_lan_id = e1000_set_lan_id_single_port,
3408 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3409 /* led_on dependent on mac type */
3410 /* led_off dependent on mac type */
3411 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3412 .reset_hw = e1000_reset_hw_ich8lan,
3413 .init_hw = e1000_init_hw_ich8lan,
3414 .setup_link = e1000_setup_link_ich8lan,
3415 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3416 /* id_led_init dependent on mac type */
3417 };
3418
3419 static struct e1000_phy_operations ich8_phy_ops = {
3420 .acquire = e1000_acquire_swflag_ich8lan,
3421 .check_reset_block = e1000_check_reset_block_ich8lan,
3422 .commit = NULL,
3423 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3424 .get_cable_length = e1000e_get_cable_length_igp_2,
3425 .read_reg = e1000e_read_phy_reg_igp,
3426 .release = e1000_release_swflag_ich8lan,
3427 .reset = e1000_phy_hw_reset_ich8lan,
3428 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3429 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3430 .write_reg = e1000e_write_phy_reg_igp,
3431 };
3432
3433 static struct e1000_nvm_operations ich8_nvm_ops = {
3434 .acquire = e1000_acquire_nvm_ich8lan,
3435 .read = e1000_read_nvm_ich8lan,
3436 .release = e1000_release_nvm_ich8lan,
3437 .update = e1000_update_nvm_checksum_ich8lan,
3438 .valid_led_default = e1000_valid_led_default_ich8lan,
3439 .validate = e1000_validate_nvm_checksum_ich8lan,
3440 .write = e1000_write_nvm_ich8lan,
3441 };
3442
3443 struct e1000_info e1000_ich8_info = {
3444 .mac = e1000_ich8lan,
3445 .flags = FLAG_HAS_WOL
3446 | FLAG_IS_ICH
3447 | FLAG_RX_CSUM_ENABLED
3448 | FLAG_HAS_CTRLEXT_ON_LOAD
3449 | FLAG_HAS_AMT
3450 | FLAG_HAS_FLASH
3451 | FLAG_APME_IN_WUC,
3452 .pba = 8,
3453 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3454 .get_variants = e1000_get_variants_ich8lan,
3455 .mac_ops = &ich8_mac_ops,
3456 .phy_ops = &ich8_phy_ops,
3457 .nvm_ops = &ich8_nvm_ops,
3458 };
3459
3460 struct e1000_info e1000_ich9_info = {
3461 .mac = e1000_ich9lan,
3462 .flags = FLAG_HAS_JUMBO_FRAMES
3463 | FLAG_IS_ICH
3464 | FLAG_HAS_WOL
3465 | FLAG_RX_CSUM_ENABLED
3466 | FLAG_HAS_CTRLEXT_ON_LOAD
3467 | FLAG_HAS_AMT
3468 | FLAG_HAS_ERT
3469 | FLAG_HAS_FLASH
3470 | FLAG_APME_IN_WUC,
3471 .pba = 10,
3472 .max_hw_frame_size = DEFAULT_JUMBO,
3473 .get_variants = e1000_get_variants_ich8lan,
3474 .mac_ops = &ich8_mac_ops,
3475 .phy_ops = &ich8_phy_ops,
3476 .nvm_ops = &ich8_nvm_ops,
3477 };
3478
3479 struct e1000_info e1000_ich10_info = {
3480 .mac = e1000_ich10lan,
3481 .flags = FLAG_HAS_JUMBO_FRAMES
3482 | FLAG_IS_ICH
3483 | FLAG_HAS_WOL
3484 | FLAG_RX_CSUM_ENABLED
3485 | FLAG_HAS_CTRLEXT_ON_LOAD
3486 | FLAG_HAS_AMT
3487 | FLAG_HAS_ERT
3488 | FLAG_HAS_FLASH
3489 | FLAG_APME_IN_WUC,
3490 .pba = 10,
3491 .max_hw_frame_size = DEFAULT_JUMBO,
3492 .get_variants = e1000_get_variants_ich8lan,
3493 .mac_ops = &ich8_mac_ops,
3494 .phy_ops = &ich8_phy_ops,
3495 .nvm_ops = &ich8_nvm_ops,
3496 };
3497
3498 struct e1000_info e1000_pch_info = {
3499 .mac = e1000_pchlan,
3500 .flags = FLAG_IS_ICH
3501 | FLAG_HAS_WOL
3502 | FLAG_RX_CSUM_ENABLED
3503 | FLAG_HAS_CTRLEXT_ON_LOAD
3504 | FLAG_HAS_AMT
3505 | FLAG_HAS_FLASH
3506 | FLAG_HAS_JUMBO_FRAMES
3507 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3508 | FLAG_APME_IN_WUC,
3509 .pba = 26,
3510 .max_hw_frame_size = 4096,
3511 .get_variants = e1000_get_variants_ich8lan,
3512 .mac_ops = &ich8_mac_ops,
3513 .phy_ops = &ich8_phy_ops,
3514 .nvm_ops = &ich8_nvm_ops,
3515 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree