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[SPARC64]: Probe PCI bus using OF device tree.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / sparc64 / kernel / pci_sun4v.c
blobeec7def379dc835f994f78396ac46da823a8b003
1 /* pci_sun4v.c: SUN4V specific PCI controller support.
2 *
3 * Copyright (C) 2006 David S. Miller (davem@davemloft.net)
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/percpu.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15
16 #include <asm/pbm.h>
17 #include <asm/iommu.h>
18 #include <asm/irq.h>
19 #include <asm/upa.h>
20 #include <asm/pstate.h>
21 #include <asm/oplib.h>
22 #include <asm/hypervisor.h>
23 #include <asm/prom.h>
24
25 #include "pci_impl.h"
26 #include "iommu_common.h"
27
28 #include "pci_sun4v.h"
29
30 #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
31
32 struct pci_iommu_batch {
33 struct pci_dev *pdev; /* Device mapping is for. */
34 unsigned long prot; /* IOMMU page protections */
35 unsigned long entry; /* Index into IOTSB. */
36 u64 *pglist; /* List of physical pages */
37 unsigned long npages; /* Number of pages in list. */
38 };
39
40 static DEFINE_PER_CPU(struct pci_iommu_batch, pci_iommu_batch);
41
42 /* Interrupts must be disabled. */
43 static inline void pci_iommu_batch_start(struct pci_dev *pdev, unsigned long prot, unsigned long entry)
44 {
45 struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
46
47 p->pdev = pdev;
48 p->prot = prot;
49 p->entry = entry;
50 p->npages = 0;
51 }
52
53 /* Interrupts must be disabled. */
54 static long pci_iommu_batch_flush(struct pci_iommu_batch *p)
55 {
56 struct pci_pbm_info *pbm = p->pdev->dev.archdata.host_controller;
57 unsigned long devhandle = pbm->devhandle;
58 unsigned long prot = p->prot;
59 unsigned long entry = p->entry;
60 u64 *pglist = p->pglist;
61 unsigned long npages = p->npages;
62
63 while (npages != 0) {
64 long num;
65
66 num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
67 npages, prot, __pa(pglist));
68 if (unlikely(num < 0)) {
69 if (printk_ratelimit())
70 printk("pci_iommu_batch_flush: IOMMU map of "
71 "[%08lx:%08lx:%lx:%lx:%lx] failed with "
72 "status %ld\n",
73 devhandle, HV_PCI_TSBID(0, entry),
74 npages, prot, __pa(pglist), num);
75 return -1;
76 }
77
78 entry += num;
79 npages -= num;
80 pglist += num;
81 }
82
83 p->entry = entry;
84 p->npages = 0;
85
86 return 0;
87 }
88
89 /* Interrupts must be disabled. */
90 static inline long pci_iommu_batch_add(u64 phys_page)
91 {
92 struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
93
94 BUG_ON(p->npages >= PGLIST_NENTS);
95
96 p->pglist[p->npages++] = phys_page;
97 if (p->npages == PGLIST_NENTS)
98 return pci_iommu_batch_flush(p);
99
100 return 0;
101 }
102
103 /* Interrupts must be disabled. */
104 static inline long pci_iommu_batch_end(void)
105 {
106 struct pci_iommu_batch *p = &__get_cpu_var(pci_iommu_batch);
107
108 BUG_ON(p->npages >= PGLIST_NENTS);
109
110 return pci_iommu_batch_flush(p);
111 }
112
113 static long pci_arena_alloc(struct pci_iommu_arena *arena, unsigned long npages)
114 {
115 unsigned long n, i, start, end, limit;
116 int pass;
117
118 limit = arena->limit;
119 start = arena->hint;
120 pass = 0;
121
122 again:
123 n = find_next_zero_bit(arena->map, limit, start);
124 end = n + npages;
125 if (unlikely(end >= limit)) {
126 if (likely(pass < 1)) {
127 limit = start;
128 start = 0;
129 pass++;
130 goto again;
131 } else {
132 /* Scanned the whole thing, give up. */
133 return -1;
134 }
135 }
136
137 for (i = n; i < end; i++) {
138 if (test_bit(i, arena->map)) {
139 start = i + 1;
140 goto again;
141 }
142 }
143
144 for (i = n; i < end; i++)
145 __set_bit(i, arena->map);
146
147 arena->hint = end;
148
149 return n;
150 }
151
152 static void pci_arena_free(struct pci_iommu_arena *arena, unsigned long base, unsigned long npages)
153 {
154 unsigned long i;
155
156 for (i = base; i < (base + npages); i++)
157 __clear_bit(i, arena->map);
158 }
159
160 static void *pci_4v_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
161 {
162 struct pci_iommu *iommu;
163 unsigned long flags, order, first_page, npages, n;
164 void *ret;
165 long entry;
166
167 size = IO_PAGE_ALIGN(size);
168 order = get_order(size);
169 if (unlikely(order >= MAX_ORDER))
170 return NULL;
171
172 npages = size >> IO_PAGE_SHIFT;
173
174 first_page = __get_free_pages(gfp, order);
175 if (unlikely(first_page == 0UL))
176 return NULL;
177
178 memset((char *)first_page, 0, PAGE_SIZE << order);
179
180 iommu = pdev->dev.archdata.iommu;
181
182 spin_lock_irqsave(&iommu->lock, flags);
183 entry = pci_arena_alloc(&iommu->arena, npages);
184 spin_unlock_irqrestore(&iommu->lock, flags);
185
186 if (unlikely(entry < 0L))
187 goto arena_alloc_fail;
188
189 *dma_addrp = (iommu->page_table_map_base +
190 (entry << IO_PAGE_SHIFT));
191 ret = (void *) first_page;
192 first_page = __pa(first_page);
193
194 local_irq_save(flags);
195
196 pci_iommu_batch_start(pdev,
197 (HV_PCI_MAP_ATTR_READ |
198 HV_PCI_MAP_ATTR_WRITE),
199 entry);
200
201 for (n = 0; n < npages; n++) {
202 long err = pci_iommu_batch_add(first_page + (n * PAGE_SIZE));
203 if (unlikely(err < 0L))
204 goto iommu_map_fail;
205 }
206
207 if (unlikely(pci_iommu_batch_end() < 0L))
208 goto iommu_map_fail;
209
210 local_irq_restore(flags);
211
212 return ret;
213
214 iommu_map_fail:
215 /* Interrupts are disabled. */
216 spin_lock(&iommu->lock);
217 pci_arena_free(&iommu->arena, entry, npages);
218 spin_unlock_irqrestore(&iommu->lock, flags);
219
220 arena_alloc_fail:
221 free_pages(first_page, order);
222 return NULL;
223 }
224
225 static void pci_4v_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
226 {
227 struct pci_pbm_info *pbm;
228 struct pci_iommu *iommu;
229 unsigned long flags, order, npages, entry;
230 u32 devhandle;
231
232 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
233 iommu = pdev->dev.archdata.iommu;
234 pbm = pdev->dev.archdata.host_controller;
235 devhandle = pbm->devhandle;
236 entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
237
238 spin_lock_irqsave(&iommu->lock, flags);
239
240 pci_arena_free(&iommu->arena, entry, npages);
241
242 do {
243 unsigned long num;
244
245 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
246 npages);
247 entry += num;
248 npages -= num;
249 } while (npages != 0);
250
251 spin_unlock_irqrestore(&iommu->lock, flags);
252
253 order = get_order(size);
254 if (order < 10)
255 free_pages((unsigned long)cpu, order);
256 }
257
258 static dma_addr_t pci_4v_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
259 {
260 struct pci_iommu *iommu;
261 unsigned long flags, npages, oaddr;
262 unsigned long i, base_paddr;
263 u32 bus_addr, ret;
264 unsigned long prot;
265 long entry;
266
267 iommu = pdev->dev.archdata.iommu;
268
269 if (unlikely(direction == PCI_DMA_NONE))
270 goto bad;
271
272 oaddr = (unsigned long)ptr;
273 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
274 npages >>= IO_PAGE_SHIFT;
275
276 spin_lock_irqsave(&iommu->lock, flags);
277 entry = pci_arena_alloc(&iommu->arena, npages);
278 spin_unlock_irqrestore(&iommu->lock, flags);
279
280 if (unlikely(entry < 0L))
281 goto bad;
282
283 bus_addr = (iommu->page_table_map_base +
284 (entry << IO_PAGE_SHIFT));
285 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
286 base_paddr = __pa(oaddr & IO_PAGE_MASK);
287 prot = HV_PCI_MAP_ATTR_READ;
288 if (direction != PCI_DMA_TODEVICE)
289 prot |= HV_PCI_MAP_ATTR_WRITE;
290
291 local_irq_save(flags);
292
293 pci_iommu_batch_start(pdev, prot, entry);
294
295 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
296 long err = pci_iommu_batch_add(base_paddr);
297 if (unlikely(err < 0L))
298 goto iommu_map_fail;
299 }
300 if (unlikely(pci_iommu_batch_end() < 0L))
301 goto iommu_map_fail;
302
303 local_irq_restore(flags);
304
305 return ret;
306
307 bad:
308 if (printk_ratelimit())
309 WARN_ON(1);
310 return PCI_DMA_ERROR_CODE;
311
312 iommu_map_fail:
313 /* Interrupts are disabled. */
314 spin_lock(&iommu->lock);
315 pci_arena_free(&iommu->arena, entry, npages);
316 spin_unlock_irqrestore(&iommu->lock, flags);
317
318 return PCI_DMA_ERROR_CODE;
319 }
320
321 static void pci_4v_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
322 {
323 struct pci_pbm_info *pbm;
324 struct pci_iommu *iommu;
325 unsigned long flags, npages;
326 long entry;
327 u32 devhandle;
328
329 if (unlikely(direction == PCI_DMA_NONE)) {
330 if (printk_ratelimit())
331 WARN_ON(1);
332 return;
333 }
334
335 iommu = pdev->dev.archdata.iommu;
336 pbm = pdev->dev.archdata.host_controller;
337 devhandle = pbm->devhandle;
338
339 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
340 npages >>= IO_PAGE_SHIFT;
341 bus_addr &= IO_PAGE_MASK;
342
343 spin_lock_irqsave(&iommu->lock, flags);
344
345 entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
346 pci_arena_free(&iommu->arena, entry, npages);
347
348 do {
349 unsigned long num;
350
351 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
352 npages);
353 entry += num;
354 npages -= num;
355 } while (npages != 0);
356
357 spin_unlock_irqrestore(&iommu->lock, flags);
358 }
359
360 #define SG_ENT_PHYS_ADDRESS(SG) \
361 (__pa(page_address((SG)->page)) + (SG)->offset)
362
363 static inline long fill_sg(long entry, struct pci_dev *pdev,
364 struct scatterlist *sg,
365 int nused, int nelems, unsigned long prot)
366 {
367 struct scatterlist *dma_sg = sg;
368 struct scatterlist *sg_end = sg + nelems;
369 unsigned long flags;
370 int i;
371
372 local_irq_save(flags);
373
374 pci_iommu_batch_start(pdev, prot, entry);
375
376 for (i = 0; i < nused; i++) {
377 unsigned long pteval = ~0UL;
378 u32 dma_npages;
379
380 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
381 dma_sg->dma_length +
382 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
383 do {
384 unsigned long offset;
385 signed int len;
386
387 /* If we are here, we know we have at least one
388 * more page to map. So walk forward until we
389 * hit a page crossing, and begin creating new
390 * mappings from that spot.
391 */
392 for (;;) {
393 unsigned long tmp;
394
395 tmp = SG_ENT_PHYS_ADDRESS(sg);
396 len = sg->length;
397 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
398 pteval = tmp & IO_PAGE_MASK;
399 offset = tmp & (IO_PAGE_SIZE - 1UL);
400 break;
401 }
402 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
403 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
404 offset = 0UL;
405 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
406 break;
407 }
408 sg++;
409 }
410
411 pteval = (pteval & IOPTE_PAGE);
412 while (len > 0) {
413 long err;
414
415 err = pci_iommu_batch_add(pteval);
416 if (unlikely(err < 0L))
417 goto iommu_map_failed;
418
419 pteval += IO_PAGE_SIZE;
420 len -= (IO_PAGE_SIZE - offset);
421 offset = 0;
422 dma_npages--;
423 }
424
425 pteval = (pteval & IOPTE_PAGE) + len;
426 sg++;
427
428 /* Skip over any tail mappings we've fully mapped,
429 * adjusting pteval along the way. Stop when we
430 * detect a page crossing event.
431 */
432 while (sg < sg_end &&
433 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
434 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
435 ((pteval ^
436 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
437 pteval += sg->length;
438 sg++;
439 }
440 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
441 pteval = ~0UL;
442 } while (dma_npages != 0);
443 dma_sg++;
444 }
445
446 if (unlikely(pci_iommu_batch_end() < 0L))
447 goto iommu_map_failed;
448
449 local_irq_restore(flags);
450 return 0;
451
452 iommu_map_failed:
453 local_irq_restore(flags);
454 return -1L;
455 }
456
457 static int pci_4v_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
458 {
459 struct pci_iommu *iommu;
460 unsigned long flags, npages, prot;
461 u32 dma_base;
462 struct scatterlist *sgtmp;
463 long entry, err;
464 int used;
465
466 /* Fast path single entry scatterlists. */
467 if (nelems == 1) {
468 sglist->dma_address =
469 pci_4v_map_single(pdev,
470 (page_address(sglist->page) + sglist->offset),
471 sglist->length, direction);
472 if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
473 return 0;
474 sglist->dma_length = sglist->length;
475 return 1;
476 }
477
478 iommu = pdev->dev.archdata.iommu;
479
480 if (unlikely(direction == PCI_DMA_NONE))
481 goto bad;
482
483 /* Step 1: Prepare scatter list. */
484 npages = prepare_sg(sglist, nelems);
485
486 /* Step 2: Allocate a cluster and context, if necessary. */
487 spin_lock_irqsave(&iommu->lock, flags);
488 entry = pci_arena_alloc(&iommu->arena, npages);
489 spin_unlock_irqrestore(&iommu->lock, flags);
490
491 if (unlikely(entry < 0L))
492 goto bad;
493
494 dma_base = iommu->page_table_map_base +
495 (entry << IO_PAGE_SHIFT);
496
497 /* Step 3: Normalize DMA addresses. */
498 used = nelems;
499
500 sgtmp = sglist;
501 while (used && sgtmp->dma_length) {
502 sgtmp->dma_address += dma_base;
503 sgtmp++;
504 used--;
505 }
506 used = nelems - used;
507
508 /* Step 4: Create the mappings. */
509 prot = HV_PCI_MAP_ATTR_READ;
510 if (direction != PCI_DMA_TODEVICE)
511 prot |= HV_PCI_MAP_ATTR_WRITE;
512
513 err = fill_sg(entry, pdev, sglist, used, nelems, prot);
514 if (unlikely(err < 0L))
515 goto iommu_map_failed;
516
517 return used;
518
519 bad:
520 if (printk_ratelimit())
521 WARN_ON(1);
522 return 0;
523
524 iommu_map_failed:
525 spin_lock_irqsave(&iommu->lock, flags);
526 pci_arena_free(&iommu->arena, entry, npages);
527 spin_unlock_irqrestore(&iommu->lock, flags);
528
529 return 0;
530 }
531
532 static void pci_4v_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
533 {
534 struct pci_pbm_info *pbm;
535 struct pci_iommu *iommu;
536 unsigned long flags, i, npages;
537 long entry;
538 u32 devhandle, bus_addr;
539
540 if (unlikely(direction == PCI_DMA_NONE)) {
541 if (printk_ratelimit())
542 WARN_ON(1);
543 }
544
545 iommu = pdev->dev.archdata.iommu;
546 pbm = pdev->dev.archdata.host_controller;
547 devhandle = pbm->devhandle;
548
549 bus_addr = sglist->dma_address & IO_PAGE_MASK;
550
551 for (i = 1; i < nelems; i++)
552 if (sglist[i].dma_length == 0)
553 break;
554 i--;
555 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
556 bus_addr) >> IO_PAGE_SHIFT;
557
558 entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
559
560 spin_lock_irqsave(&iommu->lock, flags);
561
562 pci_arena_free(&iommu->arena, entry, npages);
563
564 do {
565 unsigned long num;
566
567 num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
568 npages);
569 entry += num;
570 npages -= num;
571 } while (npages != 0);
572
573 spin_unlock_irqrestore(&iommu->lock, flags);
574 }
575
576 static void pci_4v_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
577 {
578 /* Nothing to do... */
579 }
580
581 static void pci_4v_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
582 {
583 /* Nothing to do... */
584 }
585
586 struct pci_iommu_ops pci_sun4v_iommu_ops = {
587 .alloc_consistent = pci_4v_alloc_consistent,
588 .free_consistent = pci_4v_free_consistent,
589 .map_single = pci_4v_map_single,
590 .unmap_single = pci_4v_unmap_single,
591 .map_sg = pci_4v_map_sg,
592 .unmap_sg = pci_4v_unmap_sg,
593 .dma_sync_single_for_cpu = pci_4v_dma_sync_single_for_cpu,
594 .dma_sync_sg_for_cpu = pci_4v_dma_sync_sg_for_cpu,
595 };
596
597 static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func)
598 {
599 if (bus < pbm->pci_first_busno ||
600 bus > pbm->pci_last_busno)
601 return 1;
602 return 0;
603 }
604
605 static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
606 int where, int size, u32 *value)
607 {
608 struct pci_pbm_info *pbm = bus_dev->sysdata;
609 u32 devhandle = pbm->devhandle;
610 unsigned int bus = bus_dev->number;
611 unsigned int device = PCI_SLOT(devfn);
612 unsigned int func = PCI_FUNC(devfn);
613 unsigned long ret;
614
615 if (pci_sun4v_out_of_range(pbm, bus, device, func)) {
616 ret = ~0UL;
617 } else {
618 ret = pci_sun4v_config_get(devhandle,
619 HV_PCI_DEVICE_BUILD(bus, device, func),
620 where, size);
621 #if 0
622 printk("rcfg: [%x:%x:%x:%d]=[%lx]\n",
623 devhandle, HV_PCI_DEVICE_BUILD(bus, device, func),
624 where, size, ret);
625 #endif
626 }
627 switch (size) {
628 case 1:
629 *value = ret & 0xff;
630 break;
631 case 2:
632 *value = ret & 0xffff;
633 break;
634 case 4:
635 *value = ret & 0xffffffff;
636 break;
637 };
638
639
640 return PCIBIOS_SUCCESSFUL;
641 }
642
643 static int pci_sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
644 int where, int size, u32 value)
645 {
646 struct pci_pbm_info *pbm = bus_dev->sysdata;
647 u32 devhandle = pbm->devhandle;
648 unsigned int bus = bus_dev->number;
649 unsigned int device = PCI_SLOT(devfn);
650 unsigned int func = PCI_FUNC(devfn);
651 unsigned long ret;
652
653 if (pci_sun4v_out_of_range(pbm, bus, device, func)) {
654 /* Do nothing. */
655 } else {
656 ret = pci_sun4v_config_put(devhandle,
657 HV_PCI_DEVICE_BUILD(bus, device, func),
658 where, size, value);
659 #if 0
660 printk("wcfg: [%x:%x:%x:%d] v[%x] == [%lx]\n",
661 devhandle, HV_PCI_DEVICE_BUILD(bus, device, func),
662 where, size, value, ret);
663 #endif
664 }
665 return PCIBIOS_SUCCESSFUL;
666 }
667
668 static struct pci_ops pci_sun4v_ops = {
669 .read = pci_sun4v_read_pci_cfg,
670 .write = pci_sun4v_write_pci_cfg,
671 };
672
673
674 static void pbm_scan_bus(struct pci_controller_info *p,
675 struct pci_pbm_info *pbm)
676 {
677 pbm->pci_bus = pci_scan_one_pbm(pbm);
678 }
679
680 static void pci_sun4v_scan_bus(struct pci_controller_info *p)
681 {
682 struct property *prop;
683 struct device_node *dp;
684
685 if ((dp = p->pbm_A.prom_node) != NULL) {
686 prop = of_find_property(dp, "66mhz-capable", NULL);
687 p->pbm_A.is_66mhz_capable = (prop != NULL);
688
689 pbm_scan_bus(p, &p->pbm_A);
690 }
691 if ((dp = p->pbm_B.prom_node) != NULL) {
692 prop = of_find_property(dp, "66mhz-capable", NULL);
693 p->pbm_B.is_66mhz_capable = (prop != NULL);
694
695 pbm_scan_bus(p, &p->pbm_B);
696 }
697
698 /* XXX register error interrupt handlers XXX */
699 }
700
701 static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
702 {
703 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
704 struct resource *res, *root;
705 u32 reg;
706 int where, size, is_64bit;
707
708 res = &pdev->resource[resource];
709 if (resource < 6) {
710 where = PCI_BASE_ADDRESS_0 + (resource * 4);
711 } else if (resource == PCI_ROM_RESOURCE) {
712 where = pdev->rom_base_reg;
713 } else {
714 /* Somebody might have asked allocation of a non-standard resource */
715 return;
716 }
717
718 /* XXX 64-bit MEM handling is not %100 correct... XXX */
719 is_64bit = 0;
720 if (res->flags & IORESOURCE_IO)
721 root = &pbm->io_space;
722 else {
723 root = &pbm->mem_space;
724 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
725 == PCI_BASE_ADDRESS_MEM_TYPE_64)
726 is_64bit = 1;
727 }
728
729 size = res->end - res->start;
730 pci_read_config_dword(pdev, where, &reg);
731 reg = ((reg & size) |
732 (((u32)(res->start - root->start)) & ~size));
733 if (resource == PCI_ROM_RESOURCE) {
734 reg |= PCI_ROM_ADDRESS_ENABLE;
735 res->flags |= IORESOURCE_ROM_ENABLE;
736 }
737 pci_write_config_dword(pdev, where, reg);
738
739 /* This knows that the upper 32-bits of the address
740 * must be zero. Our PCI common layer enforces this.
741 */
742 if (is_64bit)
743 pci_write_config_dword(pdev, where + 4, 0);
744 }
745
746 static void pci_sun4v_resource_adjust(struct pci_dev *pdev,
747 struct resource *res,
748 struct resource *root)
749 {
750 res->start += root->start;
751 res->end += root->start;
752 }
753
754 /* Use ranges property to determine where PCI MEM, I/O, and Config
755 * space are for this PCI bus module.
756 */
757 static void pci_sun4v_determine_mem_io_space(struct pci_pbm_info *pbm)
758 {
759 int i, saw_mem, saw_io;
760
761 saw_mem = saw_io = 0;
762 for (i = 0; i < pbm->num_pbm_ranges; i++) {
763 struct linux_prom_pci_ranges *pr = &pbm->pbm_ranges[i];
764 unsigned long a;
765 int type;
766
767 type = (pr->child_phys_hi >> 24) & 0x3;
768 a = (((unsigned long)pr->parent_phys_hi << 32UL) |
769 ((unsigned long)pr->parent_phys_lo << 0UL));
770
771 switch (type) {
772 case 1:
773 /* 16-bit IO space, 16MB */
774 pbm->io_space.start = a;
775 pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL);
776 pbm->io_space.flags = IORESOURCE_IO;
777 saw_io = 1;
778 break;
779
780 case 2:
781 /* 32-bit MEM space, 2GB */
782 pbm->mem_space.start = a;
783 pbm->mem_space.end = a + (0x80000000UL - 1UL);
784 pbm->mem_space.flags = IORESOURCE_MEM;
785 saw_mem = 1;
786 break;
787
788 case 3:
789 /* XXX 64-bit MEM handling XXX */
790
791 default:
792 break;
793 };
794 }
795
796 if (!saw_io || !saw_mem) {
797 prom_printf("%s: Fatal error, missing %s PBM range.\n",
798 pbm->name,
799 (!saw_io ? "IO" : "MEM"));
800 prom_halt();
801 }
802
803 printk("%s: PCI IO[%lx] MEM[%lx]\n",
804 pbm->name,
805 pbm->io_space.start,
806 pbm->mem_space.start);
807 }
808
809 static void pbm_register_toplevel_resources(struct pci_controller_info *p,
810 struct pci_pbm_info *pbm)
811 {
812 pbm->io_space.name = pbm->mem_space.name = pbm->name;
813
814 request_resource(&ioport_resource, &pbm->io_space);
815 request_resource(&iomem_resource, &pbm->mem_space);
816 pci_register_legacy_regions(&pbm->io_space,
817 &pbm->mem_space);
818 }
819
820 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
821 struct pci_iommu *iommu)
822 {
823 struct pci_iommu_arena *arena = &iommu->arena;
824 unsigned long i, cnt = 0;
825 u32 devhandle;
826
827 devhandle = pbm->devhandle;
828 for (i = 0; i < arena->limit; i++) {
829 unsigned long ret, io_attrs, ra;
830
831 ret = pci_sun4v_iommu_getmap(devhandle,
832 HV_PCI_TSBID(0, i),
833 &io_attrs, &ra);
834 if (ret == HV_EOK) {
835 if (page_in_phys_avail(ra)) {
836 pci_sun4v_iommu_demap(devhandle,
837 HV_PCI_TSBID(0, i), 1);
838 } else {
839 cnt++;
840 __set_bit(i, arena->map);
841 }
842 }
843 }
844
845 return cnt;
846 }
847
848 static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
849 {
850 struct pci_iommu *iommu = pbm->iommu;
851 struct property *prop;
852 unsigned long num_tsb_entries, sz;
853 u32 vdma[2], dma_mask, dma_offset;
854 int tsbsize;
855
856 prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
857 if (prop) {
858 u32 *val = prop->value;
859
860 vdma[0] = val[0];
861 vdma[1] = val[1];
862 } else {
863 /* No property, use default values. */
864 vdma[0] = 0x80000000;
865 vdma[1] = 0x80000000;
866 }
867
868 dma_mask = vdma[0];
869 switch (vdma[1]) {
870 case 0x20000000:
871 dma_mask |= 0x1fffffff;
872 tsbsize = 64;
873 break;
874
875 case 0x40000000:
876 dma_mask |= 0x3fffffff;
877 tsbsize = 128;
878 break;
879
880 case 0x80000000:
881 dma_mask |= 0x7fffffff;
882 tsbsize = 256;
883 break;
884
885 default:
886 prom_printf("PCI-SUN4V: strange virtual-dma size.\n");
887 prom_halt();
888 };
889
890 tsbsize *= (8 * 1024);
891
892 num_tsb_entries = tsbsize / sizeof(iopte_t);
893
894 dma_offset = vdma[0];
895
896 /* Setup initial software IOMMU state. */
897 spin_lock_init(&iommu->lock);
898 iommu->ctx_lowest_free = 1;
899 iommu->page_table_map_base = dma_offset;
900 iommu->dma_addr_mask = dma_mask;
901
902 /* Allocate and initialize the free area map. */
903 sz = num_tsb_entries / 8;
904 sz = (sz + 7UL) & ~7UL;
905 iommu->arena.map = kzalloc(sz, GFP_KERNEL);
906 if (!iommu->arena.map) {
907 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
908 prom_halt();
909 }
910 iommu->arena.limit = num_tsb_entries;
911
912 sz = probe_existing_entries(pbm, iommu);
913 if (sz)
914 printk("%s: Imported %lu TSB entries from OBP\n",
915 pbm->name, sz);
916 }
917
918 static void pci_sun4v_get_bus_range(struct pci_pbm_info *pbm)
919 {
920 struct property *prop;
921 unsigned int *busrange;
922
923 prop = of_find_property(pbm->prom_node, "bus-range", NULL);
924
925 busrange = prop->value;
926
927 pbm->pci_first_busno = busrange[0];
928 pbm->pci_last_busno = busrange[1];
929
930 }
931
932 #ifdef CONFIG_PCI_MSI
933 struct pci_sun4v_msiq_entry {
934 u64 version_type;
935 #define MSIQ_VERSION_MASK 0xffffffff00000000UL
936 #define MSIQ_VERSION_SHIFT 32
937 #define MSIQ_TYPE_MASK 0x00000000000000ffUL
938 #define MSIQ_TYPE_SHIFT 0
939 #define MSIQ_TYPE_NONE 0x00
940 #define MSIQ_TYPE_MSG 0x01
941 #define MSIQ_TYPE_MSI32 0x02
942 #define MSIQ_TYPE_MSI64 0x03
943 #define MSIQ_TYPE_INTX 0x08
944 #define MSIQ_TYPE_NONE2 0xff
945
946 u64 intx_sysino;
947 u64 reserved1;
948 u64 stick;
949 u64 req_id; /* bus/device/func */
950 #define MSIQ_REQID_BUS_MASK 0xff00UL
951 #define MSIQ_REQID_BUS_SHIFT 8
952 #define MSIQ_REQID_DEVICE_MASK 0x00f8UL
953 #define MSIQ_REQID_DEVICE_SHIFT 3
954 #define MSIQ_REQID_FUNC_MASK 0x0007UL
955 #define MSIQ_REQID_FUNC_SHIFT 0
956
957 u64 msi_address;
958
959 /* The format of this value is message type dependant.
960 * For MSI bits 15:0 are the data from the MSI packet.
961 * For MSI-X bits 31:0 are the data from the MSI packet.
962 * For MSG, the message code and message routing code where:
963 * bits 39:32 is the bus/device/fn of the msg target-id
964 * bits 18:16 is the message routing code
965 * bits 7:0 is the message code
966 * For INTx the low order 2-bits are:
967 * 00 - INTA
968 * 01 - INTB
969 * 10 - INTC
970 * 11 - INTD
971 */
972 u64 msi_data;
973
974 u64 reserved2;
975 };
976
977 /* For now this just runs as a pre-handler for the real interrupt handler.
978 * So we just walk through the queue and ACK all the entries, update the
979 * head pointer, and return.
980 *
981 * In the longer term it would be nice to do something more integrated
982 * wherein we can pass in some of this MSI info to the drivers. This
983 * would be most useful for PCIe fabric error messages, although we could
984 * invoke those directly from the loop here in order to pass the info around.
985 */
986 static void pci_sun4v_msi_prehandler(unsigned int ino, void *data1, void *data2)
987 {
988 struct pci_pbm_info *pbm = data1;
989 struct pci_sun4v_msiq_entry *base, *ep;
990 unsigned long msiqid, orig_head, head, type, err;
991
992 msiqid = (unsigned long) data2;
993
994 head = 0xdeadbeef;
995 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, &head);
996 if (unlikely(err))
997 goto hv_error_get;
998
999 if (unlikely(head >= (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))))
1000 goto bad_offset;
1001
1002 head /= sizeof(struct pci_sun4v_msiq_entry);
1003 orig_head = head;
1004 base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
1005 (pbm->msiq_ent_count *
1006 sizeof(struct pci_sun4v_msiq_entry))));
1007 ep = &base[head];
1008 while ((ep->version_type & MSIQ_TYPE_MASK) != 0) {
1009 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
1010 if (unlikely(type != MSIQ_TYPE_MSI32 &&
1011 type != MSIQ_TYPE_MSI64))
1012 goto bad_type;
1013
1014 pci_sun4v_msi_setstate(pbm->devhandle,
1015 ep->msi_data /* msi_num */,
1016 HV_MSISTATE_IDLE);
1017
1018 /* Clear the entry. */
1019 ep->version_type &= ~MSIQ_TYPE_MASK;
1020
1021 /* Go to next entry in ring. */
1022 head++;
1023 if (head >= pbm->msiq_ent_count)
1024 head = 0;
1025 ep = &base[head];
1026 }
1027
1028 if (likely(head != orig_head)) {
1029 /* ACK entries by updating head pointer. */
1030 head *= sizeof(struct pci_sun4v_msiq_entry);
1031 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
1032 if (unlikely(err))
1033 goto hv_error_set;
1034 }
1035 return;
1036
1037 hv_error_set:
1038 printk(KERN_EMERG "MSI: Hypervisor set head gives error %lu\n", err);
1039 goto hv_error_cont;
1040
1041 hv_error_get:
1042 printk(KERN_EMERG "MSI: Hypervisor get head gives error %lu\n", err);
1043
1044 hv_error_cont:
1045 printk(KERN_EMERG "MSI: devhandle[%x] msiqid[%lx] head[%lu]\n",
1046 pbm->devhandle, msiqid, head);
1047 return;
1048
1049 bad_offset:
1050 printk(KERN_EMERG "MSI: Hypervisor gives bad offset %lx max(%lx)\n",
1051 head, pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry));
1052 return;
1053
1054 bad_type:
1055 printk(KERN_EMERG "MSI: Entry has bad type %lx\n", type);
1056 return;
1057 }
1058
1059 static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
1060 {
1061 unsigned long size, bits_per_ulong;
1062
1063 bits_per_ulong = sizeof(unsigned long) * 8;
1064 size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
1065 size /= 8;
1066 BUG_ON(size % sizeof(unsigned long));
1067
1068 pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
1069 if (!pbm->msi_bitmap)
1070 return -ENOMEM;
1071
1072 return 0;
1073 }
1074
1075 static void msi_bitmap_free(struct pci_pbm_info *pbm)
1076 {
1077 kfree(pbm->msi_bitmap);
1078 pbm->msi_bitmap = NULL;
1079 }
1080
1081 static int msi_queue_alloc(struct pci_pbm_info *pbm)
1082 {
1083 unsigned long q_size, alloc_size, pages, order;
1084 int i;
1085
1086 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1087 alloc_size = (pbm->msiq_num * q_size);
1088 order = get_order(alloc_size);
1089 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
1090 if (pages == 0UL) {
1091 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
1092 order);
1093 return -ENOMEM;
1094 }
1095 memset((char *)pages, 0, PAGE_SIZE << order);
1096 pbm->msi_queues = (void *) pages;
1097
1098 for (i = 0; i < pbm->msiq_num; i++) {
1099 unsigned long err, base = __pa(pages + (i * q_size));
1100 unsigned long ret1, ret2;
1101
1102 err = pci_sun4v_msiq_conf(pbm->devhandle,
1103 pbm->msiq_first + i,
1104 base, pbm->msiq_ent_count);
1105 if (err) {
1106 printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
1107 err);
1108 goto h_error;
1109 }
1110
1111 err = pci_sun4v_msiq_info(pbm->devhandle,
1112 pbm->msiq_first + i,
1113 &ret1, &ret2);
1114 if (err) {
1115 printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
1116 err);
1117 goto h_error;
1118 }
1119 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
1120 printk(KERN_ERR "MSI: Bogus qconf "
1121 "expected[%lx:%x] got[%lx:%lx]\n",
1122 base, pbm->msiq_ent_count,
1123 ret1, ret2);
1124 goto h_error;
1125 }
1126 }
1127
1128 return 0;
1129
1130 h_error:
1131 free_pages(pages, order);
1132 return -EINVAL;
1133 }
1134
1135 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1136 {
1137 const u32 *val;
1138 int len;
1139
1140 val = of_get_property(pbm->prom_node, "#msi-eqs", &len);
1141 if (!val || len != 4)
1142 goto no_msi;
1143 pbm->msiq_num = *val;
1144 if (pbm->msiq_num) {
1145 const struct msiq_prop {
1146 u32 first_msiq;
1147 u32 num_msiq;
1148 u32 first_devino;
1149 } *mqp;
1150 const struct msi_range_prop {
1151 u32 first_msi;
1152 u32 num_msi;
1153 } *mrng;
1154 const struct addr_range_prop {
1155 u32 msi32_high;
1156 u32 msi32_low;
1157 u32 msi32_len;
1158 u32 msi64_high;
1159 u32 msi64_low;
1160 u32 msi64_len;
1161 } *arng;
1162
1163 val = of_get_property(pbm->prom_node, "msi-eq-size", &len);
1164 if (!val || len != 4)
1165 goto no_msi;
1166
1167 pbm->msiq_ent_count = *val;
1168
1169 mqp = of_get_property(pbm->prom_node,
1170 "msi-eq-to-devino", &len);
1171 if (!mqp || len != sizeof(struct msiq_prop))
1172 goto no_msi;
1173
1174 pbm->msiq_first = mqp->first_msiq;
1175 pbm->msiq_first_devino = mqp->first_devino;
1176
1177 val = of_get_property(pbm->prom_node, "#msi", &len);
1178 if (!val || len != 4)
1179 goto no_msi;
1180 pbm->msi_num = *val;
1181
1182 mrng = of_get_property(pbm->prom_node, "msi-ranges", &len);
1183 if (!mrng || len != sizeof(struct msi_range_prop))
1184 goto no_msi;
1185 pbm->msi_first = mrng->first_msi;
1186
1187 val = of_get_property(pbm->prom_node, "msi-data-mask", &len);
1188 if (!val || len != 4)
1189 goto no_msi;
1190 pbm->msi_data_mask = *val;
1191
1192 val = of_get_property(pbm->prom_node, "msix-data-width", &len);
1193 if (!val || len != 4)
1194 goto no_msi;
1195 pbm->msix_data_width = *val;
1196
1197 arng = of_get_property(pbm->prom_node, "msi-address-ranges",
1198 &len);
1199 if (!arng || len != sizeof(struct addr_range_prop))
1200 goto no_msi;
1201 pbm->msi32_start = ((u64)arng->msi32_high << 32) |
1202 (u64) arng->msi32_low;
1203 pbm->msi64_start = ((u64)arng->msi64_high << 32) |
1204 (u64) arng->msi64_low;
1205 pbm->msi32_len = arng->msi32_len;
1206 pbm->msi64_len = arng->msi64_len;
1207
1208 if (msi_bitmap_alloc(pbm))
1209 goto no_msi;
1210
1211 if (msi_queue_alloc(pbm)) {
1212 msi_bitmap_free(pbm);
1213 goto no_msi;
1214 }
1215
1216 printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
1217 "devino[0x%x]\n",
1218 pbm->name,
1219 pbm->msiq_first, pbm->msiq_num,
1220 pbm->msiq_ent_count,
1221 pbm->msiq_first_devino);
1222 printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
1223 "width[%u]\n",
1224 pbm->name,
1225 pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
1226 pbm->msix_data_width);
1227 printk(KERN_INFO "%s: MSI addr32[0x%lx:0x%x] "
1228 "addr64[0x%lx:0x%x]\n",
1229 pbm->name,
1230 pbm->msi32_start, pbm->msi32_len,
1231 pbm->msi64_start, pbm->msi64_len);
1232 printk(KERN_INFO "%s: MSI queues at RA [%p]\n",
1233 pbm->name,
1234 pbm->msi_queues);
1235 }
1236
1237 return;
1238
1239 no_msi:
1240 pbm->msiq_num = 0;
1241 printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
1242 }
1243
1244 static int alloc_msi(struct pci_pbm_info *pbm)
1245 {
1246 int i;
1247
1248 for (i = 0; i < pbm->msi_num; i++) {
1249 if (!test_and_set_bit(i, pbm->msi_bitmap))
1250 return i + pbm->msi_first;
1251 }
1252
1253 return -ENOENT;
1254 }
1255
1256 static void free_msi(struct pci_pbm_info *pbm, int msi_num)
1257 {
1258 msi_num -= pbm->msi_first;
1259 clear_bit(msi_num, pbm->msi_bitmap);
1260 }
1261
1262 static int pci_sun4v_setup_msi_irq(unsigned int *virt_irq_p,
1263 struct pci_dev *pdev,
1264 struct msi_desc *entry)
1265 {
1266 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1267 unsigned long devino, msiqid;
1268 struct msi_msg msg;
1269 int msi_num, err;
1270
1271 *virt_irq_p = 0;
1272
1273 msi_num = alloc_msi(pbm);
1274 if (msi_num < 0)
1275 return msi_num;
1276
1277 devino = sun4v_build_msi(pbm->devhandle, virt_irq_p,
1278 pbm->msiq_first_devino,
1279 (pbm->msiq_first_devino +
1280 pbm->msiq_num));
1281 err = -ENOMEM;
1282 if (!devino)
1283 goto out_err;
1284
1285 set_irq_msi(*virt_irq_p, entry);
1286
1287 msiqid = ((devino - pbm->msiq_first_devino) +
1288 pbm->msiq_first);
1289
1290 err = -EINVAL;
1291 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
1292 if (err)
1293 goto out_err;
1294
1295 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
1296 goto out_err;
1297
1298 if (pci_sun4v_msi_setmsiq(pbm->devhandle,
1299 msi_num, msiqid,
1300 (entry->msi_attrib.is_64 ?
1301 HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
1302 goto out_err;
1303
1304 if (pci_sun4v_msi_setstate(pbm->devhandle, msi_num, HV_MSISTATE_IDLE))
1305 goto out_err;
1306
1307 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_VALID))
1308 goto out_err;
1309
1310 pdev->dev.archdata.msi_num = msi_num;
1311
1312 if (entry->msi_attrib.is_64) {
1313 msg.address_hi = pbm->msi64_start >> 32;
1314 msg.address_lo = pbm->msi64_start & 0xffffffff;
1315 } else {
1316 msg.address_hi = 0;
1317 msg.address_lo = pbm->msi32_start;
1318 }
1319 msg.data = msi_num;
1320 write_msi_msg(*virt_irq_p, &msg);
1321
1322 irq_install_pre_handler(*virt_irq_p,
1323 pci_sun4v_msi_prehandler,
1324 pbm, (void *) msiqid);
1325
1326 return 0;
1327
1328 out_err:
1329 free_msi(pbm, msi_num);
1330 sun4v_destroy_msi(*virt_irq_p);
1331 *virt_irq_p = 0;
1332 return err;
1333
1334 }
1335
1336 static void pci_sun4v_teardown_msi_irq(unsigned int virt_irq,
1337 struct pci_dev *pdev)
1338 {
1339 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1340 unsigned long msiqid, err;
1341 unsigned int msi_num;
1342
1343 msi_num = pdev->dev.archdata.msi_num;
1344 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi_num, &msiqid);
1345 if (err) {
1346 printk(KERN_ERR "%s: getmsiq gives error %lu\n",
1347 pbm->name, err);
1348 return;
1349 }
1350
1351 pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_INVALID);
1352 pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_INVALID);
1353
1354 free_msi(pbm, msi_num);
1355
1356 /* The sun4v_destroy_msi() will liberate the devino and thus the MSIQ
1357 * allocation.
1358 */
1359 sun4v_destroy_msi(virt_irq);
1360 }
1361 #else /* CONFIG_PCI_MSI */
1362 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1363 {
1364 }
1365 #endif /* !(CONFIG_PCI_MSI) */
1366
1367 static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle)
1368 {
1369 struct pci_pbm_info *pbm;
1370 struct property *prop;
1371 int len, i;
1372
1373 if (devhandle & 0x40)
1374 pbm = &p->pbm_B;
1375 else
1376 pbm = &p->pbm_A;
1377
1378 pbm->parent = p;
1379 pbm->prom_node = dp;
1380 pbm->pci_first_slot = 1;
1381
1382 pbm->devhandle = devhandle;
1383
1384 pbm->name = dp->full_name;
1385
1386 printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1387
1388 prop = of_find_property(dp, "ranges", &len);
1389 pbm->pbm_ranges = prop->value;
1390 pbm->num_pbm_ranges =
1391 (len / sizeof(struct linux_prom_pci_ranges));
1392
1393 /* Mask out the top 8 bits of the ranges, leaving the real
1394 * physical address.
1395 */
1396 for (i = 0; i < pbm->num_pbm_ranges; i++)
1397 pbm->pbm_ranges[i].parent_phys_hi &= 0x0fffffff;
1398
1399 pci_sun4v_determine_mem_io_space(pbm);
1400 pbm_register_toplevel_resources(p, pbm);
1401
1402 prop = of_find_property(dp, "interrupt-map", &len);
1403 pbm->pbm_intmap = prop->value;
1404 pbm->num_pbm_intmap =
1405 (len / sizeof(struct linux_prom_pci_intmap));
1406
1407 prop = of_find_property(dp, "interrupt-map-mask", NULL);
1408 pbm->pbm_intmask = prop->value;
1409
1410 pci_sun4v_get_bus_range(pbm);
1411 pci_sun4v_iommu_init(pbm);
1412 pci_sun4v_msi_init(pbm);
1413 }
1414
1415 void sun4v_pci_init(struct device_node *dp, char *model_name)
1416 {
1417 struct pci_controller_info *p;
1418 struct pci_iommu *iommu;
1419 struct property *prop;
1420 struct linux_prom64_registers *regs;
1421 u32 devhandle;
1422 int i;
1423
1424 prop = of_find_property(dp, "reg", NULL);
1425 regs = prop->value;
1426
1427 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1428
1429 for (p = pci_controller_root; p; p = p->next) {
1430 struct pci_pbm_info *pbm;
1431
1432 if (p->pbm_A.prom_node && p->pbm_B.prom_node)
1433 continue;
1434
1435 pbm = (p->pbm_A.prom_node ?
1436 &p->pbm_A :
1437 &p->pbm_B);
1438
1439 if (pbm->devhandle == (devhandle ^ 0x40)) {
1440 pci_sun4v_pbm_init(p, dp, devhandle);
1441 return;
1442 }
1443 }
1444
1445 for_each_possible_cpu(i) {
1446 unsigned long page = get_zeroed_page(GFP_ATOMIC);
1447
1448 if (!page)
1449 goto fatal_memory_error;
1450
1451 per_cpu(pci_iommu_batch, i).pglist = (u64 *) page;
1452 }
1453
1454 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1455 if (!p)
1456 goto fatal_memory_error;
1457
1458 iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1459 if (!iommu)
1460 goto fatal_memory_error;
1461
1462 p->pbm_A.iommu = iommu;
1463
1464 iommu = kzalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1465 if (!iommu)
1466 goto fatal_memory_error;
1467
1468 p->pbm_B.iommu = iommu;
1469
1470 p->next = pci_controller_root;
1471 pci_controller_root = p;
1472
1473 p->index = pci_num_controllers++;
1474 p->pbms_same_domain = 0;
1475
1476 p->scan_bus = pci_sun4v_scan_bus;
1477 p->base_address_update = pci_sun4v_base_address_update;
1478 p->resource_adjust = pci_sun4v_resource_adjust;
1479 #ifdef CONFIG_PCI_MSI
1480 p->setup_msi_irq = pci_sun4v_setup_msi_irq;
1481 p->teardown_msi_irq = pci_sun4v_teardown_msi_irq;
1482 #endif
1483 p->pci_ops = &pci_sun4v_ops;
1484
1485 /* Like PSYCHO and SCHIZO we have a 2GB aligned area
1486 * for memory space.
1487 */
1488 pci_memspace_mask = 0x7fffffffUL;
1489
1490 pci_sun4v_pbm_init(p, dp, devhandle);
1491 return;
1492
1493 fatal_memory_error:
1494 prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
1495 prom_halt();
1496 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree