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Merge branch 'master' of /home/davem/src/GIT/linux-2.6/
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / tg3.c
blob46a3f86125be7659e4f35700a6ee209914febcea
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0 0
59 #define BAR_2 2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.99"
72 #define DRV_MODULE_RELDATE "April 20, 2009"
73
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90 #define TG3_TX_TIMEOUT (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
133
134 #define TG3_RAW_IP_ALIGN 2
135
136 /* number of ETHTOOL_GSTATS u64's */
137 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
139 #define TG3_NUM_TEST 6
140
141 #define FIRMWARE_TG3 "tigon/tg3.bin"
142 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
144
145 static char version[] __devinitdata =
146 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_MODULE_VERSION);
152 MODULE_FIRMWARE(FIRMWARE_TG3);
153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
156
157 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158 module_param(tg3_debug, int, 0);
159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161 static struct pci_device_id tg3_pci_tbl[] = {
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
234 {}
235 };
236
237 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
238
239 static const struct {
240 const char string[ETH_GSTRING_LEN];
241 } ethtool_stats_keys[TG3_NUM_STATS] = {
242 { "rx_octets" },
243 { "rx_fragments" },
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
247 { "rx_fcs_errors" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
254 { "rx_jabbers" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
268
269 { "tx_octets" },
270 { "tx_collisions" },
271
272 { "tx_xon_sent" },
273 { "tx_xoff_sent" },
274 { "tx_flow_control" },
275 { "tx_mac_errors" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
278 { "tx_deferred" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
299 { "tx_discards" },
300 { "tx_errors" },
301
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
304 { "rxbds_empty" },
305 { "rx_discards" },
306 { "rx_errors" },
307 { "rx_threshold_hit" },
308
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
312
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
315 { "nic_irqs" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
318 };
319
320 static const struct {
321 const char string[ETH_GSTRING_LEN];
322 } ethtool_test_keys[TG3_NUM_TEST] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
329 };
330
331 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
332 {
333 writel(val, tp->regs + off);
334 }
335
336 static u32 tg3_read32(struct tg3 *tp, u32 off)
337 {
338 return (readl(tp->regs + off));
339 }
340
341 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
342 {
343 writel(val, tp->aperegs + off);
344 }
345
346 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
347 {
348 return (readl(tp->aperegs + off));
349 }
350
351 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
352 {
353 unsigned long flags;
354
355 spin_lock_irqsave(&tp->indirect_lock, flags);
356 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
358 spin_unlock_irqrestore(&tp->indirect_lock, flags);
359 }
360
361 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
362 {
363 writel(val, tp->regs + off);
364 readl(tp->regs + off);
365 }
366
367 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
368 {
369 unsigned long flags;
370 u32 val;
371
372 spin_lock_irqsave(&tp->indirect_lock, flags);
373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
376 return val;
377 }
378
379 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
380 {
381 unsigned long flags;
382
383 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385 TG3_64BIT_REG_LOW, val);
386 return;
387 }
388 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390 TG3_64BIT_REG_LOW, val);
391 return;
392 }
393
394 spin_lock_irqsave(&tp->indirect_lock, flags);
395 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397 spin_unlock_irqrestore(&tp->indirect_lock, flags);
398
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
401 */
402 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
403 (val == 0x1)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
406 }
407 }
408
409 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
410 {
411 unsigned long flags;
412 u32 val;
413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418 return val;
419 }
420
421 /* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
425 */
426 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
427 {
428 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 /* Non-posted methods */
431 tp->write32(tp, off, val);
432 else {
433 /* Posted method */
434 tg3_write32(tp, off, val);
435 if (usec_wait)
436 udelay(usec_wait);
437 tp->read32(tp, off);
438 }
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
441 */
442 if (usec_wait)
443 udelay(usec_wait);
444 }
445
446 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
447 {
448 tp->write32_mbox(tp, off, val);
449 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451 tp->read32_mbox(tp, off);
452 }
453
454 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
455 {
456 void __iomem *mbox = tp->regs + off;
457 writel(val, mbox);
458 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
459 writel(val, mbox);
460 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
461 readl(mbox);
462 }
463
464 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
465 {
466 return (readl(tp->regs + off + GRCMBOX_BASE));
467 }
468
469 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
470 {
471 writel(val, tp->regs + off + GRCMBOX_BASE);
472 }
473
474 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
475 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
476 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
478 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
479
480 #define tw32(reg,val) tp->write32(tp, reg, val)
481 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
483 #define tr32(reg) tp->read32(tp, reg)
484
485 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
486 {
487 unsigned long flags;
488
489 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
491 return;
492
493 spin_lock_irqsave(&tp->indirect_lock, flags);
494 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
497
498 /* Always leave this as zero. */
499 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
500 } else {
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502 tw32_f(TG3PCI_MEM_WIN_DATA, val);
503
504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 }
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
508 }
509
510 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
511 {
512 unsigned long flags;
513
514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
516 *val = 0;
517 return;
518 }
519
520 spin_lock_irqsave(&tp->indirect_lock, flags);
521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
524
525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
535 }
536
537 static void tg3_ape_lock_init(struct tg3 *tp)
538 {
539 int i;
540
541 /* Make sure the driver hasn't any stale locks. */
542 for (i = 0; i < 8; i++)
543 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544 APE_LOCK_GRANT_DRIVER);
545 }
546
547 static int tg3_ape_lock(struct tg3 *tp, int locknum)
548 {
549 int i, off;
550 int ret = 0;
551 u32 status;
552
553 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
554 return 0;
555
556 switch (locknum) {
557 case TG3_APE_LOCK_GRC:
558 case TG3_APE_LOCK_MEM:
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 off = 4 * locknum;
565
566 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
567
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i = 0; i < 100; i++) {
570 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571 if (status == APE_LOCK_GRANT_DRIVER)
572 break;
573 udelay(10);
574 }
575
576 if (status != APE_LOCK_GRANT_DRIVER) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579 APE_LOCK_GRANT_DRIVER);
580
581 ret = -EBUSY;
582 }
583
584 return ret;
585 }
586
587 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
588 {
589 int off;
590
591 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
592 return;
593
594 switch (locknum) {
595 case TG3_APE_LOCK_GRC:
596 case TG3_APE_LOCK_MEM:
597 break;
598 default:
599 return;
600 }
601
602 off = 4 * locknum;
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
604 }
605
606 static void tg3_disable_ints(struct tg3 *tp)
607 {
608 tw32(TG3PCI_MISC_HOST_CTRL,
609 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
611 }
612
613 static inline void tg3_cond_int(struct tg3 *tp)
614 {
615 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616 (tp->hw_status->status & SD_STATUS_UPDATED))
617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
618 else
619 tw32(HOSTCC_MODE, tp->coalesce_mode |
620 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
621 }
622
623 static void tg3_enable_ints(struct tg3 *tp)
624 {
625 tp->irq_sync = 0;
626 wmb();
627
628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
630 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631 (tp->last_tag << 24));
632 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634 (tp->last_tag << 24));
635 tg3_cond_int(tp);
636 }
637
638 static inline unsigned int tg3_has_work(struct tg3 *tp)
639 {
640 struct tg3_hw_status *sblk = tp->hw_status;
641 unsigned int work_exists = 0;
642
643 /* check for phy events */
644 if (!(tp->tg3_flags &
645 (TG3_FLAG_USE_LINKCHG_REG |
646 TG3_FLAG_POLL_SERDES))) {
647 if (sblk->status & SD_STATUS_LINK_CHG)
648 work_exists = 1;
649 }
650 /* check for RX/TX work to do */
651 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
653 work_exists = 1;
654
655 return work_exists;
656 }
657
658 /* tg3_restart_ints
659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
661 * which reenables interrupts
662 */
663 static void tg3_restart_ints(struct tg3 *tp)
664 {
665 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
666 tp->last_tag << 24);
667 mmiowb();
668
669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
672 */
673 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
674 tg3_has_work(tp))
675 tw32(HOSTCC_MODE, tp->coalesce_mode |
676 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
677 }
678
679 static inline void tg3_netif_stop(struct tg3 *tp)
680 {
681 tp->dev->trans_start = jiffies; /* prevent tx timeout */
682 napi_disable(&tp->napi);
683 netif_tx_disable(tp->dev);
684 }
685
686 static inline void tg3_netif_start(struct tg3 *tp)
687 {
688 netif_wake_queue(tp->dev);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
692 */
693 napi_enable(&tp->napi);
694 tp->hw_status->status |= SD_STATUS_UPDATED;
695 tg3_enable_ints(tp);
696 }
697
698 static void tg3_switch_clocks(struct tg3 *tp)
699 {
700 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
701 u32 orig_clock_ctrl;
702
703 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
705 return;
706
707 orig_clock_ctrl = clock_ctrl;
708 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709 CLOCK_CTRL_CLKRUN_OENABLE |
710 0x1f);
711 tp->pci_clock_ctrl = clock_ctrl;
712
713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
715 tw32_wait_f(TG3PCI_CLOCK_CTRL,
716 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
717 }
718 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
719 tw32_wait_f(TG3PCI_CLOCK_CTRL,
720 clock_ctrl |
721 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
722 40);
723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | (CLOCK_CTRL_ALTCLK),
725 40);
726 }
727 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
728 }
729
730 #define PHY_BUSY_LOOPS 5000
731
732 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
733 {
734 u32 frame_val;
735 unsigned int loops;
736 int ret;
737
738 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739 tw32_f(MAC_MI_MODE,
740 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
741 udelay(80);
742 }
743
744 *val = 0x0;
745
746 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747 MI_COM_PHY_ADDR_MASK);
748 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749 MI_COM_REG_ADDR_MASK);
750 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
751
752 tw32_f(MAC_MI_COM, frame_val);
753
754 loops = PHY_BUSY_LOOPS;
755 while (loops != 0) {
756 udelay(10);
757 frame_val = tr32(MAC_MI_COM);
758
759 if ((frame_val & MI_COM_BUSY) == 0) {
760 udelay(5);
761 frame_val = tr32(MAC_MI_COM);
762 break;
763 }
764 loops -= 1;
765 }
766
767 ret = -EBUSY;
768 if (loops != 0) {
769 *val = frame_val & MI_COM_DATA_MASK;
770 ret = 0;
771 }
772
773 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774 tw32_f(MAC_MI_MODE, tp->mi_mode);
775 udelay(80);
776 }
777
778 return ret;
779 }
780
781 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
782 {
783 u32 frame_val;
784 unsigned int loops;
785 int ret;
786
787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
788 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
789 return 0;
790
791 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792 tw32_f(MAC_MI_MODE,
793 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 udelay(80);
795 }
796
797 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798 MI_COM_PHY_ADDR_MASK);
799 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800 MI_COM_REG_ADDR_MASK);
801 frame_val |= (val & MI_COM_DATA_MASK);
802 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
803
804 tw32_f(MAC_MI_COM, frame_val);
805
806 loops = PHY_BUSY_LOOPS;
807 while (loops != 0) {
808 udelay(10);
809 frame_val = tr32(MAC_MI_COM);
810 if ((frame_val & MI_COM_BUSY) == 0) {
811 udelay(5);
812 frame_val = tr32(MAC_MI_COM);
813 break;
814 }
815 loops -= 1;
816 }
817
818 ret = -EBUSY;
819 if (loops != 0)
820 ret = 0;
821
822 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823 tw32_f(MAC_MI_MODE, tp->mi_mode);
824 udelay(80);
825 }
826
827 return ret;
828 }
829
830 static int tg3_bmcr_reset(struct tg3 *tp)
831 {
832 u32 phy_control;
833 int limit, err;
834
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
837 */
838 phy_control = BMCR_RESET;
839 err = tg3_writephy(tp, MII_BMCR, phy_control);
840 if (err != 0)
841 return -EBUSY;
842
843 limit = 5000;
844 while (limit--) {
845 err = tg3_readphy(tp, MII_BMCR, &phy_control);
846 if (err != 0)
847 return -EBUSY;
848
849 if ((phy_control & BMCR_RESET) == 0) {
850 udelay(40);
851 break;
852 }
853 udelay(10);
854 }
855 if (limit < 0)
856 return -EBUSY;
857
858 return 0;
859 }
860
861 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
862 {
863 struct tg3 *tp = bp->priv;
864 u32 val;
865
866 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
867 return -EAGAIN;
868
869 if (tg3_readphy(tp, reg, &val))
870 return -EIO;
871
872 return val;
873 }
874
875 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
876 {
877 struct tg3 *tp = bp->priv;
878
879 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
880 return -EAGAIN;
881
882 if (tg3_writephy(tp, reg, val))
883 return -EIO;
884
885 return 0;
886 }
887
888 static int tg3_mdio_reset(struct mii_bus *bp)
889 {
890 return 0;
891 }
892
893 static void tg3_mdio_config_5785(struct tg3 *tp)
894 {
895 u32 val;
896 struct phy_device *phydev;
897
898 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900 case TG3_PHY_ID_BCM50610:
901 val = MAC_PHYCFG2_50610_LED_MODES;
902 break;
903 case TG3_PHY_ID_BCMAC131:
904 val = MAC_PHYCFG2_AC131_LED_MODES;
905 break;
906 case TG3_PHY_ID_RTL8211C:
907 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
908 break;
909 case TG3_PHY_ID_RTL8201E:
910 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
911 break;
912 default:
913 return;
914 }
915
916 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917 tw32(MAC_PHYCFG2, val);
918
919 val = tr32(MAC_PHYCFG1);
920 val &= ~MAC_PHYCFG1_RGMII_INT;
921 tw32(MAC_PHYCFG1, val);
922
923 return;
924 }
925
926 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
927 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
928 MAC_PHYCFG2_FMODE_MASK_MASK |
929 MAC_PHYCFG2_GMODE_MASK_MASK |
930 MAC_PHYCFG2_ACT_MASK_MASK |
931 MAC_PHYCFG2_QUAL_MASK_MASK |
932 MAC_PHYCFG2_INBAND_ENABLE;
933
934 tw32(MAC_PHYCFG2, val);
935
936 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
937 MAC_PHYCFG1_RGMII_SND_STAT_EN);
938 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
939 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
940 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
941 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
942 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
943 }
944 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
945
946 val = tr32(MAC_EXT_RGMII_MODE);
947 val &= ~(MAC_RGMII_MODE_RX_INT_B |
948 MAC_RGMII_MODE_RX_QUALITY |
949 MAC_RGMII_MODE_RX_ACTIVITY |
950 MAC_RGMII_MODE_RX_ENG_DET |
951 MAC_RGMII_MODE_TX_ENABLE |
952 MAC_RGMII_MODE_TX_LOWPWR |
953 MAC_RGMII_MODE_TX_RESET);
954 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
955 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
956 val |= MAC_RGMII_MODE_RX_INT_B |
957 MAC_RGMII_MODE_RX_QUALITY |
958 MAC_RGMII_MODE_RX_ACTIVITY |
959 MAC_RGMII_MODE_RX_ENG_DET;
960 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
961 val |= MAC_RGMII_MODE_TX_ENABLE |
962 MAC_RGMII_MODE_TX_LOWPWR |
963 MAC_RGMII_MODE_TX_RESET;
964 }
965 tw32(MAC_EXT_RGMII_MODE, val);
966 }
967
968 static void tg3_mdio_start(struct tg3 *tp)
969 {
970 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
971 mutex_lock(&tp->mdio_bus->mdio_lock);
972 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
973 mutex_unlock(&tp->mdio_bus->mdio_lock);
974 }
975
976 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
977 tw32_f(MAC_MI_MODE, tp->mi_mode);
978 udelay(80);
979
980 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
982 tg3_mdio_config_5785(tp);
983 }
984
985 static void tg3_mdio_stop(struct tg3 *tp)
986 {
987 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
988 mutex_lock(&tp->mdio_bus->mdio_lock);
989 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
990 mutex_unlock(&tp->mdio_bus->mdio_lock);
991 }
992 }
993
994 static int tg3_mdio_init(struct tg3 *tp)
995 {
996 int i;
997 u32 reg;
998 struct phy_device *phydev;
999
1000 tg3_mdio_start(tp);
1001
1002 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004 return 0;
1005
1006 tp->mdio_bus = mdiobus_alloc();
1007 if (tp->mdio_bus == NULL)
1008 return -ENOMEM;
1009
1010 tp->mdio_bus->name = "tg3 mdio bus";
1011 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1012 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1013 tp->mdio_bus->priv = tp;
1014 tp->mdio_bus->parent = &tp->pdev->dev;
1015 tp->mdio_bus->read = &tg3_mdio_read;
1016 tp->mdio_bus->write = &tg3_mdio_write;
1017 tp->mdio_bus->reset = &tg3_mdio_reset;
1018 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019 tp->mdio_bus->irq = &tp->mdio_irq[0];
1020
1021 for (i = 0; i < PHY_MAX_ADDR; i++)
1022 tp->mdio_bus->irq[i] = PHY_POLL;
1023
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1028 */
1029 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030 tg3_bmcr_reset(tp);
1031
1032 i = mdiobus_register(tp->mdio_bus);
1033 if (i) {
1034 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035 tp->dev->name, i);
1036 mdiobus_free(tp->mdio_bus);
1037 return i;
1038 }
1039
1040 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1041
1042 if (!phydev || !phydev->drv) {
1043 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044 mdiobus_unregister(tp->mdio_bus);
1045 mdiobus_free(tp->mdio_bus);
1046 return -ENODEV;
1047 }
1048
1049 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1050 case TG3_PHY_ID_BCM57780:
1051 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052 break;
1053 case TG3_PHY_ID_BCM50610:
1054 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1060 /* fallthru */
1061 case TG3_PHY_ID_RTL8211C:
1062 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1063 break;
1064 case TG3_PHY_ID_RTL8201E:
1065 case TG3_PHY_ID_BCMAC131:
1066 phydev->interface = PHY_INTERFACE_MODE_MII;
1067 break;
1068 }
1069
1070 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073 tg3_mdio_config_5785(tp);
1074
1075 return 0;
1076 }
1077
1078 static void tg3_mdio_fini(struct tg3 *tp)
1079 {
1080 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1082 mdiobus_unregister(tp->mdio_bus);
1083 mdiobus_free(tp->mdio_bus);
1084 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085 }
1086 }
1087
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3 *tp)
1090 {
1091 u32 val;
1092
1093 val = tr32(GRC_RX_CPU_EVENT);
1094 val |= GRC_RX_CPU_DRIVER_EVENT;
1095 tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097 tp->last_event_jiffies = jiffies;
1098 }
1099
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3 *tp)
1104 {
1105 int i;
1106 unsigned int delay_cnt;
1107 long time_remain;
1108
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain = (long)(tp->last_event_jiffies + 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112 (long)jiffies;
1113 if (time_remain < 0)
1114 return;
1115
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt = jiffies_to_usecs(time_remain);
1118 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120 delay_cnt = (delay_cnt >> 3) + 1;
1121
1122 for (i = 0; i < delay_cnt; i++) {
1123 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124 break;
1125 udelay(8);
1126 }
1127 }
1128
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3 *tp)
1131 {
1132 u32 reg;
1133 u32 val;
1134
1135 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1137 return;
1138
1139 tg3_wait_for_event_ack(tp);
1140
1141 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145 val = 0;
1146 if (!tg3_readphy(tp, MII_BMCR, &reg))
1147 val = reg << 16;
1148 if (!tg3_readphy(tp, MII_BMSR, &reg))
1149 val |= (reg & 0xffff);
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152 val = 0;
1153 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154 val = reg << 16;
1155 if (!tg3_readphy(tp, MII_LPA, &reg))
1156 val |= (reg & 0xffff);
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159 val = 0;
1160 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162 val = reg << 16;
1163 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164 val |= (reg & 0xffff);
1165 }
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169 val = reg << 16;
1170 else
1171 val = 0;
1172 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
1174 tg3_generate_fw_event(tp);
1175 }
1176
1177 static void tg3_link_report(struct tg3 *tp)
1178 {
1179 if (!netif_carrier_ok(tp->dev)) {
1180 if (netif_msg_link(tp))
1181 printk(KERN_INFO PFX "%s: Link is down.\n",
1182 tp->dev->name);
1183 tg3_ump_link_report(tp);
1184 } else if (netif_msg_link(tp)) {
1185 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186 tp->dev->name,
1187 (tp->link_config.active_speed == SPEED_1000 ?
1188 1000 :
1189 (tp->link_config.active_speed == SPEED_100 ?
1190 100 : 10)),
1191 (tp->link_config.active_duplex == DUPLEX_FULL ?
1192 "full" : "half"));
1193
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1196 tp->dev->name,
1197 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1198 "on" : "off",
1199 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1200 "on" : "off");
1201 tg3_ump_link_report(tp);
1202 }
1203 }
1204
1205 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206 {
1207 u16 miireg;
1208
1209 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1210 miireg = ADVERTISE_PAUSE_CAP;
1211 else if (flow_ctrl & FLOW_CTRL_TX)
1212 miireg = ADVERTISE_PAUSE_ASYM;
1213 else if (flow_ctrl & FLOW_CTRL_RX)
1214 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215 else
1216 miireg = 0;
1217
1218 return miireg;
1219 }
1220
1221 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222 {
1223 u16 miireg;
1224
1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1226 miireg = ADVERTISE_1000XPAUSE;
1227 else if (flow_ctrl & FLOW_CTRL_TX)
1228 miireg = ADVERTISE_1000XPSE_ASYM;
1229 else if (flow_ctrl & FLOW_CTRL_RX)
1230 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235 }
1236
1237 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238 {
1239 u8 cap = 0;
1240
1241 if (lcladv & ADVERTISE_1000XPAUSE) {
1242 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243 if (rmtadv & LPA_1000XPAUSE)
1244 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1245 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1246 cap = FLOW_CTRL_RX;
1247 } else {
1248 if (rmtadv & LPA_1000XPAUSE)
1249 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1250 }
1251 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1253 cap = FLOW_CTRL_TX;
1254 }
1255
1256 return cap;
1257 }
1258
1259 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1260 {
1261 u8 autoneg;
1262 u8 flowctrl = 0;
1263 u32 old_rx_mode = tp->rx_mode;
1264 u32 old_tx_mode = tp->tx_mode;
1265
1266 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1267 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1268 else
1269 autoneg = tp->link_config.autoneg;
1270
1271 if (autoneg == AUTONEG_ENABLE &&
1272 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1274 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1275 else
1276 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1277 } else
1278 flowctrl = tp->link_config.flowctrl;
1279
1280 tp->link_config.active_flowctrl = flowctrl;
1281
1282 if (flowctrl & FLOW_CTRL_RX)
1283 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284 else
1285 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
1287 if (old_rx_mode != tp->rx_mode)
1288 tw32_f(MAC_RX_MODE, tp->rx_mode);
1289
1290 if (flowctrl & FLOW_CTRL_TX)
1291 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292 else
1293 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
1295 if (old_tx_mode != tp->tx_mode)
1296 tw32_f(MAC_TX_MODE, tp->tx_mode);
1297 }
1298
1299 static void tg3_adjust_link(struct net_device *dev)
1300 {
1301 u8 oldflowctrl, linkmesg = 0;
1302 u32 mac_mode, lcl_adv, rmt_adv;
1303 struct tg3 *tp = netdev_priv(dev);
1304 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1305
1306 spin_lock(&tp->lock);
1307
1308 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309 MAC_MODE_HALF_DUPLEX);
1310
1311 oldflowctrl = tp->link_config.active_flowctrl;
1312
1313 if (phydev->link) {
1314 lcl_adv = 0;
1315 rmt_adv = 0;
1316
1317 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318 mac_mode |= MAC_MODE_PORT_MODE_MII;
1319 else
1320 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322 if (phydev->duplex == DUPLEX_HALF)
1323 mac_mode |= MAC_MODE_HALF_DUPLEX;
1324 else {
1325 lcl_adv = tg3_advert_flowctrl_1000T(
1326 tp->link_config.flowctrl);
1327
1328 if (phydev->pause)
1329 rmt_adv = LPA_PAUSE_CAP;
1330 if (phydev->asym_pause)
1331 rmt_adv |= LPA_PAUSE_ASYM;
1332 }
1333
1334 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335 } else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (mac_mode != tp->mac_mode) {
1339 tp->mac_mode = mac_mode;
1340 tw32_f(MAC_MODE, tp->mac_mode);
1341 udelay(40);
1342 }
1343
1344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345 if (phydev->speed == SPEED_10)
1346 tw32(MAC_MI_STAT,
1347 MAC_MI_STAT_10MBPS_MODE |
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349 else
1350 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351 }
1352
1353 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354 tw32(MAC_TX_LENGTHS,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356 (6 << TX_LENGTHS_IPG_SHIFT) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358 else
1359 tw32(MAC_TX_LENGTHS,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361 (6 << TX_LENGTHS_IPG_SHIFT) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366 phydev->speed != tp->link_config.active_speed ||
1367 phydev->duplex != tp->link_config.active_duplex ||
1368 oldflowctrl != tp->link_config.active_flowctrl)
1369 linkmesg = 1;
1370
1371 tp->link_config.active_speed = phydev->speed;
1372 tp->link_config.active_duplex = phydev->duplex;
1373
1374 spin_unlock(&tp->lock);
1375
1376 if (linkmesg)
1377 tg3_link_report(tp);
1378 }
1379
1380 static int tg3_phy_init(struct tg3 *tp)
1381 {
1382 struct phy_device *phydev;
1383
1384 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385 return 0;
1386
1387 /* Bring the PHY back to a known state. */
1388 tg3_bmcr_reset(tp);
1389
1390 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1391
1392 /* Attach the MAC to the PHY. */
1393 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1394 phydev->dev_flags, phydev->interface);
1395 if (IS_ERR(phydev)) {
1396 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397 return PTR_ERR(phydev);
1398 }
1399
1400 /* Mask with MAC supported features. */
1401 switch (phydev->interface) {
1402 case PHY_INTERFACE_MODE_GMII:
1403 case PHY_INTERFACE_MODE_RGMII:
1404 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405 phydev->supported &= (PHY_GBIT_FEATURES |
1406 SUPPORTED_Pause |
1407 SUPPORTED_Asym_Pause);
1408 break;
1409 }
1410 /* fallthru */
1411 case PHY_INTERFACE_MODE_MII:
1412 phydev->supported &= (PHY_BASIC_FEATURES |
1413 SUPPORTED_Pause |
1414 SUPPORTED_Asym_Pause);
1415 break;
1416 default:
1417 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418 return -EINVAL;
1419 }
1420
1421 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1422
1423 phydev->advertising = phydev->supported;
1424
1425 return 0;
1426 }
1427
1428 static void tg3_phy_start(struct tg3 *tp)
1429 {
1430 struct phy_device *phydev;
1431
1432 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433 return;
1434
1435 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1436
1437 if (tp->link_config.phy_is_low_power) {
1438 tp->link_config.phy_is_low_power = 0;
1439 phydev->speed = tp->link_config.orig_speed;
1440 phydev->duplex = tp->link_config.orig_duplex;
1441 phydev->autoneg = tp->link_config.orig_autoneg;
1442 phydev->advertising = tp->link_config.orig_advertising;
1443 }
1444
1445 phy_start(phydev);
1446
1447 phy_start_aneg(phydev);
1448 }
1449
1450 static void tg3_phy_stop(struct tg3 *tp)
1451 {
1452 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453 return;
1454
1455 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1456 }
1457
1458 static void tg3_phy_fini(struct tg3 *tp)
1459 {
1460 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1461 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1462 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463 }
1464 }
1465
1466 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467 {
1468 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470 }
1471
1472 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473 {
1474 u32 reg;
1475
1476 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
1478 return;
1479
1480 reg = MII_TG3_MISC_SHDW_WREN |
1481 MII_TG3_MISC_SHDW_SCR5_SEL |
1482 MII_TG3_MISC_SHDW_SCR5_LPED |
1483 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1484 MII_TG3_MISC_SHDW_SCR5_SDTL |
1485 MII_TG3_MISC_SHDW_SCR5_C125OE;
1486 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1487 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1488
1489 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1490
1491
1492 reg = MII_TG3_MISC_SHDW_WREN |
1493 MII_TG3_MISC_SHDW_APD_SEL |
1494 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1495 if (enable)
1496 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1497
1498 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1499 }
1500
1501 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1502 {
1503 u32 phy;
1504
1505 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1506 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1507 return;
1508
1509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1510 u32 ephy;
1511
1512 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1513 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1514 ephy | MII_TG3_EPHY_SHADOW_EN);
1515 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1516 if (enable)
1517 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1518 else
1519 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1520 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1521 }
1522 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1523 }
1524 } else {
1525 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1526 MII_TG3_AUXCTL_SHDWSEL_MISC;
1527 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1528 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1531 else
1532 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1533 phy |= MII_TG3_AUXCTL_MISC_WREN;
1534 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1535 }
1536 }
1537 }
1538
1539 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1540 {
1541 u32 val;
1542
1543 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1544 return;
1545
1546 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1547 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1548 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1549 (val | (1 << 15) | (1 << 4)));
1550 }
1551
1552 static void tg3_phy_apply_otp(struct tg3 *tp)
1553 {
1554 u32 otp, phy;
1555
1556 if (!tp->phy_otp)
1557 return;
1558
1559 otp = tp->phy_otp;
1560
1561 /* Enable SM_DSP clock and tx 6dB coding. */
1562 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1563 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1564 MII_TG3_AUXCTL_ACTL_TX_6DB;
1565 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1566
1567 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1568 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1569 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1570
1571 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1572 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1573 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1574
1575 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1576 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1577 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1578
1579 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1580 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1581
1582 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1583 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1584
1585 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1586 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1587 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1588
1589 /* Turn off SM_DSP clock. */
1590 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1591 MII_TG3_AUXCTL_ACTL_TX_6DB;
1592 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1593 }
1594
1595 static int tg3_wait_macro_done(struct tg3 *tp)
1596 {
1597 int limit = 100;
1598
1599 while (limit--) {
1600 u32 tmp32;
1601
1602 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1603 if ((tmp32 & 0x1000) == 0)
1604 break;
1605 }
1606 }
1607 if (limit < 0)
1608 return -EBUSY;
1609
1610 return 0;
1611 }
1612
1613 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1614 {
1615 static const u32 test_pat[4][6] = {
1616 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1617 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1618 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1619 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1620 };
1621 int chan;
1622
1623 for (chan = 0; chan < 4; chan++) {
1624 int i;
1625
1626 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1627 (chan * 0x2000) | 0x0200);
1628 tg3_writephy(tp, 0x16, 0x0002);
1629
1630 for (i = 0; i < 6; i++)
1631 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1632 test_pat[chan][i]);
1633
1634 tg3_writephy(tp, 0x16, 0x0202);
1635 if (tg3_wait_macro_done(tp)) {
1636 *resetp = 1;
1637 return -EBUSY;
1638 }
1639
1640 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1641 (chan * 0x2000) | 0x0200);
1642 tg3_writephy(tp, 0x16, 0x0082);
1643 if (tg3_wait_macro_done(tp)) {
1644 *resetp = 1;
1645 return -EBUSY;
1646 }
1647
1648 tg3_writephy(tp, 0x16, 0x0802);
1649 if (tg3_wait_macro_done(tp)) {
1650 *resetp = 1;
1651 return -EBUSY;
1652 }
1653
1654 for (i = 0; i < 6; i += 2) {
1655 u32 low, high;
1656
1657 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1658 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1659 tg3_wait_macro_done(tp)) {
1660 *resetp = 1;
1661 return -EBUSY;
1662 }
1663 low &= 0x7fff;
1664 high &= 0x000f;
1665 if (low != test_pat[chan][i] ||
1666 high != test_pat[chan][i+1]) {
1667 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1668 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1669 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1670
1671 return -EBUSY;
1672 }
1673 }
1674 }
1675
1676 return 0;
1677 }
1678
1679 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1680 {
1681 int chan;
1682
1683 for (chan = 0; chan < 4; chan++) {
1684 int i;
1685
1686 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1687 (chan * 0x2000) | 0x0200);
1688 tg3_writephy(tp, 0x16, 0x0002);
1689 for (i = 0; i < 6; i++)
1690 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1691 tg3_writephy(tp, 0x16, 0x0202);
1692 if (tg3_wait_macro_done(tp))
1693 return -EBUSY;
1694 }
1695
1696 return 0;
1697 }
1698
1699 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1700 {
1701 u32 reg32, phy9_orig;
1702 int retries, do_phy_reset, err;
1703
1704 retries = 10;
1705 do_phy_reset = 1;
1706 do {
1707 if (do_phy_reset) {
1708 err = tg3_bmcr_reset(tp);
1709 if (err)
1710 return err;
1711 do_phy_reset = 0;
1712 }
1713
1714 /* Disable transmitter and interrupt. */
1715 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1716 continue;
1717
1718 reg32 |= 0x3000;
1719 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1720
1721 /* Set full-duplex, 1000 mbps. */
1722 tg3_writephy(tp, MII_BMCR,
1723 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1724
1725 /* Set to master mode. */
1726 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1727 continue;
1728
1729 tg3_writephy(tp, MII_TG3_CTRL,
1730 (MII_TG3_CTRL_AS_MASTER |
1731 MII_TG3_CTRL_ENABLE_AS_MASTER));
1732
1733 /* Enable SM_DSP_CLOCK and 6dB. */
1734 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1735
1736 /* Block the PHY control access. */
1737 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1738 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1739
1740 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1741 if (!err)
1742 break;
1743 } while (--retries);
1744
1745 err = tg3_phy_reset_chanpat(tp);
1746 if (err)
1747 return err;
1748
1749 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1750 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1751
1752 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1753 tg3_writephy(tp, 0x16, 0x0000);
1754
1755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1756 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1757 /* Set Extended packet length bit for jumbo frames */
1758 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1759 }
1760 else {
1761 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1762 }
1763
1764 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1765
1766 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1767 reg32 &= ~0x3000;
1768 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1769 } else if (!err)
1770 err = -EBUSY;
1771
1772 return err;
1773 }
1774
1775 /* This will reset the tigon3 PHY if there is no valid
1776 * link unless the FORCE argument is non-zero.
1777 */
1778 static int tg3_phy_reset(struct tg3 *tp)
1779 {
1780 u32 cpmuctrl;
1781 u32 phy_status;
1782 int err;
1783
1784 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1785 u32 val;
1786
1787 val = tr32(GRC_MISC_CFG);
1788 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1789 udelay(40);
1790 }
1791 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1792 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1793 if (err != 0)
1794 return -EBUSY;
1795
1796 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1797 netif_carrier_off(tp->dev);
1798 tg3_link_report(tp);
1799 }
1800
1801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1803 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1804 err = tg3_phy_reset_5703_4_5(tp);
1805 if (err)
1806 return err;
1807 goto out;
1808 }
1809
1810 cpmuctrl = 0;
1811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1812 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1813 cpmuctrl = tr32(TG3_CPMU_CTRL);
1814 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1815 tw32(TG3_CPMU_CTRL,
1816 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1817 }
1818
1819 err = tg3_bmcr_reset(tp);
1820 if (err)
1821 return err;
1822
1823 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1824 u32 phy;
1825
1826 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1827 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1828
1829 tw32(TG3_CPMU_CTRL, cpmuctrl);
1830 }
1831
1832 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1833 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1834 u32 val;
1835
1836 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1837 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1838 CPMU_LSPD_1000MB_MACCLK_12_5) {
1839 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1840 udelay(40);
1841 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1842 }
1843 }
1844
1845 tg3_phy_apply_otp(tp);
1846
1847 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1848 tg3_phy_toggle_apd(tp, true);
1849 else
1850 tg3_phy_toggle_apd(tp, false);
1851
1852 out:
1853 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1855 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1856 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1857 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1858 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1859 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1860 }
1861 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1862 tg3_writephy(tp, 0x1c, 0x8d68);
1863 tg3_writephy(tp, 0x1c, 0x8d68);
1864 }
1865 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1866 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1867 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1868 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1871 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1872 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1873 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1874 }
1875 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1876 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1877 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1878 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1880 tg3_writephy(tp, MII_TG3_TEST1,
1881 MII_TG3_TEST1_TRIM_EN | 0x4);
1882 } else
1883 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1884 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1885 }
1886 /* Set Extended packet length bit (bit 14) on all chips that */
1887 /* support jumbo frames */
1888 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1889 /* Cannot do read-modify-write on 5401 */
1890 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1891 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1892 u32 phy_reg;
1893
1894 /* Set bit 14 with read-modify-write to preserve other bits */
1895 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1896 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1897 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1898 }
1899
1900 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1901 * jumbo frames transmission.
1902 */
1903 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1904 u32 phy_reg;
1905
1906 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1907 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1908 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1909 }
1910
1911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1912 /* adjust output voltage */
1913 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1914 }
1915
1916 tg3_phy_toggle_automdix(tp, 1);
1917 tg3_phy_set_wirespeed(tp);
1918 return 0;
1919 }
1920
1921 static void tg3_frob_aux_power(struct tg3 *tp)
1922 {
1923 struct tg3 *tp_peer = tp;
1924
1925 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1926 return;
1927
1928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1929 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1930 struct net_device *dev_peer;
1931
1932 dev_peer = pci_get_drvdata(tp->pdev_peer);
1933 /* remove_one() may have been run on the peer. */
1934 if (!dev_peer)
1935 tp_peer = tp;
1936 else
1937 tp_peer = netdev_priv(dev_peer);
1938 }
1939
1940 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1941 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1942 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1943 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1946 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1947 (GRC_LCLCTRL_GPIO_OE0 |
1948 GRC_LCLCTRL_GPIO_OE1 |
1949 GRC_LCLCTRL_GPIO_OE2 |
1950 GRC_LCLCTRL_GPIO_OUTPUT0 |
1951 GRC_LCLCTRL_GPIO_OUTPUT1),
1952 100);
1953 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
1954 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
1955 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1956 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1957 GRC_LCLCTRL_GPIO_OE1 |
1958 GRC_LCLCTRL_GPIO_OE2 |
1959 GRC_LCLCTRL_GPIO_OUTPUT0 |
1960 GRC_LCLCTRL_GPIO_OUTPUT1 |
1961 tp->grc_local_ctrl;
1962 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1963
1964 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1965 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1966
1967 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1968 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1969 } else {
1970 u32 no_gpio2;
1971 u32 grc_local_ctrl = 0;
1972
1973 if (tp_peer != tp &&
1974 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1975 return;
1976
1977 /* Workaround to prevent overdrawing Amps. */
1978 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1979 ASIC_REV_5714) {
1980 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1981 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1982 grc_local_ctrl, 100);
1983 }
1984
1985 /* On 5753 and variants, GPIO2 cannot be used. */
1986 no_gpio2 = tp->nic_sram_data_cfg &
1987 NIC_SRAM_DATA_CFG_NO_GPIO2;
1988
1989 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1990 GRC_LCLCTRL_GPIO_OE1 |
1991 GRC_LCLCTRL_GPIO_OE2 |
1992 GRC_LCLCTRL_GPIO_OUTPUT1 |
1993 GRC_LCLCTRL_GPIO_OUTPUT2;
1994 if (no_gpio2) {
1995 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1996 GRC_LCLCTRL_GPIO_OUTPUT2);
1997 }
1998 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1999 grc_local_ctrl, 100);
2000
2001 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2002
2003 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2004 grc_local_ctrl, 100);
2005
2006 if (!no_gpio2) {
2007 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2008 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2009 grc_local_ctrl, 100);
2010 }
2011 }
2012 } else {
2013 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2014 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2015 if (tp_peer != tp &&
2016 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2017 return;
2018
2019 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2020 (GRC_LCLCTRL_GPIO_OE1 |
2021 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2022
2023 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2024 GRC_LCLCTRL_GPIO_OE1, 100);
2025
2026 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2027 (GRC_LCLCTRL_GPIO_OE1 |
2028 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2029 }
2030 }
2031 }
2032
2033 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2034 {
2035 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2036 return 1;
2037 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2038 if (speed != SPEED_10)
2039 return 1;
2040 } else if (speed == SPEED_10)
2041 return 1;
2042
2043 return 0;
2044 }
2045
2046 static int tg3_setup_phy(struct tg3 *, int);
2047
2048 #define RESET_KIND_SHUTDOWN 0
2049 #define RESET_KIND_INIT 1
2050 #define RESET_KIND_SUSPEND 2
2051
2052 static void tg3_write_sig_post_reset(struct tg3 *, int);
2053 static int tg3_halt_cpu(struct tg3 *, u32);
2054
2055 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2056 {
2057 u32 val;
2058
2059 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2061 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2062 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2063
2064 sg_dig_ctrl |=
2065 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2066 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2067 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2068 }
2069 return;
2070 }
2071
2072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2073 tg3_bmcr_reset(tp);
2074 val = tr32(GRC_MISC_CFG);
2075 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2076 udelay(40);
2077 return;
2078 } else if (do_low_power) {
2079 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2080 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2081
2082 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2083 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2084 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2085 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2086 MII_TG3_AUXCTL_PCTL_VREG_11V);
2087 }
2088
2089 /* The PHY should not be powered down on some chips because
2090 * of bugs.
2091 */
2092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2094 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2095 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2096 return;
2097
2098 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2099 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2100 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2101 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2102 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2103 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2104 }
2105
2106 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2107 }
2108
2109 /* tp->lock is held. */
2110 static int tg3_nvram_lock(struct tg3 *tp)
2111 {
2112 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2113 int i;
2114
2115 if (tp->nvram_lock_cnt == 0) {
2116 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2117 for (i = 0; i < 8000; i++) {
2118 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2119 break;
2120 udelay(20);
2121 }
2122 if (i == 8000) {
2123 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2124 return -ENODEV;
2125 }
2126 }
2127 tp->nvram_lock_cnt++;
2128 }
2129 return 0;
2130 }
2131
2132 /* tp->lock is held. */
2133 static void tg3_nvram_unlock(struct tg3 *tp)
2134 {
2135 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2136 if (tp->nvram_lock_cnt > 0)
2137 tp->nvram_lock_cnt--;
2138 if (tp->nvram_lock_cnt == 0)
2139 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2140 }
2141 }
2142
2143 /* tp->lock is held. */
2144 static void tg3_enable_nvram_access(struct tg3 *tp)
2145 {
2146 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2147 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2148 u32 nvaccess = tr32(NVRAM_ACCESS);
2149
2150 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2151 }
2152 }
2153
2154 /* tp->lock is held. */
2155 static void tg3_disable_nvram_access(struct tg3 *tp)
2156 {
2157 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2158 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2159 u32 nvaccess = tr32(NVRAM_ACCESS);
2160
2161 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2162 }
2163 }
2164
2165 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2166 u32 offset, u32 *val)
2167 {
2168 u32 tmp;
2169 int i;
2170
2171 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2172 return -EINVAL;
2173
2174 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2175 EEPROM_ADDR_DEVID_MASK |
2176 EEPROM_ADDR_READ);
2177 tw32(GRC_EEPROM_ADDR,
2178 tmp |
2179 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2180 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2181 EEPROM_ADDR_ADDR_MASK) |
2182 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2183
2184 for (i = 0; i < 1000; i++) {
2185 tmp = tr32(GRC_EEPROM_ADDR);
2186
2187 if (tmp & EEPROM_ADDR_COMPLETE)
2188 break;
2189 msleep(1);
2190 }
2191 if (!(tmp & EEPROM_ADDR_COMPLETE))
2192 return -EBUSY;
2193
2194 tmp = tr32(GRC_EEPROM_DATA);
2195
2196 /*
2197 * The data will always be opposite the native endian
2198 * format. Perform a blind byteswap to compensate.
2199 */
2200 *val = swab32(tmp);
2201
2202 return 0;
2203 }
2204
2205 #define NVRAM_CMD_TIMEOUT 10000
2206
2207 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2208 {
2209 int i;
2210
2211 tw32(NVRAM_CMD, nvram_cmd);
2212 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2213 udelay(10);
2214 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2215 udelay(10);
2216 break;
2217 }
2218 }
2219
2220 if (i == NVRAM_CMD_TIMEOUT)
2221 return -EBUSY;
2222
2223 return 0;
2224 }
2225
2226 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2227 {
2228 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2229 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2230 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2231 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2232 (tp->nvram_jedecnum == JEDEC_ATMEL))
2233
2234 addr = ((addr / tp->nvram_pagesize) <<
2235 ATMEL_AT45DB0X1B_PAGE_POS) +
2236 (addr % tp->nvram_pagesize);
2237
2238 return addr;
2239 }
2240
2241 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2242 {
2243 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2244 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2245 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2246 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2247 (tp->nvram_jedecnum == JEDEC_ATMEL))
2248
2249 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2250 tp->nvram_pagesize) +
2251 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2252
2253 return addr;
2254 }
2255
2256 /* NOTE: Data read in from NVRAM is byteswapped according to
2257 * the byteswapping settings for all other register accesses.
2258 * tg3 devices are BE devices, so on a BE machine, the data
2259 * returned will be exactly as it is seen in NVRAM. On a LE
2260 * machine, the 32-bit value will be byteswapped.
2261 */
2262 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2263 {
2264 int ret;
2265
2266 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2267 return tg3_nvram_read_using_eeprom(tp, offset, val);
2268
2269 offset = tg3_nvram_phys_addr(tp, offset);
2270
2271 if (offset > NVRAM_ADDR_MSK)
2272 return -EINVAL;
2273
2274 ret = tg3_nvram_lock(tp);
2275 if (ret)
2276 return ret;
2277
2278 tg3_enable_nvram_access(tp);
2279
2280 tw32(NVRAM_ADDR, offset);
2281 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2282 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2283
2284 if (ret == 0)
2285 *val = tr32(NVRAM_RDDATA);
2286
2287 tg3_disable_nvram_access(tp);
2288
2289 tg3_nvram_unlock(tp);
2290
2291 return ret;
2292 }
2293
2294 /* Ensures NVRAM data is in bytestream format. */
2295 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2296 {
2297 u32 v;
2298 int res = tg3_nvram_read(tp, offset, &v);
2299 if (!res)
2300 *val = cpu_to_be32(v);
2301 return res;
2302 }
2303
2304 /* tp->lock is held. */
2305 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2306 {
2307 u32 addr_high, addr_low;
2308 int i;
2309
2310 addr_high = ((tp->dev->dev_addr[0] << 8) |
2311 tp->dev->dev_addr[1]);
2312 addr_low = ((tp->dev->dev_addr[2] << 24) |
2313 (tp->dev->dev_addr[3] << 16) |
2314 (tp->dev->dev_addr[4] << 8) |
2315 (tp->dev->dev_addr[5] << 0));
2316 for (i = 0; i < 4; i++) {
2317 if (i == 1 && skip_mac_1)
2318 continue;
2319 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2320 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2321 }
2322
2323 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2324 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2325 for (i = 0; i < 12; i++) {
2326 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2327 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2328 }
2329 }
2330
2331 addr_high = (tp->dev->dev_addr[0] +
2332 tp->dev->dev_addr[1] +
2333 tp->dev->dev_addr[2] +
2334 tp->dev->dev_addr[3] +
2335 tp->dev->dev_addr[4] +
2336 tp->dev->dev_addr[5]) &
2337 TX_BACKOFF_SEED_MASK;
2338 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2339 }
2340
2341 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2342 {
2343 u32 misc_host_ctrl;
2344 bool device_should_wake, do_low_power;
2345
2346 /* Make sure register accesses (indirect or otherwise)
2347 * will function correctly.
2348 */
2349 pci_write_config_dword(tp->pdev,
2350 TG3PCI_MISC_HOST_CTRL,
2351 tp->misc_host_ctrl);
2352
2353 switch (state) {
2354 case PCI_D0:
2355 pci_enable_wake(tp->pdev, state, false);
2356 pci_set_power_state(tp->pdev, PCI_D0);
2357
2358 /* Switch out of Vaux if it is a NIC */
2359 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2360 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2361
2362 return 0;
2363
2364 case PCI_D1:
2365 case PCI_D2:
2366 case PCI_D3hot:
2367 break;
2368
2369 default:
2370 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2371 tp->dev->name, state);
2372 return -EINVAL;
2373 }
2374
2375 /* Restore the CLKREQ setting. */
2376 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2377 u16 lnkctl;
2378
2379 pci_read_config_word(tp->pdev,
2380 tp->pcie_cap + PCI_EXP_LNKCTL,
2381 &lnkctl);
2382 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2383 pci_write_config_word(tp->pdev,
2384 tp->pcie_cap + PCI_EXP_LNKCTL,
2385 lnkctl);
2386 }
2387
2388 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2389 tw32(TG3PCI_MISC_HOST_CTRL,
2390 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2391
2392 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2393 device_may_wakeup(&tp->pdev->dev) &&
2394 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2395
2396 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2397 do_low_power = false;
2398 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2399 !tp->link_config.phy_is_low_power) {
2400 struct phy_device *phydev;
2401 u32 phyid, advertising;
2402
2403 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2404
2405 tp->link_config.phy_is_low_power = 1;
2406
2407 tp->link_config.orig_speed = phydev->speed;
2408 tp->link_config.orig_duplex = phydev->duplex;
2409 tp->link_config.orig_autoneg = phydev->autoneg;
2410 tp->link_config.orig_advertising = phydev->advertising;
2411
2412 advertising = ADVERTISED_TP |
2413 ADVERTISED_Pause |
2414 ADVERTISED_Autoneg |
2415 ADVERTISED_10baseT_Half;
2416
2417 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2418 device_should_wake) {
2419 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2420 advertising |=
2421 ADVERTISED_100baseT_Half |
2422 ADVERTISED_100baseT_Full |
2423 ADVERTISED_10baseT_Full;
2424 else
2425 advertising |= ADVERTISED_10baseT_Full;
2426 }
2427
2428 phydev->advertising = advertising;
2429
2430 phy_start_aneg(phydev);
2431
2432 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2433 if (phyid != TG3_PHY_ID_BCMAC131) {
2434 phyid &= TG3_PHY_OUI_MASK;
2435 if (phyid == TG3_PHY_OUI_1 ||
2436 phyid == TG3_PHY_OUI_2 ||
2437 phyid == TG3_PHY_OUI_3)
2438 do_low_power = true;
2439 }
2440 }
2441 } else {
2442 do_low_power = true;
2443
2444 if (tp->link_config.phy_is_low_power == 0) {
2445 tp->link_config.phy_is_low_power = 1;
2446 tp->link_config.orig_speed = tp->link_config.speed;
2447 tp->link_config.orig_duplex = tp->link_config.duplex;
2448 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2449 }
2450
2451 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2452 tp->link_config.speed = SPEED_10;
2453 tp->link_config.duplex = DUPLEX_HALF;
2454 tp->link_config.autoneg = AUTONEG_ENABLE;
2455 tg3_setup_phy(tp, 0);
2456 }
2457 }
2458
2459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2460 u32 val;
2461
2462 val = tr32(GRC_VCPU_EXT_CTRL);
2463 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2464 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2465 int i;
2466 u32 val;
2467
2468 for (i = 0; i < 200; i++) {
2469 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2470 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2471 break;
2472 msleep(1);
2473 }
2474 }
2475 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2476 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2477 WOL_DRV_STATE_SHUTDOWN |
2478 WOL_DRV_WOL |
2479 WOL_SET_MAGIC_PKT);
2480
2481 if (device_should_wake) {
2482 u32 mac_mode;
2483
2484 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2485 if (do_low_power) {
2486 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2487 udelay(40);
2488 }
2489
2490 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2491 mac_mode = MAC_MODE_PORT_MODE_GMII;
2492 else
2493 mac_mode = MAC_MODE_PORT_MODE_MII;
2494
2495 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2496 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2497 ASIC_REV_5700) {
2498 u32 speed = (tp->tg3_flags &
2499 TG3_FLAG_WOL_SPEED_100MB) ?
2500 SPEED_100 : SPEED_10;
2501 if (tg3_5700_link_polarity(tp, speed))
2502 mac_mode |= MAC_MODE_LINK_POLARITY;
2503 else
2504 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2505 }
2506 } else {
2507 mac_mode = MAC_MODE_PORT_MODE_TBI;
2508 }
2509
2510 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2511 tw32(MAC_LED_CTRL, tp->led_ctrl);
2512
2513 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2514 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2515 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2516 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2517 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2518 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2519
2520 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2521 mac_mode |= tp->mac_mode &
2522 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2523 if (mac_mode & MAC_MODE_APE_TX_EN)
2524 mac_mode |= MAC_MODE_TDE_ENABLE;
2525 }
2526
2527 tw32_f(MAC_MODE, mac_mode);
2528 udelay(100);
2529
2530 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2531 udelay(10);
2532 }
2533
2534 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2535 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2536 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2537 u32 base_val;
2538
2539 base_val = tp->pci_clock_ctrl;
2540 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2541 CLOCK_CTRL_TXCLK_DISABLE);
2542
2543 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2544 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2545 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2546 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2547 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2548 /* do nothing */
2549 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2550 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2551 u32 newbits1, newbits2;
2552
2553 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2554 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2555 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2556 CLOCK_CTRL_TXCLK_DISABLE |
2557 CLOCK_CTRL_ALTCLK);
2558 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2559 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2560 newbits1 = CLOCK_CTRL_625_CORE;
2561 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2562 } else {
2563 newbits1 = CLOCK_CTRL_ALTCLK;
2564 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2565 }
2566
2567 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2568 40);
2569
2570 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2571 40);
2572
2573 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2574 u32 newbits3;
2575
2576 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2577 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2578 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2579 CLOCK_CTRL_TXCLK_DISABLE |
2580 CLOCK_CTRL_44MHZ_CORE);
2581 } else {
2582 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2583 }
2584
2585 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2586 tp->pci_clock_ctrl | newbits3, 40);
2587 }
2588 }
2589
2590 if (!(device_should_wake) &&
2591 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2592 tg3_power_down_phy(tp, do_low_power);
2593
2594 tg3_frob_aux_power(tp);
2595
2596 /* Workaround for unstable PLL clock */
2597 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2598 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2599 u32 val = tr32(0x7d00);
2600
2601 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2602 tw32(0x7d00, val);
2603 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2604 int err;
2605
2606 err = tg3_nvram_lock(tp);
2607 tg3_halt_cpu(tp, RX_CPU_BASE);
2608 if (!err)
2609 tg3_nvram_unlock(tp);
2610 }
2611 }
2612
2613 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2614
2615 if (device_should_wake)
2616 pci_enable_wake(tp->pdev, state, true);
2617
2618 /* Finally, set the new power state. */
2619 pci_set_power_state(tp->pdev, state);
2620
2621 return 0;
2622 }
2623
2624 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2625 {
2626 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2627 case MII_TG3_AUX_STAT_10HALF:
2628 *speed = SPEED_10;
2629 *duplex = DUPLEX_HALF;
2630 break;
2631
2632 case MII_TG3_AUX_STAT_10FULL:
2633 *speed = SPEED_10;
2634 *duplex = DUPLEX_FULL;
2635 break;
2636
2637 case MII_TG3_AUX_STAT_100HALF:
2638 *speed = SPEED_100;
2639 *duplex = DUPLEX_HALF;
2640 break;
2641
2642 case MII_TG3_AUX_STAT_100FULL:
2643 *speed = SPEED_100;
2644 *duplex = DUPLEX_FULL;
2645 break;
2646
2647 case MII_TG3_AUX_STAT_1000HALF:
2648 *speed = SPEED_1000;
2649 *duplex = DUPLEX_HALF;
2650 break;
2651
2652 case MII_TG3_AUX_STAT_1000FULL:
2653 *speed = SPEED_1000;
2654 *duplex = DUPLEX_FULL;
2655 break;
2656
2657 default:
2658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2659 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2660 SPEED_10;
2661 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2662 DUPLEX_HALF;
2663 break;
2664 }
2665 *speed = SPEED_INVALID;
2666 *duplex = DUPLEX_INVALID;
2667 break;
2668 }
2669 }
2670
2671 static void tg3_phy_copper_begin(struct tg3 *tp)
2672 {
2673 u32 new_adv;
2674 int i;
2675
2676 if (tp->link_config.phy_is_low_power) {
2677 /* Entering low power mode. Disable gigabit and
2678 * 100baseT advertisements.
2679 */
2680 tg3_writephy(tp, MII_TG3_CTRL, 0);
2681
2682 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2683 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2684 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2685 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2686
2687 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2688 } else if (tp->link_config.speed == SPEED_INVALID) {
2689 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2690 tp->link_config.advertising &=
2691 ~(ADVERTISED_1000baseT_Half |
2692 ADVERTISED_1000baseT_Full);
2693
2694 new_adv = ADVERTISE_CSMA;
2695 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2696 new_adv |= ADVERTISE_10HALF;
2697 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2698 new_adv |= ADVERTISE_10FULL;
2699 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2700 new_adv |= ADVERTISE_100HALF;
2701 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2702 new_adv |= ADVERTISE_100FULL;
2703
2704 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2705
2706 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2707
2708 if (tp->link_config.advertising &
2709 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2710 new_adv = 0;
2711 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2712 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2713 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2714 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2715 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2716 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2717 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2718 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2719 MII_TG3_CTRL_ENABLE_AS_MASTER);
2720 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2721 } else {
2722 tg3_writephy(tp, MII_TG3_CTRL, 0);
2723 }
2724 } else {
2725 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2726 new_adv |= ADVERTISE_CSMA;
2727
2728 /* Asking for a specific link mode. */
2729 if (tp->link_config.speed == SPEED_1000) {
2730 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2731
2732 if (tp->link_config.duplex == DUPLEX_FULL)
2733 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2734 else
2735 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2736 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2737 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2738 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2739 MII_TG3_CTRL_ENABLE_AS_MASTER);
2740 } else {
2741 if (tp->link_config.speed == SPEED_100) {
2742 if (tp->link_config.duplex == DUPLEX_FULL)
2743 new_adv |= ADVERTISE_100FULL;
2744 else
2745 new_adv |= ADVERTISE_100HALF;
2746 } else {
2747 if (tp->link_config.duplex == DUPLEX_FULL)
2748 new_adv |= ADVERTISE_10FULL;
2749 else
2750 new_adv |= ADVERTISE_10HALF;
2751 }
2752 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2753
2754 new_adv = 0;
2755 }
2756
2757 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2758 }
2759
2760 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2761 tp->link_config.speed != SPEED_INVALID) {
2762 u32 bmcr, orig_bmcr;
2763
2764 tp->link_config.active_speed = tp->link_config.speed;
2765 tp->link_config.active_duplex = tp->link_config.duplex;
2766
2767 bmcr = 0;
2768 switch (tp->link_config.speed) {
2769 default:
2770 case SPEED_10:
2771 break;
2772
2773 case SPEED_100:
2774 bmcr |= BMCR_SPEED100;
2775 break;
2776
2777 case SPEED_1000:
2778 bmcr |= TG3_BMCR_SPEED1000;
2779 break;
2780 }
2781
2782 if (tp->link_config.duplex == DUPLEX_FULL)
2783 bmcr |= BMCR_FULLDPLX;
2784
2785 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2786 (bmcr != orig_bmcr)) {
2787 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2788 for (i = 0; i < 1500; i++) {
2789 u32 tmp;
2790
2791 udelay(10);
2792 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2793 tg3_readphy(tp, MII_BMSR, &tmp))
2794 continue;
2795 if (!(tmp & BMSR_LSTATUS)) {
2796 udelay(40);
2797 break;
2798 }
2799 }
2800 tg3_writephy(tp, MII_BMCR, bmcr);
2801 udelay(40);
2802 }
2803 } else {
2804 tg3_writephy(tp, MII_BMCR,
2805 BMCR_ANENABLE | BMCR_ANRESTART);
2806 }
2807 }
2808
2809 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2810 {
2811 int err;
2812
2813 /* Turn off tap power management. */
2814 /* Set Extended packet length bit */
2815 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2816
2817 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2818 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2819
2820 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2821 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2822
2823 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2824 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2825
2826 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2827 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2828
2829 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2830 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2831
2832 udelay(40);
2833
2834 return err;
2835 }
2836
2837 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2838 {
2839 u32 adv_reg, all_mask = 0;
2840
2841 if (mask & ADVERTISED_10baseT_Half)
2842 all_mask |= ADVERTISE_10HALF;
2843 if (mask & ADVERTISED_10baseT_Full)
2844 all_mask |= ADVERTISE_10FULL;
2845 if (mask & ADVERTISED_100baseT_Half)
2846 all_mask |= ADVERTISE_100HALF;
2847 if (mask & ADVERTISED_100baseT_Full)
2848 all_mask |= ADVERTISE_100FULL;
2849
2850 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2851 return 0;
2852
2853 if ((adv_reg & all_mask) != all_mask)
2854 return 0;
2855 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2856 u32 tg3_ctrl;
2857
2858 all_mask = 0;
2859 if (mask & ADVERTISED_1000baseT_Half)
2860 all_mask |= ADVERTISE_1000HALF;
2861 if (mask & ADVERTISED_1000baseT_Full)
2862 all_mask |= ADVERTISE_1000FULL;
2863
2864 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2865 return 0;
2866
2867 if ((tg3_ctrl & all_mask) != all_mask)
2868 return 0;
2869 }
2870 return 1;
2871 }
2872
2873 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2874 {
2875 u32 curadv, reqadv;
2876
2877 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2878 return 1;
2879
2880 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2881 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2882
2883 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2884 if (curadv != reqadv)
2885 return 0;
2886
2887 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2888 tg3_readphy(tp, MII_LPA, rmtadv);
2889 } else {
2890 /* Reprogram the advertisement register, even if it
2891 * does not affect the current link. If the link
2892 * gets renegotiated in the future, we can save an
2893 * additional renegotiation cycle by advertising
2894 * it correctly in the first place.
2895 */
2896 if (curadv != reqadv) {
2897 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2898 ADVERTISE_PAUSE_ASYM);
2899 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2900 }
2901 }
2902
2903 return 1;
2904 }
2905
2906 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2907 {
2908 int current_link_up;
2909 u32 bmsr, dummy;
2910 u32 lcl_adv, rmt_adv;
2911 u16 current_speed;
2912 u8 current_duplex;
2913 int i, err;
2914
2915 tw32(MAC_EVENT, 0);
2916
2917 tw32_f(MAC_STATUS,
2918 (MAC_STATUS_SYNC_CHANGED |
2919 MAC_STATUS_CFG_CHANGED |
2920 MAC_STATUS_MI_COMPLETION |
2921 MAC_STATUS_LNKSTATE_CHANGED));
2922 udelay(40);
2923
2924 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2925 tw32_f(MAC_MI_MODE,
2926 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2927 udelay(80);
2928 }
2929
2930 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2931
2932 /* Some third-party PHYs need to be reset on link going
2933 * down.
2934 */
2935 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2937 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2938 netif_carrier_ok(tp->dev)) {
2939 tg3_readphy(tp, MII_BMSR, &bmsr);
2940 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2941 !(bmsr & BMSR_LSTATUS))
2942 force_reset = 1;
2943 }
2944 if (force_reset)
2945 tg3_phy_reset(tp);
2946
2947 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2948 tg3_readphy(tp, MII_BMSR, &bmsr);
2949 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2950 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2951 bmsr = 0;
2952
2953 if (!(bmsr & BMSR_LSTATUS)) {
2954 err = tg3_init_5401phy_dsp(tp);
2955 if (err)
2956 return err;
2957
2958 tg3_readphy(tp, MII_BMSR, &bmsr);
2959 for (i = 0; i < 1000; i++) {
2960 udelay(10);
2961 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2962 (bmsr & BMSR_LSTATUS)) {
2963 udelay(40);
2964 break;
2965 }
2966 }
2967
2968 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2969 !(bmsr & BMSR_LSTATUS) &&
2970 tp->link_config.active_speed == SPEED_1000) {
2971 err = tg3_phy_reset(tp);
2972 if (!err)
2973 err = tg3_init_5401phy_dsp(tp);
2974 if (err)
2975 return err;
2976 }
2977 }
2978 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2979 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2980 /* 5701 {A0,B0} CRC bug workaround */
2981 tg3_writephy(tp, 0x15, 0x0a75);
2982 tg3_writephy(tp, 0x1c, 0x8c68);
2983 tg3_writephy(tp, 0x1c, 0x8d68);
2984 tg3_writephy(tp, 0x1c, 0x8c68);
2985 }
2986
2987 /* Clear pending interrupts... */
2988 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2989 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2990
2991 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2992 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2993 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2994 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2995
2996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2998 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2999 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3000 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3001 else
3002 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3003 }
3004
3005 current_link_up = 0;
3006 current_speed = SPEED_INVALID;
3007 current_duplex = DUPLEX_INVALID;
3008
3009 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3010 u32 val;
3011
3012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3013 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3014 if (!(val & (1 << 10))) {
3015 val |= (1 << 10);
3016 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3017 goto relink;
3018 }
3019 }
3020
3021 bmsr = 0;
3022 for (i = 0; i < 100; i++) {
3023 tg3_readphy(tp, MII_BMSR, &bmsr);
3024 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3025 (bmsr & BMSR_LSTATUS))
3026 break;
3027 udelay(40);
3028 }
3029
3030 if (bmsr & BMSR_LSTATUS) {
3031 u32 aux_stat, bmcr;
3032
3033 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3034 for (i = 0; i < 2000; i++) {
3035 udelay(10);
3036 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3037 aux_stat)
3038 break;
3039 }
3040
3041 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3042 &current_speed,
3043 &current_duplex);
3044
3045 bmcr = 0;
3046 for (i = 0; i < 200; i++) {
3047 tg3_readphy(tp, MII_BMCR, &bmcr);
3048 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3049 continue;
3050 if (bmcr && bmcr != 0x7fff)
3051 break;
3052 udelay(10);
3053 }
3054
3055 lcl_adv = 0;
3056 rmt_adv = 0;
3057
3058 tp->link_config.active_speed = current_speed;
3059 tp->link_config.active_duplex = current_duplex;
3060
3061 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3062 if ((bmcr & BMCR_ANENABLE) &&
3063 tg3_copper_is_advertising_all(tp,
3064 tp->link_config.advertising)) {
3065 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3066 &rmt_adv))
3067 current_link_up = 1;
3068 }
3069 } else {
3070 if (!(bmcr & BMCR_ANENABLE) &&
3071 tp->link_config.speed == current_speed &&
3072 tp->link_config.duplex == current_duplex &&
3073 tp->link_config.flowctrl ==
3074 tp->link_config.active_flowctrl) {
3075 current_link_up = 1;
3076 }
3077 }
3078
3079 if (current_link_up == 1 &&
3080 tp->link_config.active_duplex == DUPLEX_FULL)
3081 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3082 }
3083
3084 relink:
3085 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3086 u32 tmp;
3087
3088 tg3_phy_copper_begin(tp);
3089
3090 tg3_readphy(tp, MII_BMSR, &tmp);
3091 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3092 (tmp & BMSR_LSTATUS))
3093 current_link_up = 1;
3094 }
3095
3096 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3097 if (current_link_up == 1) {
3098 if (tp->link_config.active_speed == SPEED_100 ||
3099 tp->link_config.active_speed == SPEED_10)
3100 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3101 else
3102 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3103 } else
3104 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3105
3106 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3107 if (tp->link_config.active_duplex == DUPLEX_HALF)
3108 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3109
3110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3111 if (current_link_up == 1 &&
3112 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3113 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3114 else
3115 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3116 }
3117
3118 /* ??? Without this setting Netgear GA302T PHY does not
3119 * ??? send/receive packets...
3120 */
3121 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3122 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3123 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3124 tw32_f(MAC_MI_MODE, tp->mi_mode);
3125 udelay(80);
3126 }
3127
3128 tw32_f(MAC_MODE, tp->mac_mode);
3129 udelay(40);
3130
3131 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3132 /* Polled via timer. */
3133 tw32_f(MAC_EVENT, 0);
3134 } else {
3135 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3136 }
3137 udelay(40);
3138
3139 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3140 current_link_up == 1 &&
3141 tp->link_config.active_speed == SPEED_1000 &&
3142 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3143 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3144 udelay(120);
3145 tw32_f(MAC_STATUS,
3146 (MAC_STATUS_SYNC_CHANGED |
3147 MAC_STATUS_CFG_CHANGED));
3148 udelay(40);
3149 tg3_write_mem(tp,
3150 NIC_SRAM_FIRMWARE_MBOX,
3151 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3152 }
3153
3154 /* Prevent send BD corruption. */
3155 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3156 u16 oldlnkctl, newlnkctl;
3157
3158 pci_read_config_word(tp->pdev,
3159 tp->pcie_cap + PCI_EXP_LNKCTL,
3160 &oldlnkctl);
3161 if (tp->link_config.active_speed == SPEED_100 ||
3162 tp->link_config.active_speed == SPEED_10)
3163 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3164 else
3165 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3166 if (newlnkctl != oldlnkctl)
3167 pci_write_config_word(tp->pdev,
3168 tp->pcie_cap + PCI_EXP_LNKCTL,
3169 newlnkctl);
3170 }
3171
3172 if (current_link_up != netif_carrier_ok(tp->dev)) {
3173 if (current_link_up)
3174 netif_carrier_on(tp->dev);
3175 else
3176 netif_carrier_off(tp->dev);
3177 tg3_link_report(tp);
3178 }
3179
3180 return 0;
3181 }
3182
3183 struct tg3_fiber_aneginfo {
3184 int state;
3185 #define ANEG_STATE_UNKNOWN 0
3186 #define ANEG_STATE_AN_ENABLE 1
3187 #define ANEG_STATE_RESTART_INIT 2
3188 #define ANEG_STATE_RESTART 3
3189 #define ANEG_STATE_DISABLE_LINK_OK 4
3190 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3191 #define ANEG_STATE_ABILITY_DETECT 6
3192 #define ANEG_STATE_ACK_DETECT_INIT 7
3193 #define ANEG_STATE_ACK_DETECT 8
3194 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3195 #define ANEG_STATE_COMPLETE_ACK 10
3196 #define ANEG_STATE_IDLE_DETECT_INIT 11
3197 #define ANEG_STATE_IDLE_DETECT 12
3198 #define ANEG_STATE_LINK_OK 13
3199 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3200 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3201
3202 u32 flags;
3203 #define MR_AN_ENABLE 0x00000001
3204 #define MR_RESTART_AN 0x00000002
3205 #define MR_AN_COMPLETE 0x00000004
3206 #define MR_PAGE_RX 0x00000008
3207 #define MR_NP_LOADED 0x00000010
3208 #define MR_TOGGLE_TX 0x00000020
3209 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3210 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3211 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3212 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3213 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3214 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3215 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3216 #define MR_TOGGLE_RX 0x00002000
3217 #define MR_NP_RX 0x00004000
3218
3219 #define MR_LINK_OK 0x80000000
3220
3221 unsigned long link_time, cur_time;
3222
3223 u32 ability_match_cfg;
3224 int ability_match_count;
3225
3226 char ability_match, idle_match, ack_match;
3227
3228 u32 txconfig, rxconfig;
3229 #define ANEG_CFG_NP 0x00000080
3230 #define ANEG_CFG_ACK 0x00000040
3231 #define ANEG_CFG_RF2 0x00000020
3232 #define ANEG_CFG_RF1 0x00000010
3233 #define ANEG_CFG_PS2 0x00000001
3234 #define ANEG_CFG_PS1 0x00008000
3235 #define ANEG_CFG_HD 0x00004000
3236 #define ANEG_CFG_FD 0x00002000
3237 #define ANEG_CFG_INVAL 0x00001f06
3238
3239 };
3240 #define ANEG_OK 0
3241 #define ANEG_DONE 1
3242 #define ANEG_TIMER_ENAB 2
3243 #define ANEG_FAILED -1
3244
3245 #define ANEG_STATE_SETTLE_TIME 10000
3246
3247 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3248 struct tg3_fiber_aneginfo *ap)
3249 {
3250 u16 flowctrl;
3251 unsigned long delta;
3252 u32 rx_cfg_reg;
3253 int ret;
3254
3255 if (ap->state == ANEG_STATE_UNKNOWN) {
3256 ap->rxconfig = 0;
3257 ap->link_time = 0;
3258 ap->cur_time = 0;
3259 ap->ability_match_cfg = 0;
3260 ap->ability_match_count = 0;
3261 ap->ability_match = 0;
3262 ap->idle_match = 0;
3263 ap->ack_match = 0;
3264 }
3265 ap->cur_time++;
3266
3267 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3268 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3269
3270 if (rx_cfg_reg != ap->ability_match_cfg) {
3271 ap->ability_match_cfg = rx_cfg_reg;
3272 ap->ability_match = 0;
3273 ap->ability_match_count = 0;
3274 } else {
3275 if (++ap->ability_match_count > 1) {
3276 ap->ability_match = 1;
3277 ap->ability_match_cfg = rx_cfg_reg;
3278 }
3279 }
3280 if (rx_cfg_reg & ANEG_CFG_ACK)
3281 ap->ack_match = 1;
3282 else
3283 ap->ack_match = 0;
3284
3285 ap->idle_match = 0;
3286 } else {
3287 ap->idle_match = 1;
3288 ap->ability_match_cfg = 0;
3289 ap->ability_match_count = 0;
3290 ap->ability_match = 0;
3291 ap->ack_match = 0;
3292
3293 rx_cfg_reg = 0;
3294 }
3295
3296 ap->rxconfig = rx_cfg_reg;
3297 ret = ANEG_OK;
3298
3299 switch(ap->state) {
3300 case ANEG_STATE_UNKNOWN:
3301 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3302 ap->state = ANEG_STATE_AN_ENABLE;
3303
3304 /* fallthru */
3305 case ANEG_STATE_AN_ENABLE:
3306 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3307 if (ap->flags & MR_AN_ENABLE) {
3308 ap->link_time = 0;
3309 ap->cur_time = 0;
3310 ap->ability_match_cfg = 0;
3311 ap->ability_match_count = 0;
3312 ap->ability_match = 0;
3313 ap->idle_match = 0;
3314 ap->ack_match = 0;
3315
3316 ap->state = ANEG_STATE_RESTART_INIT;
3317 } else {
3318 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3319 }
3320 break;
3321
3322 case ANEG_STATE_RESTART_INIT:
3323 ap->link_time = ap->cur_time;
3324 ap->flags &= ~(MR_NP_LOADED);
3325 ap->txconfig = 0;
3326 tw32(MAC_TX_AUTO_NEG, 0);
3327 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3328 tw32_f(MAC_MODE, tp->mac_mode);
3329 udelay(40);
3330
3331 ret = ANEG_TIMER_ENAB;
3332 ap->state = ANEG_STATE_RESTART;
3333
3334 /* fallthru */
3335 case ANEG_STATE_RESTART:
3336 delta = ap->cur_time - ap->link_time;
3337 if (delta > ANEG_STATE_SETTLE_TIME) {
3338 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3339 } else {
3340 ret = ANEG_TIMER_ENAB;
3341 }
3342 break;
3343
3344 case ANEG_STATE_DISABLE_LINK_OK:
3345 ret = ANEG_DONE;
3346 break;
3347
3348 case ANEG_STATE_ABILITY_DETECT_INIT:
3349 ap->flags &= ~(MR_TOGGLE_TX);
3350 ap->txconfig = ANEG_CFG_FD;
3351 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3352 if (flowctrl & ADVERTISE_1000XPAUSE)
3353 ap->txconfig |= ANEG_CFG_PS1;
3354 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3355 ap->txconfig |= ANEG_CFG_PS2;
3356 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3357 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3358 tw32_f(MAC_MODE, tp->mac_mode);
3359 udelay(40);
3360
3361 ap->state = ANEG_STATE_ABILITY_DETECT;
3362 break;
3363
3364 case ANEG_STATE_ABILITY_DETECT:
3365 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3366 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3367 }
3368 break;
3369
3370 case ANEG_STATE_ACK_DETECT_INIT:
3371 ap->txconfig |= ANEG_CFG_ACK;
3372 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3373 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3374 tw32_f(MAC_MODE, tp->mac_mode);
3375 udelay(40);
3376
3377 ap->state = ANEG_STATE_ACK_DETECT;
3378
3379 /* fallthru */
3380 case ANEG_STATE_ACK_DETECT:
3381 if (ap->ack_match != 0) {
3382 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3383 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3384 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3385 } else {
3386 ap->state = ANEG_STATE_AN_ENABLE;
3387 }
3388 } else if (ap->ability_match != 0 &&
3389 ap->rxconfig == 0) {
3390 ap->state = ANEG_STATE_AN_ENABLE;
3391 }
3392 break;
3393
3394 case ANEG_STATE_COMPLETE_ACK_INIT:
3395 if (ap->rxconfig & ANEG_CFG_INVAL) {
3396 ret = ANEG_FAILED;
3397 break;
3398 }
3399 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3400 MR_LP_ADV_HALF_DUPLEX |
3401 MR_LP_ADV_SYM_PAUSE |
3402 MR_LP_ADV_ASYM_PAUSE |
3403 MR_LP_ADV_REMOTE_FAULT1 |
3404 MR_LP_ADV_REMOTE_FAULT2 |
3405 MR_LP_ADV_NEXT_PAGE |
3406 MR_TOGGLE_RX |
3407 MR_NP_RX);
3408 if (ap->rxconfig & ANEG_CFG_FD)
3409 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3410 if (ap->rxconfig & ANEG_CFG_HD)
3411 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3412 if (ap->rxconfig & ANEG_CFG_PS1)
3413 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3414 if (ap->rxconfig & ANEG_CFG_PS2)
3415 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3416 if (ap->rxconfig & ANEG_CFG_RF1)
3417 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3418 if (ap->rxconfig & ANEG_CFG_RF2)
3419 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3420 if (ap->rxconfig & ANEG_CFG_NP)
3421 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3422
3423 ap->link_time = ap->cur_time;
3424
3425 ap->flags ^= (MR_TOGGLE_TX);
3426 if (ap->rxconfig & 0x0008)
3427 ap->flags |= MR_TOGGLE_RX;
3428 if (ap->rxconfig & ANEG_CFG_NP)
3429 ap->flags |= MR_NP_RX;
3430 ap->flags |= MR_PAGE_RX;
3431
3432 ap->state = ANEG_STATE_COMPLETE_ACK;
3433 ret = ANEG_TIMER_ENAB;
3434 break;
3435
3436 case ANEG_STATE_COMPLETE_ACK:
3437 if (ap->ability_match != 0 &&
3438 ap->rxconfig == 0) {
3439 ap->state = ANEG_STATE_AN_ENABLE;
3440 break;
3441 }
3442 delta = ap->cur_time - ap->link_time;
3443 if (delta > ANEG_STATE_SETTLE_TIME) {
3444 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3445 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3446 } else {
3447 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3448 !(ap->flags & MR_NP_RX)) {
3449 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3450 } else {
3451 ret = ANEG_FAILED;
3452 }
3453 }
3454 }
3455 break;
3456
3457 case ANEG_STATE_IDLE_DETECT_INIT:
3458 ap->link_time = ap->cur_time;
3459 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3460 tw32_f(MAC_MODE, tp->mac_mode);
3461 udelay(40);
3462
3463 ap->state = ANEG_STATE_IDLE_DETECT;
3464 ret = ANEG_TIMER_ENAB;
3465 break;
3466
3467 case ANEG_STATE_IDLE_DETECT:
3468 if (ap->ability_match != 0 &&
3469 ap->rxconfig == 0) {
3470 ap->state = ANEG_STATE_AN_ENABLE;
3471 break;
3472 }
3473 delta = ap->cur_time - ap->link_time;
3474 if (delta > ANEG_STATE_SETTLE_TIME) {
3475 /* XXX another gem from the Broadcom driver :( */
3476 ap->state = ANEG_STATE_LINK_OK;
3477 }
3478 break;
3479
3480 case ANEG_STATE_LINK_OK:
3481 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3482 ret = ANEG_DONE;
3483 break;
3484
3485 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3486 /* ??? unimplemented */
3487 break;
3488
3489 case ANEG_STATE_NEXT_PAGE_WAIT:
3490 /* ??? unimplemented */
3491 break;
3492
3493 default:
3494 ret = ANEG_FAILED;
3495 break;
3496 }
3497
3498 return ret;
3499 }
3500
3501 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3502 {
3503 int res = 0;
3504 struct tg3_fiber_aneginfo aninfo;
3505 int status = ANEG_FAILED;
3506 unsigned int tick;
3507 u32 tmp;
3508
3509 tw32_f(MAC_TX_AUTO_NEG, 0);
3510
3511 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3512 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3513 udelay(40);
3514
3515 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3516 udelay(40);
3517
3518 memset(&aninfo, 0, sizeof(aninfo));
3519 aninfo.flags |= MR_AN_ENABLE;
3520 aninfo.state = ANEG_STATE_UNKNOWN;
3521 aninfo.cur_time = 0;
3522 tick = 0;
3523 while (++tick < 195000) {
3524 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3525 if (status == ANEG_DONE || status == ANEG_FAILED)
3526 break;
3527
3528 udelay(1);
3529 }
3530
3531 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3532 tw32_f(MAC_MODE, tp->mac_mode);
3533 udelay(40);
3534
3535 *txflags = aninfo.txconfig;
3536 *rxflags = aninfo.flags;
3537
3538 if (status == ANEG_DONE &&
3539 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3540 MR_LP_ADV_FULL_DUPLEX)))
3541 res = 1;
3542
3543 return res;
3544 }
3545
3546 static void tg3_init_bcm8002(struct tg3 *tp)
3547 {
3548 u32 mac_status = tr32(MAC_STATUS);
3549 int i;
3550
3551 /* Reset when initting first time or we have a link. */
3552 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3553 !(mac_status & MAC_STATUS_PCS_SYNCED))
3554 return;
3555
3556 /* Set PLL lock range. */
3557 tg3_writephy(tp, 0x16, 0x8007);
3558
3559 /* SW reset */
3560 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3561
3562 /* Wait for reset to complete. */
3563 /* XXX schedule_timeout() ... */
3564 for (i = 0; i < 500; i++)
3565 udelay(10);
3566
3567 /* Config mode; select PMA/Ch 1 regs. */
3568 tg3_writephy(tp, 0x10, 0x8411);
3569
3570 /* Enable auto-lock and comdet, select txclk for tx. */
3571 tg3_writephy(tp, 0x11, 0x0a10);
3572
3573 tg3_writephy(tp, 0x18, 0x00a0);
3574 tg3_writephy(tp, 0x16, 0x41ff);
3575
3576 /* Assert and deassert POR. */
3577 tg3_writephy(tp, 0x13, 0x0400);
3578 udelay(40);
3579 tg3_writephy(tp, 0x13, 0x0000);
3580
3581 tg3_writephy(tp, 0x11, 0x0a50);
3582 udelay(40);
3583 tg3_writephy(tp, 0x11, 0x0a10);
3584
3585 /* Wait for signal to stabilize */
3586 /* XXX schedule_timeout() ... */
3587 for (i = 0; i < 15000; i++)
3588 udelay(10);
3589
3590 /* Deselect the channel register so we can read the PHYID
3591 * later.
3592 */
3593 tg3_writephy(tp, 0x10, 0x8011);
3594 }
3595
3596 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3597 {
3598 u16 flowctrl;
3599 u32 sg_dig_ctrl, sg_dig_status;
3600 u32 serdes_cfg, expected_sg_dig_ctrl;
3601 int workaround, port_a;
3602 int current_link_up;
3603
3604 serdes_cfg = 0;
3605 expected_sg_dig_ctrl = 0;
3606 workaround = 0;
3607 port_a = 1;
3608 current_link_up = 0;
3609
3610 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3611 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3612 workaround = 1;
3613 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3614 port_a = 0;
3615
3616 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3617 /* preserve bits 20-23 for voltage regulator */
3618 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3619 }
3620
3621 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3622
3623 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3624 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3625 if (workaround) {
3626 u32 val = serdes_cfg;
3627
3628 if (port_a)
3629 val |= 0xc010000;
3630 else
3631 val |= 0x4010000;
3632 tw32_f(MAC_SERDES_CFG, val);
3633 }
3634
3635 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3636 }
3637 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3638 tg3_setup_flow_control(tp, 0, 0);
3639 current_link_up = 1;
3640 }
3641 goto out;
3642 }
3643
3644 /* Want auto-negotiation. */
3645 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3646
3647 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3648 if (flowctrl & ADVERTISE_1000XPAUSE)
3649 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3650 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3651 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3652
3653 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3654 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3655 tp->serdes_counter &&
3656 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3657 MAC_STATUS_RCVD_CFG)) ==
3658 MAC_STATUS_PCS_SYNCED)) {
3659 tp->serdes_counter--;
3660 current_link_up = 1;
3661 goto out;
3662 }
3663 restart_autoneg:
3664 if (workaround)
3665 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3666 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3667 udelay(5);
3668 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3669
3670 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3671 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3672 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3673 MAC_STATUS_SIGNAL_DET)) {
3674 sg_dig_status = tr32(SG_DIG_STATUS);
3675 mac_status = tr32(MAC_STATUS);
3676
3677 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3678 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3679 u32 local_adv = 0, remote_adv = 0;
3680
3681 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3682 local_adv |= ADVERTISE_1000XPAUSE;
3683 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3684 local_adv |= ADVERTISE_1000XPSE_ASYM;
3685
3686 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3687 remote_adv |= LPA_1000XPAUSE;
3688 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3689 remote_adv |= LPA_1000XPAUSE_ASYM;
3690
3691 tg3_setup_flow_control(tp, local_adv, remote_adv);
3692 current_link_up = 1;
3693 tp->serdes_counter = 0;
3694 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3695 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3696 if (tp->serdes_counter)
3697 tp->serdes_counter--;
3698 else {
3699 if (workaround) {
3700 u32 val = serdes_cfg;
3701
3702 if (port_a)
3703 val |= 0xc010000;
3704 else
3705 val |= 0x4010000;
3706
3707 tw32_f(MAC_SERDES_CFG, val);
3708 }
3709
3710 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3711 udelay(40);
3712
3713 /* Link parallel detection - link is up */
3714 /* only if we have PCS_SYNC and not */
3715 /* receiving config code words */
3716 mac_status = tr32(MAC_STATUS);
3717 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3718 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3719 tg3_setup_flow_control(tp, 0, 0);
3720 current_link_up = 1;
3721 tp->tg3_flags2 |=
3722 TG3_FLG2_PARALLEL_DETECT;
3723 tp->serdes_counter =
3724 SERDES_PARALLEL_DET_TIMEOUT;
3725 } else
3726 goto restart_autoneg;
3727 }
3728 }
3729 } else {
3730 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3731 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3732 }
3733
3734 out:
3735 return current_link_up;
3736 }
3737
3738 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3739 {
3740 int current_link_up = 0;
3741
3742 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3743 goto out;
3744
3745 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3746 u32 txflags, rxflags;
3747 int i;
3748
3749 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3750 u32 local_adv = 0, remote_adv = 0;
3751
3752 if (txflags & ANEG_CFG_PS1)
3753 local_adv |= ADVERTISE_1000XPAUSE;
3754 if (txflags & ANEG_CFG_PS2)
3755 local_adv |= ADVERTISE_1000XPSE_ASYM;
3756
3757 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3758 remote_adv |= LPA_1000XPAUSE;
3759 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3760 remote_adv |= LPA_1000XPAUSE_ASYM;
3761
3762 tg3_setup_flow_control(tp, local_adv, remote_adv);
3763
3764 current_link_up = 1;
3765 }
3766 for (i = 0; i < 30; i++) {
3767 udelay(20);
3768 tw32_f(MAC_STATUS,
3769 (MAC_STATUS_SYNC_CHANGED |
3770 MAC_STATUS_CFG_CHANGED));
3771 udelay(40);
3772 if ((tr32(MAC_STATUS) &
3773 (MAC_STATUS_SYNC_CHANGED |
3774 MAC_STATUS_CFG_CHANGED)) == 0)
3775 break;
3776 }
3777
3778 mac_status = tr32(MAC_STATUS);
3779 if (current_link_up == 0 &&
3780 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3781 !(mac_status & MAC_STATUS_RCVD_CFG))
3782 current_link_up = 1;
3783 } else {
3784 tg3_setup_flow_control(tp, 0, 0);
3785
3786 /* Forcing 1000FD link up. */
3787 current_link_up = 1;
3788
3789 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3790 udelay(40);
3791
3792 tw32_f(MAC_MODE, tp->mac_mode);
3793 udelay(40);
3794 }
3795
3796 out:
3797 return current_link_up;
3798 }
3799
3800 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3801 {
3802 u32 orig_pause_cfg;
3803 u16 orig_active_speed;
3804 u8 orig_active_duplex;
3805 u32 mac_status;
3806 int current_link_up;
3807 int i;
3808
3809 orig_pause_cfg = tp->link_config.active_flowctrl;
3810 orig_active_speed = tp->link_config.active_speed;
3811 orig_active_duplex = tp->link_config.active_duplex;
3812
3813 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3814 netif_carrier_ok(tp->dev) &&
3815 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3816 mac_status = tr32(MAC_STATUS);
3817 mac_status &= (MAC_STATUS_PCS_SYNCED |
3818 MAC_STATUS_SIGNAL_DET |
3819 MAC_STATUS_CFG_CHANGED |
3820 MAC_STATUS_RCVD_CFG);
3821 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3822 MAC_STATUS_SIGNAL_DET)) {
3823 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3824 MAC_STATUS_CFG_CHANGED));
3825 return 0;
3826 }
3827 }
3828
3829 tw32_f(MAC_TX_AUTO_NEG, 0);
3830
3831 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3832 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3833 tw32_f(MAC_MODE, tp->mac_mode);
3834 udelay(40);
3835
3836 if (tp->phy_id == PHY_ID_BCM8002)
3837 tg3_init_bcm8002(tp);
3838
3839 /* Enable link change event even when serdes polling. */
3840 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3841 udelay(40);
3842
3843 current_link_up = 0;
3844 mac_status = tr32(MAC_STATUS);
3845
3846 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3847 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3848 else
3849 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3850
3851 tp->hw_status->status =
3852 (SD_STATUS_UPDATED |
3853 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3854
3855 for (i = 0; i < 100; i++) {
3856 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3857 MAC_STATUS_CFG_CHANGED));
3858 udelay(5);
3859 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3860 MAC_STATUS_CFG_CHANGED |
3861 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3862 break;
3863 }
3864
3865 mac_status = tr32(MAC_STATUS);
3866 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3867 current_link_up = 0;
3868 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3869 tp->serdes_counter == 0) {
3870 tw32_f(MAC_MODE, (tp->mac_mode |
3871 MAC_MODE_SEND_CONFIGS));
3872 udelay(1);
3873 tw32_f(MAC_MODE, tp->mac_mode);
3874 }
3875 }
3876
3877 if (current_link_up == 1) {
3878 tp->link_config.active_speed = SPEED_1000;
3879 tp->link_config.active_duplex = DUPLEX_FULL;
3880 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3881 LED_CTRL_LNKLED_OVERRIDE |
3882 LED_CTRL_1000MBPS_ON));
3883 } else {
3884 tp->link_config.active_speed = SPEED_INVALID;
3885 tp->link_config.active_duplex = DUPLEX_INVALID;
3886 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3887 LED_CTRL_LNKLED_OVERRIDE |
3888 LED_CTRL_TRAFFIC_OVERRIDE));
3889 }
3890
3891 if (current_link_up != netif_carrier_ok(tp->dev)) {
3892 if (current_link_up)
3893 netif_carrier_on(tp->dev);
3894 else
3895 netif_carrier_off(tp->dev);
3896 tg3_link_report(tp);
3897 } else {
3898 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3899 if (orig_pause_cfg != now_pause_cfg ||
3900 orig_active_speed != tp->link_config.active_speed ||
3901 orig_active_duplex != tp->link_config.active_duplex)
3902 tg3_link_report(tp);
3903 }
3904
3905 return 0;
3906 }
3907
3908 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3909 {
3910 int current_link_up, err = 0;
3911 u32 bmsr, bmcr;
3912 u16 current_speed;
3913 u8 current_duplex;
3914 u32 local_adv, remote_adv;
3915
3916 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3917 tw32_f(MAC_MODE, tp->mac_mode);
3918 udelay(40);
3919
3920 tw32(MAC_EVENT, 0);
3921
3922 tw32_f(MAC_STATUS,
3923 (MAC_STATUS_SYNC_CHANGED |
3924 MAC_STATUS_CFG_CHANGED |
3925 MAC_STATUS_MI_COMPLETION |
3926 MAC_STATUS_LNKSTATE_CHANGED));
3927 udelay(40);
3928
3929 if (force_reset)
3930 tg3_phy_reset(tp);
3931
3932 current_link_up = 0;
3933 current_speed = SPEED_INVALID;
3934 current_duplex = DUPLEX_INVALID;
3935
3936 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3937 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3938 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3939 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3940 bmsr |= BMSR_LSTATUS;
3941 else
3942 bmsr &= ~BMSR_LSTATUS;
3943 }
3944
3945 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3946
3947 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3948 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3949 /* do nothing, just check for link up at the end */
3950 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3951 u32 adv, new_adv;
3952
3953 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3954 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3955 ADVERTISE_1000XPAUSE |
3956 ADVERTISE_1000XPSE_ASYM |
3957 ADVERTISE_SLCT);
3958
3959 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3960
3961 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3962 new_adv |= ADVERTISE_1000XHALF;
3963 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3964 new_adv |= ADVERTISE_1000XFULL;
3965
3966 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3967 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3968 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3969 tg3_writephy(tp, MII_BMCR, bmcr);
3970
3971 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3972 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3973 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3974
3975 return err;
3976 }
3977 } else {
3978 u32 new_bmcr;
3979
3980 bmcr &= ~BMCR_SPEED1000;
3981 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3982
3983 if (tp->link_config.duplex == DUPLEX_FULL)
3984 new_bmcr |= BMCR_FULLDPLX;
3985
3986 if (new_bmcr != bmcr) {
3987 /* BMCR_SPEED1000 is a reserved bit that needs
3988 * to be set on write.
3989 */
3990 new_bmcr |= BMCR_SPEED1000;
3991
3992 /* Force a linkdown */
3993 if (netif_carrier_ok(tp->dev)) {
3994 u32 adv;
3995
3996 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3997 adv &= ~(ADVERTISE_1000XFULL |
3998 ADVERTISE_1000XHALF |
3999 ADVERTISE_SLCT);
4000 tg3_writephy(tp, MII_ADVERTISE, adv);
4001 tg3_writephy(tp, MII_BMCR, bmcr |
4002 BMCR_ANRESTART |
4003 BMCR_ANENABLE);
4004 udelay(10);
4005 netif_carrier_off(tp->dev);
4006 }
4007 tg3_writephy(tp, MII_BMCR, new_bmcr);
4008 bmcr = new_bmcr;
4009 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4010 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4011 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4012 ASIC_REV_5714) {
4013 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4014 bmsr |= BMSR_LSTATUS;
4015 else
4016 bmsr &= ~BMSR_LSTATUS;
4017 }
4018 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4019 }
4020 }
4021
4022 if (bmsr & BMSR_LSTATUS) {
4023 current_speed = SPEED_1000;
4024 current_link_up = 1;
4025 if (bmcr & BMCR_FULLDPLX)
4026 current_duplex = DUPLEX_FULL;
4027 else
4028 current_duplex = DUPLEX_HALF;
4029
4030 local_adv = 0;
4031 remote_adv = 0;
4032
4033 if (bmcr & BMCR_ANENABLE) {
4034 u32 common;
4035
4036 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4037 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4038 common = local_adv & remote_adv;
4039 if (common & (ADVERTISE_1000XHALF |
4040 ADVERTISE_1000XFULL)) {
4041 if (common & ADVERTISE_1000XFULL)
4042 current_duplex = DUPLEX_FULL;
4043 else
4044 current_duplex = DUPLEX_HALF;
4045 }
4046 else
4047 current_link_up = 0;
4048 }
4049 }
4050
4051 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4052 tg3_setup_flow_control(tp, local_adv, remote_adv);
4053
4054 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4055 if (tp->link_config.active_duplex == DUPLEX_HALF)
4056 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4057
4058 tw32_f(MAC_MODE, tp->mac_mode);
4059 udelay(40);
4060
4061 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4062
4063 tp->link_config.active_speed = current_speed;
4064 tp->link_config.active_duplex = current_duplex;
4065
4066 if (current_link_up != netif_carrier_ok(tp->dev)) {
4067 if (current_link_up)
4068 netif_carrier_on(tp->dev);
4069 else {
4070 netif_carrier_off(tp->dev);
4071 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4072 }
4073 tg3_link_report(tp);
4074 }
4075 return err;
4076 }
4077
4078 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4079 {
4080 if (tp->serdes_counter) {
4081 /* Give autoneg time to complete. */
4082 tp->serdes_counter--;
4083 return;
4084 }
4085 if (!netif_carrier_ok(tp->dev) &&
4086 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4087 u32 bmcr;
4088
4089 tg3_readphy(tp, MII_BMCR, &bmcr);
4090 if (bmcr & BMCR_ANENABLE) {
4091 u32 phy1, phy2;
4092
4093 /* Select shadow register 0x1f */
4094 tg3_writephy(tp, 0x1c, 0x7c00);
4095 tg3_readphy(tp, 0x1c, &phy1);
4096
4097 /* Select expansion interrupt status register */
4098 tg3_writephy(tp, 0x17, 0x0f01);
4099 tg3_readphy(tp, 0x15, &phy2);
4100 tg3_readphy(tp, 0x15, &phy2);
4101
4102 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4103 /* We have signal detect and not receiving
4104 * config code words, link is up by parallel
4105 * detection.
4106 */
4107
4108 bmcr &= ~BMCR_ANENABLE;
4109 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4110 tg3_writephy(tp, MII_BMCR, bmcr);
4111 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4112 }
4113 }
4114 }
4115 else if (netif_carrier_ok(tp->dev) &&
4116 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4117 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4118 u32 phy2;
4119
4120 /* Select expansion interrupt status register */
4121 tg3_writephy(tp, 0x17, 0x0f01);
4122 tg3_readphy(tp, 0x15, &phy2);
4123 if (phy2 & 0x20) {
4124 u32 bmcr;
4125
4126 /* Config code words received, turn on autoneg. */
4127 tg3_readphy(tp, MII_BMCR, &bmcr);
4128 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4129
4130 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4131
4132 }
4133 }
4134 }
4135
4136 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4137 {
4138 int err;
4139
4140 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4141 err = tg3_setup_fiber_phy(tp, force_reset);
4142 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4143 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4144 } else {
4145 err = tg3_setup_copper_phy(tp, force_reset);
4146 }
4147
4148 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4149 u32 val, scale;
4150
4151 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4152 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4153 scale = 65;
4154 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4155 scale = 6;
4156 else
4157 scale = 12;
4158
4159 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4160 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4161 tw32(GRC_MISC_CFG, val);
4162 }
4163
4164 if (tp->link_config.active_speed == SPEED_1000 &&
4165 tp->link_config.active_duplex == DUPLEX_HALF)
4166 tw32(MAC_TX_LENGTHS,
4167 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4168 (6 << TX_LENGTHS_IPG_SHIFT) |
4169 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4170 else
4171 tw32(MAC_TX_LENGTHS,
4172 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4173 (6 << TX_LENGTHS_IPG_SHIFT) |
4174 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4175
4176 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4177 if (netif_carrier_ok(tp->dev)) {
4178 tw32(HOSTCC_STAT_COAL_TICKS,
4179 tp->coal.stats_block_coalesce_usecs);
4180 } else {
4181 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4182 }
4183 }
4184
4185 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4186 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4187 if (!netif_carrier_ok(tp->dev))
4188 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4189 tp->pwrmgmt_thresh;
4190 else
4191 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4192 tw32(PCIE_PWR_MGMT_THRESH, val);
4193 }
4194
4195 return err;
4196 }
4197
4198 /* This is called whenever we suspect that the system chipset is re-
4199 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4200 * is bogus tx completions. We try to recover by setting the
4201 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4202 * in the workqueue.
4203 */
4204 static void tg3_tx_recover(struct tg3 *tp)
4205 {
4206 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4207 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4208
4209 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4210 "mapped I/O cycles to the network device, attempting to "
4211 "recover. Please report the problem to the driver maintainer "
4212 "and include system chipset information.\n", tp->dev->name);
4213
4214 spin_lock(&tp->lock);
4215 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4216 spin_unlock(&tp->lock);
4217 }
4218
4219 static inline u32 tg3_tx_avail(struct tg3 *tp)
4220 {
4221 smp_mb();
4222 return (tp->tx_pending -
4223 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4224 }
4225
4226 /* Tigon3 never reports partial packet sends. So we do not
4227 * need special logic to handle SKBs that have not had all
4228 * of their frags sent yet, like SunGEM does.
4229 */
4230 static void tg3_tx(struct tg3 *tp)
4231 {
4232 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4233 u32 sw_idx = tp->tx_cons;
4234
4235 while (sw_idx != hw_idx) {
4236 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4237 struct sk_buff *skb = ri->skb;
4238 int i, tx_bug = 0;
4239
4240 if (unlikely(skb == NULL)) {
4241 tg3_tx_recover(tp);
4242 return;
4243 }
4244
4245 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4246
4247 ri->skb = NULL;
4248
4249 sw_idx = NEXT_TX(sw_idx);
4250
4251 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4252 ri = &tp->tx_buffers[sw_idx];
4253 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4254 tx_bug = 1;
4255 sw_idx = NEXT_TX(sw_idx);
4256 }
4257
4258 dev_kfree_skb(skb);
4259
4260 if (unlikely(tx_bug)) {
4261 tg3_tx_recover(tp);
4262 return;
4263 }
4264 }
4265
4266 tp->tx_cons = sw_idx;
4267
4268 /* Need to make the tx_cons update visible to tg3_start_xmit()
4269 * before checking for netif_queue_stopped(). Without the
4270 * memory barrier, there is a small possibility that tg3_start_xmit()
4271 * will miss it and cause the queue to be stopped forever.
4272 */
4273 smp_mb();
4274
4275 if (unlikely(netif_queue_stopped(tp->dev) &&
4276 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4277 netif_tx_lock(tp->dev);
4278 if (netif_queue_stopped(tp->dev) &&
4279 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4280 netif_wake_queue(tp->dev);
4281 netif_tx_unlock(tp->dev);
4282 }
4283 }
4284
4285 /* Returns size of skb allocated or < 0 on error.
4286 *
4287 * We only need to fill in the address because the other members
4288 * of the RX descriptor are invariant, see tg3_init_rings.
4289 *
4290 * Note the purposeful assymetry of cpu vs. chip accesses. For
4291 * posting buffers we only dirty the first cache line of the RX
4292 * descriptor (containing the address). Whereas for the RX status
4293 * buffers the cpu only reads the last cacheline of the RX descriptor
4294 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4295 */
4296 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4297 int src_idx, u32 dest_idx_unmasked)
4298 {
4299 struct tg3_rx_buffer_desc *desc;
4300 struct ring_info *map, *src_map;
4301 struct sk_buff *skb;
4302 dma_addr_t mapping;
4303 int skb_size, dest_idx;
4304
4305 src_map = NULL;
4306 switch (opaque_key) {
4307 case RXD_OPAQUE_RING_STD:
4308 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4309 desc = &tp->rx_std[dest_idx];
4310 map = &tp->rx_std_buffers[dest_idx];
4311 if (src_idx >= 0)
4312 src_map = &tp->rx_std_buffers[src_idx];
4313 skb_size = tp->rx_pkt_buf_sz;
4314 break;
4315
4316 case RXD_OPAQUE_RING_JUMBO:
4317 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4318 desc = &tp->rx_jumbo[dest_idx];
4319 map = &tp->rx_jumbo_buffers[dest_idx];
4320 if (src_idx >= 0)
4321 src_map = &tp->rx_jumbo_buffers[src_idx];
4322 skb_size = RX_JUMBO_PKT_BUF_SZ;
4323 break;
4324
4325 default:
4326 return -EINVAL;
4327 }
4328
4329 /* Do not overwrite any of the map or rp information
4330 * until we are sure we can commit to a new buffer.
4331 *
4332 * Callers depend upon this behavior and assume that
4333 * we leave everything unchanged if we fail.
4334 */
4335 skb = netdev_alloc_skb(tp->dev, skb_size);
4336 if (skb == NULL)
4337 return -ENOMEM;
4338
4339 skb_reserve(skb, tp->rx_offset);
4340
4341 mapping = pci_map_single(tp->pdev, skb->data,
4342 skb_size - tp->rx_offset,
4343 PCI_DMA_FROMDEVICE);
4344
4345 map->skb = skb;
4346 pci_unmap_addr_set(map, mapping, mapping);
4347
4348 if (src_map != NULL)
4349 src_map->skb = NULL;
4350
4351 desc->addr_hi = ((u64)mapping >> 32);
4352 desc->addr_lo = ((u64)mapping & 0xffffffff);
4353
4354 return skb_size;
4355 }
4356
4357 /* We only need to move over in the address because the other
4358 * members of the RX descriptor are invariant. See notes above
4359 * tg3_alloc_rx_skb for full details.
4360 */
4361 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4362 int src_idx, u32 dest_idx_unmasked)
4363 {
4364 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4365 struct ring_info *src_map, *dest_map;
4366 int dest_idx;
4367
4368 switch (opaque_key) {
4369 case RXD_OPAQUE_RING_STD:
4370 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4371 dest_desc = &tp->rx_std[dest_idx];
4372 dest_map = &tp->rx_std_buffers[dest_idx];
4373 src_desc = &tp->rx_std[src_idx];
4374 src_map = &tp->rx_std_buffers[src_idx];
4375 break;
4376
4377 case RXD_OPAQUE_RING_JUMBO:
4378 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4379 dest_desc = &tp->rx_jumbo[dest_idx];
4380 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4381 src_desc = &tp->rx_jumbo[src_idx];
4382 src_map = &tp->rx_jumbo_buffers[src_idx];
4383 break;
4384
4385 default:
4386 return;
4387 }
4388
4389 dest_map->skb = src_map->skb;
4390 pci_unmap_addr_set(dest_map, mapping,
4391 pci_unmap_addr(src_map, mapping));
4392 dest_desc->addr_hi = src_desc->addr_hi;
4393 dest_desc->addr_lo = src_desc->addr_lo;
4394
4395 src_map->skb = NULL;
4396 }
4397
4398 #if TG3_VLAN_TAG_USED
4399 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4400 {
4401 return vlan_gro_receive(&tp->napi, tp->vlgrp, vlan_tag, skb);
4402 }
4403 #endif
4404
4405 /* The RX ring scheme is composed of multiple rings which post fresh
4406 * buffers to the chip, and one special ring the chip uses to report
4407 * status back to the host.
4408 *
4409 * The special ring reports the status of received packets to the
4410 * host. The chip does not write into the original descriptor the
4411 * RX buffer was obtained from. The chip simply takes the original
4412 * descriptor as provided by the host, updates the status and length
4413 * field, then writes this into the next status ring entry.
4414 *
4415 * Each ring the host uses to post buffers to the chip is described
4416 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4417 * it is first placed into the on-chip ram. When the packet's length
4418 * is known, it walks down the TG3_BDINFO entries to select the ring.
4419 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4420 * which is within the range of the new packet's length is chosen.
4421 *
4422 * The "separate ring for rx status" scheme may sound queer, but it makes
4423 * sense from a cache coherency perspective. If only the host writes
4424 * to the buffer post rings, and only the chip writes to the rx status
4425 * rings, then cache lines never move beyond shared-modified state.
4426 * If both the host and chip were to write into the same ring, cache line
4427 * eviction could occur since both entities want it in an exclusive state.
4428 */
4429 static int tg3_rx(struct tg3 *tp, int budget)
4430 {
4431 u32 work_mask, rx_std_posted = 0;
4432 u32 sw_idx = tp->rx_rcb_ptr;
4433 u16 hw_idx;
4434 int received;
4435
4436 hw_idx = tp->hw_status->idx[0].rx_producer;
4437 /*
4438 * We need to order the read of hw_idx and the read of
4439 * the opaque cookie.
4440 */
4441 rmb();
4442 work_mask = 0;
4443 received = 0;
4444 while (sw_idx != hw_idx && budget > 0) {
4445 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4446 unsigned int len;
4447 struct sk_buff *skb;
4448 dma_addr_t dma_addr;
4449 u32 opaque_key, desc_idx, *post_ptr;
4450
4451 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4452 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4453 if (opaque_key == RXD_OPAQUE_RING_STD) {
4454 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4455 mapping);
4456 skb = tp->rx_std_buffers[desc_idx].skb;
4457 post_ptr = &tp->rx_std_ptr;
4458 rx_std_posted++;
4459 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4460 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4461 mapping);
4462 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4463 post_ptr = &tp->rx_jumbo_ptr;
4464 }
4465 else {
4466 goto next_pkt_nopost;
4467 }
4468
4469 work_mask |= opaque_key;
4470
4471 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4472 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4473 drop_it:
4474 tg3_recycle_rx(tp, opaque_key,
4475 desc_idx, *post_ptr);
4476 drop_it_no_recycle:
4477 /* Other statistics kept track of by card. */
4478 tp->net_stats.rx_dropped++;
4479 goto next_pkt;
4480 }
4481
4482 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4483 ETH_FCS_LEN;
4484
4485 if (len > RX_COPY_THRESHOLD
4486 && tp->rx_offset == NET_IP_ALIGN
4487 /* rx_offset will likely not equal NET_IP_ALIGN
4488 * if this is a 5701 card running in PCI-X mode
4489 * [see tg3_get_invariants()]
4490 */
4491 ) {
4492 int skb_size;
4493
4494 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4495 desc_idx, *post_ptr);
4496 if (skb_size < 0)
4497 goto drop_it;
4498
4499 pci_unmap_single(tp->pdev, dma_addr,
4500 skb_size - tp->rx_offset,
4501 PCI_DMA_FROMDEVICE);
4502
4503 skb_put(skb, len);
4504 } else {
4505 struct sk_buff *copy_skb;
4506
4507 tg3_recycle_rx(tp, opaque_key,
4508 desc_idx, *post_ptr);
4509
4510 copy_skb = netdev_alloc_skb(tp->dev,
4511 len + TG3_RAW_IP_ALIGN);
4512 if (copy_skb == NULL)
4513 goto drop_it_no_recycle;
4514
4515 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4516 skb_put(copy_skb, len);
4517 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4518 skb_copy_from_linear_data(skb, copy_skb->data, len);
4519 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4520
4521 /* We'll reuse the original ring buffer. */
4522 skb = copy_skb;
4523 }
4524
4525 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4526 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4527 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4528 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4529 skb->ip_summed = CHECKSUM_UNNECESSARY;
4530 else
4531 skb->ip_summed = CHECKSUM_NONE;
4532
4533 skb->protocol = eth_type_trans(skb, tp->dev);
4534
4535 if (len > (tp->dev->mtu + ETH_HLEN) &&
4536 skb->protocol != htons(ETH_P_8021Q)) {
4537 dev_kfree_skb(skb);
4538 goto next_pkt;
4539 }
4540
4541 #if TG3_VLAN_TAG_USED
4542 if (tp->vlgrp != NULL &&
4543 desc->type_flags & RXD_FLAG_VLAN) {
4544 tg3_vlan_rx(tp, skb,
4545 desc->err_vlan & RXD_VLAN_MASK);
4546 } else
4547 #endif
4548 napi_gro_receive(&tp->napi, skb);
4549
4550 received++;
4551 budget--;
4552
4553 next_pkt:
4554 (*post_ptr)++;
4555
4556 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4557 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4558
4559 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4560 TG3_64BIT_REG_LOW, idx);
4561 work_mask &= ~RXD_OPAQUE_RING_STD;
4562 rx_std_posted = 0;
4563 }
4564 next_pkt_nopost:
4565 sw_idx++;
4566 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4567
4568 /* Refresh hw_idx to see if there is new work */
4569 if (sw_idx == hw_idx) {
4570 hw_idx = tp->hw_status->idx[0].rx_producer;
4571 rmb();
4572 }
4573 }
4574
4575 /* ACK the status ring. */
4576 tp->rx_rcb_ptr = sw_idx;
4577 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4578
4579 /* Refill RX ring(s). */
4580 if (work_mask & RXD_OPAQUE_RING_STD) {
4581 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4582 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4583 sw_idx);
4584 }
4585 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4586 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4587 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4588 sw_idx);
4589 }
4590 mmiowb();
4591
4592 return received;
4593 }
4594
4595 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4596 {
4597 struct tg3_hw_status *sblk = tp->hw_status;
4598
4599 /* handle link change and other phy events */
4600 if (!(tp->tg3_flags &
4601 (TG3_FLAG_USE_LINKCHG_REG |
4602 TG3_FLAG_POLL_SERDES))) {
4603 if (sblk->status & SD_STATUS_LINK_CHG) {
4604 sblk->status = SD_STATUS_UPDATED |
4605 (sblk->status & ~SD_STATUS_LINK_CHG);
4606 spin_lock(&tp->lock);
4607 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4608 tw32_f(MAC_STATUS,
4609 (MAC_STATUS_SYNC_CHANGED |
4610 MAC_STATUS_CFG_CHANGED |
4611 MAC_STATUS_MI_COMPLETION |
4612 MAC_STATUS_LNKSTATE_CHANGED));
4613 udelay(40);
4614 } else
4615 tg3_setup_phy(tp, 0);
4616 spin_unlock(&tp->lock);
4617 }
4618 }
4619
4620 /* run TX completion thread */
4621 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4622 tg3_tx(tp);
4623 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4624 return work_done;
4625 }
4626
4627 /* run RX thread, within the bounds set by NAPI.
4628 * All RX "locking" is done by ensuring outside
4629 * code synchronizes with tg3->napi.poll()
4630 */
4631 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4632 work_done += tg3_rx(tp, budget - work_done);
4633
4634 return work_done;
4635 }
4636
4637 static int tg3_poll(struct napi_struct *napi, int budget)
4638 {
4639 struct tg3 *tp = container_of(napi, struct tg3, napi);
4640 int work_done = 0;
4641 struct tg3_hw_status *sblk = tp->hw_status;
4642
4643 while (1) {
4644 work_done = tg3_poll_work(tp, work_done, budget);
4645
4646 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4647 goto tx_recovery;
4648
4649 if (unlikely(work_done >= budget))
4650 break;
4651
4652 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4653 /* tp->last_tag is used in tg3_restart_ints() below
4654 * to tell the hw how much work has been processed,
4655 * so we must read it before checking for more work.
4656 */
4657 tp->last_tag = sblk->status_tag;
4658 tp->last_irq_tag = tp->last_tag;
4659 rmb();
4660 } else
4661 sblk->status &= ~SD_STATUS_UPDATED;
4662
4663 if (likely(!tg3_has_work(tp))) {
4664 napi_complete(napi);
4665 tg3_restart_ints(tp);
4666 break;
4667 }
4668 }
4669
4670 return work_done;
4671
4672 tx_recovery:
4673 /* work_done is guaranteed to be less than budget. */
4674 napi_complete(napi);
4675 schedule_work(&tp->reset_task);
4676 return work_done;
4677 }
4678
4679 static void tg3_irq_quiesce(struct tg3 *tp)
4680 {
4681 BUG_ON(tp->irq_sync);
4682
4683 tp->irq_sync = 1;
4684 smp_mb();
4685
4686 synchronize_irq(tp->pdev->irq);
4687 }
4688
4689 static inline int tg3_irq_sync(struct tg3 *tp)
4690 {
4691 return tp->irq_sync;
4692 }
4693
4694 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4695 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4696 * with as well. Most of the time, this is not necessary except when
4697 * shutting down the device.
4698 */
4699 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4700 {
4701 spin_lock_bh(&tp->lock);
4702 if (irq_sync)
4703 tg3_irq_quiesce(tp);
4704 }
4705
4706 static inline void tg3_full_unlock(struct tg3 *tp)
4707 {
4708 spin_unlock_bh(&tp->lock);
4709 }
4710
4711 /* One-shot MSI handler - Chip automatically disables interrupt
4712 * after sending MSI so driver doesn't have to do it.
4713 */
4714 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4715 {
4716 struct net_device *dev = dev_id;
4717 struct tg3 *tp = netdev_priv(dev);
4718
4719 prefetch(tp->hw_status);
4720 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4721
4722 if (likely(!tg3_irq_sync(tp)))
4723 napi_schedule(&tp->napi);
4724
4725 return IRQ_HANDLED;
4726 }
4727
4728 /* MSI ISR - No need to check for interrupt sharing and no need to
4729 * flush status block and interrupt mailbox. PCI ordering rules
4730 * guarantee that MSI will arrive after the status block.
4731 */
4732 static irqreturn_t tg3_msi(int irq, void *dev_id)
4733 {
4734 struct net_device *dev = dev_id;
4735 struct tg3 *tp = netdev_priv(dev);
4736
4737 prefetch(tp->hw_status);
4738 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4739 /*
4740 * Writing any value to intr-mbox-0 clears PCI INTA# and
4741 * chip-internal interrupt pending events.
4742 * Writing non-zero to intr-mbox-0 additional tells the
4743 * NIC to stop sending us irqs, engaging "in-intr-handler"
4744 * event coalescing.
4745 */
4746 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4747 if (likely(!tg3_irq_sync(tp)))
4748 napi_schedule(&tp->napi);
4749
4750 return IRQ_RETVAL(1);
4751 }
4752
4753 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4754 {
4755 struct net_device *dev = dev_id;
4756 struct tg3 *tp = netdev_priv(dev);
4757 struct tg3_hw_status *sblk = tp->hw_status;
4758 unsigned int handled = 1;
4759
4760 /* In INTx mode, it is possible for the interrupt to arrive at
4761 * the CPU before the status block posted prior to the interrupt.
4762 * Reading the PCI State register will confirm whether the
4763 * interrupt is ours and will flush the status block.
4764 */
4765 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4766 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4767 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4768 handled = 0;
4769 goto out;
4770 }
4771 }
4772
4773 /*
4774 * Writing any value to intr-mbox-0 clears PCI INTA# and
4775 * chip-internal interrupt pending events.
4776 * Writing non-zero to intr-mbox-0 additional tells the
4777 * NIC to stop sending us irqs, engaging "in-intr-handler"
4778 * event coalescing.
4779 *
4780 * Flush the mailbox to de-assert the IRQ immediately to prevent
4781 * spurious interrupts. The flush impacts performance but
4782 * excessive spurious interrupts can be worse in some cases.
4783 */
4784 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4785 if (tg3_irq_sync(tp))
4786 goto out;
4787 sblk->status &= ~SD_STATUS_UPDATED;
4788 if (likely(tg3_has_work(tp))) {
4789 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4790 napi_schedule(&tp->napi);
4791 } else {
4792 /* No work, shared interrupt perhaps? re-enable
4793 * interrupts, and flush that PCI write
4794 */
4795 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4796 0x00000000);
4797 }
4798 out:
4799 return IRQ_RETVAL(handled);
4800 }
4801
4802 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4803 {
4804 struct net_device *dev = dev_id;
4805 struct tg3 *tp = netdev_priv(dev);
4806 struct tg3_hw_status *sblk = tp->hw_status;
4807 unsigned int handled = 1;
4808
4809 /* In INTx mode, it is possible for the interrupt to arrive at
4810 * the CPU before the status block posted prior to the interrupt.
4811 * Reading the PCI State register will confirm whether the
4812 * interrupt is ours and will flush the status block.
4813 */
4814 if (unlikely(sblk->status_tag == tp->last_irq_tag)) {
4815 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4816 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4817 handled = 0;
4818 goto out;
4819 }
4820 }
4821
4822 /*
4823 * writing any value to intr-mbox-0 clears PCI INTA# and
4824 * chip-internal interrupt pending events.
4825 * writing non-zero to intr-mbox-0 additional tells the
4826 * NIC to stop sending us irqs, engaging "in-intr-handler"
4827 * event coalescing.
4828 *
4829 * Flush the mailbox to de-assert the IRQ immediately to prevent
4830 * spurious interrupts. The flush impacts performance but
4831 * excessive spurious interrupts can be worse in some cases.
4832 */
4833 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4834
4835 /*
4836 * In a shared interrupt configuration, sometimes other devices'
4837 * interrupts will scream. We record the current status tag here
4838 * so that the above check can report that the screaming interrupts
4839 * are unhandled. Eventually they will be silenced.
4840 */
4841 tp->last_irq_tag = sblk->status_tag;
4842
4843 if (tg3_irq_sync(tp))
4844 goto out;
4845
4846 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4847
4848 napi_schedule(&tp->napi);
4849
4850 out:
4851 return IRQ_RETVAL(handled);
4852 }
4853
4854 /* ISR for interrupt test */
4855 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4856 {
4857 struct net_device *dev = dev_id;
4858 struct tg3 *tp = netdev_priv(dev);
4859 struct tg3_hw_status *sblk = tp->hw_status;
4860
4861 if ((sblk->status & SD_STATUS_UPDATED) ||
4862 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4863 tg3_disable_ints(tp);
4864 return IRQ_RETVAL(1);
4865 }
4866 return IRQ_RETVAL(0);
4867 }
4868
4869 static int tg3_init_hw(struct tg3 *, int);
4870 static int tg3_halt(struct tg3 *, int, int);
4871
4872 /* Restart hardware after configuration changes, self-test, etc.
4873 * Invoked with tp->lock held.
4874 */
4875 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4876 __releases(tp->lock)
4877 __acquires(tp->lock)
4878 {
4879 int err;
4880
4881 err = tg3_init_hw(tp, reset_phy);
4882 if (err) {
4883 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4884 "aborting.\n", tp->dev->name);
4885 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4886 tg3_full_unlock(tp);
4887 del_timer_sync(&tp->timer);
4888 tp->irq_sync = 0;
4889 napi_enable(&tp->napi);
4890 dev_close(tp->dev);
4891 tg3_full_lock(tp, 0);
4892 }
4893 return err;
4894 }
4895
4896 #ifdef CONFIG_NET_POLL_CONTROLLER
4897 static void tg3_poll_controller(struct net_device *dev)
4898 {
4899 struct tg3 *tp = netdev_priv(dev);
4900
4901 tg3_interrupt(tp->pdev->irq, dev);
4902 }
4903 #endif
4904
4905 static void tg3_reset_task(struct work_struct *work)
4906 {
4907 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4908 int err;
4909 unsigned int restart_timer;
4910
4911 tg3_full_lock(tp, 0);
4912
4913 if (!netif_running(tp->dev)) {
4914 tg3_full_unlock(tp);
4915 return;
4916 }
4917
4918 tg3_full_unlock(tp);
4919
4920 tg3_phy_stop(tp);
4921
4922 tg3_netif_stop(tp);
4923
4924 tg3_full_lock(tp, 1);
4925
4926 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4927 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4928
4929 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4930 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4931 tp->write32_rx_mbox = tg3_write_flush_reg32;
4932 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4933 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4934 }
4935
4936 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4937 err = tg3_init_hw(tp, 1);
4938 if (err)
4939 goto out;
4940
4941 tg3_netif_start(tp);
4942
4943 if (restart_timer)
4944 mod_timer(&tp->timer, jiffies + 1);
4945
4946 out:
4947 tg3_full_unlock(tp);
4948
4949 if (!err)
4950 tg3_phy_start(tp);
4951 }
4952
4953 static void tg3_dump_short_state(struct tg3 *tp)
4954 {
4955 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4956 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4957 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4958 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4959 }
4960
4961 static void tg3_tx_timeout(struct net_device *dev)
4962 {
4963 struct tg3 *tp = netdev_priv(dev);
4964
4965 if (netif_msg_tx_err(tp)) {
4966 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4967 dev->name);
4968 tg3_dump_short_state(tp);
4969 }
4970
4971 schedule_work(&tp->reset_task);
4972 }
4973
4974 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4975 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4976 {
4977 u32 base = (u32) mapping & 0xffffffff;
4978
4979 return ((base > 0xffffdcc0) &&
4980 (base + len + 8 < base));
4981 }
4982
4983 /* Test for DMA addresses > 40-bit */
4984 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4985 int len)
4986 {
4987 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4988 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4989 return (((u64) mapping + len) > DMA_BIT_MASK(40));
4990 return 0;
4991 #else
4992 return 0;
4993 #endif
4994 }
4995
4996 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4997
4998 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4999 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5000 u32 last_plus_one, u32 *start,
5001 u32 base_flags, u32 mss)
5002 {
5003 struct sk_buff *new_skb;
5004 dma_addr_t new_addr = 0;
5005 u32 entry = *start;
5006 int i, ret = 0;
5007
5008 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5009 new_skb = skb_copy(skb, GFP_ATOMIC);
5010 else {
5011 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5012
5013 new_skb = skb_copy_expand(skb,
5014 skb_headroom(skb) + more_headroom,
5015 skb_tailroom(skb), GFP_ATOMIC);
5016 }
5017
5018 if (!new_skb) {
5019 ret = -1;
5020 } else {
5021 /* New SKB is guaranteed to be linear. */
5022 entry = *start;
5023 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5024 new_addr = skb_shinfo(new_skb)->dma_head;
5025
5026 /* Make sure new skb does not cross any 4G boundaries.
5027 * Drop the packet if it does.
5028 */
5029 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5030 if (!ret)
5031 skb_dma_unmap(&tp->pdev->dev, new_skb,
5032 DMA_TO_DEVICE);
5033 ret = -1;
5034 dev_kfree_skb(new_skb);
5035 new_skb = NULL;
5036 } else {
5037 tg3_set_txd(tp, entry, new_addr, new_skb->len,
5038 base_flags, 1 | (mss << 1));
5039 *start = NEXT_TX(entry);
5040 }
5041 }
5042
5043 /* Now clean up the sw ring entries. */
5044 i = 0;
5045 while (entry != last_plus_one) {
5046 if (i == 0) {
5047 tp->tx_buffers[entry].skb = new_skb;
5048 } else {
5049 tp->tx_buffers[entry].skb = NULL;
5050 }
5051 entry = NEXT_TX(entry);
5052 i++;
5053 }
5054
5055 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5056 dev_kfree_skb(skb);
5057
5058 return ret;
5059 }
5060
5061 static void tg3_set_txd(struct tg3 *tp, int entry,
5062 dma_addr_t mapping, int len, u32 flags,
5063 u32 mss_and_is_end)
5064 {
5065 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
5066 int is_end = (mss_and_is_end & 0x1);
5067 u32 mss = (mss_and_is_end >> 1);
5068 u32 vlan_tag = 0;
5069
5070 if (is_end)
5071 flags |= TXD_FLAG_END;
5072 if (flags & TXD_FLAG_VLAN) {
5073 vlan_tag = flags >> 16;
5074 flags &= 0xffff;
5075 }
5076 vlan_tag |= (mss << TXD_MSS_SHIFT);
5077
5078 txd->addr_hi = ((u64) mapping >> 32);
5079 txd->addr_lo = ((u64) mapping & 0xffffffff);
5080 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5081 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5082 }
5083
5084 /* hard_start_xmit for devices that don't have any bugs and
5085 * support TG3_FLG2_HW_TSO_2 only.
5086 */
5087 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5088 {
5089 struct tg3 *tp = netdev_priv(dev);
5090 u32 len, entry, base_flags, mss;
5091 struct skb_shared_info *sp;
5092 dma_addr_t mapping;
5093
5094 len = skb_headlen(skb);
5095
5096 /* We are running in BH disabled context with netif_tx_lock
5097 * and TX reclaim runs via tp->napi.poll inside of a software
5098 * interrupt. Furthermore, IRQ processing runs lockless so we have
5099 * no IRQ context deadlocks to worry about either. Rejoice!
5100 */
5101 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5102 if (!netif_queue_stopped(dev)) {
5103 netif_stop_queue(dev);
5104
5105 /* This is a hard error, log it. */
5106 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5107 "queue awake!\n", dev->name);
5108 }
5109 return NETDEV_TX_BUSY;
5110 }
5111
5112 entry = tp->tx_prod;
5113 base_flags = 0;
5114 mss = 0;
5115 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5116 int tcp_opt_len, ip_tcp_len;
5117
5118 if (skb_header_cloned(skb) &&
5119 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5120 dev_kfree_skb(skb);
5121 goto out_unlock;
5122 }
5123
5124 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5125 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
5126 else {
5127 struct iphdr *iph = ip_hdr(skb);
5128
5129 tcp_opt_len = tcp_optlen(skb);
5130 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5131
5132 iph->check = 0;
5133 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5134 mss |= (ip_tcp_len + tcp_opt_len) << 9;
5135 }
5136
5137 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5138 TXD_FLAG_CPU_POST_DMA);
5139
5140 tcp_hdr(skb)->check = 0;
5141
5142 }
5143 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5144 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5145 #if TG3_VLAN_TAG_USED
5146 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5147 base_flags |= (TXD_FLAG_VLAN |
5148 (vlan_tx_tag_get(skb) << 16));
5149 #endif
5150
5151 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5152 dev_kfree_skb(skb);
5153 goto out_unlock;
5154 }
5155
5156 sp = skb_shinfo(skb);
5157
5158 mapping = sp->dma_head;
5159
5160 tp->tx_buffers[entry].skb = skb;
5161
5162 tg3_set_txd(tp, entry, mapping, len, base_flags,
5163 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5164
5165 entry = NEXT_TX(entry);
5166
5167 /* Now loop through additional data fragments, and queue them. */
5168 if (skb_shinfo(skb)->nr_frags > 0) {
5169 unsigned int i, last;
5170
5171 last = skb_shinfo(skb)->nr_frags - 1;
5172 for (i = 0; i <= last; i++) {
5173 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5174
5175 len = frag->size;
5176 mapping = sp->dma_maps[i];
5177 tp->tx_buffers[entry].skb = NULL;
5178
5179 tg3_set_txd(tp, entry, mapping, len,
5180 base_flags, (i == last) | (mss << 1));
5181
5182 entry = NEXT_TX(entry);
5183 }
5184 }
5185
5186 /* Packets are ready, update Tx producer idx local and on card. */
5187 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5188
5189 tp->tx_prod = entry;
5190 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5191 netif_stop_queue(dev);
5192 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5193 netif_wake_queue(tp->dev);
5194 }
5195
5196 out_unlock:
5197 mmiowb();
5198
5199 return NETDEV_TX_OK;
5200 }
5201
5202 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5203
5204 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5205 * TSO header is greater than 80 bytes.
5206 */
5207 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5208 {
5209 struct sk_buff *segs, *nskb;
5210
5211 /* Estimate the number of fragments in the worst case */
5212 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5213 netif_stop_queue(tp->dev);
5214 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5215 return NETDEV_TX_BUSY;
5216
5217 netif_wake_queue(tp->dev);
5218 }
5219
5220 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5221 if (IS_ERR(segs))
5222 goto tg3_tso_bug_end;
5223
5224 do {
5225 nskb = segs;
5226 segs = segs->next;
5227 nskb->next = NULL;
5228 tg3_start_xmit_dma_bug(nskb, tp->dev);
5229 } while (segs);
5230
5231 tg3_tso_bug_end:
5232 dev_kfree_skb(skb);
5233
5234 return NETDEV_TX_OK;
5235 }
5236
5237 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5238 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5239 */
5240 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5241 {
5242 struct tg3 *tp = netdev_priv(dev);
5243 u32 len, entry, base_flags, mss;
5244 struct skb_shared_info *sp;
5245 int would_hit_hwbug;
5246 dma_addr_t mapping;
5247
5248 len = skb_headlen(skb);
5249
5250 /* We are running in BH disabled context with netif_tx_lock
5251 * and TX reclaim runs via tp->napi.poll inside of a software
5252 * interrupt. Furthermore, IRQ processing runs lockless so we have
5253 * no IRQ context deadlocks to worry about either. Rejoice!
5254 */
5255 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5256 if (!netif_queue_stopped(dev)) {
5257 netif_stop_queue(dev);
5258
5259 /* This is a hard error, log it. */
5260 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5261 "queue awake!\n", dev->name);
5262 }
5263 return NETDEV_TX_BUSY;
5264 }
5265
5266 entry = tp->tx_prod;
5267 base_flags = 0;
5268 if (skb->ip_summed == CHECKSUM_PARTIAL)
5269 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5270 mss = 0;
5271 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5272 struct iphdr *iph;
5273 int tcp_opt_len, ip_tcp_len, hdr_len;
5274
5275 if (skb_header_cloned(skb) &&
5276 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5277 dev_kfree_skb(skb);
5278 goto out_unlock;
5279 }
5280
5281 tcp_opt_len = tcp_optlen(skb);
5282 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5283
5284 hdr_len = ip_tcp_len + tcp_opt_len;
5285 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5286 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5287 return (tg3_tso_bug(tp, skb));
5288
5289 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5290 TXD_FLAG_CPU_POST_DMA);
5291
5292 iph = ip_hdr(skb);
5293 iph->check = 0;
5294 iph->tot_len = htons(mss + hdr_len);
5295 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5296 tcp_hdr(skb)->check = 0;
5297 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5298 } else
5299 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5300 iph->daddr, 0,
5301 IPPROTO_TCP,
5302 0);
5303
5304 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5305 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5306 if (tcp_opt_len || iph->ihl > 5) {
5307 int tsflags;
5308
5309 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5310 mss |= (tsflags << 11);
5311 }
5312 } else {
5313 if (tcp_opt_len || iph->ihl > 5) {
5314 int tsflags;
5315
5316 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5317 base_flags |= tsflags << 12;
5318 }
5319 }
5320 }
5321 #if TG3_VLAN_TAG_USED
5322 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5323 base_flags |= (TXD_FLAG_VLAN |
5324 (vlan_tx_tag_get(skb) << 16));
5325 #endif
5326
5327 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5328 dev_kfree_skb(skb);
5329 goto out_unlock;
5330 }
5331
5332 sp = skb_shinfo(skb);
5333
5334 mapping = sp->dma_head;
5335
5336 tp->tx_buffers[entry].skb = skb;
5337
5338 would_hit_hwbug = 0;
5339
5340 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5341 would_hit_hwbug = 1;
5342 else if (tg3_4g_overflow_test(mapping, len))
5343 would_hit_hwbug = 1;
5344
5345 tg3_set_txd(tp, entry, mapping, len, base_flags,
5346 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5347
5348 entry = NEXT_TX(entry);
5349
5350 /* Now loop through additional data fragments, and queue them. */
5351 if (skb_shinfo(skb)->nr_frags > 0) {
5352 unsigned int i, last;
5353
5354 last = skb_shinfo(skb)->nr_frags - 1;
5355 for (i = 0; i <= last; i++) {
5356 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5357
5358 len = frag->size;
5359 mapping = sp->dma_maps[i];
5360
5361 tp->tx_buffers[entry].skb = NULL;
5362
5363 if (tg3_4g_overflow_test(mapping, len))
5364 would_hit_hwbug = 1;
5365
5366 if (tg3_40bit_overflow_test(tp, mapping, len))
5367 would_hit_hwbug = 1;
5368
5369 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5370 tg3_set_txd(tp, entry, mapping, len,
5371 base_flags, (i == last)|(mss << 1));
5372 else
5373 tg3_set_txd(tp, entry, mapping, len,
5374 base_flags, (i == last));
5375
5376 entry = NEXT_TX(entry);
5377 }
5378 }
5379
5380 if (would_hit_hwbug) {
5381 u32 last_plus_one = entry;
5382 u32 start;
5383
5384 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5385 start &= (TG3_TX_RING_SIZE - 1);
5386
5387 /* If the workaround fails due to memory/mapping
5388 * failure, silently drop this packet.
5389 */
5390 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5391 &start, base_flags, mss))
5392 goto out_unlock;
5393
5394 entry = start;
5395 }
5396
5397 /* Packets are ready, update Tx producer idx local and on card. */
5398 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5399
5400 tp->tx_prod = entry;
5401 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5402 netif_stop_queue(dev);
5403 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5404 netif_wake_queue(tp->dev);
5405 }
5406
5407 out_unlock:
5408 mmiowb();
5409
5410 return NETDEV_TX_OK;
5411 }
5412
5413 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5414 int new_mtu)
5415 {
5416 dev->mtu = new_mtu;
5417
5418 if (new_mtu > ETH_DATA_LEN) {
5419 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5420 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5421 ethtool_op_set_tso(dev, 0);
5422 }
5423 else
5424 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5425 } else {
5426 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5427 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5428 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5429 }
5430 }
5431
5432 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5433 {
5434 struct tg3 *tp = netdev_priv(dev);
5435 int err;
5436
5437 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5438 return -EINVAL;
5439
5440 if (!netif_running(dev)) {
5441 /* We'll just catch it later when the
5442 * device is up'd.
5443 */
5444 tg3_set_mtu(dev, tp, new_mtu);
5445 return 0;
5446 }
5447
5448 tg3_phy_stop(tp);
5449
5450 tg3_netif_stop(tp);
5451
5452 tg3_full_lock(tp, 1);
5453
5454 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5455
5456 tg3_set_mtu(dev, tp, new_mtu);
5457
5458 err = tg3_restart_hw(tp, 0);
5459
5460 if (!err)
5461 tg3_netif_start(tp);
5462
5463 tg3_full_unlock(tp);
5464
5465 if (!err)
5466 tg3_phy_start(tp);
5467
5468 return err;
5469 }
5470
5471 /* Free up pending packets in all rx/tx rings.
5472 *
5473 * The chip has been shut down and the driver detached from
5474 * the networking, so no interrupts or new tx packets will
5475 * end up in the driver. tp->{tx,}lock is not held and we are not
5476 * in an interrupt context and thus may sleep.
5477 */
5478 static void tg3_free_rings(struct tg3 *tp)
5479 {
5480 struct ring_info *rxp;
5481 int i;
5482
5483 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5484 rxp = &tp->rx_std_buffers[i];
5485
5486 if (rxp->skb == NULL)
5487 continue;
5488 pci_unmap_single(tp->pdev,
5489 pci_unmap_addr(rxp, mapping),
5490 tp->rx_pkt_buf_sz - tp->rx_offset,
5491 PCI_DMA_FROMDEVICE);
5492 dev_kfree_skb_any(rxp->skb);
5493 rxp->skb = NULL;
5494 }
5495
5496 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5497 rxp = &tp->rx_jumbo_buffers[i];
5498
5499 if (rxp->skb == NULL)
5500 continue;
5501 pci_unmap_single(tp->pdev,
5502 pci_unmap_addr(rxp, mapping),
5503 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5504 PCI_DMA_FROMDEVICE);
5505 dev_kfree_skb_any(rxp->skb);
5506 rxp->skb = NULL;
5507 }
5508
5509 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5510 struct tx_ring_info *txp;
5511 struct sk_buff *skb;
5512
5513 txp = &tp->tx_buffers[i];
5514 skb = txp->skb;
5515
5516 if (skb == NULL) {
5517 i++;
5518 continue;
5519 }
5520
5521 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5522
5523 txp->skb = NULL;
5524
5525 i += skb_shinfo(skb)->nr_frags + 1;
5526
5527 dev_kfree_skb_any(skb);
5528 }
5529 }
5530
5531 /* Initialize tx/rx rings for packet processing.
5532 *
5533 * The chip has been shut down and the driver detached from
5534 * the networking, so no interrupts or new tx packets will
5535 * end up in the driver. tp->{tx,}lock are held and thus
5536 * we may not sleep.
5537 */
5538 static int tg3_init_rings(struct tg3 *tp)
5539 {
5540 u32 i;
5541
5542 /* Free up all the SKBs. */
5543 tg3_free_rings(tp);
5544
5545 /* Zero out all descriptors. */
5546 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5547 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5548 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5549 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5550
5551 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5552 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5553 (tp->dev->mtu > ETH_DATA_LEN))
5554 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5555
5556 /* Initialize invariants of the rings, we only set this
5557 * stuff once. This works because the card does not
5558 * write into the rx buffer posting rings.
5559 */
5560 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5561 struct tg3_rx_buffer_desc *rxd;
5562
5563 rxd = &tp->rx_std[i];
5564 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5565 << RXD_LEN_SHIFT;
5566 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5567 rxd->opaque = (RXD_OPAQUE_RING_STD |
5568 (i << RXD_OPAQUE_INDEX_SHIFT));
5569 }
5570
5571 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5572 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5573 struct tg3_rx_buffer_desc *rxd;
5574
5575 rxd = &tp->rx_jumbo[i];
5576 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5577 << RXD_LEN_SHIFT;
5578 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5579 RXD_FLAG_JUMBO;
5580 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5581 (i << RXD_OPAQUE_INDEX_SHIFT));
5582 }
5583 }
5584
5585 /* Now allocate fresh SKBs for each rx ring. */
5586 for (i = 0; i < tp->rx_pending; i++) {
5587 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5588 printk(KERN_WARNING PFX
5589 "%s: Using a smaller RX standard ring, "
5590 "only %d out of %d buffers were allocated "
5591 "successfully.\n",
5592 tp->dev->name, i, tp->rx_pending);
5593 if (i == 0)
5594 return -ENOMEM;
5595 tp->rx_pending = i;
5596 break;
5597 }
5598 }
5599
5600 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5601 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5602 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5603 -1, i) < 0) {
5604 printk(KERN_WARNING PFX
5605 "%s: Using a smaller RX jumbo ring, "
5606 "only %d out of %d buffers were "
5607 "allocated successfully.\n",
5608 tp->dev->name, i, tp->rx_jumbo_pending);
5609 if (i == 0) {
5610 tg3_free_rings(tp);
5611 return -ENOMEM;
5612 }
5613 tp->rx_jumbo_pending = i;
5614 break;
5615 }
5616 }
5617 }
5618 return 0;
5619 }
5620
5621 /*
5622 * Must not be invoked with interrupt sources disabled and
5623 * the hardware shutdown down.
5624 */
5625 static void tg3_free_consistent(struct tg3 *tp)
5626 {
5627 kfree(tp->rx_std_buffers);
5628 tp->rx_std_buffers = NULL;
5629 if (tp->rx_std) {
5630 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5631 tp->rx_std, tp->rx_std_mapping);
5632 tp->rx_std = NULL;
5633 }
5634 if (tp->rx_jumbo) {
5635 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5636 tp->rx_jumbo, tp->rx_jumbo_mapping);
5637 tp->rx_jumbo = NULL;
5638 }
5639 if (tp->rx_rcb) {
5640 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5641 tp->rx_rcb, tp->rx_rcb_mapping);
5642 tp->rx_rcb = NULL;
5643 }
5644 if (tp->tx_ring) {
5645 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5646 tp->tx_ring, tp->tx_desc_mapping);
5647 tp->tx_ring = NULL;
5648 }
5649 if (tp->hw_status) {
5650 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5651 tp->hw_status, tp->status_mapping);
5652 tp->hw_status = NULL;
5653 }
5654 if (tp->hw_stats) {
5655 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5656 tp->hw_stats, tp->stats_mapping);
5657 tp->hw_stats = NULL;
5658 }
5659 }
5660
5661 /*
5662 * Must not be invoked with interrupt sources disabled and
5663 * the hardware shutdown down. Can sleep.
5664 */
5665 static int tg3_alloc_consistent(struct tg3 *tp)
5666 {
5667 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5668 (TG3_RX_RING_SIZE +
5669 TG3_RX_JUMBO_RING_SIZE)) +
5670 (sizeof(struct tx_ring_info) *
5671 TG3_TX_RING_SIZE),
5672 GFP_KERNEL);
5673 if (!tp->rx_std_buffers)
5674 return -ENOMEM;
5675
5676 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5677 tp->tx_buffers = (struct tx_ring_info *)
5678 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5679
5680 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5681 &tp->rx_std_mapping);
5682 if (!tp->rx_std)
5683 goto err_out;
5684
5685 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5686 &tp->rx_jumbo_mapping);
5687
5688 if (!tp->rx_jumbo)
5689 goto err_out;
5690
5691 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5692 &tp->rx_rcb_mapping);
5693 if (!tp->rx_rcb)
5694 goto err_out;
5695
5696 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5697 &tp->tx_desc_mapping);
5698 if (!tp->tx_ring)
5699 goto err_out;
5700
5701 tp->hw_status = pci_alloc_consistent(tp->pdev,
5702 TG3_HW_STATUS_SIZE,
5703 &tp->status_mapping);
5704 if (!tp->hw_status)
5705 goto err_out;
5706
5707 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5708 sizeof(struct tg3_hw_stats),
5709 &tp->stats_mapping);
5710 if (!tp->hw_stats)
5711 goto err_out;
5712
5713 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5714 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5715
5716 return 0;
5717
5718 err_out:
5719 tg3_free_consistent(tp);
5720 return -ENOMEM;
5721 }
5722
5723 #define MAX_WAIT_CNT 1000
5724
5725 /* To stop a block, clear the enable bit and poll till it
5726 * clears. tp->lock is held.
5727 */
5728 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5729 {
5730 unsigned int i;
5731 u32 val;
5732
5733 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5734 switch (ofs) {
5735 case RCVLSC_MODE:
5736 case DMAC_MODE:
5737 case MBFREE_MODE:
5738 case BUFMGR_MODE:
5739 case MEMARB_MODE:
5740 /* We can't enable/disable these bits of the
5741 * 5705/5750, just say success.
5742 */
5743 return 0;
5744
5745 default:
5746 break;
5747 }
5748 }
5749
5750 val = tr32(ofs);
5751 val &= ~enable_bit;
5752 tw32_f(ofs, val);
5753
5754 for (i = 0; i < MAX_WAIT_CNT; i++) {
5755 udelay(100);
5756 val = tr32(ofs);
5757 if ((val & enable_bit) == 0)
5758 break;
5759 }
5760
5761 if (i == MAX_WAIT_CNT && !silent) {
5762 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5763 "ofs=%lx enable_bit=%x\n",
5764 ofs, enable_bit);
5765 return -ENODEV;
5766 }
5767
5768 return 0;
5769 }
5770
5771 /* tp->lock is held. */
5772 static int tg3_abort_hw(struct tg3 *tp, int silent)
5773 {
5774 int i, err;
5775
5776 tg3_disable_ints(tp);
5777
5778 tp->rx_mode &= ~RX_MODE_ENABLE;
5779 tw32_f(MAC_RX_MODE, tp->rx_mode);
5780 udelay(10);
5781
5782 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5783 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5784 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5785 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5786 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5787 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5788
5789 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5790 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5791 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5792 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5793 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5794 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5795 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5796
5797 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5798 tw32_f(MAC_MODE, tp->mac_mode);
5799 udelay(40);
5800
5801 tp->tx_mode &= ~TX_MODE_ENABLE;
5802 tw32_f(MAC_TX_MODE, tp->tx_mode);
5803
5804 for (i = 0; i < MAX_WAIT_CNT; i++) {
5805 udelay(100);
5806 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5807 break;
5808 }
5809 if (i >= MAX_WAIT_CNT) {
5810 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5811 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5812 tp->dev->name, tr32(MAC_TX_MODE));
5813 err |= -ENODEV;
5814 }
5815
5816 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5817 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5818 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5819
5820 tw32(FTQ_RESET, 0xffffffff);
5821 tw32(FTQ_RESET, 0x00000000);
5822
5823 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5824 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5825
5826 if (tp->hw_status)
5827 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5828 if (tp->hw_stats)
5829 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5830
5831 return err;
5832 }
5833
5834 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5835 {
5836 int i;
5837 u32 apedata;
5838
5839 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5840 if (apedata != APE_SEG_SIG_MAGIC)
5841 return;
5842
5843 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5844 if (!(apedata & APE_FW_STATUS_READY))
5845 return;
5846
5847 /* Wait for up to 1 millisecond for APE to service previous event. */
5848 for (i = 0; i < 10; i++) {
5849 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5850 return;
5851
5852 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5853
5854 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5855 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5856 event | APE_EVENT_STATUS_EVENT_PENDING);
5857
5858 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5859
5860 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5861 break;
5862
5863 udelay(100);
5864 }
5865
5866 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5867 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5868 }
5869
5870 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5871 {
5872 u32 event;
5873 u32 apedata;
5874
5875 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5876 return;
5877
5878 switch (kind) {
5879 case RESET_KIND_INIT:
5880 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5881 APE_HOST_SEG_SIG_MAGIC);
5882 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5883 APE_HOST_SEG_LEN_MAGIC);
5884 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5885 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5886 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5887 APE_HOST_DRIVER_ID_MAGIC);
5888 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5889 APE_HOST_BEHAV_NO_PHYLOCK);
5890
5891 event = APE_EVENT_STATUS_STATE_START;
5892 break;
5893 case RESET_KIND_SHUTDOWN:
5894 /* With the interface we are currently using,
5895 * APE does not track driver state. Wiping
5896 * out the HOST SEGMENT SIGNATURE forces
5897 * the APE to assume OS absent status.
5898 */
5899 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5900
5901 event = APE_EVENT_STATUS_STATE_UNLOAD;
5902 break;
5903 case RESET_KIND_SUSPEND:
5904 event = APE_EVENT_STATUS_STATE_SUSPEND;
5905 break;
5906 default:
5907 return;
5908 }
5909
5910 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5911
5912 tg3_ape_send_event(tp, event);
5913 }
5914
5915 /* tp->lock is held. */
5916 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5917 {
5918 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5919 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5920
5921 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5922 switch (kind) {
5923 case RESET_KIND_INIT:
5924 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5925 DRV_STATE_START);
5926 break;
5927
5928 case RESET_KIND_SHUTDOWN:
5929 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5930 DRV_STATE_UNLOAD);
5931 break;
5932
5933 case RESET_KIND_SUSPEND:
5934 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5935 DRV_STATE_SUSPEND);
5936 break;
5937
5938 default:
5939 break;
5940 }
5941 }
5942
5943 if (kind == RESET_KIND_INIT ||
5944 kind == RESET_KIND_SUSPEND)
5945 tg3_ape_driver_state_change(tp, kind);
5946 }
5947
5948 /* tp->lock is held. */
5949 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5950 {
5951 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5952 switch (kind) {
5953 case RESET_KIND_INIT:
5954 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5955 DRV_STATE_START_DONE);
5956 break;
5957
5958 case RESET_KIND_SHUTDOWN:
5959 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5960 DRV_STATE_UNLOAD_DONE);
5961 break;
5962
5963 default:
5964 break;
5965 }
5966 }
5967
5968 if (kind == RESET_KIND_SHUTDOWN)
5969 tg3_ape_driver_state_change(tp, kind);
5970 }
5971
5972 /* tp->lock is held. */
5973 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5974 {
5975 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5976 switch (kind) {
5977 case RESET_KIND_INIT:
5978 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5979 DRV_STATE_START);
5980 break;
5981
5982 case RESET_KIND_SHUTDOWN:
5983 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5984 DRV_STATE_UNLOAD);
5985 break;
5986
5987 case RESET_KIND_SUSPEND:
5988 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5989 DRV_STATE_SUSPEND);
5990 break;
5991
5992 default:
5993 break;
5994 }
5995 }
5996 }
5997
5998 static int tg3_poll_fw(struct tg3 *tp)
5999 {
6000 int i;
6001 u32 val;
6002
6003 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6004 /* Wait up to 20ms for init done. */
6005 for (i = 0; i < 200; i++) {
6006 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6007 return 0;
6008 udelay(100);
6009 }
6010 return -ENODEV;
6011 }
6012
6013 /* Wait for firmware initialization to complete. */
6014 for (i = 0; i < 100000; i++) {
6015 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6016 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6017 break;
6018 udelay(10);
6019 }
6020
6021 /* Chip might not be fitted with firmware. Some Sun onboard
6022 * parts are configured like that. So don't signal the timeout
6023 * of the above loop as an error, but do report the lack of
6024 * running firmware once.
6025 */
6026 if (i >= 100000 &&
6027 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6028 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6029
6030 printk(KERN_INFO PFX "%s: No firmware running.\n",
6031 tp->dev->name);
6032 }
6033
6034 return 0;
6035 }
6036
6037 /* Save PCI command register before chip reset */
6038 static void tg3_save_pci_state(struct tg3 *tp)
6039 {
6040 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6041 }
6042
6043 /* Restore PCI state after chip reset */
6044 static void tg3_restore_pci_state(struct tg3 *tp)
6045 {
6046 u32 val;
6047
6048 /* Re-enable indirect register accesses. */
6049 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6050 tp->misc_host_ctrl);
6051
6052 /* Set MAX PCI retry to zero. */
6053 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6054 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6055 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6056 val |= PCISTATE_RETRY_SAME_DMA;
6057 /* Allow reads and writes to the APE register and memory space. */
6058 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6059 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6060 PCISTATE_ALLOW_APE_SHMEM_WR;
6061 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6062
6063 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6064
6065 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6066 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6067 pcie_set_readrq(tp->pdev, 4096);
6068 else {
6069 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6070 tp->pci_cacheline_sz);
6071 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6072 tp->pci_lat_timer);
6073 }
6074 }
6075
6076 /* Make sure PCI-X relaxed ordering bit is clear. */
6077 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6078 u16 pcix_cmd;
6079
6080 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6081 &pcix_cmd);
6082 pcix_cmd &= ~PCI_X_CMD_ERO;
6083 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6084 pcix_cmd);
6085 }
6086
6087 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6088
6089 /* Chip reset on 5780 will reset MSI enable bit,
6090 * so need to restore it.
6091 */
6092 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6093 u16 ctrl;
6094
6095 pci_read_config_word(tp->pdev,
6096 tp->msi_cap + PCI_MSI_FLAGS,
6097 &ctrl);
6098 pci_write_config_word(tp->pdev,
6099 tp->msi_cap + PCI_MSI_FLAGS,
6100 ctrl | PCI_MSI_FLAGS_ENABLE);
6101 val = tr32(MSGINT_MODE);
6102 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6103 }
6104 }
6105 }
6106
6107 static void tg3_stop_fw(struct tg3 *);
6108
6109 /* tp->lock is held. */
6110 static int tg3_chip_reset(struct tg3 *tp)
6111 {
6112 u32 val;
6113 void (*write_op)(struct tg3 *, u32, u32);
6114 int err;
6115
6116 tg3_nvram_lock(tp);
6117
6118 tg3_mdio_stop(tp);
6119
6120 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6121
6122 /* No matching tg3_nvram_unlock() after this because
6123 * chip reset below will undo the nvram lock.
6124 */
6125 tp->nvram_lock_cnt = 0;
6126
6127 /* GRC_MISC_CFG core clock reset will clear the memory
6128 * enable bit in PCI register 4 and the MSI enable bit
6129 * on some chips, so we save relevant registers here.
6130 */
6131 tg3_save_pci_state(tp);
6132
6133 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6134 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6135 tw32(GRC_FASTBOOT_PC, 0);
6136
6137 /*
6138 * We must avoid the readl() that normally takes place.
6139 * It locks machines, causes machine checks, and other
6140 * fun things. So, temporarily disable the 5701
6141 * hardware workaround, while we do the reset.
6142 */
6143 write_op = tp->write32;
6144 if (write_op == tg3_write_flush_reg32)
6145 tp->write32 = tg3_write32;
6146
6147 /* Prevent the irq handler from reading or writing PCI registers
6148 * during chip reset when the memory enable bit in the PCI command
6149 * register may be cleared. The chip does not generate interrupt
6150 * at this time, but the irq handler may still be called due to irq
6151 * sharing or irqpoll.
6152 */
6153 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6154 if (tp->hw_status) {
6155 tp->hw_status->status = 0;
6156 tp->hw_status->status_tag = 0;
6157 }
6158 tp->last_tag = 0;
6159 tp->last_irq_tag = 0;
6160 smp_mb();
6161 synchronize_irq(tp->pdev->irq);
6162
6163 /* do the reset */
6164 val = GRC_MISC_CFG_CORECLK_RESET;
6165
6166 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6167 if (tr32(0x7e2c) == 0x60) {
6168 tw32(0x7e2c, 0x20);
6169 }
6170 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6171 tw32(GRC_MISC_CFG, (1 << 29));
6172 val |= (1 << 29);
6173 }
6174 }
6175
6176 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6177 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6178 tw32(GRC_VCPU_EXT_CTRL,
6179 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6180 }
6181
6182 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6183 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6184 tw32(GRC_MISC_CFG, val);
6185
6186 /* restore 5701 hardware bug workaround write method */
6187 tp->write32 = write_op;
6188
6189 /* Unfortunately, we have to delay before the PCI read back.
6190 * Some 575X chips even will not respond to a PCI cfg access
6191 * when the reset command is given to the chip.
6192 *
6193 * How do these hardware designers expect things to work
6194 * properly if the PCI write is posted for a long period
6195 * of time? It is always necessary to have some method by
6196 * which a register read back can occur to push the write
6197 * out which does the reset.
6198 *
6199 * For most tg3 variants the trick below was working.
6200 * Ho hum...
6201 */
6202 udelay(120);
6203
6204 /* Flush PCI posted writes. The normal MMIO registers
6205 * are inaccessible at this time so this is the only
6206 * way to make this reliably (actually, this is no longer
6207 * the case, see above). I tried to use indirect
6208 * register read/write but this upset some 5701 variants.
6209 */
6210 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6211
6212 udelay(120);
6213
6214 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6215 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6216 int i;
6217 u32 cfg_val;
6218
6219 /* Wait for link training to complete. */
6220 for (i = 0; i < 5000; i++)
6221 udelay(100);
6222
6223 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6224 pci_write_config_dword(tp->pdev, 0xc4,
6225 cfg_val | (1 << 15));
6226 }
6227
6228 /* Set PCIE max payload size to 128 bytes and
6229 * clear the "no snoop" and "relaxed ordering" bits.
6230 */
6231 pci_write_config_word(tp->pdev,
6232 tp->pcie_cap + PCI_EXP_DEVCTL,
6233 0);
6234
6235 pcie_set_readrq(tp->pdev, 4096);
6236
6237 /* Clear error status */
6238 pci_write_config_word(tp->pdev,
6239 tp->pcie_cap + PCI_EXP_DEVSTA,
6240 PCI_EXP_DEVSTA_CED |
6241 PCI_EXP_DEVSTA_NFED |
6242 PCI_EXP_DEVSTA_FED |
6243 PCI_EXP_DEVSTA_URD);
6244 }
6245
6246 tg3_restore_pci_state(tp);
6247
6248 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6249
6250 val = 0;
6251 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6252 val = tr32(MEMARB_MODE);
6253 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6254
6255 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6256 tg3_stop_fw(tp);
6257 tw32(0x5000, 0x400);
6258 }
6259
6260 tw32(GRC_MODE, tp->grc_mode);
6261
6262 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6263 val = tr32(0xc4);
6264
6265 tw32(0xc4, val | (1 << 15));
6266 }
6267
6268 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6269 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6270 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6271 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6272 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6273 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6274 }
6275
6276 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6277 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6278 tw32_f(MAC_MODE, tp->mac_mode);
6279 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6280 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6281 tw32_f(MAC_MODE, tp->mac_mode);
6282 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6283 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6284 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6285 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6286 tw32_f(MAC_MODE, tp->mac_mode);
6287 } else
6288 tw32_f(MAC_MODE, 0);
6289 udelay(40);
6290
6291 tg3_mdio_start(tp);
6292
6293 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6294
6295 err = tg3_poll_fw(tp);
6296 if (err)
6297 return err;
6298
6299 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6300 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6301 val = tr32(0x7c00);
6302
6303 tw32(0x7c00, val | (1 << 25));
6304 }
6305
6306 /* Reprobe ASF enable state. */
6307 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6308 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6309 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6310 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6311 u32 nic_cfg;
6312
6313 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6314 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6315 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6316 tp->last_event_jiffies = jiffies;
6317 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6318 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6319 }
6320 }
6321
6322 return 0;
6323 }
6324
6325 /* tp->lock is held. */
6326 static void tg3_stop_fw(struct tg3 *tp)
6327 {
6328 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6329 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6330 /* Wait for RX cpu to ACK the previous event. */
6331 tg3_wait_for_event_ack(tp);
6332
6333 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6334
6335 tg3_generate_fw_event(tp);
6336
6337 /* Wait for RX cpu to ACK this event. */
6338 tg3_wait_for_event_ack(tp);
6339 }
6340 }
6341
6342 /* tp->lock is held. */
6343 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6344 {
6345 int err;
6346
6347 tg3_stop_fw(tp);
6348
6349 tg3_write_sig_pre_reset(tp, kind);
6350
6351 tg3_abort_hw(tp, silent);
6352 err = tg3_chip_reset(tp);
6353
6354 __tg3_set_mac_addr(tp, 0);
6355
6356 tg3_write_sig_legacy(tp, kind);
6357 tg3_write_sig_post_reset(tp, kind);
6358
6359 if (err)
6360 return err;
6361
6362 return 0;
6363 }
6364
6365 #define RX_CPU_SCRATCH_BASE 0x30000
6366 #define RX_CPU_SCRATCH_SIZE 0x04000
6367 #define TX_CPU_SCRATCH_BASE 0x34000
6368 #define TX_CPU_SCRATCH_SIZE 0x04000
6369
6370 /* tp->lock is held. */
6371 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6372 {
6373 int i;
6374
6375 BUG_ON(offset == TX_CPU_BASE &&
6376 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6377
6378 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6379 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6380
6381 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6382 return 0;
6383 }
6384 if (offset == RX_CPU_BASE) {
6385 for (i = 0; i < 10000; i++) {
6386 tw32(offset + CPU_STATE, 0xffffffff);
6387 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6388 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6389 break;
6390 }
6391
6392 tw32(offset + CPU_STATE, 0xffffffff);
6393 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6394 udelay(10);
6395 } else {
6396 for (i = 0; i < 10000; i++) {
6397 tw32(offset + CPU_STATE, 0xffffffff);
6398 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6399 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6400 break;
6401 }
6402 }
6403
6404 if (i >= 10000) {
6405 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6406 "and %s CPU\n",
6407 tp->dev->name,
6408 (offset == RX_CPU_BASE ? "RX" : "TX"));
6409 return -ENODEV;
6410 }
6411
6412 /* Clear firmware's nvram arbitration. */
6413 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6414 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6415 return 0;
6416 }
6417
6418 struct fw_info {
6419 unsigned int fw_base;
6420 unsigned int fw_len;
6421 const __be32 *fw_data;
6422 };
6423
6424 /* tp->lock is held. */
6425 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6426 int cpu_scratch_size, struct fw_info *info)
6427 {
6428 int err, lock_err, i;
6429 void (*write_op)(struct tg3 *, u32, u32);
6430
6431 if (cpu_base == TX_CPU_BASE &&
6432 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6433 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6434 "TX cpu firmware on %s which is 5705.\n",
6435 tp->dev->name);
6436 return -EINVAL;
6437 }
6438
6439 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6440 write_op = tg3_write_mem;
6441 else
6442 write_op = tg3_write_indirect_reg32;
6443
6444 /* It is possible that bootcode is still loading at this point.
6445 * Get the nvram lock first before halting the cpu.
6446 */
6447 lock_err = tg3_nvram_lock(tp);
6448 err = tg3_halt_cpu(tp, cpu_base);
6449 if (!lock_err)
6450 tg3_nvram_unlock(tp);
6451 if (err)
6452 goto out;
6453
6454 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6455 write_op(tp, cpu_scratch_base + i, 0);
6456 tw32(cpu_base + CPU_STATE, 0xffffffff);
6457 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6458 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6459 write_op(tp, (cpu_scratch_base +
6460 (info->fw_base & 0xffff) +
6461 (i * sizeof(u32))),
6462 be32_to_cpu(info->fw_data[i]));
6463
6464 err = 0;
6465
6466 out:
6467 return err;
6468 }
6469
6470 /* tp->lock is held. */
6471 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6472 {
6473 struct fw_info info;
6474 const __be32 *fw_data;
6475 int err, i;
6476
6477 fw_data = (void *)tp->fw->data;
6478
6479 /* Firmware blob starts with version numbers, followed by
6480 start address and length. We are setting complete length.
6481 length = end_address_of_bss - start_address_of_text.
6482 Remainder is the blob to be loaded contiguously
6483 from start address. */
6484
6485 info.fw_base = be32_to_cpu(fw_data[1]);
6486 info.fw_len = tp->fw->size - 12;
6487 info.fw_data = &fw_data[3];
6488
6489 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6490 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6491 &info);
6492 if (err)
6493 return err;
6494
6495 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6496 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6497 &info);
6498 if (err)
6499 return err;
6500
6501 /* Now startup only the RX cpu. */
6502 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6503 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6504
6505 for (i = 0; i < 5; i++) {
6506 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6507 break;
6508 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6509 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6510 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6511 udelay(1000);
6512 }
6513 if (i >= 5) {
6514 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6515 "to set RX CPU PC, is %08x should be %08x\n",
6516 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6517 info.fw_base);
6518 return -ENODEV;
6519 }
6520 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6521 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6522
6523 return 0;
6524 }
6525
6526 /* 5705 needs a special version of the TSO firmware. */
6527
6528 /* tp->lock is held. */
6529 static int tg3_load_tso_firmware(struct tg3 *tp)
6530 {
6531 struct fw_info info;
6532 const __be32 *fw_data;
6533 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6534 int err, i;
6535
6536 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6537 return 0;
6538
6539 fw_data = (void *)tp->fw->data;
6540
6541 /* Firmware blob starts with version numbers, followed by
6542 start address and length. We are setting complete length.
6543 length = end_address_of_bss - start_address_of_text.
6544 Remainder is the blob to be loaded contiguously
6545 from start address. */
6546
6547 info.fw_base = be32_to_cpu(fw_data[1]);
6548 cpu_scratch_size = tp->fw_len;
6549 info.fw_len = tp->fw->size - 12;
6550 info.fw_data = &fw_data[3];
6551
6552 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6553 cpu_base = RX_CPU_BASE;
6554 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6555 } else {
6556 cpu_base = TX_CPU_BASE;
6557 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6558 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6559 }
6560
6561 err = tg3_load_firmware_cpu(tp, cpu_base,
6562 cpu_scratch_base, cpu_scratch_size,
6563 &info);
6564 if (err)
6565 return err;
6566
6567 /* Now startup the cpu. */
6568 tw32(cpu_base + CPU_STATE, 0xffffffff);
6569 tw32_f(cpu_base + CPU_PC, info.fw_base);
6570
6571 for (i = 0; i < 5; i++) {
6572 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6573 break;
6574 tw32(cpu_base + CPU_STATE, 0xffffffff);
6575 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6576 tw32_f(cpu_base + CPU_PC, info.fw_base);
6577 udelay(1000);
6578 }
6579 if (i >= 5) {
6580 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6581 "to set CPU PC, is %08x should be %08x\n",
6582 tp->dev->name, tr32(cpu_base + CPU_PC),
6583 info.fw_base);
6584 return -ENODEV;
6585 }
6586 tw32(cpu_base + CPU_STATE, 0xffffffff);
6587 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6588 return 0;
6589 }
6590
6591
6592 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6593 {
6594 struct tg3 *tp = netdev_priv(dev);
6595 struct sockaddr *addr = p;
6596 int err = 0, skip_mac_1 = 0;
6597
6598 if (!is_valid_ether_addr(addr->sa_data))
6599 return -EINVAL;
6600
6601 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6602
6603 if (!netif_running(dev))
6604 return 0;
6605
6606 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6607 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6608
6609 addr0_high = tr32(MAC_ADDR_0_HIGH);
6610 addr0_low = tr32(MAC_ADDR_0_LOW);
6611 addr1_high = tr32(MAC_ADDR_1_HIGH);
6612 addr1_low = tr32(MAC_ADDR_1_LOW);
6613
6614 /* Skip MAC addr 1 if ASF is using it. */
6615 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6616 !(addr1_high == 0 && addr1_low == 0))
6617 skip_mac_1 = 1;
6618 }
6619 spin_lock_bh(&tp->lock);
6620 __tg3_set_mac_addr(tp, skip_mac_1);
6621 spin_unlock_bh(&tp->lock);
6622
6623 return err;
6624 }
6625
6626 /* tp->lock is held. */
6627 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6628 dma_addr_t mapping, u32 maxlen_flags,
6629 u32 nic_addr)
6630 {
6631 tg3_write_mem(tp,
6632 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6633 ((u64) mapping >> 32));
6634 tg3_write_mem(tp,
6635 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6636 ((u64) mapping & 0xffffffff));
6637 tg3_write_mem(tp,
6638 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6639 maxlen_flags);
6640
6641 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6642 tg3_write_mem(tp,
6643 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6644 nic_addr);
6645 }
6646
6647 static void __tg3_set_rx_mode(struct net_device *);
6648 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6649 {
6650 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6651 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6652 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6653 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6654 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6655 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6656 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6657 }
6658 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6659 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6660 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6661 u32 val = ec->stats_block_coalesce_usecs;
6662
6663 if (!netif_carrier_ok(tp->dev))
6664 val = 0;
6665
6666 tw32(HOSTCC_STAT_COAL_TICKS, val);
6667 }
6668 }
6669
6670 /* tp->lock is held. */
6671 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6672 {
6673 u32 val, rdmac_mode;
6674 int i, err, limit;
6675
6676 tg3_disable_ints(tp);
6677
6678 tg3_stop_fw(tp);
6679
6680 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6681
6682 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6683 tg3_abort_hw(tp, 1);
6684 }
6685
6686 if (reset_phy &&
6687 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6688 tg3_phy_reset(tp);
6689
6690 err = tg3_chip_reset(tp);
6691 if (err)
6692 return err;
6693
6694 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6695
6696 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6697 val = tr32(TG3_CPMU_CTRL);
6698 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6699 tw32(TG3_CPMU_CTRL, val);
6700
6701 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6702 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6703 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6704 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6705
6706 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6707 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6708 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6709 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6710
6711 val = tr32(TG3_CPMU_HST_ACC);
6712 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6713 val |= CPMU_HST_ACC_MACCLK_6_25;
6714 tw32(TG3_CPMU_HST_ACC, val);
6715 }
6716
6717 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6718 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6719 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6720 PCIE_PWR_MGMT_L1_THRESH_4MS;
6721 tw32(PCIE_PWR_MGMT_THRESH, val);
6722 }
6723
6724 /* This works around an issue with Athlon chipsets on
6725 * B3 tigon3 silicon. This bit has no effect on any
6726 * other revision. But do not set this on PCI Express
6727 * chips and don't even touch the clocks if the CPMU is present.
6728 */
6729 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6730 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6731 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6732 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6733 }
6734
6735 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6736 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6737 val = tr32(TG3PCI_PCISTATE);
6738 val |= PCISTATE_RETRY_SAME_DMA;
6739 tw32(TG3PCI_PCISTATE, val);
6740 }
6741
6742 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6743 /* Allow reads and writes to the
6744 * APE register and memory space.
6745 */
6746 val = tr32(TG3PCI_PCISTATE);
6747 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6748 PCISTATE_ALLOW_APE_SHMEM_WR;
6749 tw32(TG3PCI_PCISTATE, val);
6750 }
6751
6752 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6753 /* Enable some hw fixes. */
6754 val = tr32(TG3PCI_MSI_DATA);
6755 val |= (1 << 26) | (1 << 28) | (1 << 29);
6756 tw32(TG3PCI_MSI_DATA, val);
6757 }
6758
6759 /* Descriptor ring init may make accesses to the
6760 * NIC SRAM area to setup the TX descriptors, so we
6761 * can only do this after the hardware has been
6762 * successfully reset.
6763 */
6764 err = tg3_init_rings(tp);
6765 if (err)
6766 return err;
6767
6768 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6769 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6770 /* This value is determined during the probe time DMA
6771 * engine test, tg3_test_dma.
6772 */
6773 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6774 }
6775
6776 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6777 GRC_MODE_4X_NIC_SEND_RINGS |
6778 GRC_MODE_NO_TX_PHDR_CSUM |
6779 GRC_MODE_NO_RX_PHDR_CSUM);
6780 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6781
6782 /* Pseudo-header checksum is done by hardware logic and not
6783 * the offload processers, so make the chip do the pseudo-
6784 * header checksums on receive. For transmit it is more
6785 * convenient to do the pseudo-header checksum in software
6786 * as Linux does that on transmit for us in all cases.
6787 */
6788 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6789
6790 tw32(GRC_MODE,
6791 tp->grc_mode |
6792 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6793
6794 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6795 val = tr32(GRC_MISC_CFG);
6796 val &= ~0xff;
6797 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6798 tw32(GRC_MISC_CFG, val);
6799
6800 /* Initialize MBUF/DESC pool. */
6801 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6802 /* Do nothing. */
6803 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6804 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6806 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6807 else
6808 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6809 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6810 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6811 }
6812 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6813 int fw_len;
6814
6815 fw_len = tp->fw_len;
6816 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6817 tw32(BUFMGR_MB_POOL_ADDR,
6818 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6819 tw32(BUFMGR_MB_POOL_SIZE,
6820 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6821 }
6822
6823 if (tp->dev->mtu <= ETH_DATA_LEN) {
6824 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6825 tp->bufmgr_config.mbuf_read_dma_low_water);
6826 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6827 tp->bufmgr_config.mbuf_mac_rx_low_water);
6828 tw32(BUFMGR_MB_HIGH_WATER,
6829 tp->bufmgr_config.mbuf_high_water);
6830 } else {
6831 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6832 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6833 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6834 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6835 tw32(BUFMGR_MB_HIGH_WATER,
6836 tp->bufmgr_config.mbuf_high_water_jumbo);
6837 }
6838 tw32(BUFMGR_DMA_LOW_WATER,
6839 tp->bufmgr_config.dma_low_water);
6840 tw32(BUFMGR_DMA_HIGH_WATER,
6841 tp->bufmgr_config.dma_high_water);
6842
6843 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6844 for (i = 0; i < 2000; i++) {
6845 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6846 break;
6847 udelay(10);
6848 }
6849 if (i >= 2000) {
6850 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6851 tp->dev->name);
6852 return -ENODEV;
6853 }
6854
6855 /* Setup replenish threshold. */
6856 val = tp->rx_pending / 8;
6857 if (val == 0)
6858 val = 1;
6859 else if (val > tp->rx_std_max_post)
6860 val = tp->rx_std_max_post;
6861 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6862 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6863 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6864
6865 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6866 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6867 }
6868
6869 tw32(RCVBDI_STD_THRESH, val);
6870
6871 /* Initialize TG3_BDINFO's at:
6872 * RCVDBDI_STD_BD: standard eth size rx ring
6873 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6874 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6875 *
6876 * like so:
6877 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6878 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6879 * ring attribute flags
6880 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6881 *
6882 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6883 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6884 *
6885 * The size of each ring is fixed in the firmware, but the location is
6886 * configurable.
6887 */
6888 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6889 ((u64) tp->rx_std_mapping >> 32));
6890 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6891 ((u64) tp->rx_std_mapping & 0xffffffff));
6892 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6893 NIC_SRAM_RX_BUFFER_DESC);
6894
6895 /* Don't even try to program the JUMBO/MINI buffer descriptor
6896 * configs on 5705.
6897 */
6898 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6899 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6900 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6901 } else {
6902 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6903 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6904
6905 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6906 BDINFO_FLAGS_DISABLED);
6907
6908 /* Setup replenish threshold. */
6909 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6910
6911 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6912 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6913 ((u64) tp->rx_jumbo_mapping >> 32));
6914 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6915 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6916 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6917 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6918 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6919 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6920 } else {
6921 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6922 BDINFO_FLAGS_DISABLED);
6923 }
6924
6925 }
6926
6927 /* There is only one send ring on 5705/5750, no need to explicitly
6928 * disable the others.
6929 */
6930 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6931 /* Clear out send RCB ring in SRAM. */
6932 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6933 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6934 BDINFO_FLAGS_DISABLED);
6935 }
6936
6937 tp->tx_prod = 0;
6938 tp->tx_cons = 0;
6939 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6940 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6941
6942 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6943 tp->tx_desc_mapping,
6944 (TG3_TX_RING_SIZE <<
6945 BDINFO_FLAGS_MAXLEN_SHIFT),
6946 NIC_SRAM_TX_BUFFER_DESC);
6947
6948 /* There is only one receive return ring on 5705/5750, no need
6949 * to explicitly disable the others.
6950 */
6951 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6952 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6953 i += TG3_BDINFO_SIZE) {
6954 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6955 BDINFO_FLAGS_DISABLED);
6956 }
6957 }
6958
6959 tp->rx_rcb_ptr = 0;
6960 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6961
6962 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6963 tp->rx_rcb_mapping,
6964 (TG3_RX_RCB_RING_SIZE(tp) <<
6965 BDINFO_FLAGS_MAXLEN_SHIFT),
6966 0);
6967
6968 tp->rx_std_ptr = tp->rx_pending;
6969 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6970 tp->rx_std_ptr);
6971
6972 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6973 tp->rx_jumbo_pending : 0;
6974 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6975 tp->rx_jumbo_ptr);
6976
6977 /* Initialize MAC address and backoff seed. */
6978 __tg3_set_mac_addr(tp, 0);
6979
6980 /* MTU + ethernet header + FCS + optional VLAN tag */
6981 tw32(MAC_RX_MTU_SIZE,
6982 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
6983
6984 /* The slot time is changed by tg3_setup_phy if we
6985 * run at gigabit with half duplex.
6986 */
6987 tw32(MAC_TX_LENGTHS,
6988 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6989 (6 << TX_LENGTHS_IPG_SHIFT) |
6990 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6991
6992 /* Receive rules. */
6993 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6994 tw32(RCVLPC_CONFIG, 0x0181);
6995
6996 /* Calculate RDMAC_MODE setting early, we need it to determine
6997 * the RCVLPC_STATE_ENABLE mask.
6998 */
6999 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7000 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7001 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7002 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7003 RDMAC_MODE_LNGREAD_ENAB);
7004
7005 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7006 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7007 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7008 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7009 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7010 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7011
7012 /* If statement applies to 5705 and 5750 PCI devices only */
7013 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7014 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7015 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7016 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7017 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7018 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7019 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7020 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7021 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7022 }
7023 }
7024
7025 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7026 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7027
7028 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7029 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7030
7031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7032 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7033 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7034
7035 /* Receive/send statistics. */
7036 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7037 val = tr32(RCVLPC_STATS_ENABLE);
7038 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7039 tw32(RCVLPC_STATS_ENABLE, val);
7040 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7041 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7042 val = tr32(RCVLPC_STATS_ENABLE);
7043 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7044 tw32(RCVLPC_STATS_ENABLE, val);
7045 } else {
7046 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7047 }
7048 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7049 tw32(SNDDATAI_STATSENAB, 0xffffff);
7050 tw32(SNDDATAI_STATSCTRL,
7051 (SNDDATAI_SCTRL_ENABLE |
7052 SNDDATAI_SCTRL_FASTUPD));
7053
7054 /* Setup host coalescing engine. */
7055 tw32(HOSTCC_MODE, 0);
7056 for (i = 0; i < 2000; i++) {
7057 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7058 break;
7059 udelay(10);
7060 }
7061
7062 __tg3_set_coalesce(tp, &tp->coal);
7063
7064 /* set status block DMA address */
7065 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7066 ((u64) tp->status_mapping >> 32));
7067 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7068 ((u64) tp->status_mapping & 0xffffffff));
7069
7070 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7071 /* Status/statistics block address. See tg3_timer,
7072 * the tg3_periodic_fetch_stats call there, and
7073 * tg3_get_stats to see how this works for 5705/5750 chips.
7074 */
7075 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7076 ((u64) tp->stats_mapping >> 32));
7077 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7078 ((u64) tp->stats_mapping & 0xffffffff));
7079 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7080 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7081 }
7082
7083 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7084
7085 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7086 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7087 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7088 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7089
7090 /* Clear statistics/status block in chip, and status block in ram. */
7091 for (i = NIC_SRAM_STATS_BLK;
7092 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7093 i += sizeof(u32)) {
7094 tg3_write_mem(tp, i, 0);
7095 udelay(40);
7096 }
7097 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7098
7099 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7100 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7101 /* reset to prevent losing 1st rx packet intermittently */
7102 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7103 udelay(10);
7104 }
7105
7106 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7107 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7108 else
7109 tp->mac_mode = 0;
7110 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7111 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7112 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7113 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7114 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7115 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7116 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7117 udelay(40);
7118
7119 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7120 * If TG3_FLG2_IS_NIC is zero, we should read the
7121 * register to preserve the GPIO settings for LOMs. The GPIOs,
7122 * whether used as inputs or outputs, are set by boot code after
7123 * reset.
7124 */
7125 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7126 u32 gpio_mask;
7127
7128 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7129 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7130 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7131
7132 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7133 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7134 GRC_LCLCTRL_GPIO_OUTPUT3;
7135
7136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7137 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7138
7139 tp->grc_local_ctrl &= ~gpio_mask;
7140 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7141
7142 /* GPIO1 must be driven high for eeprom write protect */
7143 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7144 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7145 GRC_LCLCTRL_GPIO_OUTPUT1);
7146 }
7147 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7148 udelay(100);
7149
7150 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7151
7152 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7153 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7154 udelay(40);
7155 }
7156
7157 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7158 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7159 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7160 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7161 WDMAC_MODE_LNGREAD_ENAB);
7162
7163 /* If statement applies to 5705 and 5750 PCI devices only */
7164 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7165 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7166 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7167 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7168 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7169 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7170 /* nothing */
7171 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7172 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7173 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7174 val |= WDMAC_MODE_RX_ACCEL;
7175 }
7176 }
7177
7178 /* Enable host coalescing bug fix */
7179 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7180 val |= WDMAC_MODE_STATUS_TAG_FIX;
7181
7182 tw32_f(WDMAC_MODE, val);
7183 udelay(40);
7184
7185 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7186 u16 pcix_cmd;
7187
7188 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7189 &pcix_cmd);
7190 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7191 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7192 pcix_cmd |= PCI_X_CMD_READ_2K;
7193 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7194 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7195 pcix_cmd |= PCI_X_CMD_READ_2K;
7196 }
7197 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7198 pcix_cmd);
7199 }
7200
7201 tw32_f(RDMAC_MODE, rdmac_mode);
7202 udelay(40);
7203
7204 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7205 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7206 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7207
7208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7209 tw32(SNDDATAC_MODE,
7210 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7211 else
7212 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7213
7214 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7215 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7216 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7217 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7218 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7219 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7220 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7221 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7222
7223 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7224 err = tg3_load_5701_a0_firmware_fix(tp);
7225 if (err)
7226 return err;
7227 }
7228
7229 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7230 err = tg3_load_tso_firmware(tp);
7231 if (err)
7232 return err;
7233 }
7234
7235 tp->tx_mode = TX_MODE_ENABLE;
7236 tw32_f(MAC_TX_MODE, tp->tx_mode);
7237 udelay(100);
7238
7239 tp->rx_mode = RX_MODE_ENABLE;
7240 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7241 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7242
7243 tw32_f(MAC_RX_MODE, tp->rx_mode);
7244 udelay(10);
7245
7246 tw32(MAC_LED_CTRL, tp->led_ctrl);
7247
7248 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7249 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7250 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7251 udelay(10);
7252 }
7253 tw32_f(MAC_RX_MODE, tp->rx_mode);
7254 udelay(10);
7255
7256 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7257 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7258 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7259 /* Set drive transmission level to 1.2V */
7260 /* only if the signal pre-emphasis bit is not set */
7261 val = tr32(MAC_SERDES_CFG);
7262 val &= 0xfffff000;
7263 val |= 0x880;
7264 tw32(MAC_SERDES_CFG, val);
7265 }
7266 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7267 tw32(MAC_SERDES_CFG, 0x616000);
7268 }
7269
7270 /* Prevent chip from dropping frames when flow control
7271 * is enabled.
7272 */
7273 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7274
7275 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7276 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7277 /* Use hardware link auto-negotiation */
7278 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7279 }
7280
7281 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7282 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7283 u32 tmp;
7284
7285 tmp = tr32(SERDES_RX_CTRL);
7286 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7287 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7288 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7289 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7290 }
7291
7292 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7293 if (tp->link_config.phy_is_low_power) {
7294 tp->link_config.phy_is_low_power = 0;
7295 tp->link_config.speed = tp->link_config.orig_speed;
7296 tp->link_config.duplex = tp->link_config.orig_duplex;
7297 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7298 }
7299
7300 err = tg3_setup_phy(tp, 0);
7301 if (err)
7302 return err;
7303
7304 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7305 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7306 u32 tmp;
7307
7308 /* Clear CRC stats. */
7309 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7310 tg3_writephy(tp, MII_TG3_TEST1,
7311 tmp | MII_TG3_TEST1_CRC_EN);
7312 tg3_readphy(tp, 0x14, &tmp);
7313 }
7314 }
7315 }
7316
7317 __tg3_set_rx_mode(tp->dev);
7318
7319 /* Initialize receive rules. */
7320 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7321 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7322 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7323 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7324
7325 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7326 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7327 limit = 8;
7328 else
7329 limit = 16;
7330 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7331 limit -= 4;
7332 switch (limit) {
7333 case 16:
7334 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7335 case 15:
7336 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7337 case 14:
7338 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7339 case 13:
7340 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7341 case 12:
7342 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7343 case 11:
7344 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7345 case 10:
7346 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7347 case 9:
7348 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7349 case 8:
7350 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7351 case 7:
7352 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7353 case 6:
7354 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7355 case 5:
7356 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7357 case 4:
7358 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7359 case 3:
7360 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7361 case 2:
7362 case 1:
7363
7364 default:
7365 break;
7366 }
7367
7368 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7369 /* Write our heartbeat update interval to APE. */
7370 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7371 APE_HOST_HEARTBEAT_INT_DISABLE);
7372
7373 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7374
7375 return 0;
7376 }
7377
7378 /* Called at device open time to get the chip ready for
7379 * packet processing. Invoked with tp->lock held.
7380 */
7381 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7382 {
7383 tg3_switch_clocks(tp);
7384
7385 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7386
7387 return tg3_reset_hw(tp, reset_phy);
7388 }
7389
7390 #define TG3_STAT_ADD32(PSTAT, REG) \
7391 do { u32 __val = tr32(REG); \
7392 (PSTAT)->low += __val; \
7393 if ((PSTAT)->low < __val) \
7394 (PSTAT)->high += 1; \
7395 } while (0)
7396
7397 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7398 {
7399 struct tg3_hw_stats *sp = tp->hw_stats;
7400
7401 if (!netif_carrier_ok(tp->dev))
7402 return;
7403
7404 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7405 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7406 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7407 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7408 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7409 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7410 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7411 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7412 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7413 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7414 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7415 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7416 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7417
7418 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7419 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7420 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7421 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7422 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7423 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7424 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7425 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7426 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7427 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7428 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7429 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7430 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7431 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7432
7433 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7434 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7435 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7436 }
7437
7438 static void tg3_timer(unsigned long __opaque)
7439 {
7440 struct tg3 *tp = (struct tg3 *) __opaque;
7441
7442 if (tp->irq_sync)
7443 goto restart_timer;
7444
7445 spin_lock(&tp->lock);
7446
7447 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7448 /* All of this garbage is because when using non-tagged
7449 * IRQ status the mailbox/status_block protocol the chip
7450 * uses with the cpu is race prone.
7451 */
7452 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7453 tw32(GRC_LOCAL_CTRL,
7454 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7455 } else {
7456 tw32(HOSTCC_MODE, tp->coalesce_mode |
7457 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7458 }
7459
7460 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7461 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7462 spin_unlock(&tp->lock);
7463 schedule_work(&tp->reset_task);
7464 return;
7465 }
7466 }
7467
7468 /* This part only runs once per second. */
7469 if (!--tp->timer_counter) {
7470 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7471 tg3_periodic_fetch_stats(tp);
7472
7473 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7474 u32 mac_stat;
7475 int phy_event;
7476
7477 mac_stat = tr32(MAC_STATUS);
7478
7479 phy_event = 0;
7480 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7481 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7482 phy_event = 1;
7483 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7484 phy_event = 1;
7485
7486 if (phy_event)
7487 tg3_setup_phy(tp, 0);
7488 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7489 u32 mac_stat = tr32(MAC_STATUS);
7490 int need_setup = 0;
7491
7492 if (netif_carrier_ok(tp->dev) &&
7493 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7494 need_setup = 1;
7495 }
7496 if (! netif_carrier_ok(tp->dev) &&
7497 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7498 MAC_STATUS_SIGNAL_DET))) {
7499 need_setup = 1;
7500 }
7501 if (need_setup) {
7502 if (!tp->serdes_counter) {
7503 tw32_f(MAC_MODE,
7504 (tp->mac_mode &
7505 ~MAC_MODE_PORT_MODE_MASK));
7506 udelay(40);
7507 tw32_f(MAC_MODE, tp->mac_mode);
7508 udelay(40);
7509 }
7510 tg3_setup_phy(tp, 0);
7511 }
7512 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7513 tg3_serdes_parallel_detect(tp);
7514
7515 tp->timer_counter = tp->timer_multiplier;
7516 }
7517
7518 /* Heartbeat is only sent once every 2 seconds.
7519 *
7520 * The heartbeat is to tell the ASF firmware that the host
7521 * driver is still alive. In the event that the OS crashes,
7522 * ASF needs to reset the hardware to free up the FIFO space
7523 * that may be filled with rx packets destined for the host.
7524 * If the FIFO is full, ASF will no longer function properly.
7525 *
7526 * Unintended resets have been reported on real time kernels
7527 * where the timer doesn't run on time. Netpoll will also have
7528 * same problem.
7529 *
7530 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7531 * to check the ring condition when the heartbeat is expiring
7532 * before doing the reset. This will prevent most unintended
7533 * resets.
7534 */
7535 if (!--tp->asf_counter) {
7536 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7537 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7538 tg3_wait_for_event_ack(tp);
7539
7540 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7541 FWCMD_NICDRV_ALIVE3);
7542 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7543 /* 5 seconds timeout */
7544 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7545
7546 tg3_generate_fw_event(tp);
7547 }
7548 tp->asf_counter = tp->asf_multiplier;
7549 }
7550
7551 spin_unlock(&tp->lock);
7552
7553 restart_timer:
7554 tp->timer.expires = jiffies + tp->timer_offset;
7555 add_timer(&tp->timer);
7556 }
7557
7558 static int tg3_request_irq(struct tg3 *tp)
7559 {
7560 irq_handler_t fn;
7561 unsigned long flags;
7562 struct net_device *dev = tp->dev;
7563
7564 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7565 fn = tg3_msi;
7566 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7567 fn = tg3_msi_1shot;
7568 flags = IRQF_SAMPLE_RANDOM;
7569 } else {
7570 fn = tg3_interrupt;
7571 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7572 fn = tg3_interrupt_tagged;
7573 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7574 }
7575 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7576 }
7577
7578 static int tg3_test_interrupt(struct tg3 *tp)
7579 {
7580 struct net_device *dev = tp->dev;
7581 int err, i, intr_ok = 0;
7582
7583 if (!netif_running(dev))
7584 return -ENODEV;
7585
7586 tg3_disable_ints(tp);
7587
7588 free_irq(tp->pdev->irq, dev);
7589
7590 err = request_irq(tp->pdev->irq, tg3_test_isr,
7591 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7592 if (err)
7593 return err;
7594
7595 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7596 tg3_enable_ints(tp);
7597
7598 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7599 HOSTCC_MODE_NOW);
7600
7601 for (i = 0; i < 5; i++) {
7602 u32 int_mbox, misc_host_ctrl;
7603
7604 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7605 TG3_64BIT_REG_LOW);
7606 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7607
7608 if ((int_mbox != 0) ||
7609 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7610 intr_ok = 1;
7611 break;
7612 }
7613
7614 msleep(10);
7615 }
7616
7617 tg3_disable_ints(tp);
7618
7619 free_irq(tp->pdev->irq, dev);
7620
7621 err = tg3_request_irq(tp);
7622
7623 if (err)
7624 return err;
7625
7626 if (intr_ok)
7627 return 0;
7628
7629 return -EIO;
7630 }
7631
7632 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7633 * successfully restored
7634 */
7635 static int tg3_test_msi(struct tg3 *tp)
7636 {
7637 struct net_device *dev = tp->dev;
7638 int err;
7639 u16 pci_cmd;
7640
7641 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7642 return 0;
7643
7644 /* Turn off SERR reporting in case MSI terminates with Master
7645 * Abort.
7646 */
7647 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7648 pci_write_config_word(tp->pdev, PCI_COMMAND,
7649 pci_cmd & ~PCI_COMMAND_SERR);
7650
7651 err = tg3_test_interrupt(tp);
7652
7653 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7654
7655 if (!err)
7656 return 0;
7657
7658 /* other failures */
7659 if (err != -EIO)
7660 return err;
7661
7662 /* MSI test failed, go back to INTx mode */
7663 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7664 "switching to INTx mode. Please report this failure to "
7665 "the PCI maintainer and include system chipset information.\n",
7666 tp->dev->name);
7667
7668 free_irq(tp->pdev->irq, dev);
7669 pci_disable_msi(tp->pdev);
7670
7671 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7672
7673 err = tg3_request_irq(tp);
7674 if (err)
7675 return err;
7676
7677 /* Need to reset the chip because the MSI cycle may have terminated
7678 * with Master Abort.
7679 */
7680 tg3_full_lock(tp, 1);
7681
7682 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7683 err = tg3_init_hw(tp, 1);
7684
7685 tg3_full_unlock(tp);
7686
7687 if (err)
7688 free_irq(tp->pdev->irq, dev);
7689
7690 return err;
7691 }
7692
7693 static int tg3_request_firmware(struct tg3 *tp)
7694 {
7695 const __be32 *fw_data;
7696
7697 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
7698 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
7699 tp->dev->name, tp->fw_needed);
7700 return -ENOENT;
7701 }
7702
7703 fw_data = (void *)tp->fw->data;
7704
7705 /* Firmware blob starts with version numbers, followed by
7706 * start address and _full_ length including BSS sections
7707 * (which must be longer than the actual data, of course
7708 */
7709
7710 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
7711 if (tp->fw_len < (tp->fw->size - 12)) {
7712 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
7713 tp->dev->name, tp->fw_len, tp->fw_needed);
7714 release_firmware(tp->fw);
7715 tp->fw = NULL;
7716 return -EINVAL;
7717 }
7718
7719 /* We no longer need firmware; we have it. */
7720 tp->fw_needed = NULL;
7721 return 0;
7722 }
7723
7724 static int tg3_open(struct net_device *dev)
7725 {
7726 struct tg3 *tp = netdev_priv(dev);
7727 int err;
7728
7729 if (tp->fw_needed) {
7730 err = tg3_request_firmware(tp);
7731 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7732 if (err)
7733 return err;
7734 } else if (err) {
7735 printk(KERN_WARNING "%s: TSO capability disabled.\n",
7736 tp->dev->name);
7737 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
7738 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7739 printk(KERN_NOTICE "%s: TSO capability restored.\n",
7740 tp->dev->name);
7741 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
7742 }
7743 }
7744
7745 netif_carrier_off(tp->dev);
7746
7747 err = tg3_set_power_state(tp, PCI_D0);
7748 if (err)
7749 return err;
7750
7751 tg3_full_lock(tp, 0);
7752
7753 tg3_disable_ints(tp);
7754 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7755
7756 tg3_full_unlock(tp);
7757
7758 /* The placement of this call is tied
7759 * to the setup and use of Host TX descriptors.
7760 */
7761 err = tg3_alloc_consistent(tp);
7762 if (err)
7763 return err;
7764
7765 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7766 /* All MSI supporting chips should support tagged
7767 * status. Assert that this is the case.
7768 */
7769 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7770 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7771 "Not using MSI.\n", tp->dev->name);
7772 } else if (pci_enable_msi(tp->pdev) == 0) {
7773 u32 msi_mode;
7774
7775 msi_mode = tr32(MSGINT_MODE);
7776 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7777 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7778 }
7779 }
7780 err = tg3_request_irq(tp);
7781
7782 if (err) {
7783 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7784 pci_disable_msi(tp->pdev);
7785 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7786 }
7787 tg3_free_consistent(tp);
7788 return err;
7789 }
7790
7791 napi_enable(&tp->napi);
7792
7793 tg3_full_lock(tp, 0);
7794
7795 err = tg3_init_hw(tp, 1);
7796 if (err) {
7797 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7798 tg3_free_rings(tp);
7799 } else {
7800 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7801 tp->timer_offset = HZ;
7802 else
7803 tp->timer_offset = HZ / 10;
7804
7805 BUG_ON(tp->timer_offset > HZ);
7806 tp->timer_counter = tp->timer_multiplier =
7807 (HZ / tp->timer_offset);
7808 tp->asf_counter = tp->asf_multiplier =
7809 ((HZ / tp->timer_offset) * 2);
7810
7811 init_timer(&tp->timer);
7812 tp->timer.expires = jiffies + tp->timer_offset;
7813 tp->timer.data = (unsigned long) tp;
7814 tp->timer.function = tg3_timer;
7815 }
7816
7817 tg3_full_unlock(tp);
7818
7819 if (err) {
7820 napi_disable(&tp->napi);
7821 free_irq(tp->pdev->irq, dev);
7822 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7823 pci_disable_msi(tp->pdev);
7824 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7825 }
7826 tg3_free_consistent(tp);
7827 return err;
7828 }
7829
7830 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7831 err = tg3_test_msi(tp);
7832
7833 if (err) {
7834 tg3_full_lock(tp, 0);
7835
7836 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7837 pci_disable_msi(tp->pdev);
7838 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7839 }
7840 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7841 tg3_free_rings(tp);
7842 tg3_free_consistent(tp);
7843
7844 tg3_full_unlock(tp);
7845
7846 napi_disable(&tp->napi);
7847
7848 return err;
7849 }
7850
7851 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7852 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7853 u32 val = tr32(PCIE_TRANSACTION_CFG);
7854
7855 tw32(PCIE_TRANSACTION_CFG,
7856 val | PCIE_TRANS_CFG_1SHOT_MSI);
7857 }
7858 }
7859 }
7860
7861 tg3_phy_start(tp);
7862
7863 tg3_full_lock(tp, 0);
7864
7865 add_timer(&tp->timer);
7866 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7867 tg3_enable_ints(tp);
7868
7869 tg3_full_unlock(tp);
7870
7871 netif_start_queue(dev);
7872
7873 return 0;
7874 }
7875
7876 #if 0
7877 /*static*/ void tg3_dump_state(struct tg3 *tp)
7878 {
7879 u32 val32, val32_2, val32_3, val32_4, val32_5;
7880 u16 val16;
7881 int i;
7882
7883 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7884 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7885 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7886 val16, val32);
7887
7888 /* MAC block */
7889 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7890 tr32(MAC_MODE), tr32(MAC_STATUS));
7891 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7892 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7893 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7894 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7895 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7896 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7897
7898 /* Send data initiator control block */
7899 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7900 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7901 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7902 tr32(SNDDATAI_STATSCTRL));
7903
7904 /* Send data completion control block */
7905 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7906
7907 /* Send BD ring selector block */
7908 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7909 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7910
7911 /* Send BD initiator control block */
7912 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7913 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7914
7915 /* Send BD completion control block */
7916 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7917
7918 /* Receive list placement control block */
7919 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7920 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7921 printk(" RCVLPC_STATSCTRL[%08x]\n",
7922 tr32(RCVLPC_STATSCTRL));
7923
7924 /* Receive data and receive BD initiator control block */
7925 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7926 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7927
7928 /* Receive data completion control block */
7929 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7930 tr32(RCVDCC_MODE));
7931
7932 /* Receive BD initiator control block */
7933 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7934 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7935
7936 /* Receive BD completion control block */
7937 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7938 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7939
7940 /* Receive list selector control block */
7941 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7942 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7943
7944 /* Mbuf cluster free block */
7945 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7946 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7947
7948 /* Host coalescing control block */
7949 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7950 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7951 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7952 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7953 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7954 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7955 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7956 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7957 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7958 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7959 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7960 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7961
7962 /* Memory arbiter control block */
7963 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7964 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7965
7966 /* Buffer manager control block */
7967 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7968 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7969 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7970 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7971 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7972 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7973 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7974 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7975
7976 /* Read DMA control block */
7977 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7978 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7979
7980 /* Write DMA control block */
7981 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7982 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7983
7984 /* DMA completion block */
7985 printk("DEBUG: DMAC_MODE[%08x]\n",
7986 tr32(DMAC_MODE));
7987
7988 /* GRC block */
7989 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7990 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7991 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7992 tr32(GRC_LOCAL_CTRL));
7993
7994 /* TG3_BDINFOs */
7995 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7996 tr32(RCVDBDI_JUMBO_BD + 0x0),
7997 tr32(RCVDBDI_JUMBO_BD + 0x4),
7998 tr32(RCVDBDI_JUMBO_BD + 0x8),
7999 tr32(RCVDBDI_JUMBO_BD + 0xc));
8000 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8001 tr32(RCVDBDI_STD_BD + 0x0),
8002 tr32(RCVDBDI_STD_BD + 0x4),
8003 tr32(RCVDBDI_STD_BD + 0x8),
8004 tr32(RCVDBDI_STD_BD + 0xc));
8005 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8006 tr32(RCVDBDI_MINI_BD + 0x0),
8007 tr32(RCVDBDI_MINI_BD + 0x4),
8008 tr32(RCVDBDI_MINI_BD + 0x8),
8009 tr32(RCVDBDI_MINI_BD + 0xc));
8010
8011 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8012 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8013 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8014 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8015 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8016 val32, val32_2, val32_3, val32_4);
8017
8018 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8019 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8020 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8021 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8022 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8023 val32, val32_2, val32_3, val32_4);
8024
8025 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8026 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8027 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8028 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8029 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8030 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8031 val32, val32_2, val32_3, val32_4, val32_5);
8032
8033 /* SW status block */
8034 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8035 tp->hw_status->status,
8036 tp->hw_status->status_tag,
8037 tp->hw_status->rx_jumbo_consumer,
8038 tp->hw_status->rx_consumer,
8039 tp->hw_status->rx_mini_consumer,
8040 tp->hw_status->idx[0].rx_producer,
8041 tp->hw_status->idx[0].tx_consumer);
8042
8043 /* SW statistics block */
8044 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8045 ((u32 *)tp->hw_stats)[0],
8046 ((u32 *)tp->hw_stats)[1],
8047 ((u32 *)tp->hw_stats)[2],
8048 ((u32 *)tp->hw_stats)[3]);
8049
8050 /* Mailboxes */
8051 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8052 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8053 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8054 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8055 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8056
8057 /* NIC side send descriptors. */
8058 for (i = 0; i < 6; i++) {
8059 unsigned long txd;
8060
8061 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8062 + (i * sizeof(struct tg3_tx_buffer_desc));
8063 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8064 i,
8065 readl(txd + 0x0), readl(txd + 0x4),
8066 readl(txd + 0x8), readl(txd + 0xc));
8067 }
8068
8069 /* NIC side RX descriptors. */
8070 for (i = 0; i < 6; i++) {
8071 unsigned long rxd;
8072
8073 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8074 + (i * sizeof(struct tg3_rx_buffer_desc));
8075 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8076 i,
8077 readl(rxd + 0x0), readl(rxd + 0x4),
8078 readl(rxd + 0x8), readl(rxd + 0xc));
8079 rxd += (4 * sizeof(u32));
8080 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8081 i,
8082 readl(rxd + 0x0), readl(rxd + 0x4),
8083 readl(rxd + 0x8), readl(rxd + 0xc));
8084 }
8085
8086 for (i = 0; i < 6; i++) {
8087 unsigned long rxd;
8088
8089 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8090 + (i * sizeof(struct tg3_rx_buffer_desc));
8091 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8092 i,
8093 readl(rxd + 0x0), readl(rxd + 0x4),
8094 readl(rxd + 0x8), readl(rxd + 0xc));
8095 rxd += (4 * sizeof(u32));
8096 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8097 i,
8098 readl(rxd + 0x0), readl(rxd + 0x4),
8099 readl(rxd + 0x8), readl(rxd + 0xc));
8100 }
8101 }
8102 #endif
8103
8104 static struct net_device_stats *tg3_get_stats(struct net_device *);
8105 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8106
8107 static int tg3_close(struct net_device *dev)
8108 {
8109 struct tg3 *tp = netdev_priv(dev);
8110
8111 napi_disable(&tp->napi);
8112 cancel_work_sync(&tp->reset_task);
8113
8114 netif_stop_queue(dev);
8115
8116 del_timer_sync(&tp->timer);
8117
8118 tg3_full_lock(tp, 1);
8119 #if 0
8120 tg3_dump_state(tp);
8121 #endif
8122
8123 tg3_disable_ints(tp);
8124
8125 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8126 tg3_free_rings(tp);
8127 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8128
8129 tg3_full_unlock(tp);
8130
8131 free_irq(tp->pdev->irq, dev);
8132 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8133 pci_disable_msi(tp->pdev);
8134 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8135 }
8136
8137 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8138 sizeof(tp->net_stats_prev));
8139 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8140 sizeof(tp->estats_prev));
8141
8142 tg3_free_consistent(tp);
8143
8144 tg3_set_power_state(tp, PCI_D3hot);
8145
8146 netif_carrier_off(tp->dev);
8147
8148 return 0;
8149 }
8150
8151 static inline unsigned long get_stat64(tg3_stat64_t *val)
8152 {
8153 unsigned long ret;
8154
8155 #if (BITS_PER_LONG == 32)
8156 ret = val->low;
8157 #else
8158 ret = ((u64)val->high << 32) | ((u64)val->low);
8159 #endif
8160 return ret;
8161 }
8162
8163 static inline u64 get_estat64(tg3_stat64_t *val)
8164 {
8165 return ((u64)val->high << 32) | ((u64)val->low);
8166 }
8167
8168 static unsigned long calc_crc_errors(struct tg3 *tp)
8169 {
8170 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8171
8172 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8173 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8174 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8175 u32 val;
8176
8177 spin_lock_bh(&tp->lock);
8178 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8179 tg3_writephy(tp, MII_TG3_TEST1,
8180 val | MII_TG3_TEST1_CRC_EN);
8181 tg3_readphy(tp, 0x14, &val);
8182 } else
8183 val = 0;
8184 spin_unlock_bh(&tp->lock);
8185
8186 tp->phy_crc_errors += val;
8187
8188 return tp->phy_crc_errors;
8189 }
8190
8191 return get_stat64(&hw_stats->rx_fcs_errors);
8192 }
8193
8194 #define ESTAT_ADD(member) \
8195 estats->member = old_estats->member + \
8196 get_estat64(&hw_stats->member)
8197
8198 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8199 {
8200 struct tg3_ethtool_stats *estats = &tp->estats;
8201 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8202 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8203
8204 if (!hw_stats)
8205 return old_estats;
8206
8207 ESTAT_ADD(rx_octets);
8208 ESTAT_ADD(rx_fragments);
8209 ESTAT_ADD(rx_ucast_packets);
8210 ESTAT_ADD(rx_mcast_packets);
8211 ESTAT_ADD(rx_bcast_packets);
8212 ESTAT_ADD(rx_fcs_errors);
8213 ESTAT_ADD(rx_align_errors);
8214 ESTAT_ADD(rx_xon_pause_rcvd);
8215 ESTAT_ADD(rx_xoff_pause_rcvd);
8216 ESTAT_ADD(rx_mac_ctrl_rcvd);
8217 ESTAT_ADD(rx_xoff_entered);
8218 ESTAT_ADD(rx_frame_too_long_errors);
8219 ESTAT_ADD(rx_jabbers);
8220 ESTAT_ADD(rx_undersize_packets);
8221 ESTAT_ADD(rx_in_length_errors);
8222 ESTAT_ADD(rx_out_length_errors);
8223 ESTAT_ADD(rx_64_or_less_octet_packets);
8224 ESTAT_ADD(rx_65_to_127_octet_packets);
8225 ESTAT_ADD(rx_128_to_255_octet_packets);
8226 ESTAT_ADD(rx_256_to_511_octet_packets);
8227 ESTAT_ADD(rx_512_to_1023_octet_packets);
8228 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8229 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8230 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8231 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8232 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8233
8234 ESTAT_ADD(tx_octets);
8235 ESTAT_ADD(tx_collisions);
8236 ESTAT_ADD(tx_xon_sent);
8237 ESTAT_ADD(tx_xoff_sent);
8238 ESTAT_ADD(tx_flow_control);
8239 ESTAT_ADD(tx_mac_errors);
8240 ESTAT_ADD(tx_single_collisions);
8241 ESTAT_ADD(tx_mult_collisions);
8242 ESTAT_ADD(tx_deferred);
8243 ESTAT_ADD(tx_excessive_collisions);
8244 ESTAT_ADD(tx_late_collisions);
8245 ESTAT_ADD(tx_collide_2times);
8246 ESTAT_ADD(tx_collide_3times);
8247 ESTAT_ADD(tx_collide_4times);
8248 ESTAT_ADD(tx_collide_5times);
8249 ESTAT_ADD(tx_collide_6times);
8250 ESTAT_ADD(tx_collide_7times);
8251 ESTAT_ADD(tx_collide_8times);
8252 ESTAT_ADD(tx_collide_9times);
8253 ESTAT_ADD(tx_collide_10times);
8254 ESTAT_ADD(tx_collide_11times);
8255 ESTAT_ADD(tx_collide_12times);
8256 ESTAT_ADD(tx_collide_13times);
8257 ESTAT_ADD(tx_collide_14times);
8258 ESTAT_ADD(tx_collide_15times);
8259 ESTAT_ADD(tx_ucast_packets);
8260 ESTAT_ADD(tx_mcast_packets);
8261 ESTAT_ADD(tx_bcast_packets);
8262 ESTAT_ADD(tx_carrier_sense_errors);
8263 ESTAT_ADD(tx_discards);
8264 ESTAT_ADD(tx_errors);
8265
8266 ESTAT_ADD(dma_writeq_full);
8267 ESTAT_ADD(dma_write_prioq_full);
8268 ESTAT_ADD(rxbds_empty);
8269 ESTAT_ADD(rx_discards);
8270 ESTAT_ADD(rx_errors);
8271 ESTAT_ADD(rx_threshold_hit);
8272
8273 ESTAT_ADD(dma_readq_full);
8274 ESTAT_ADD(dma_read_prioq_full);
8275 ESTAT_ADD(tx_comp_queue_full);
8276
8277 ESTAT_ADD(ring_set_send_prod_index);
8278 ESTAT_ADD(ring_status_update);
8279 ESTAT_ADD(nic_irqs);
8280 ESTAT_ADD(nic_avoided_irqs);
8281 ESTAT_ADD(nic_tx_threshold_hit);
8282
8283 return estats;
8284 }
8285
8286 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8287 {
8288 struct tg3 *tp = netdev_priv(dev);
8289 struct net_device_stats *stats = &tp->net_stats;
8290 struct net_device_stats *old_stats = &tp->net_stats_prev;
8291 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8292
8293 if (!hw_stats)
8294 return old_stats;
8295
8296 stats->rx_packets = old_stats->rx_packets +
8297 get_stat64(&hw_stats->rx_ucast_packets) +
8298 get_stat64(&hw_stats->rx_mcast_packets) +
8299 get_stat64(&hw_stats->rx_bcast_packets);
8300
8301 stats->tx_packets = old_stats->tx_packets +
8302 get_stat64(&hw_stats->tx_ucast_packets) +
8303 get_stat64(&hw_stats->tx_mcast_packets) +
8304 get_stat64(&hw_stats->tx_bcast_packets);
8305
8306 stats->rx_bytes = old_stats->rx_bytes +
8307 get_stat64(&hw_stats->rx_octets);
8308 stats->tx_bytes = old_stats->tx_bytes +
8309 get_stat64(&hw_stats->tx_octets);
8310
8311 stats->rx_errors = old_stats->rx_errors +
8312 get_stat64(&hw_stats->rx_errors);
8313 stats->tx_errors = old_stats->tx_errors +
8314 get_stat64(&hw_stats->tx_errors) +
8315 get_stat64(&hw_stats->tx_mac_errors) +
8316 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8317 get_stat64(&hw_stats->tx_discards);
8318
8319 stats->multicast = old_stats->multicast +
8320 get_stat64(&hw_stats->rx_mcast_packets);
8321 stats->collisions = old_stats->collisions +
8322 get_stat64(&hw_stats->tx_collisions);
8323
8324 stats->rx_length_errors = old_stats->rx_length_errors +
8325 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8326 get_stat64(&hw_stats->rx_undersize_packets);
8327
8328 stats->rx_over_errors = old_stats->rx_over_errors +
8329 get_stat64(&hw_stats->rxbds_empty);
8330 stats->rx_frame_errors = old_stats->rx_frame_errors +
8331 get_stat64(&hw_stats->rx_align_errors);
8332 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8333 get_stat64(&hw_stats->tx_discards);
8334 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8335 get_stat64(&hw_stats->tx_carrier_sense_errors);
8336
8337 stats->rx_crc_errors = old_stats->rx_crc_errors +
8338 calc_crc_errors(tp);
8339
8340 stats->rx_missed_errors = old_stats->rx_missed_errors +
8341 get_stat64(&hw_stats->rx_discards);
8342
8343 return stats;
8344 }
8345
8346 static inline u32 calc_crc(unsigned char *buf, int len)
8347 {
8348 u32 reg;
8349 u32 tmp;
8350 int j, k;
8351
8352 reg = 0xffffffff;
8353
8354 for (j = 0; j < len; j++) {
8355 reg ^= buf[j];
8356
8357 for (k = 0; k < 8; k++) {
8358 tmp = reg & 0x01;
8359
8360 reg >>= 1;
8361
8362 if (tmp) {
8363 reg ^= 0xedb88320;
8364 }
8365 }
8366 }
8367
8368 return ~reg;
8369 }
8370
8371 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8372 {
8373 /* accept or reject all multicast frames */
8374 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8375 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8376 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8377 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8378 }
8379
8380 static void __tg3_set_rx_mode(struct net_device *dev)
8381 {
8382 struct tg3 *tp = netdev_priv(dev);
8383 u32 rx_mode;
8384
8385 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8386 RX_MODE_KEEP_VLAN_TAG);
8387
8388 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8389 * flag clear.
8390 */
8391 #if TG3_VLAN_TAG_USED
8392 if (!tp->vlgrp &&
8393 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8394 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8395 #else
8396 /* By definition, VLAN is disabled always in this
8397 * case.
8398 */
8399 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8400 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8401 #endif
8402
8403 if (dev->flags & IFF_PROMISC) {
8404 /* Promiscuous mode. */
8405 rx_mode |= RX_MODE_PROMISC;
8406 } else if (dev->flags & IFF_ALLMULTI) {
8407 /* Accept all multicast. */
8408 tg3_set_multi (tp, 1);
8409 } else if (dev->mc_count < 1) {
8410 /* Reject all multicast. */
8411 tg3_set_multi (tp, 0);
8412 } else {
8413 /* Accept one or more multicast(s). */
8414 struct dev_mc_list *mclist;
8415 unsigned int i;
8416 u32 mc_filter[4] = { 0, };
8417 u32 regidx;
8418 u32 bit;
8419 u32 crc;
8420
8421 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8422 i++, mclist = mclist->next) {
8423
8424 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8425 bit = ~crc & 0x7f;
8426 regidx = (bit & 0x60) >> 5;
8427 bit &= 0x1f;
8428 mc_filter[regidx] |= (1 << bit);
8429 }
8430
8431 tw32(MAC_HASH_REG_0, mc_filter[0]);
8432 tw32(MAC_HASH_REG_1, mc_filter[1]);
8433 tw32(MAC_HASH_REG_2, mc_filter[2]);
8434 tw32(MAC_HASH_REG_3, mc_filter[3]);
8435 }
8436
8437 if (rx_mode != tp->rx_mode) {
8438 tp->rx_mode = rx_mode;
8439 tw32_f(MAC_RX_MODE, rx_mode);
8440 udelay(10);
8441 }
8442 }
8443
8444 static void tg3_set_rx_mode(struct net_device *dev)
8445 {
8446 struct tg3 *tp = netdev_priv(dev);
8447
8448 if (!netif_running(dev))
8449 return;
8450
8451 tg3_full_lock(tp, 0);
8452 __tg3_set_rx_mode(dev);
8453 tg3_full_unlock(tp);
8454 }
8455
8456 #define TG3_REGDUMP_LEN (32 * 1024)
8457
8458 static int tg3_get_regs_len(struct net_device *dev)
8459 {
8460 return TG3_REGDUMP_LEN;
8461 }
8462
8463 static void tg3_get_regs(struct net_device *dev,
8464 struct ethtool_regs *regs, void *_p)
8465 {
8466 u32 *p = _p;
8467 struct tg3 *tp = netdev_priv(dev);
8468 u8 *orig_p = _p;
8469 int i;
8470
8471 regs->version = 0;
8472
8473 memset(p, 0, TG3_REGDUMP_LEN);
8474
8475 if (tp->link_config.phy_is_low_power)
8476 return;
8477
8478 tg3_full_lock(tp, 0);
8479
8480 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8481 #define GET_REG32_LOOP(base,len) \
8482 do { p = (u32 *)(orig_p + (base)); \
8483 for (i = 0; i < len; i += 4) \
8484 __GET_REG32((base) + i); \
8485 } while (0)
8486 #define GET_REG32_1(reg) \
8487 do { p = (u32 *)(orig_p + (reg)); \
8488 __GET_REG32((reg)); \
8489 } while (0)
8490
8491 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8492 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8493 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8494 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8495 GET_REG32_1(SNDDATAC_MODE);
8496 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8497 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8498 GET_REG32_1(SNDBDC_MODE);
8499 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8500 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8501 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8502 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8503 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8504 GET_REG32_1(RCVDCC_MODE);
8505 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8506 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8507 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8508 GET_REG32_1(MBFREE_MODE);
8509 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8510 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8511 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8512 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8513 GET_REG32_LOOP(WDMAC_MODE, 0x08);
8514 GET_REG32_1(RX_CPU_MODE);
8515 GET_REG32_1(RX_CPU_STATE);
8516 GET_REG32_1(RX_CPU_PGMCTR);
8517 GET_REG32_1(RX_CPU_HWBKPT);
8518 GET_REG32_1(TX_CPU_MODE);
8519 GET_REG32_1(TX_CPU_STATE);
8520 GET_REG32_1(TX_CPU_PGMCTR);
8521 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8522 GET_REG32_LOOP(FTQ_RESET, 0x120);
8523 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8524 GET_REG32_1(DMAC_MODE);
8525 GET_REG32_LOOP(GRC_MODE, 0x4c);
8526 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8527 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8528
8529 #undef __GET_REG32
8530 #undef GET_REG32_LOOP
8531 #undef GET_REG32_1
8532
8533 tg3_full_unlock(tp);
8534 }
8535
8536 static int tg3_get_eeprom_len(struct net_device *dev)
8537 {
8538 struct tg3 *tp = netdev_priv(dev);
8539
8540 return tp->nvram_size;
8541 }
8542
8543 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8544 {
8545 struct tg3 *tp = netdev_priv(dev);
8546 int ret;
8547 u8 *pd;
8548 u32 i, offset, len, b_offset, b_count;
8549 __be32 val;
8550
8551 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
8552 return -EINVAL;
8553
8554 if (tp->link_config.phy_is_low_power)
8555 return -EAGAIN;
8556
8557 offset = eeprom->offset;
8558 len = eeprom->len;
8559 eeprom->len = 0;
8560
8561 eeprom->magic = TG3_EEPROM_MAGIC;
8562
8563 if (offset & 3) {
8564 /* adjustments to start on required 4 byte boundary */
8565 b_offset = offset & 3;
8566 b_count = 4 - b_offset;
8567 if (b_count > len) {
8568 /* i.e. offset=1 len=2 */
8569 b_count = len;
8570 }
8571 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
8572 if (ret)
8573 return ret;
8574 memcpy(data, ((char*)&val) + b_offset, b_count);
8575 len -= b_count;
8576 offset += b_count;
8577 eeprom->len += b_count;
8578 }
8579
8580 /* read bytes upto the last 4 byte boundary */
8581 pd = &data[eeprom->len];
8582 for (i = 0; i < (len - (len & 3)); i += 4) {
8583 ret = tg3_nvram_read_be32(tp, offset + i, &val);
8584 if (ret) {
8585 eeprom->len += i;
8586 return ret;
8587 }
8588 memcpy(pd + i, &val, 4);
8589 }
8590 eeprom->len += i;
8591
8592 if (len & 3) {
8593 /* read last bytes not ending on 4 byte boundary */
8594 pd = &data[eeprom->len];
8595 b_count = len & 3;
8596 b_offset = offset + len - b_count;
8597 ret = tg3_nvram_read_be32(tp, b_offset, &val);
8598 if (ret)
8599 return ret;
8600 memcpy(pd, &val, b_count);
8601 eeprom->len += b_count;
8602 }
8603 return 0;
8604 }
8605
8606 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8607
8608 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8609 {
8610 struct tg3 *tp = netdev_priv(dev);
8611 int ret;
8612 u32 offset, len, b_offset, odd_len;
8613 u8 *buf;
8614 __be32 start, end;
8615
8616 if (tp->link_config.phy_is_low_power)
8617 return -EAGAIN;
8618
8619 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
8620 eeprom->magic != TG3_EEPROM_MAGIC)
8621 return -EINVAL;
8622
8623 offset = eeprom->offset;
8624 len = eeprom->len;
8625
8626 if ((b_offset = (offset & 3))) {
8627 /* adjustments to start on required 4 byte boundary */
8628 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
8629 if (ret)
8630 return ret;
8631 len += b_offset;
8632 offset &= ~3;
8633 if (len < 4)
8634 len = 4;
8635 }
8636
8637 odd_len = 0;
8638 if (len & 3) {
8639 /* adjustments to end on required 4 byte boundary */
8640 odd_len = 1;
8641 len = (len + 3) & ~3;
8642 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
8643 if (ret)
8644 return ret;
8645 }
8646
8647 buf = data;
8648 if (b_offset || odd_len) {
8649 buf = kmalloc(len, GFP_KERNEL);
8650 if (!buf)
8651 return -ENOMEM;
8652 if (b_offset)
8653 memcpy(buf, &start, 4);
8654 if (odd_len)
8655 memcpy(buf+len-4, &end, 4);
8656 memcpy(buf + b_offset, data, eeprom->len);
8657 }
8658
8659 ret = tg3_nvram_write_block(tp, offset, len, buf);
8660
8661 if (buf != data)
8662 kfree(buf);
8663
8664 return ret;
8665 }
8666
8667 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8668 {
8669 struct tg3 *tp = netdev_priv(dev);
8670
8671 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8672 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8673 return -EAGAIN;
8674 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8675 }
8676
8677 cmd->supported = (SUPPORTED_Autoneg);
8678
8679 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8680 cmd->supported |= (SUPPORTED_1000baseT_Half |
8681 SUPPORTED_1000baseT_Full);
8682
8683 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8684 cmd->supported |= (SUPPORTED_100baseT_Half |
8685 SUPPORTED_100baseT_Full |
8686 SUPPORTED_10baseT_Half |
8687 SUPPORTED_10baseT_Full |
8688 SUPPORTED_TP);
8689 cmd->port = PORT_TP;
8690 } else {
8691 cmd->supported |= SUPPORTED_FIBRE;
8692 cmd->port = PORT_FIBRE;
8693 }
8694
8695 cmd->advertising = tp->link_config.advertising;
8696 if (netif_running(dev)) {
8697 cmd->speed = tp->link_config.active_speed;
8698 cmd->duplex = tp->link_config.active_duplex;
8699 }
8700 cmd->phy_address = PHY_ADDR;
8701 cmd->transceiver = XCVR_INTERNAL;
8702 cmd->autoneg = tp->link_config.autoneg;
8703 cmd->maxtxpkt = 0;
8704 cmd->maxrxpkt = 0;
8705 return 0;
8706 }
8707
8708 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8709 {
8710 struct tg3 *tp = netdev_priv(dev);
8711
8712 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8713 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8714 return -EAGAIN;
8715 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8716 }
8717
8718 if (cmd->autoneg != AUTONEG_ENABLE &&
8719 cmd->autoneg != AUTONEG_DISABLE)
8720 return -EINVAL;
8721
8722 if (cmd->autoneg == AUTONEG_DISABLE &&
8723 cmd->duplex != DUPLEX_FULL &&
8724 cmd->duplex != DUPLEX_HALF)
8725 return -EINVAL;
8726
8727 if (cmd->autoneg == AUTONEG_ENABLE) {
8728 u32 mask = ADVERTISED_Autoneg |
8729 ADVERTISED_Pause |
8730 ADVERTISED_Asym_Pause;
8731
8732 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8733 mask |= ADVERTISED_1000baseT_Half |
8734 ADVERTISED_1000baseT_Full;
8735
8736 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
8737 mask |= ADVERTISED_100baseT_Half |
8738 ADVERTISED_100baseT_Full |
8739 ADVERTISED_10baseT_Half |
8740 ADVERTISED_10baseT_Full |
8741 ADVERTISED_TP;
8742 else
8743 mask |= ADVERTISED_FIBRE;
8744
8745 if (cmd->advertising & ~mask)
8746 return -EINVAL;
8747
8748 mask &= (ADVERTISED_1000baseT_Half |
8749 ADVERTISED_1000baseT_Full |
8750 ADVERTISED_100baseT_Half |
8751 ADVERTISED_100baseT_Full |
8752 ADVERTISED_10baseT_Half |
8753 ADVERTISED_10baseT_Full);
8754
8755 cmd->advertising &= mask;
8756 } else {
8757 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8758 if (cmd->speed != SPEED_1000)
8759 return -EINVAL;
8760
8761 if (cmd->duplex != DUPLEX_FULL)
8762 return -EINVAL;
8763 } else {
8764 if (cmd->speed != SPEED_100 &&
8765 cmd->speed != SPEED_10)
8766 return -EINVAL;
8767 }
8768 }
8769
8770 tg3_full_lock(tp, 0);
8771
8772 tp->link_config.autoneg = cmd->autoneg;
8773 if (cmd->autoneg == AUTONEG_ENABLE) {
8774 tp->link_config.advertising = (cmd->advertising |
8775 ADVERTISED_Autoneg);
8776 tp->link_config.speed = SPEED_INVALID;
8777 tp->link_config.duplex = DUPLEX_INVALID;
8778 } else {
8779 tp->link_config.advertising = 0;
8780 tp->link_config.speed = cmd->speed;
8781 tp->link_config.duplex = cmd->duplex;
8782 }
8783
8784 tp->link_config.orig_speed = tp->link_config.speed;
8785 tp->link_config.orig_duplex = tp->link_config.duplex;
8786 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8787
8788 if (netif_running(dev))
8789 tg3_setup_phy(tp, 1);
8790
8791 tg3_full_unlock(tp);
8792
8793 return 0;
8794 }
8795
8796 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8797 {
8798 struct tg3 *tp = netdev_priv(dev);
8799
8800 strcpy(info->driver, DRV_MODULE_NAME);
8801 strcpy(info->version, DRV_MODULE_VERSION);
8802 strcpy(info->fw_version, tp->fw_ver);
8803 strcpy(info->bus_info, pci_name(tp->pdev));
8804 }
8805
8806 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8807 {
8808 struct tg3 *tp = netdev_priv(dev);
8809
8810 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8811 device_can_wakeup(&tp->pdev->dev))
8812 wol->supported = WAKE_MAGIC;
8813 else
8814 wol->supported = 0;
8815 wol->wolopts = 0;
8816 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8817 device_can_wakeup(&tp->pdev->dev))
8818 wol->wolopts = WAKE_MAGIC;
8819 memset(&wol->sopass, 0, sizeof(wol->sopass));
8820 }
8821
8822 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8823 {
8824 struct tg3 *tp = netdev_priv(dev);
8825 struct device *dp = &tp->pdev->dev;
8826
8827 if (wol->wolopts & ~WAKE_MAGIC)
8828 return -EINVAL;
8829 if ((wol->wolopts & WAKE_MAGIC) &&
8830 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8831 return -EINVAL;
8832
8833 spin_lock_bh(&tp->lock);
8834 if (wol->wolopts & WAKE_MAGIC) {
8835 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8836 device_set_wakeup_enable(dp, true);
8837 } else {
8838 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8839 device_set_wakeup_enable(dp, false);
8840 }
8841 spin_unlock_bh(&tp->lock);
8842
8843 return 0;
8844 }
8845
8846 static u32 tg3_get_msglevel(struct net_device *dev)
8847 {
8848 struct tg3 *tp = netdev_priv(dev);
8849 return tp->msg_enable;
8850 }
8851
8852 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8853 {
8854 struct tg3 *tp = netdev_priv(dev);
8855 tp->msg_enable = value;
8856 }
8857
8858 static int tg3_set_tso(struct net_device *dev, u32 value)
8859 {
8860 struct tg3 *tp = netdev_priv(dev);
8861
8862 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8863 if (value)
8864 return -EINVAL;
8865 return 0;
8866 }
8867 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8868 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
8869 if (value) {
8870 dev->features |= NETIF_F_TSO6;
8871 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8872 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8873 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
8874 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8876 dev->features |= NETIF_F_TSO_ECN;
8877 } else
8878 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8879 }
8880 return ethtool_op_set_tso(dev, value);
8881 }
8882
8883 static int tg3_nway_reset(struct net_device *dev)
8884 {
8885 struct tg3 *tp = netdev_priv(dev);
8886 int r;
8887
8888 if (!netif_running(dev))
8889 return -EAGAIN;
8890
8891 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8892 return -EINVAL;
8893
8894 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8895 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8896 return -EAGAIN;
8897 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
8898 } else {
8899 u32 bmcr;
8900
8901 spin_lock_bh(&tp->lock);
8902 r = -EINVAL;
8903 tg3_readphy(tp, MII_BMCR, &bmcr);
8904 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8905 ((bmcr & BMCR_ANENABLE) ||
8906 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8907 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8908 BMCR_ANENABLE);
8909 r = 0;
8910 }
8911 spin_unlock_bh(&tp->lock);
8912 }
8913
8914 return r;
8915 }
8916
8917 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8918 {
8919 struct tg3 *tp = netdev_priv(dev);
8920
8921 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8922 ering->rx_mini_max_pending = 0;
8923 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8924 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8925 else
8926 ering->rx_jumbo_max_pending = 0;
8927
8928 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8929
8930 ering->rx_pending = tp->rx_pending;
8931 ering->rx_mini_pending = 0;
8932 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8933 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8934 else
8935 ering->rx_jumbo_pending = 0;
8936
8937 ering->tx_pending = tp->tx_pending;
8938 }
8939
8940 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8941 {
8942 struct tg3 *tp = netdev_priv(dev);
8943 int irq_sync = 0, err = 0;
8944
8945 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8946 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8947 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8948 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8949 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8950 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8951 return -EINVAL;
8952
8953 if (netif_running(dev)) {
8954 tg3_phy_stop(tp);
8955 tg3_netif_stop(tp);
8956 irq_sync = 1;
8957 }
8958
8959 tg3_full_lock(tp, irq_sync);
8960
8961 tp->rx_pending = ering->rx_pending;
8962
8963 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8964 tp->rx_pending > 63)
8965 tp->rx_pending = 63;
8966 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8967 tp->tx_pending = ering->tx_pending;
8968
8969 if (netif_running(dev)) {
8970 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8971 err = tg3_restart_hw(tp, 1);
8972 if (!err)
8973 tg3_netif_start(tp);
8974 }
8975
8976 tg3_full_unlock(tp);
8977
8978 if (irq_sync && !err)
8979 tg3_phy_start(tp);
8980
8981 return err;
8982 }
8983
8984 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8985 {
8986 struct tg3 *tp = netdev_priv(dev);
8987
8988 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8989
8990 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8991 epause->rx_pause = 1;
8992 else
8993 epause->rx_pause = 0;
8994
8995 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8996 epause->tx_pause = 1;
8997 else
8998 epause->tx_pause = 0;
8999 }
9000
9001 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9002 {
9003 struct tg3 *tp = netdev_priv(dev);
9004 int err = 0;
9005
9006 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9007 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9008 return -EAGAIN;
9009
9010 if (epause->autoneg) {
9011 u32 newadv;
9012 struct phy_device *phydev;
9013
9014 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9015
9016 if (epause->rx_pause) {
9017 if (epause->tx_pause)
9018 newadv = ADVERTISED_Pause;
9019 else
9020 newadv = ADVERTISED_Pause |
9021 ADVERTISED_Asym_Pause;
9022 } else if (epause->tx_pause) {
9023 newadv = ADVERTISED_Asym_Pause;
9024 } else
9025 newadv = 0;
9026
9027 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9028 u32 oldadv = phydev->advertising &
9029 (ADVERTISED_Pause |
9030 ADVERTISED_Asym_Pause);
9031 if (oldadv != newadv) {
9032 phydev->advertising &=
9033 ~(ADVERTISED_Pause |
9034 ADVERTISED_Asym_Pause);
9035 phydev->advertising |= newadv;
9036 err = phy_start_aneg(phydev);
9037 }
9038 } else {
9039 tp->link_config.advertising &=
9040 ~(ADVERTISED_Pause |
9041 ADVERTISED_Asym_Pause);
9042 tp->link_config.advertising |= newadv;
9043 }
9044 } else {
9045 if (epause->rx_pause)
9046 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9047 else
9048 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9049
9050 if (epause->tx_pause)
9051 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9052 else
9053 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9054
9055 if (netif_running(dev))
9056 tg3_setup_flow_control(tp, 0, 0);
9057 }
9058 } else {
9059 int irq_sync = 0;
9060
9061 if (netif_running(dev)) {
9062 tg3_netif_stop(tp);
9063 irq_sync = 1;
9064 }
9065
9066 tg3_full_lock(tp, irq_sync);
9067
9068 if (epause->autoneg)
9069 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9070 else
9071 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9072 if (epause->rx_pause)
9073 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9074 else
9075 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9076 if (epause->tx_pause)
9077 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9078 else
9079 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9080
9081 if (netif_running(dev)) {
9082 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9083 err = tg3_restart_hw(tp, 1);
9084 if (!err)
9085 tg3_netif_start(tp);
9086 }
9087
9088 tg3_full_unlock(tp);
9089 }
9090
9091 return err;
9092 }
9093
9094 static u32 tg3_get_rx_csum(struct net_device *dev)
9095 {
9096 struct tg3 *tp = netdev_priv(dev);
9097 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9098 }
9099
9100 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9101 {
9102 struct tg3 *tp = netdev_priv(dev);
9103
9104 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9105 if (data != 0)
9106 return -EINVAL;
9107 return 0;
9108 }
9109
9110 spin_lock_bh(&tp->lock);
9111 if (data)
9112 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9113 else
9114 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9115 spin_unlock_bh(&tp->lock);
9116
9117 return 0;
9118 }
9119
9120 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9121 {
9122 struct tg3 *tp = netdev_priv(dev);
9123
9124 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9125 if (data != 0)
9126 return -EINVAL;
9127 return 0;
9128 }
9129
9130 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9131 ethtool_op_set_tx_ipv6_csum(dev, data);
9132 else
9133 ethtool_op_set_tx_csum(dev, data);
9134
9135 return 0;
9136 }
9137
9138 static int tg3_get_sset_count (struct net_device *dev, int sset)
9139 {
9140 switch (sset) {
9141 case ETH_SS_TEST:
9142 return TG3_NUM_TEST;
9143 case ETH_SS_STATS:
9144 return TG3_NUM_STATS;
9145 default:
9146 return -EOPNOTSUPP;
9147 }
9148 }
9149
9150 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9151 {
9152 switch (stringset) {
9153 case ETH_SS_STATS:
9154 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9155 break;
9156 case ETH_SS_TEST:
9157 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9158 break;
9159 default:
9160 WARN_ON(1); /* we need a WARN() */
9161 break;
9162 }
9163 }
9164
9165 static int tg3_phys_id(struct net_device *dev, u32 data)
9166 {
9167 struct tg3 *tp = netdev_priv(dev);
9168 int i;
9169
9170 if (!netif_running(tp->dev))
9171 return -EAGAIN;
9172
9173 if (data == 0)
9174 data = UINT_MAX / 2;
9175
9176 for (i = 0; i < (data * 2); i++) {
9177 if ((i % 2) == 0)
9178 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9179 LED_CTRL_1000MBPS_ON |
9180 LED_CTRL_100MBPS_ON |
9181 LED_CTRL_10MBPS_ON |
9182 LED_CTRL_TRAFFIC_OVERRIDE |
9183 LED_CTRL_TRAFFIC_BLINK |
9184 LED_CTRL_TRAFFIC_LED);
9185
9186 else
9187 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9188 LED_CTRL_TRAFFIC_OVERRIDE);
9189
9190 if (msleep_interruptible(500))
9191 break;
9192 }
9193 tw32(MAC_LED_CTRL, tp->led_ctrl);
9194 return 0;
9195 }
9196
9197 static void tg3_get_ethtool_stats (struct net_device *dev,
9198 struct ethtool_stats *estats, u64 *tmp_stats)
9199 {
9200 struct tg3 *tp = netdev_priv(dev);
9201 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9202 }
9203
9204 #define NVRAM_TEST_SIZE 0x100
9205 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9206 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9207 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9208 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9209 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9210
9211 static int tg3_test_nvram(struct tg3 *tp)
9212 {
9213 u32 csum, magic;
9214 __be32 *buf;
9215 int i, j, k, err = 0, size;
9216
9217 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9218 return 0;
9219
9220 if (tg3_nvram_read(tp, 0, &magic) != 0)
9221 return -EIO;
9222
9223 if (magic == TG3_EEPROM_MAGIC)
9224 size = NVRAM_TEST_SIZE;
9225 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9226 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9227 TG3_EEPROM_SB_FORMAT_1) {
9228 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9229 case TG3_EEPROM_SB_REVISION_0:
9230 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9231 break;
9232 case TG3_EEPROM_SB_REVISION_2:
9233 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9234 break;
9235 case TG3_EEPROM_SB_REVISION_3:
9236 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9237 break;
9238 default:
9239 return 0;
9240 }
9241 } else
9242 return 0;
9243 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9244 size = NVRAM_SELFBOOT_HW_SIZE;
9245 else
9246 return -EIO;
9247
9248 buf = kmalloc(size, GFP_KERNEL);
9249 if (buf == NULL)
9250 return -ENOMEM;
9251
9252 err = -EIO;
9253 for (i = 0, j = 0; i < size; i += 4, j++) {
9254 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9255 if (err)
9256 break;
9257 }
9258 if (i < size)
9259 goto out;
9260
9261 /* Selfboot format */
9262 magic = be32_to_cpu(buf[0]);
9263 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9264 TG3_EEPROM_MAGIC_FW) {
9265 u8 *buf8 = (u8 *) buf, csum8 = 0;
9266
9267 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9268 TG3_EEPROM_SB_REVISION_2) {
9269 /* For rev 2, the csum doesn't include the MBA. */
9270 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9271 csum8 += buf8[i];
9272 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9273 csum8 += buf8[i];
9274 } else {
9275 for (i = 0; i < size; i++)
9276 csum8 += buf8[i];
9277 }
9278
9279 if (csum8 == 0) {
9280 err = 0;
9281 goto out;
9282 }
9283
9284 err = -EIO;
9285 goto out;
9286 }
9287
9288 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9289 TG3_EEPROM_MAGIC_HW) {
9290 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9291 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9292 u8 *buf8 = (u8 *) buf;
9293
9294 /* Separate the parity bits and the data bytes. */
9295 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9296 if ((i == 0) || (i == 8)) {
9297 int l;
9298 u8 msk;
9299
9300 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9301 parity[k++] = buf8[i] & msk;
9302 i++;
9303 }
9304 else if (i == 16) {
9305 int l;
9306 u8 msk;
9307
9308 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9309 parity[k++] = buf8[i] & msk;
9310 i++;
9311
9312 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9313 parity[k++] = buf8[i] & msk;
9314 i++;
9315 }
9316 data[j++] = buf8[i];
9317 }
9318
9319 err = -EIO;
9320 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9321 u8 hw8 = hweight8(data[i]);
9322
9323 if ((hw8 & 0x1) && parity[i])
9324 goto out;
9325 else if (!(hw8 & 0x1) && !parity[i])
9326 goto out;
9327 }
9328 err = 0;
9329 goto out;
9330 }
9331
9332 /* Bootstrap checksum at offset 0x10 */
9333 csum = calc_crc((unsigned char *) buf, 0x10);
9334 if (csum != be32_to_cpu(buf[0x10/4]))
9335 goto out;
9336
9337 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9338 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9339 if (csum != be32_to_cpu(buf[0xfc/4]))
9340 goto out;
9341
9342 err = 0;
9343
9344 out:
9345 kfree(buf);
9346 return err;
9347 }
9348
9349 #define TG3_SERDES_TIMEOUT_SEC 2
9350 #define TG3_COPPER_TIMEOUT_SEC 6
9351
9352 static int tg3_test_link(struct tg3 *tp)
9353 {
9354 int i, max;
9355
9356 if (!netif_running(tp->dev))
9357 return -ENODEV;
9358
9359 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9360 max = TG3_SERDES_TIMEOUT_SEC;
9361 else
9362 max = TG3_COPPER_TIMEOUT_SEC;
9363
9364 for (i = 0; i < max; i++) {
9365 if (netif_carrier_ok(tp->dev))
9366 return 0;
9367
9368 if (msleep_interruptible(1000))
9369 break;
9370 }
9371
9372 return -EIO;
9373 }
9374
9375 /* Only test the commonly used registers */
9376 static int tg3_test_registers(struct tg3 *tp)
9377 {
9378 int i, is_5705, is_5750;
9379 u32 offset, read_mask, write_mask, val, save_val, read_val;
9380 static struct {
9381 u16 offset;
9382 u16 flags;
9383 #define TG3_FL_5705 0x1
9384 #define TG3_FL_NOT_5705 0x2
9385 #define TG3_FL_NOT_5788 0x4
9386 #define TG3_FL_NOT_5750 0x8
9387 u32 read_mask;
9388 u32 write_mask;
9389 } reg_tbl[] = {
9390 /* MAC Control Registers */
9391 { MAC_MODE, TG3_FL_NOT_5705,
9392 0x00000000, 0x00ef6f8c },
9393 { MAC_MODE, TG3_FL_5705,
9394 0x00000000, 0x01ef6b8c },
9395 { MAC_STATUS, TG3_FL_NOT_5705,
9396 0x03800107, 0x00000000 },
9397 { MAC_STATUS, TG3_FL_5705,
9398 0x03800100, 0x00000000 },
9399 { MAC_ADDR_0_HIGH, 0x0000,
9400 0x00000000, 0x0000ffff },
9401 { MAC_ADDR_0_LOW, 0x0000,
9402 0x00000000, 0xffffffff },
9403 { MAC_RX_MTU_SIZE, 0x0000,
9404 0x00000000, 0x0000ffff },
9405 { MAC_TX_MODE, 0x0000,
9406 0x00000000, 0x00000070 },
9407 { MAC_TX_LENGTHS, 0x0000,
9408 0x00000000, 0x00003fff },
9409 { MAC_RX_MODE, TG3_FL_NOT_5705,
9410 0x00000000, 0x000007fc },
9411 { MAC_RX_MODE, TG3_FL_5705,
9412 0x00000000, 0x000007dc },
9413 { MAC_HASH_REG_0, 0x0000,
9414 0x00000000, 0xffffffff },
9415 { MAC_HASH_REG_1, 0x0000,
9416 0x00000000, 0xffffffff },
9417 { MAC_HASH_REG_2, 0x0000,
9418 0x00000000, 0xffffffff },
9419 { MAC_HASH_REG_3, 0x0000,
9420 0x00000000, 0xffffffff },
9421
9422 /* Receive Data and Receive BD Initiator Control Registers. */
9423 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9424 0x00000000, 0xffffffff },
9425 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9426 0x00000000, 0xffffffff },
9427 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9428 0x00000000, 0x00000003 },
9429 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9430 0x00000000, 0xffffffff },
9431 { RCVDBDI_STD_BD+0, 0x0000,
9432 0x00000000, 0xffffffff },
9433 { RCVDBDI_STD_BD+4, 0x0000,
9434 0x00000000, 0xffffffff },
9435 { RCVDBDI_STD_BD+8, 0x0000,
9436 0x00000000, 0xffff0002 },
9437 { RCVDBDI_STD_BD+0xc, 0x0000,
9438 0x00000000, 0xffffffff },
9439
9440 /* Receive BD Initiator Control Registers. */
9441 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9442 0x00000000, 0xffffffff },
9443 { RCVBDI_STD_THRESH, TG3_FL_5705,
9444 0x00000000, 0x000003ff },
9445 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9446 0x00000000, 0xffffffff },
9447
9448 /* Host Coalescing Control Registers. */
9449 { HOSTCC_MODE, TG3_FL_NOT_5705,
9450 0x00000000, 0x00000004 },
9451 { HOSTCC_MODE, TG3_FL_5705,
9452 0x00000000, 0x000000f6 },
9453 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9454 0x00000000, 0xffffffff },
9455 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9456 0x00000000, 0x000003ff },
9457 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9458 0x00000000, 0xffffffff },
9459 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9460 0x00000000, 0x000003ff },
9461 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9462 0x00000000, 0xffffffff },
9463 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9464 0x00000000, 0x000000ff },
9465 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9466 0x00000000, 0xffffffff },
9467 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9468 0x00000000, 0x000000ff },
9469 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9470 0x00000000, 0xffffffff },
9471 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9472 0x00000000, 0xffffffff },
9473 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9474 0x00000000, 0xffffffff },
9475 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9476 0x00000000, 0x000000ff },
9477 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9478 0x00000000, 0xffffffff },
9479 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9480 0x00000000, 0x000000ff },
9481 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9482 0x00000000, 0xffffffff },
9483 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9484 0x00000000, 0xffffffff },
9485 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9486 0x00000000, 0xffffffff },
9487 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9488 0x00000000, 0xffffffff },
9489 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9490 0x00000000, 0xffffffff },
9491 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9492 0xffffffff, 0x00000000 },
9493 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9494 0xffffffff, 0x00000000 },
9495
9496 /* Buffer Manager Control Registers. */
9497 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9498 0x00000000, 0x007fff80 },
9499 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9500 0x00000000, 0x007fffff },
9501 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9502 0x00000000, 0x0000003f },
9503 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9504 0x00000000, 0x000001ff },
9505 { BUFMGR_MB_HIGH_WATER, 0x0000,
9506 0x00000000, 0x000001ff },
9507 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9508 0xffffffff, 0x00000000 },
9509 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9510 0xffffffff, 0x00000000 },
9511
9512 /* Mailbox Registers */
9513 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9514 0x00000000, 0x000001ff },
9515 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9516 0x00000000, 0x000001ff },
9517 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9518 0x00000000, 0x000007ff },
9519 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9520 0x00000000, 0x000001ff },
9521
9522 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9523 };
9524
9525 is_5705 = is_5750 = 0;
9526 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9527 is_5705 = 1;
9528 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9529 is_5750 = 1;
9530 }
9531
9532 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9533 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9534 continue;
9535
9536 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9537 continue;
9538
9539 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9540 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9541 continue;
9542
9543 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9544 continue;
9545
9546 offset = (u32) reg_tbl[i].offset;
9547 read_mask = reg_tbl[i].read_mask;
9548 write_mask = reg_tbl[i].write_mask;
9549
9550 /* Save the original register content */
9551 save_val = tr32(offset);
9552
9553 /* Determine the read-only value. */
9554 read_val = save_val & read_mask;
9555
9556 /* Write zero to the register, then make sure the read-only bits
9557 * are not changed and the read/write bits are all zeros.
9558 */
9559 tw32(offset, 0);
9560
9561 val = tr32(offset);
9562
9563 /* Test the read-only and read/write bits. */
9564 if (((val & read_mask) != read_val) || (val & write_mask))
9565 goto out;
9566
9567 /* Write ones to all the bits defined by RdMask and WrMask, then
9568 * make sure the read-only bits are not changed and the
9569 * read/write bits are all ones.
9570 */
9571 tw32(offset, read_mask | write_mask);
9572
9573 val = tr32(offset);
9574
9575 /* Test the read-only bits. */
9576 if ((val & read_mask) != read_val)
9577 goto out;
9578
9579 /* Test the read/write bits. */
9580 if ((val & write_mask) != write_mask)
9581 goto out;
9582
9583 tw32(offset, save_val);
9584 }
9585
9586 return 0;
9587
9588 out:
9589 if (netif_msg_hw(tp))
9590 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9591 offset);
9592 tw32(offset, save_val);
9593 return -EIO;
9594 }
9595
9596 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9597 {
9598 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9599 int i;
9600 u32 j;
9601
9602 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9603 for (j = 0; j < len; j += 4) {
9604 u32 val;
9605
9606 tg3_write_mem(tp, offset + j, test_pattern[i]);
9607 tg3_read_mem(tp, offset + j, &val);
9608 if (val != test_pattern[i])
9609 return -EIO;
9610 }
9611 }
9612 return 0;
9613 }
9614
9615 static int tg3_test_memory(struct tg3 *tp)
9616 {
9617 static struct mem_entry {
9618 u32 offset;
9619 u32 len;
9620 } mem_tbl_570x[] = {
9621 { 0x00000000, 0x00b50},
9622 { 0x00002000, 0x1c000},
9623 { 0xffffffff, 0x00000}
9624 }, mem_tbl_5705[] = {
9625 { 0x00000100, 0x0000c},
9626 { 0x00000200, 0x00008},
9627 { 0x00004000, 0x00800},
9628 { 0x00006000, 0x01000},
9629 { 0x00008000, 0x02000},
9630 { 0x00010000, 0x0e000},
9631 { 0xffffffff, 0x00000}
9632 }, mem_tbl_5755[] = {
9633 { 0x00000200, 0x00008},
9634 { 0x00004000, 0x00800},
9635 { 0x00006000, 0x00800},
9636 { 0x00008000, 0x02000},
9637 { 0x00010000, 0x0c000},
9638 { 0xffffffff, 0x00000}
9639 }, mem_tbl_5906[] = {
9640 { 0x00000200, 0x00008},
9641 { 0x00004000, 0x00400},
9642 { 0x00006000, 0x00400},
9643 { 0x00008000, 0x01000},
9644 { 0x00010000, 0x01000},
9645 { 0xffffffff, 0x00000}
9646 };
9647 struct mem_entry *mem_tbl;
9648 int err = 0;
9649 int i;
9650
9651 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9652 mem_tbl = mem_tbl_5755;
9653 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9654 mem_tbl = mem_tbl_5906;
9655 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9656 mem_tbl = mem_tbl_5705;
9657 else
9658 mem_tbl = mem_tbl_570x;
9659
9660 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9661 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9662 mem_tbl[i].len)) != 0)
9663 break;
9664 }
9665
9666 return err;
9667 }
9668
9669 #define TG3_MAC_LOOPBACK 0
9670 #define TG3_PHY_LOOPBACK 1
9671
9672 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9673 {
9674 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9675 u32 desc_idx;
9676 struct sk_buff *skb, *rx_skb;
9677 u8 *tx_data;
9678 dma_addr_t map;
9679 int num_pkts, tx_len, rx_len, i, err;
9680 struct tg3_rx_buffer_desc *desc;
9681
9682 if (loopback_mode == TG3_MAC_LOOPBACK) {
9683 /* HW errata - mac loopback fails in some cases on 5780.
9684 * Normal traffic and PHY loopback are not affected by
9685 * errata.
9686 */
9687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9688 return 0;
9689
9690 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9691 MAC_MODE_PORT_INT_LPBACK;
9692 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9693 mac_mode |= MAC_MODE_LINK_POLARITY;
9694 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9695 mac_mode |= MAC_MODE_PORT_MODE_MII;
9696 else
9697 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9698 tw32(MAC_MODE, mac_mode);
9699 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9700 u32 val;
9701
9702 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9703 u32 phytest;
9704
9705 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9706 u32 phy;
9707
9708 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9709 phytest | MII_TG3_EPHY_SHADOW_EN);
9710 if (!tg3_readphy(tp, 0x1b, &phy))
9711 tg3_writephy(tp, 0x1b, phy & ~0x20);
9712 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9713 }
9714 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9715 } else
9716 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9717
9718 tg3_phy_toggle_automdix(tp, 0);
9719
9720 tg3_writephy(tp, MII_BMCR, val);
9721 udelay(40);
9722
9723 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9724 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9725 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9726 mac_mode |= MAC_MODE_PORT_MODE_MII;
9727 } else
9728 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9729
9730 /* reset to prevent losing 1st rx packet intermittently */
9731 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9732 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9733 udelay(10);
9734 tw32_f(MAC_RX_MODE, tp->rx_mode);
9735 }
9736 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9737 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9738 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9739 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9740 mac_mode |= MAC_MODE_LINK_POLARITY;
9741 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9742 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9743 }
9744 tw32(MAC_MODE, mac_mode);
9745 }
9746 else
9747 return -EINVAL;
9748
9749 err = -EIO;
9750
9751 tx_len = 1514;
9752 skb = netdev_alloc_skb(tp->dev, tx_len);
9753 if (!skb)
9754 return -ENOMEM;
9755
9756 tx_data = skb_put(skb, tx_len);
9757 memcpy(tx_data, tp->dev->dev_addr, 6);
9758 memset(tx_data + 6, 0x0, 8);
9759
9760 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9761
9762 for (i = 14; i < tx_len; i++)
9763 tx_data[i] = (u8) (i & 0xff);
9764
9765 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9766
9767 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9768 HOSTCC_MODE_NOW);
9769
9770 udelay(10);
9771
9772 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9773
9774 num_pkts = 0;
9775
9776 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9777
9778 tp->tx_prod++;
9779 num_pkts++;
9780
9781 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9782 tp->tx_prod);
9783 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9784
9785 udelay(10);
9786
9787 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9788 for (i = 0; i < 25; i++) {
9789 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9790 HOSTCC_MODE_NOW);
9791
9792 udelay(10);
9793
9794 tx_idx = tp->hw_status->idx[0].tx_consumer;
9795 rx_idx = tp->hw_status->idx[0].rx_producer;
9796 if ((tx_idx == tp->tx_prod) &&
9797 (rx_idx == (rx_start_idx + num_pkts)))
9798 break;
9799 }
9800
9801 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9802 dev_kfree_skb(skb);
9803
9804 if (tx_idx != tp->tx_prod)
9805 goto out;
9806
9807 if (rx_idx != rx_start_idx + num_pkts)
9808 goto out;
9809
9810 desc = &tp->rx_rcb[rx_start_idx];
9811 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9812 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9813 if (opaque_key != RXD_OPAQUE_RING_STD)
9814 goto out;
9815
9816 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9817 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9818 goto out;
9819
9820 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9821 if (rx_len != tx_len)
9822 goto out;
9823
9824 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9825
9826 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9827 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9828
9829 for (i = 14; i < tx_len; i++) {
9830 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9831 goto out;
9832 }
9833 err = 0;
9834
9835 /* tg3_free_rings will unmap and free the rx_skb */
9836 out:
9837 return err;
9838 }
9839
9840 #define TG3_MAC_LOOPBACK_FAILED 1
9841 #define TG3_PHY_LOOPBACK_FAILED 2
9842 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9843 TG3_PHY_LOOPBACK_FAILED)
9844
9845 static int tg3_test_loopback(struct tg3 *tp)
9846 {
9847 int err = 0;
9848 u32 cpmuctrl = 0;
9849
9850 if (!netif_running(tp->dev))
9851 return TG3_LOOPBACK_FAILED;
9852
9853 err = tg3_reset_hw(tp, 1);
9854 if (err)
9855 return TG3_LOOPBACK_FAILED;
9856
9857 /* Turn off gphy autopowerdown. */
9858 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9859 tg3_phy_toggle_apd(tp, false);
9860
9861 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9862 int i;
9863 u32 status;
9864
9865 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9866
9867 /* Wait for up to 40 microseconds to acquire lock. */
9868 for (i = 0; i < 4; i++) {
9869 status = tr32(TG3_CPMU_MUTEX_GNT);
9870 if (status == CPMU_MUTEX_GNT_DRIVER)
9871 break;
9872 udelay(10);
9873 }
9874
9875 if (status != CPMU_MUTEX_GNT_DRIVER)
9876 return TG3_LOOPBACK_FAILED;
9877
9878 /* Turn off link-based power management. */
9879 cpmuctrl = tr32(TG3_CPMU_CTRL);
9880 tw32(TG3_CPMU_CTRL,
9881 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9882 CPMU_CTRL_LINK_AWARE_MODE));
9883 }
9884
9885 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9886 err |= TG3_MAC_LOOPBACK_FAILED;
9887
9888 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9889 tw32(TG3_CPMU_CTRL, cpmuctrl);
9890
9891 /* Release the mutex */
9892 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9893 }
9894
9895 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9896 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9897 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9898 err |= TG3_PHY_LOOPBACK_FAILED;
9899 }
9900
9901 /* Re-enable gphy autopowerdown. */
9902 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9903 tg3_phy_toggle_apd(tp, true);
9904
9905 return err;
9906 }
9907
9908 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9909 u64 *data)
9910 {
9911 struct tg3 *tp = netdev_priv(dev);
9912
9913 if (tp->link_config.phy_is_low_power)
9914 tg3_set_power_state(tp, PCI_D0);
9915
9916 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9917
9918 if (tg3_test_nvram(tp) != 0) {
9919 etest->flags |= ETH_TEST_FL_FAILED;
9920 data[0] = 1;
9921 }
9922 if (tg3_test_link(tp) != 0) {
9923 etest->flags |= ETH_TEST_FL_FAILED;
9924 data[1] = 1;
9925 }
9926 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9927 int err, err2 = 0, irq_sync = 0;
9928
9929 if (netif_running(dev)) {
9930 tg3_phy_stop(tp);
9931 tg3_netif_stop(tp);
9932 irq_sync = 1;
9933 }
9934
9935 tg3_full_lock(tp, irq_sync);
9936
9937 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9938 err = tg3_nvram_lock(tp);
9939 tg3_halt_cpu(tp, RX_CPU_BASE);
9940 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9941 tg3_halt_cpu(tp, TX_CPU_BASE);
9942 if (!err)
9943 tg3_nvram_unlock(tp);
9944
9945 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9946 tg3_phy_reset(tp);
9947
9948 if (tg3_test_registers(tp) != 0) {
9949 etest->flags |= ETH_TEST_FL_FAILED;
9950 data[2] = 1;
9951 }
9952 if (tg3_test_memory(tp) != 0) {
9953 etest->flags |= ETH_TEST_FL_FAILED;
9954 data[3] = 1;
9955 }
9956 if ((data[4] = tg3_test_loopback(tp)) != 0)
9957 etest->flags |= ETH_TEST_FL_FAILED;
9958
9959 tg3_full_unlock(tp);
9960
9961 if (tg3_test_interrupt(tp) != 0) {
9962 etest->flags |= ETH_TEST_FL_FAILED;
9963 data[5] = 1;
9964 }
9965
9966 tg3_full_lock(tp, 0);
9967
9968 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9969 if (netif_running(dev)) {
9970 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9971 err2 = tg3_restart_hw(tp, 1);
9972 if (!err2)
9973 tg3_netif_start(tp);
9974 }
9975
9976 tg3_full_unlock(tp);
9977
9978 if (irq_sync && !err2)
9979 tg3_phy_start(tp);
9980 }
9981 if (tp->link_config.phy_is_low_power)
9982 tg3_set_power_state(tp, PCI_D3hot);
9983
9984 }
9985
9986 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9987 {
9988 struct mii_ioctl_data *data = if_mii(ifr);
9989 struct tg3 *tp = netdev_priv(dev);
9990 int err;
9991
9992 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9993 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9994 return -EAGAIN;
9995 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
9996 }
9997
9998 switch(cmd) {
9999 case SIOCGMIIPHY:
10000 data->phy_id = PHY_ADDR;
10001
10002 /* fallthru */
10003 case SIOCGMIIREG: {
10004 u32 mii_regval;
10005
10006 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10007 break; /* We have no PHY */
10008
10009 if (tp->link_config.phy_is_low_power)
10010 return -EAGAIN;
10011
10012 spin_lock_bh(&tp->lock);
10013 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10014 spin_unlock_bh(&tp->lock);
10015
10016 data->val_out = mii_regval;
10017
10018 return err;
10019 }
10020
10021 case SIOCSMIIREG:
10022 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10023 break; /* We have no PHY */
10024
10025 if (!capable(CAP_NET_ADMIN))
10026 return -EPERM;
10027
10028 if (tp->link_config.phy_is_low_power)
10029 return -EAGAIN;
10030
10031 spin_lock_bh(&tp->lock);
10032 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10033 spin_unlock_bh(&tp->lock);
10034
10035 return err;
10036
10037 default:
10038 /* do nothing */
10039 break;
10040 }
10041 return -EOPNOTSUPP;
10042 }
10043
10044 #if TG3_VLAN_TAG_USED
10045 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10046 {
10047 struct tg3 *tp = netdev_priv(dev);
10048
10049 if (!netif_running(dev)) {
10050 tp->vlgrp = grp;
10051 return;
10052 }
10053
10054 tg3_netif_stop(tp);
10055
10056 tg3_full_lock(tp, 0);
10057
10058 tp->vlgrp = grp;
10059
10060 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10061 __tg3_set_rx_mode(dev);
10062
10063 tg3_netif_start(tp);
10064
10065 tg3_full_unlock(tp);
10066 }
10067 #endif
10068
10069 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10070 {
10071 struct tg3 *tp = netdev_priv(dev);
10072
10073 memcpy(ec, &tp->coal, sizeof(*ec));
10074 return 0;
10075 }
10076
10077 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10078 {
10079 struct tg3 *tp = netdev_priv(dev);
10080 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10081 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10082
10083 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10084 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10085 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10086 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10087 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10088 }
10089
10090 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10091 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10092 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10093 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10094 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10095 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10096 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10097 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10098 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10099 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10100 return -EINVAL;
10101
10102 /* No rx interrupts will be generated if both are zero */
10103 if ((ec->rx_coalesce_usecs == 0) &&
10104 (ec->rx_max_coalesced_frames == 0))
10105 return -EINVAL;
10106
10107 /* No tx interrupts will be generated if both are zero */
10108 if ((ec->tx_coalesce_usecs == 0) &&
10109 (ec->tx_max_coalesced_frames == 0))
10110 return -EINVAL;
10111
10112 /* Only copy relevant parameters, ignore all others. */
10113 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10114 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10115 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10116 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10117 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10118 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10119 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10120 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10121 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10122
10123 if (netif_running(dev)) {
10124 tg3_full_lock(tp, 0);
10125 __tg3_set_coalesce(tp, &tp->coal);
10126 tg3_full_unlock(tp);
10127 }
10128 return 0;
10129 }
10130
10131 static const struct ethtool_ops tg3_ethtool_ops = {
10132 .get_settings = tg3_get_settings,
10133 .set_settings = tg3_set_settings,
10134 .get_drvinfo = tg3_get_drvinfo,
10135 .get_regs_len = tg3_get_regs_len,
10136 .get_regs = tg3_get_regs,
10137 .get_wol = tg3_get_wol,
10138 .set_wol = tg3_set_wol,
10139 .get_msglevel = tg3_get_msglevel,
10140 .set_msglevel = tg3_set_msglevel,
10141 .nway_reset = tg3_nway_reset,
10142 .get_link = ethtool_op_get_link,
10143 .get_eeprom_len = tg3_get_eeprom_len,
10144 .get_eeprom = tg3_get_eeprom,
10145 .set_eeprom = tg3_set_eeprom,
10146 .get_ringparam = tg3_get_ringparam,
10147 .set_ringparam = tg3_set_ringparam,
10148 .get_pauseparam = tg3_get_pauseparam,
10149 .set_pauseparam = tg3_set_pauseparam,
10150 .get_rx_csum = tg3_get_rx_csum,
10151 .set_rx_csum = tg3_set_rx_csum,
10152 .set_tx_csum = tg3_set_tx_csum,
10153 .set_sg = ethtool_op_set_sg,
10154 .set_tso = tg3_set_tso,
10155 .self_test = tg3_self_test,
10156 .get_strings = tg3_get_strings,
10157 .phys_id = tg3_phys_id,
10158 .get_ethtool_stats = tg3_get_ethtool_stats,
10159 .get_coalesce = tg3_get_coalesce,
10160 .set_coalesce = tg3_set_coalesce,
10161 .get_sset_count = tg3_get_sset_count,
10162 };
10163
10164 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10165 {
10166 u32 cursize, val, magic;
10167
10168 tp->nvram_size = EEPROM_CHIP_SIZE;
10169
10170 if (tg3_nvram_read(tp, 0, &magic) != 0)
10171 return;
10172
10173 if ((magic != TG3_EEPROM_MAGIC) &&
10174 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10175 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10176 return;
10177
10178 /*
10179 * Size the chip by reading offsets at increasing powers of two.
10180 * When we encounter our validation signature, we know the addressing
10181 * has wrapped around, and thus have our chip size.
10182 */
10183 cursize = 0x10;
10184
10185 while (cursize < tp->nvram_size) {
10186 if (tg3_nvram_read(tp, cursize, &val) != 0)
10187 return;
10188
10189 if (val == magic)
10190 break;
10191
10192 cursize <<= 1;
10193 }
10194
10195 tp->nvram_size = cursize;
10196 }
10197
10198 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10199 {
10200 u32 val;
10201
10202 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10203 tg3_nvram_read(tp, 0, &val) != 0)
10204 return;
10205
10206 /* Selfboot format */
10207 if (val != TG3_EEPROM_MAGIC) {
10208 tg3_get_eeprom_size(tp);
10209 return;
10210 }
10211
10212 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10213 if (val != 0) {
10214 /* This is confusing. We want to operate on the
10215 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10216 * call will read from NVRAM and byteswap the data
10217 * according to the byteswapping settings for all
10218 * other register accesses. This ensures the data we
10219 * want will always reside in the lower 16-bits.
10220 * However, the data in NVRAM is in LE format, which
10221 * means the data from the NVRAM read will always be
10222 * opposite the endianness of the CPU. The 16-bit
10223 * byteswap then brings the data to CPU endianness.
10224 */
10225 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10226 return;
10227 }
10228 }
10229 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10230 }
10231
10232 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10233 {
10234 u32 nvcfg1;
10235
10236 nvcfg1 = tr32(NVRAM_CFG1);
10237 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10238 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10239 }
10240 else {
10241 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10242 tw32(NVRAM_CFG1, nvcfg1);
10243 }
10244
10245 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10246 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10247 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10248 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10249 tp->nvram_jedecnum = JEDEC_ATMEL;
10250 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10251 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10252 break;
10253 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10254 tp->nvram_jedecnum = JEDEC_ATMEL;
10255 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10256 break;
10257 case FLASH_VENDOR_ATMEL_EEPROM:
10258 tp->nvram_jedecnum = JEDEC_ATMEL;
10259 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10260 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10261 break;
10262 case FLASH_VENDOR_ST:
10263 tp->nvram_jedecnum = JEDEC_ST;
10264 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10265 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10266 break;
10267 case FLASH_VENDOR_SAIFUN:
10268 tp->nvram_jedecnum = JEDEC_SAIFUN;
10269 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10270 break;
10271 case FLASH_VENDOR_SST_SMALL:
10272 case FLASH_VENDOR_SST_LARGE:
10273 tp->nvram_jedecnum = JEDEC_SST;
10274 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10275 break;
10276 }
10277 }
10278 else {
10279 tp->nvram_jedecnum = JEDEC_ATMEL;
10280 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10281 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10282 }
10283 }
10284
10285 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10286 {
10287 u32 nvcfg1;
10288
10289 nvcfg1 = tr32(NVRAM_CFG1);
10290
10291 /* NVRAM protection for TPM */
10292 if (nvcfg1 & (1 << 27))
10293 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10294
10295 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10296 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10297 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10298 tp->nvram_jedecnum = JEDEC_ATMEL;
10299 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10300 break;
10301 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10302 tp->nvram_jedecnum = JEDEC_ATMEL;
10303 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10304 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10305 break;
10306 case FLASH_5752VENDOR_ST_M45PE10:
10307 case FLASH_5752VENDOR_ST_M45PE20:
10308 case FLASH_5752VENDOR_ST_M45PE40:
10309 tp->nvram_jedecnum = JEDEC_ST;
10310 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10311 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10312 break;
10313 }
10314
10315 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10316 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10317 case FLASH_5752PAGE_SIZE_256:
10318 tp->nvram_pagesize = 256;
10319 break;
10320 case FLASH_5752PAGE_SIZE_512:
10321 tp->nvram_pagesize = 512;
10322 break;
10323 case FLASH_5752PAGE_SIZE_1K:
10324 tp->nvram_pagesize = 1024;
10325 break;
10326 case FLASH_5752PAGE_SIZE_2K:
10327 tp->nvram_pagesize = 2048;
10328 break;
10329 case FLASH_5752PAGE_SIZE_4K:
10330 tp->nvram_pagesize = 4096;
10331 break;
10332 case FLASH_5752PAGE_SIZE_264:
10333 tp->nvram_pagesize = 264;
10334 break;
10335 }
10336 }
10337 else {
10338 /* For eeprom, set pagesize to maximum eeprom size */
10339 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10340
10341 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10342 tw32(NVRAM_CFG1, nvcfg1);
10343 }
10344 }
10345
10346 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10347 {
10348 u32 nvcfg1, protect = 0;
10349
10350 nvcfg1 = tr32(NVRAM_CFG1);
10351
10352 /* NVRAM protection for TPM */
10353 if (nvcfg1 & (1 << 27)) {
10354 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10355 protect = 1;
10356 }
10357
10358 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10359 switch (nvcfg1) {
10360 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10361 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10362 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10363 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10364 tp->nvram_jedecnum = JEDEC_ATMEL;
10365 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10366 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10367 tp->nvram_pagesize = 264;
10368 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10369 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10370 tp->nvram_size = (protect ? 0x3e200 :
10371 TG3_NVRAM_SIZE_512KB);
10372 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10373 tp->nvram_size = (protect ? 0x1f200 :
10374 TG3_NVRAM_SIZE_256KB);
10375 else
10376 tp->nvram_size = (protect ? 0x1f200 :
10377 TG3_NVRAM_SIZE_128KB);
10378 break;
10379 case FLASH_5752VENDOR_ST_M45PE10:
10380 case FLASH_5752VENDOR_ST_M45PE20:
10381 case FLASH_5752VENDOR_ST_M45PE40:
10382 tp->nvram_jedecnum = JEDEC_ST;
10383 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10384 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10385 tp->nvram_pagesize = 256;
10386 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10387 tp->nvram_size = (protect ?
10388 TG3_NVRAM_SIZE_64KB :
10389 TG3_NVRAM_SIZE_128KB);
10390 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10391 tp->nvram_size = (protect ?
10392 TG3_NVRAM_SIZE_64KB :
10393 TG3_NVRAM_SIZE_256KB);
10394 else
10395 tp->nvram_size = (protect ?
10396 TG3_NVRAM_SIZE_128KB :
10397 TG3_NVRAM_SIZE_512KB);
10398 break;
10399 }
10400 }
10401
10402 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10403 {
10404 u32 nvcfg1;
10405
10406 nvcfg1 = tr32(NVRAM_CFG1);
10407
10408 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10409 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10410 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10411 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10412 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10413 tp->nvram_jedecnum = JEDEC_ATMEL;
10414 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10415 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10416
10417 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10418 tw32(NVRAM_CFG1, nvcfg1);
10419 break;
10420 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10421 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10422 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10423 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10424 tp->nvram_jedecnum = JEDEC_ATMEL;
10425 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10426 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10427 tp->nvram_pagesize = 264;
10428 break;
10429 case FLASH_5752VENDOR_ST_M45PE10:
10430 case FLASH_5752VENDOR_ST_M45PE20:
10431 case FLASH_5752VENDOR_ST_M45PE40:
10432 tp->nvram_jedecnum = JEDEC_ST;
10433 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10434 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10435 tp->nvram_pagesize = 256;
10436 break;
10437 }
10438 }
10439
10440 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10441 {
10442 u32 nvcfg1, protect = 0;
10443
10444 nvcfg1 = tr32(NVRAM_CFG1);
10445
10446 /* NVRAM protection for TPM */
10447 if (nvcfg1 & (1 << 27)) {
10448 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10449 protect = 1;
10450 }
10451
10452 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10453 switch (nvcfg1) {
10454 case FLASH_5761VENDOR_ATMEL_ADB021D:
10455 case FLASH_5761VENDOR_ATMEL_ADB041D:
10456 case FLASH_5761VENDOR_ATMEL_ADB081D:
10457 case FLASH_5761VENDOR_ATMEL_ADB161D:
10458 case FLASH_5761VENDOR_ATMEL_MDB021D:
10459 case FLASH_5761VENDOR_ATMEL_MDB041D:
10460 case FLASH_5761VENDOR_ATMEL_MDB081D:
10461 case FLASH_5761VENDOR_ATMEL_MDB161D:
10462 tp->nvram_jedecnum = JEDEC_ATMEL;
10463 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10464 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10465 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10466 tp->nvram_pagesize = 256;
10467 break;
10468 case FLASH_5761VENDOR_ST_A_M45PE20:
10469 case FLASH_5761VENDOR_ST_A_M45PE40:
10470 case FLASH_5761VENDOR_ST_A_M45PE80:
10471 case FLASH_5761VENDOR_ST_A_M45PE16:
10472 case FLASH_5761VENDOR_ST_M_M45PE20:
10473 case FLASH_5761VENDOR_ST_M_M45PE40:
10474 case FLASH_5761VENDOR_ST_M_M45PE80:
10475 case FLASH_5761VENDOR_ST_M_M45PE16:
10476 tp->nvram_jedecnum = JEDEC_ST;
10477 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10478 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10479 tp->nvram_pagesize = 256;
10480 break;
10481 }
10482
10483 if (protect) {
10484 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10485 } else {
10486 switch (nvcfg1) {
10487 case FLASH_5761VENDOR_ATMEL_ADB161D:
10488 case FLASH_5761VENDOR_ATMEL_MDB161D:
10489 case FLASH_5761VENDOR_ST_A_M45PE16:
10490 case FLASH_5761VENDOR_ST_M_M45PE16:
10491 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10492 break;
10493 case FLASH_5761VENDOR_ATMEL_ADB081D:
10494 case FLASH_5761VENDOR_ATMEL_MDB081D:
10495 case FLASH_5761VENDOR_ST_A_M45PE80:
10496 case FLASH_5761VENDOR_ST_M_M45PE80:
10497 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10498 break;
10499 case FLASH_5761VENDOR_ATMEL_ADB041D:
10500 case FLASH_5761VENDOR_ATMEL_MDB041D:
10501 case FLASH_5761VENDOR_ST_A_M45PE40:
10502 case FLASH_5761VENDOR_ST_M_M45PE40:
10503 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10504 break;
10505 case FLASH_5761VENDOR_ATMEL_ADB021D:
10506 case FLASH_5761VENDOR_ATMEL_MDB021D:
10507 case FLASH_5761VENDOR_ST_A_M45PE20:
10508 case FLASH_5761VENDOR_ST_M_M45PE20:
10509 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10510 break;
10511 }
10512 }
10513 }
10514
10515 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10516 {
10517 tp->nvram_jedecnum = JEDEC_ATMEL;
10518 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10519 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10520 }
10521
10522 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10523 {
10524 u32 nvcfg1;
10525
10526 nvcfg1 = tr32(NVRAM_CFG1);
10527
10528 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10529 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10530 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10531 tp->nvram_jedecnum = JEDEC_ATMEL;
10532 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10533 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10534
10535 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10536 tw32(NVRAM_CFG1, nvcfg1);
10537 return;
10538 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10539 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10540 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10541 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10542 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10543 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10544 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10545 tp->nvram_jedecnum = JEDEC_ATMEL;
10546 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10547 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10548
10549 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10550 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10551 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10552 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10553 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10554 break;
10555 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10556 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10557 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10558 break;
10559 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10560 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10561 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10562 break;
10563 }
10564 break;
10565 case FLASH_5752VENDOR_ST_M45PE10:
10566 case FLASH_5752VENDOR_ST_M45PE20:
10567 case FLASH_5752VENDOR_ST_M45PE40:
10568 tp->nvram_jedecnum = JEDEC_ST;
10569 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10570 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10571
10572 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10573 case FLASH_5752VENDOR_ST_M45PE10:
10574 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10575 break;
10576 case FLASH_5752VENDOR_ST_M45PE20:
10577 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10578 break;
10579 case FLASH_5752VENDOR_ST_M45PE40:
10580 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10581 break;
10582 }
10583 break;
10584 default:
10585 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
10586 return;
10587 }
10588
10589 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10590 case FLASH_5752PAGE_SIZE_256:
10591 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10592 tp->nvram_pagesize = 256;
10593 break;
10594 case FLASH_5752PAGE_SIZE_512:
10595 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10596 tp->nvram_pagesize = 512;
10597 break;
10598 case FLASH_5752PAGE_SIZE_1K:
10599 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10600 tp->nvram_pagesize = 1024;
10601 break;
10602 case FLASH_5752PAGE_SIZE_2K:
10603 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10604 tp->nvram_pagesize = 2048;
10605 break;
10606 case FLASH_5752PAGE_SIZE_4K:
10607 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10608 tp->nvram_pagesize = 4096;
10609 break;
10610 case FLASH_5752PAGE_SIZE_264:
10611 tp->nvram_pagesize = 264;
10612 break;
10613 case FLASH_5752PAGE_SIZE_528:
10614 tp->nvram_pagesize = 528;
10615 break;
10616 }
10617 }
10618
10619 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10620 static void __devinit tg3_nvram_init(struct tg3 *tp)
10621 {
10622 tw32_f(GRC_EEPROM_ADDR,
10623 (EEPROM_ADDR_FSM_RESET |
10624 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10625 EEPROM_ADDR_CLKPERD_SHIFT)));
10626
10627 msleep(1);
10628
10629 /* Enable seeprom accesses. */
10630 tw32_f(GRC_LOCAL_CTRL,
10631 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10632 udelay(100);
10633
10634 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10635 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10636 tp->tg3_flags |= TG3_FLAG_NVRAM;
10637
10638 if (tg3_nvram_lock(tp)) {
10639 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10640 "tg3_nvram_init failed.\n", tp->dev->name);
10641 return;
10642 }
10643 tg3_enable_nvram_access(tp);
10644
10645 tp->nvram_size = 0;
10646
10647 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10648 tg3_get_5752_nvram_info(tp);
10649 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10650 tg3_get_5755_nvram_info(tp);
10651 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10652 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10653 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10654 tg3_get_5787_nvram_info(tp);
10655 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10656 tg3_get_5761_nvram_info(tp);
10657 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10658 tg3_get_5906_nvram_info(tp);
10659 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10660 tg3_get_57780_nvram_info(tp);
10661 else
10662 tg3_get_nvram_info(tp);
10663
10664 if (tp->nvram_size == 0)
10665 tg3_get_nvram_size(tp);
10666
10667 tg3_disable_nvram_access(tp);
10668 tg3_nvram_unlock(tp);
10669
10670 } else {
10671 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10672
10673 tg3_get_eeprom_size(tp);
10674 }
10675 }
10676
10677 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10678 u32 offset, u32 len, u8 *buf)
10679 {
10680 int i, j, rc = 0;
10681 u32 val;
10682
10683 for (i = 0; i < len; i += 4) {
10684 u32 addr;
10685 __be32 data;
10686
10687 addr = offset + i;
10688
10689 memcpy(&data, buf + i, 4);
10690
10691 /*
10692 * The SEEPROM interface expects the data to always be opposite
10693 * the native endian format. We accomplish this by reversing
10694 * all the operations that would have been performed on the
10695 * data from a call to tg3_nvram_read_be32().
10696 */
10697 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
10698
10699 val = tr32(GRC_EEPROM_ADDR);
10700 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10701
10702 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10703 EEPROM_ADDR_READ);
10704 tw32(GRC_EEPROM_ADDR, val |
10705 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10706 (addr & EEPROM_ADDR_ADDR_MASK) |
10707 EEPROM_ADDR_START |
10708 EEPROM_ADDR_WRITE);
10709
10710 for (j = 0; j < 1000; j++) {
10711 val = tr32(GRC_EEPROM_ADDR);
10712
10713 if (val & EEPROM_ADDR_COMPLETE)
10714 break;
10715 msleep(1);
10716 }
10717 if (!(val & EEPROM_ADDR_COMPLETE)) {
10718 rc = -EBUSY;
10719 break;
10720 }
10721 }
10722
10723 return rc;
10724 }
10725
10726 /* offset and length are dword aligned */
10727 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10728 u8 *buf)
10729 {
10730 int ret = 0;
10731 u32 pagesize = tp->nvram_pagesize;
10732 u32 pagemask = pagesize - 1;
10733 u32 nvram_cmd;
10734 u8 *tmp;
10735
10736 tmp = kmalloc(pagesize, GFP_KERNEL);
10737 if (tmp == NULL)
10738 return -ENOMEM;
10739
10740 while (len) {
10741 int j;
10742 u32 phy_addr, page_off, size;
10743
10744 phy_addr = offset & ~pagemask;
10745
10746 for (j = 0; j < pagesize; j += 4) {
10747 ret = tg3_nvram_read_be32(tp, phy_addr + j,
10748 (__be32 *) (tmp + j));
10749 if (ret)
10750 break;
10751 }
10752 if (ret)
10753 break;
10754
10755 page_off = offset & pagemask;
10756 size = pagesize;
10757 if (len < size)
10758 size = len;
10759
10760 len -= size;
10761
10762 memcpy(tmp + page_off, buf, size);
10763
10764 offset = offset + (pagesize - page_off);
10765
10766 tg3_enable_nvram_access(tp);
10767
10768 /*
10769 * Before we can erase the flash page, we need
10770 * to issue a special "write enable" command.
10771 */
10772 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10773
10774 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10775 break;
10776
10777 /* Erase the target page */
10778 tw32(NVRAM_ADDR, phy_addr);
10779
10780 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10781 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10782
10783 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10784 break;
10785
10786 /* Issue another write enable to start the write. */
10787 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10788
10789 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10790 break;
10791
10792 for (j = 0; j < pagesize; j += 4) {
10793 __be32 data;
10794
10795 data = *((__be32 *) (tmp + j));
10796
10797 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10798
10799 tw32(NVRAM_ADDR, phy_addr + j);
10800
10801 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10802 NVRAM_CMD_WR;
10803
10804 if (j == 0)
10805 nvram_cmd |= NVRAM_CMD_FIRST;
10806 else if (j == (pagesize - 4))
10807 nvram_cmd |= NVRAM_CMD_LAST;
10808
10809 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10810 break;
10811 }
10812 if (ret)
10813 break;
10814 }
10815
10816 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10817 tg3_nvram_exec_cmd(tp, nvram_cmd);
10818
10819 kfree(tmp);
10820
10821 return ret;
10822 }
10823
10824 /* offset and length are dword aligned */
10825 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10826 u8 *buf)
10827 {
10828 int i, ret = 0;
10829
10830 for (i = 0; i < len; i += 4, offset += 4) {
10831 u32 page_off, phy_addr, nvram_cmd;
10832 __be32 data;
10833
10834 memcpy(&data, buf + i, 4);
10835 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10836
10837 page_off = offset % tp->nvram_pagesize;
10838
10839 phy_addr = tg3_nvram_phys_addr(tp, offset);
10840
10841 tw32(NVRAM_ADDR, phy_addr);
10842
10843 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10844
10845 if ((page_off == 0) || (i == 0))
10846 nvram_cmd |= NVRAM_CMD_FIRST;
10847 if (page_off == (tp->nvram_pagesize - 4))
10848 nvram_cmd |= NVRAM_CMD_LAST;
10849
10850 if (i == (len - 4))
10851 nvram_cmd |= NVRAM_CMD_LAST;
10852
10853 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10854 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10855 (tp->nvram_jedecnum == JEDEC_ST) &&
10856 (nvram_cmd & NVRAM_CMD_FIRST)) {
10857
10858 if ((ret = tg3_nvram_exec_cmd(tp,
10859 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10860 NVRAM_CMD_DONE)))
10861
10862 break;
10863 }
10864 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10865 /* We always do complete word writes to eeprom. */
10866 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10867 }
10868
10869 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10870 break;
10871 }
10872 return ret;
10873 }
10874
10875 /* offset and length are dword aligned */
10876 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10877 {
10878 int ret;
10879
10880 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10881 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10882 ~GRC_LCLCTRL_GPIO_OUTPUT1);
10883 udelay(40);
10884 }
10885
10886 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10887 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10888 }
10889 else {
10890 u32 grc_mode;
10891
10892 ret = tg3_nvram_lock(tp);
10893 if (ret)
10894 return ret;
10895
10896 tg3_enable_nvram_access(tp);
10897 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10898 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10899 tw32(NVRAM_WRITE1, 0x406);
10900
10901 grc_mode = tr32(GRC_MODE);
10902 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10903
10904 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10905 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10906
10907 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10908 buf);
10909 }
10910 else {
10911 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10912 buf);
10913 }
10914
10915 grc_mode = tr32(GRC_MODE);
10916 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10917
10918 tg3_disable_nvram_access(tp);
10919 tg3_nvram_unlock(tp);
10920 }
10921
10922 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10923 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10924 udelay(40);
10925 }
10926
10927 return ret;
10928 }
10929
10930 struct subsys_tbl_ent {
10931 u16 subsys_vendor, subsys_devid;
10932 u32 phy_id;
10933 };
10934
10935 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10936 /* Broadcom boards. */
10937 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10938 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10939 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10940 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10941 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10942 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10943 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10944 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10945 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10946 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10947 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10948
10949 /* 3com boards. */
10950 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10951 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10952 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10953 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10954 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10955
10956 /* DELL boards. */
10957 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10958 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10959 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10960 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10961
10962 /* Compaq boards. */
10963 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10964 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10965 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10966 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10967 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10968
10969 /* IBM boards. */
10970 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10971 };
10972
10973 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10974 {
10975 int i;
10976
10977 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10978 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10979 tp->pdev->subsystem_vendor) &&
10980 (subsys_id_to_phy_id[i].subsys_devid ==
10981 tp->pdev->subsystem_device))
10982 return &subsys_id_to_phy_id[i];
10983 }
10984 return NULL;
10985 }
10986
10987 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10988 {
10989 u32 val;
10990 u16 pmcsr;
10991
10992 /* On some early chips the SRAM cannot be accessed in D3hot state,
10993 * so need make sure we're in D0.
10994 */
10995 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10996 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10997 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10998 msleep(1);
10999
11000 /* Make sure register accesses (indirect or otherwise)
11001 * will function correctly.
11002 */
11003 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11004 tp->misc_host_ctrl);
11005
11006 /* The memory arbiter has to be enabled in order for SRAM accesses
11007 * to succeed. Normally on powerup the tg3 chip firmware will make
11008 * sure it is enabled, but other entities such as system netboot
11009 * code might disable it.
11010 */
11011 val = tr32(MEMARB_MODE);
11012 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11013
11014 tp->phy_id = PHY_ID_INVALID;
11015 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11016
11017 /* Assume an onboard device and WOL capable by default. */
11018 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11019
11020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11021 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11022 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11023 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11024 }
11025 val = tr32(VCPU_CFGSHDW);
11026 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11027 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11028 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11029 (val & VCPU_CFGSHDW_WOL_MAGPKT))
11030 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11031 goto done;
11032 }
11033
11034 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11035 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11036 u32 nic_cfg, led_cfg;
11037 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11038 int eeprom_phy_serdes = 0;
11039
11040 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11041 tp->nic_sram_data_cfg = nic_cfg;
11042
11043 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11044 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11045 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11046 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11047 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11048 (ver > 0) && (ver < 0x100))
11049 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11050
11051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11052 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11053
11054 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11055 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11056 eeprom_phy_serdes = 1;
11057
11058 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11059 if (nic_phy_id != 0) {
11060 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11061 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11062
11063 eeprom_phy_id = (id1 >> 16) << 10;
11064 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11065 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11066 } else
11067 eeprom_phy_id = 0;
11068
11069 tp->phy_id = eeprom_phy_id;
11070 if (eeprom_phy_serdes) {
11071 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11072 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11073 else
11074 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11075 }
11076
11077 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11078 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11079 SHASTA_EXT_LED_MODE_MASK);
11080 else
11081 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11082
11083 switch (led_cfg) {
11084 default:
11085 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11086 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11087 break;
11088
11089 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11090 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11091 break;
11092
11093 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11094 tp->led_ctrl = LED_CTRL_MODE_MAC;
11095
11096 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11097 * read on some older 5700/5701 bootcode.
11098 */
11099 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11100 ASIC_REV_5700 ||
11101 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11102 ASIC_REV_5701)
11103 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11104
11105 break;
11106
11107 case SHASTA_EXT_LED_SHARED:
11108 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11109 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11110 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11111 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11112 LED_CTRL_MODE_PHY_2);
11113 break;
11114
11115 case SHASTA_EXT_LED_MAC:
11116 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11117 break;
11118
11119 case SHASTA_EXT_LED_COMBO:
11120 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11121 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11122 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11123 LED_CTRL_MODE_PHY_2);
11124 break;
11125
11126 }
11127
11128 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11129 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11130 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11131 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11132
11133 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11134 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11135
11136 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11137 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11138 if ((tp->pdev->subsystem_vendor ==
11139 PCI_VENDOR_ID_ARIMA) &&
11140 (tp->pdev->subsystem_device == 0x205a ||
11141 tp->pdev->subsystem_device == 0x2063))
11142 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11143 } else {
11144 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11145 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11146 }
11147
11148 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11149 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11150 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11151 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11152 }
11153
11154 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11155 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11156 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11157
11158 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11159 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11160 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11161
11162 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11163 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11164 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11165
11166 if (cfg2 & (1 << 17))
11167 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11168
11169 /* serdes signal pre-emphasis in register 0x590 set by */
11170 /* bootcode if bit 18 is set */
11171 if (cfg2 & (1 << 18))
11172 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11173
11174 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11175 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11176 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11177 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11178
11179 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11180 u32 cfg3;
11181
11182 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11183 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11184 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11185 }
11186
11187 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11188 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11189 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11190 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11191 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11192 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11193 }
11194 done:
11195 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11196 device_set_wakeup_enable(&tp->pdev->dev,
11197 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11198 }
11199
11200 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11201 {
11202 int i;
11203 u32 val;
11204
11205 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11206 tw32(OTP_CTRL, cmd);
11207
11208 /* Wait for up to 1 ms for command to execute. */
11209 for (i = 0; i < 100; i++) {
11210 val = tr32(OTP_STATUS);
11211 if (val & OTP_STATUS_CMD_DONE)
11212 break;
11213 udelay(10);
11214 }
11215
11216 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11217 }
11218
11219 /* Read the gphy configuration from the OTP region of the chip. The gphy
11220 * configuration is a 32-bit value that straddles the alignment boundary.
11221 * We do two 32-bit reads and then shift and merge the results.
11222 */
11223 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11224 {
11225 u32 bhalf_otp, thalf_otp;
11226
11227 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11228
11229 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11230 return 0;
11231
11232 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11233
11234 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11235 return 0;
11236
11237 thalf_otp = tr32(OTP_READ_DATA);
11238
11239 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11240
11241 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11242 return 0;
11243
11244 bhalf_otp = tr32(OTP_READ_DATA);
11245
11246 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11247 }
11248
11249 static int __devinit tg3_phy_probe(struct tg3 *tp)
11250 {
11251 u32 hw_phy_id_1, hw_phy_id_2;
11252 u32 hw_phy_id, hw_phy_id_masked;
11253 int err;
11254
11255 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11256 return tg3_phy_init(tp);
11257
11258 /* Reading the PHY ID register can conflict with ASF
11259 * firmware access to the PHY hardware.
11260 */
11261 err = 0;
11262 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11263 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11264 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11265 } else {
11266 /* Now read the physical PHY_ID from the chip and verify
11267 * that it is sane. If it doesn't look good, we fall back
11268 * to either the hard-coded table based PHY_ID and failing
11269 * that the value found in the eeprom area.
11270 */
11271 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11272 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11273
11274 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11275 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11276 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11277
11278 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11279 }
11280
11281 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11282 tp->phy_id = hw_phy_id;
11283 if (hw_phy_id_masked == PHY_ID_BCM8002)
11284 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11285 else
11286 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11287 } else {
11288 if (tp->phy_id != PHY_ID_INVALID) {
11289 /* Do nothing, phy ID already set up in
11290 * tg3_get_eeprom_hw_cfg().
11291 */
11292 } else {
11293 struct subsys_tbl_ent *p;
11294
11295 /* No eeprom signature? Try the hardcoded
11296 * subsys device table.
11297 */
11298 p = lookup_by_subsys(tp);
11299 if (!p)
11300 return -ENODEV;
11301
11302 tp->phy_id = p->phy_id;
11303 if (!tp->phy_id ||
11304 tp->phy_id == PHY_ID_BCM8002)
11305 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11306 }
11307 }
11308
11309 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11310 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11311 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11312 u32 bmsr, adv_reg, tg3_ctrl, mask;
11313
11314 tg3_readphy(tp, MII_BMSR, &bmsr);
11315 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11316 (bmsr & BMSR_LSTATUS))
11317 goto skip_phy_reset;
11318
11319 err = tg3_phy_reset(tp);
11320 if (err)
11321 return err;
11322
11323 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11324 ADVERTISE_100HALF | ADVERTISE_100FULL |
11325 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11326 tg3_ctrl = 0;
11327 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11328 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11329 MII_TG3_CTRL_ADV_1000_FULL);
11330 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11331 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11332 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11333 MII_TG3_CTRL_ENABLE_AS_MASTER);
11334 }
11335
11336 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11337 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11338 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11339 if (!tg3_copper_is_advertising_all(tp, mask)) {
11340 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11341
11342 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11343 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11344
11345 tg3_writephy(tp, MII_BMCR,
11346 BMCR_ANENABLE | BMCR_ANRESTART);
11347 }
11348 tg3_phy_set_wirespeed(tp);
11349
11350 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11351 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11352 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11353 }
11354
11355 skip_phy_reset:
11356 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11357 err = tg3_init_5401phy_dsp(tp);
11358 if (err)
11359 return err;
11360 }
11361
11362 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11363 err = tg3_init_5401phy_dsp(tp);
11364 }
11365
11366 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11367 tp->link_config.advertising =
11368 (ADVERTISED_1000baseT_Half |
11369 ADVERTISED_1000baseT_Full |
11370 ADVERTISED_Autoneg |
11371 ADVERTISED_FIBRE);
11372 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11373 tp->link_config.advertising &=
11374 ~(ADVERTISED_1000baseT_Half |
11375 ADVERTISED_1000baseT_Full);
11376
11377 return err;
11378 }
11379
11380 static void __devinit tg3_read_partno(struct tg3 *tp)
11381 {
11382 unsigned char vpd_data[256]; /* in little-endian format */
11383 unsigned int i;
11384 u32 magic;
11385
11386 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11387 tg3_nvram_read(tp, 0x0, &magic))
11388 goto out_not_found;
11389
11390 if (magic == TG3_EEPROM_MAGIC) {
11391 for (i = 0; i < 256; i += 4) {
11392 u32 tmp;
11393
11394 /* The data is in little-endian format in NVRAM.
11395 * Use the big-endian read routines to preserve
11396 * the byte order as it exists in NVRAM.
11397 */
11398 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
11399 goto out_not_found;
11400
11401 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
11402 }
11403 } else {
11404 int vpd_cap;
11405
11406 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11407 for (i = 0; i < 256; i += 4) {
11408 u32 tmp, j = 0;
11409 __le32 v;
11410 u16 tmp16;
11411
11412 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11413 i);
11414 while (j++ < 100) {
11415 pci_read_config_word(tp->pdev, vpd_cap +
11416 PCI_VPD_ADDR, &tmp16);
11417 if (tmp16 & 0x8000)
11418 break;
11419 msleep(1);
11420 }
11421 if (!(tmp16 & 0x8000))
11422 goto out_not_found;
11423
11424 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11425 &tmp);
11426 v = cpu_to_le32(tmp);
11427 memcpy(&vpd_data[i], &v, sizeof(v));
11428 }
11429 }
11430
11431 /* Now parse and find the part number. */
11432 for (i = 0; i < 254; ) {
11433 unsigned char val = vpd_data[i];
11434 unsigned int block_end;
11435
11436 if (val == 0x82 || val == 0x91) {
11437 i = (i + 3 +
11438 (vpd_data[i + 1] +
11439 (vpd_data[i + 2] << 8)));
11440 continue;
11441 }
11442
11443 if (val != 0x90)
11444 goto out_not_found;
11445
11446 block_end = (i + 3 +
11447 (vpd_data[i + 1] +
11448 (vpd_data[i + 2] << 8)));
11449 i += 3;
11450
11451 if (block_end > 256)
11452 goto out_not_found;
11453
11454 while (i < (block_end - 2)) {
11455 if (vpd_data[i + 0] == 'P' &&
11456 vpd_data[i + 1] == 'N') {
11457 int partno_len = vpd_data[i + 2];
11458
11459 i += 3;
11460 if (partno_len > 24 || (partno_len + i) > 256)
11461 goto out_not_found;
11462
11463 memcpy(tp->board_part_number,
11464 &vpd_data[i], partno_len);
11465
11466 /* Success. */
11467 return;
11468 }
11469 i += 3 + vpd_data[i + 2];
11470 }
11471
11472 /* Part number not found. */
11473 goto out_not_found;
11474 }
11475
11476 out_not_found:
11477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11478 strcpy(tp->board_part_number, "BCM95906");
11479 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11480 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
11481 strcpy(tp->board_part_number, "BCM57780");
11482 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11483 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
11484 strcpy(tp->board_part_number, "BCM57760");
11485 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
11486 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
11487 strcpy(tp->board_part_number, "BCM57790");
11488 else
11489 strcpy(tp->board_part_number, "none");
11490 }
11491
11492 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11493 {
11494 u32 val;
11495
11496 if (tg3_nvram_read(tp, offset, &val) ||
11497 (val & 0xfc000000) != 0x0c000000 ||
11498 tg3_nvram_read(tp, offset + 4, &val) ||
11499 val != 0)
11500 return 0;
11501
11502 return 1;
11503 }
11504
11505 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
11506 {
11507 u32 val, offset, start, ver_offset;
11508 int i;
11509 bool newver = false;
11510
11511 if (tg3_nvram_read(tp, 0xc, &offset) ||
11512 tg3_nvram_read(tp, 0x4, &start))
11513 return;
11514
11515 offset = tg3_nvram_logical_addr(tp, offset);
11516
11517 if (tg3_nvram_read(tp, offset, &val))
11518 return;
11519
11520 if ((val & 0xfc000000) == 0x0c000000) {
11521 if (tg3_nvram_read(tp, offset + 4, &val))
11522 return;
11523
11524 if (val == 0)
11525 newver = true;
11526 }
11527
11528 if (newver) {
11529 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
11530 return;
11531
11532 offset = offset + ver_offset - start;
11533 for (i = 0; i < 16; i += 4) {
11534 __be32 v;
11535 if (tg3_nvram_read_be32(tp, offset + i, &v))
11536 return;
11537
11538 memcpy(tp->fw_ver + i, &v, sizeof(v));
11539 }
11540 } else {
11541 u32 major, minor;
11542
11543 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
11544 return;
11545
11546 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
11547 TG3_NVM_BCVER_MAJSFT;
11548 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
11549 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
11550 }
11551 }
11552
11553 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
11554 {
11555 u32 val, major, minor;
11556
11557 /* Use native endian representation */
11558 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
11559 return;
11560
11561 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
11562 TG3_NVM_HWSB_CFG1_MAJSFT;
11563 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
11564 TG3_NVM_HWSB_CFG1_MINSFT;
11565
11566 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
11567 }
11568
11569 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11570 {
11571 u32 offset, major, minor, build;
11572
11573 tp->fw_ver[0] = 's';
11574 tp->fw_ver[1] = 'b';
11575 tp->fw_ver[2] = '\0';
11576
11577 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11578 return;
11579
11580 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11581 case TG3_EEPROM_SB_REVISION_0:
11582 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11583 break;
11584 case TG3_EEPROM_SB_REVISION_2:
11585 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11586 break;
11587 case TG3_EEPROM_SB_REVISION_3:
11588 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11589 break;
11590 default:
11591 return;
11592 }
11593
11594 if (tg3_nvram_read(tp, offset, &val))
11595 return;
11596
11597 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11598 TG3_EEPROM_SB_EDH_BLD_SHFT;
11599 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11600 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11601 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11602
11603 if (minor > 99 || build > 26)
11604 return;
11605
11606 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11607
11608 if (build > 0) {
11609 tp->fw_ver[8] = 'a' + build - 1;
11610 tp->fw_ver[9] = '\0';
11611 }
11612 }
11613
11614 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
11615 {
11616 u32 val, offset, start;
11617 int i, vlen;
11618
11619 for (offset = TG3_NVM_DIR_START;
11620 offset < TG3_NVM_DIR_END;
11621 offset += TG3_NVM_DIRENT_SIZE) {
11622 if (tg3_nvram_read(tp, offset, &val))
11623 return;
11624
11625 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11626 break;
11627 }
11628
11629 if (offset == TG3_NVM_DIR_END)
11630 return;
11631
11632 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11633 start = 0x08000000;
11634 else if (tg3_nvram_read(tp, offset - 4, &start))
11635 return;
11636
11637 if (tg3_nvram_read(tp, offset + 4, &offset) ||
11638 !tg3_fw_img_is_valid(tp, offset) ||
11639 tg3_nvram_read(tp, offset + 8, &val))
11640 return;
11641
11642 offset += val - start;
11643
11644 vlen = strlen(tp->fw_ver);
11645
11646 tp->fw_ver[vlen++] = ',';
11647 tp->fw_ver[vlen++] = ' ';
11648
11649 for (i = 0; i < 4; i++) {
11650 __be32 v;
11651 if (tg3_nvram_read_be32(tp, offset, &v))
11652 return;
11653
11654 offset += sizeof(v);
11655
11656 if (vlen > TG3_VER_SIZE - sizeof(v)) {
11657 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
11658 break;
11659 }
11660
11661 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
11662 vlen += sizeof(v);
11663 }
11664 }
11665
11666 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
11667 {
11668 int vlen;
11669 u32 apedata;
11670
11671 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
11672 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
11673 return;
11674
11675 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
11676 if (apedata != APE_SEG_SIG_MAGIC)
11677 return;
11678
11679 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
11680 if (!(apedata & APE_FW_STATUS_READY))
11681 return;
11682
11683 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
11684
11685 vlen = strlen(tp->fw_ver);
11686
11687 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
11688 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
11689 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
11690 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
11691 (apedata & APE_FW_VERSION_BLDMSK));
11692 }
11693
11694 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11695 {
11696 u32 val;
11697
11698 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
11699 tp->fw_ver[0] = 's';
11700 tp->fw_ver[1] = 'b';
11701 tp->fw_ver[2] = '\0';
11702
11703 return;
11704 }
11705
11706 if (tg3_nvram_read(tp, 0, &val))
11707 return;
11708
11709 if (val == TG3_EEPROM_MAGIC)
11710 tg3_read_bc_ver(tp);
11711 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11712 tg3_read_sb_ver(tp, val);
11713 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11714 tg3_read_hwsb_ver(tp);
11715 else
11716 return;
11717
11718 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11719 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11720 return;
11721
11722 tg3_read_mgmtfw_ver(tp);
11723
11724 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11725 }
11726
11727 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11728
11729 static int __devinit tg3_get_invariants(struct tg3 *tp)
11730 {
11731 static struct pci_device_id write_reorder_chipsets[] = {
11732 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11733 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11734 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11735 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11736 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11737 PCI_DEVICE_ID_VIA_8385_0) },
11738 { },
11739 };
11740 u32 misc_ctrl_reg;
11741 u32 pci_state_reg, grc_misc_cfg;
11742 u32 val;
11743 u16 pci_cmd;
11744 int err;
11745
11746 /* Force memory write invalidate off. If we leave it on,
11747 * then on 5700_BX chips we have to enable a workaround.
11748 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11749 * to match the cacheline size. The Broadcom driver have this
11750 * workaround but turns MWI off all the times so never uses
11751 * it. This seems to suggest that the workaround is insufficient.
11752 */
11753 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11754 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11755 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11756
11757 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11758 * has the register indirect write enable bit set before
11759 * we try to access any of the MMIO registers. It is also
11760 * critical that the PCI-X hw workaround situation is decided
11761 * before that as well.
11762 */
11763 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11764 &misc_ctrl_reg);
11765
11766 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11767 MISC_HOST_CTRL_CHIPREV_SHIFT);
11768 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11769 u32 prod_id_asic_rev;
11770
11771 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11772 &prod_id_asic_rev);
11773 tp->pci_chip_rev_id = prod_id_asic_rev;
11774 }
11775
11776 /* Wrong chip ID in 5752 A0. This code can be removed later
11777 * as A0 is not in production.
11778 */
11779 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11780 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11781
11782 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11783 * we need to disable memory and use config. cycles
11784 * only to access all registers. The 5702/03 chips
11785 * can mistakenly decode the special cycles from the
11786 * ICH chipsets as memory write cycles, causing corruption
11787 * of register and memory space. Only certain ICH bridges
11788 * will drive special cycles with non-zero data during the
11789 * address phase which can fall within the 5703's address
11790 * range. This is not an ICH bug as the PCI spec allows
11791 * non-zero address during special cycles. However, only
11792 * these ICH bridges are known to drive non-zero addresses
11793 * during special cycles.
11794 *
11795 * Since special cycles do not cross PCI bridges, we only
11796 * enable this workaround if the 5703 is on the secondary
11797 * bus of these ICH bridges.
11798 */
11799 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11800 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11801 static struct tg3_dev_id {
11802 u32 vendor;
11803 u32 device;
11804 u32 rev;
11805 } ich_chipsets[] = {
11806 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11807 PCI_ANY_ID },
11808 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11809 PCI_ANY_ID },
11810 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11811 0xa },
11812 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11813 PCI_ANY_ID },
11814 { },
11815 };
11816 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11817 struct pci_dev *bridge = NULL;
11818
11819 while (pci_id->vendor != 0) {
11820 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11821 bridge);
11822 if (!bridge) {
11823 pci_id++;
11824 continue;
11825 }
11826 if (pci_id->rev != PCI_ANY_ID) {
11827 if (bridge->revision > pci_id->rev)
11828 continue;
11829 }
11830 if (bridge->subordinate &&
11831 (bridge->subordinate->number ==
11832 tp->pdev->bus->number)) {
11833
11834 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11835 pci_dev_put(bridge);
11836 break;
11837 }
11838 }
11839 }
11840
11841 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11842 static struct tg3_dev_id {
11843 u32 vendor;
11844 u32 device;
11845 } bridge_chipsets[] = {
11846 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11847 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11848 { },
11849 };
11850 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11851 struct pci_dev *bridge = NULL;
11852
11853 while (pci_id->vendor != 0) {
11854 bridge = pci_get_device(pci_id->vendor,
11855 pci_id->device,
11856 bridge);
11857 if (!bridge) {
11858 pci_id++;
11859 continue;
11860 }
11861 if (bridge->subordinate &&
11862 (bridge->subordinate->number <=
11863 tp->pdev->bus->number) &&
11864 (bridge->subordinate->subordinate >=
11865 tp->pdev->bus->number)) {
11866 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11867 pci_dev_put(bridge);
11868 break;
11869 }
11870 }
11871 }
11872
11873 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11874 * DMA addresses > 40-bit. This bridge may have other additional
11875 * 57xx devices behind it in some 4-port NIC designs for example.
11876 * Any tg3 device found behind the bridge will also need the 40-bit
11877 * DMA workaround.
11878 */
11879 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11880 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11881 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11882 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11883 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11884 }
11885 else {
11886 struct pci_dev *bridge = NULL;
11887
11888 do {
11889 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11890 PCI_DEVICE_ID_SERVERWORKS_EPB,
11891 bridge);
11892 if (bridge && bridge->subordinate &&
11893 (bridge->subordinate->number <=
11894 tp->pdev->bus->number) &&
11895 (bridge->subordinate->subordinate >=
11896 tp->pdev->bus->number)) {
11897 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11898 pci_dev_put(bridge);
11899 break;
11900 }
11901 } while (bridge);
11902 }
11903
11904 /* Initialize misc host control in PCI block. */
11905 tp->misc_host_ctrl |= (misc_ctrl_reg &
11906 MISC_HOST_CTRL_CHIPREV);
11907 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11908 tp->misc_host_ctrl);
11909
11910 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11911 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11912 tp->pdev_peer = tg3_find_peer(tp);
11913
11914 /* Intentionally exclude ASIC_REV_5906 */
11915 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11916 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11917 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11918 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11919 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11920 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11921 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11922
11923 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11924 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11925 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11926 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11927 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11928 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11929
11930 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11931 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11932 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11933
11934 /* 5700 B0 chips do not support checksumming correctly due
11935 * to hardware bugs.
11936 */
11937 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11938 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11939 else {
11940 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11941 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11942 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11943 tp->dev->features |= NETIF_F_IPV6_CSUM;
11944 }
11945
11946 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11947 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11948 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11949 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11950 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11951 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11952 tp->pdev_peer == tp->pdev))
11953 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11954
11955 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11956 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11957 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11958 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11959 } else {
11960 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11961 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11962 ASIC_REV_5750 &&
11963 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
11964 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11965 }
11966 }
11967
11968 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11969 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11970 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11971
11972 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11973 &pci_state_reg);
11974
11975 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11976 if (tp->pcie_cap != 0) {
11977 u16 lnkctl;
11978
11979 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11980
11981 pcie_set_readrq(tp->pdev, 4096);
11982
11983 pci_read_config_word(tp->pdev,
11984 tp->pcie_cap + PCI_EXP_LNKCTL,
11985 &lnkctl);
11986 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
11987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11988 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11991 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
11992 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
11993 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
11994 }
11995 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
11996 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11997 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11998 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11999 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12000 if (!tp->pcix_cap) {
12001 printk(KERN_ERR PFX "Cannot find PCI-X "
12002 "capability, aborting.\n");
12003 return -EIO;
12004 }
12005
12006 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12007 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12008 }
12009
12010 /* If we have an AMD 762 or VIA K8T800 chipset, write
12011 * reordering to the mailbox registers done by the host
12012 * controller can cause major troubles. We read back from
12013 * every mailbox register write to force the writes to be
12014 * posted to the chip in order.
12015 */
12016 if (pci_dev_present(write_reorder_chipsets) &&
12017 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12018 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12019
12020 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12021 &tp->pci_cacheline_sz);
12022 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12023 &tp->pci_lat_timer);
12024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12025 tp->pci_lat_timer < 64) {
12026 tp->pci_lat_timer = 64;
12027 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12028 tp->pci_lat_timer);
12029 }
12030
12031 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12032 /* 5700 BX chips need to have their TX producer index
12033 * mailboxes written twice to workaround a bug.
12034 */
12035 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12036
12037 /* If we are in PCI-X mode, enable register write workaround.
12038 *
12039 * The workaround is to use indirect register accesses
12040 * for all chip writes not to mailbox registers.
12041 */
12042 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12043 u32 pm_reg;
12044
12045 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12046
12047 /* The chip can have it's power management PCI config
12048 * space registers clobbered due to this bug.
12049 * So explicitly force the chip into D0 here.
12050 */
12051 pci_read_config_dword(tp->pdev,
12052 tp->pm_cap + PCI_PM_CTRL,
12053 &pm_reg);
12054 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12055 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12056 pci_write_config_dword(tp->pdev,
12057 tp->pm_cap + PCI_PM_CTRL,
12058 pm_reg);
12059
12060 /* Also, force SERR#/PERR# in PCI command. */
12061 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12062 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12063 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12064 }
12065 }
12066
12067 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12068 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12069 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12070 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12071
12072 /* Chip-specific fixup from Broadcom driver */
12073 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12074 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12075 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12076 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12077 }
12078
12079 /* Default fast path register access methods */
12080 tp->read32 = tg3_read32;
12081 tp->write32 = tg3_write32;
12082 tp->read32_mbox = tg3_read32;
12083 tp->write32_mbox = tg3_write32;
12084 tp->write32_tx_mbox = tg3_write32;
12085 tp->write32_rx_mbox = tg3_write32;
12086
12087 /* Various workaround register access methods */
12088 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12089 tp->write32 = tg3_write_indirect_reg32;
12090 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12091 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12092 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12093 /*
12094 * Back to back register writes can cause problems on these
12095 * chips, the workaround is to read back all reg writes
12096 * except those to mailbox regs.
12097 *
12098 * See tg3_write_indirect_reg32().
12099 */
12100 tp->write32 = tg3_write_flush_reg32;
12101 }
12102
12103
12104 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12105 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12106 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12107 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12108 tp->write32_rx_mbox = tg3_write_flush_reg32;
12109 }
12110
12111 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12112 tp->read32 = tg3_read_indirect_reg32;
12113 tp->write32 = tg3_write_indirect_reg32;
12114 tp->read32_mbox = tg3_read_indirect_mbox;
12115 tp->write32_mbox = tg3_write_indirect_mbox;
12116 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12117 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12118
12119 iounmap(tp->regs);
12120 tp->regs = NULL;
12121
12122 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12123 pci_cmd &= ~PCI_COMMAND_MEMORY;
12124 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12125 }
12126 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12127 tp->read32_mbox = tg3_read32_mbox_5906;
12128 tp->write32_mbox = tg3_write32_mbox_5906;
12129 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12130 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12131 }
12132
12133 if (tp->write32 == tg3_write_indirect_reg32 ||
12134 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12135 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12137 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12138
12139 /* Get eeprom hw config before calling tg3_set_power_state().
12140 * In particular, the TG3_FLG2_IS_NIC flag must be
12141 * determined before calling tg3_set_power_state() so that
12142 * we know whether or not to switch out of Vaux power.
12143 * When the flag is set, it means that GPIO1 is used for eeprom
12144 * write protect and also implies that it is a LOM where GPIOs
12145 * are not used to switch power.
12146 */
12147 tg3_get_eeprom_hw_cfg(tp);
12148
12149 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12150 /* Allow reads and writes to the
12151 * APE register and memory space.
12152 */
12153 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12154 PCISTATE_ALLOW_APE_SHMEM_WR;
12155 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12156 pci_state_reg);
12157 }
12158
12159 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12160 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12161 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12162 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12163 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12164
12165 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12166 * GPIO1 driven high will bring 5700's external PHY out of reset.
12167 * It is also used as eeprom write protect on LOMs.
12168 */
12169 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12170 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12171 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12172 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12173 GRC_LCLCTRL_GPIO_OUTPUT1);
12174 /* Unused GPIO3 must be driven as output on 5752 because there
12175 * are no pull-up resistors on unused GPIO pins.
12176 */
12177 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12178 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12179
12180 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12181 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12182 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12183
12184 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12185 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12186 /* Turn off the debug UART. */
12187 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12188 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12189 /* Keep VMain power. */
12190 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12191 GRC_LCLCTRL_GPIO_OUTPUT0;
12192 }
12193
12194 /* Force the chip into D0. */
12195 err = tg3_set_power_state(tp, PCI_D0);
12196 if (err) {
12197 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12198 pci_name(tp->pdev));
12199 return err;
12200 }
12201
12202 /* Derive initial jumbo mode from MTU assigned in
12203 * ether_setup() via the alloc_etherdev() call
12204 */
12205 if (tp->dev->mtu > ETH_DATA_LEN &&
12206 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12207 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12208
12209 /* Determine WakeOnLan speed to use. */
12210 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12211 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12212 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12213 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12214 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12215 } else {
12216 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12217 }
12218
12219 /* A few boards don't want Ethernet@WireSpeed phy feature */
12220 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12221 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12222 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12223 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12224 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12225 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12226 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12227
12228 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12229 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12230 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12231 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12232 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12233
12234 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12235 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12236 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12237 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12238 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12239 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12240 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12241 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12242 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12243 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12244 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12245 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12246 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12247 } else
12248 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12249 }
12250
12251 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12252 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12253 tp->phy_otp = tg3_read_otp_phycfg(tp);
12254 if (tp->phy_otp == 0)
12255 tp->phy_otp = TG3_OTP_DEFAULT;
12256 }
12257
12258 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12259 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12260 else
12261 tp->mi_mode = MAC_MI_MODE_BASE;
12262
12263 tp->coalesce_mode = 0;
12264 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12265 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12266 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12267
12268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12269 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12270 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12271
12272 err = tg3_mdio_init(tp);
12273 if (err)
12274 return err;
12275
12276 /* Initialize data/descriptor byte/word swapping. */
12277 val = tr32(GRC_MODE);
12278 val &= GRC_MODE_HOST_STACKUP;
12279 tw32(GRC_MODE, val | tp->grc_mode);
12280
12281 tg3_switch_clocks(tp);
12282
12283 /* Clear this out for sanity. */
12284 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12285
12286 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12287 &pci_state_reg);
12288 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12289 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12290 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12291
12292 if (chiprevid == CHIPREV_ID_5701_A0 ||
12293 chiprevid == CHIPREV_ID_5701_B0 ||
12294 chiprevid == CHIPREV_ID_5701_B2 ||
12295 chiprevid == CHIPREV_ID_5701_B5) {
12296 void __iomem *sram_base;
12297
12298 /* Write some dummy words into the SRAM status block
12299 * area, see if it reads back correctly. If the return
12300 * value is bad, force enable the PCIX workaround.
12301 */
12302 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12303
12304 writel(0x00000000, sram_base);
12305 writel(0x00000000, sram_base + 4);
12306 writel(0xffffffff, sram_base + 4);
12307 if (readl(sram_base) != 0x00000000)
12308 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12309 }
12310 }
12311
12312 udelay(50);
12313 tg3_nvram_init(tp);
12314
12315 grc_misc_cfg = tr32(GRC_MISC_CFG);
12316 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12317
12318 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12319 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12320 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12321 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12322
12323 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12324 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12325 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12326 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12327 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12328 HOSTCC_MODE_CLRTICK_TXBD);
12329
12330 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12331 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12332 tp->misc_host_ctrl);
12333 }
12334
12335 /* Preserve the APE MAC_MODE bits */
12336 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12337 tp->mac_mode = tr32(MAC_MODE) |
12338 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12339 else
12340 tp->mac_mode = TG3_DEF_MAC_MODE;
12341
12342 /* these are limited to 10/100 only */
12343 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12344 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12345 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12346 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12347 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12348 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12349 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12350 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12351 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12352 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12353 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12354 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12355 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12356 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12357
12358 err = tg3_phy_probe(tp);
12359 if (err) {
12360 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12361 pci_name(tp->pdev), err);
12362 /* ... but do not return immediately ... */
12363 tg3_mdio_fini(tp);
12364 }
12365
12366 tg3_read_partno(tp);
12367 tg3_read_fw_ver(tp);
12368
12369 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12370 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12371 } else {
12372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12373 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12374 else
12375 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12376 }
12377
12378 /* 5700 {AX,BX} chips have a broken status block link
12379 * change bit implementation, so we must use the
12380 * status register in those cases.
12381 */
12382 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12383 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12384 else
12385 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12386
12387 /* The led_ctrl is set during tg3_phy_probe, here we might
12388 * have to force the link status polling mechanism based
12389 * upon subsystem IDs.
12390 */
12391 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12392 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12393 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12394 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12395 TG3_FLAG_USE_LINKCHG_REG);
12396 }
12397
12398 /* For all SERDES we poll the MAC status register. */
12399 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12400 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12401 else
12402 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12403
12404 tp->rx_offset = NET_IP_ALIGN;
12405 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12406 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12407 tp->rx_offset = 0;
12408
12409 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12410
12411 /* Increment the rx prod index on the rx std ring by at most
12412 * 8 for these chips to workaround hw errata.
12413 */
12414 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12415 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12416 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12417 tp->rx_std_max_post = 8;
12418
12419 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12420 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12421 PCIE_PWR_MGMT_L1_THRESH_MSK;
12422
12423 return err;
12424 }
12425
12426 #ifdef CONFIG_SPARC
12427 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12428 {
12429 struct net_device *dev = tp->dev;
12430 struct pci_dev *pdev = tp->pdev;
12431 struct device_node *dp = pci_device_to_OF_node(pdev);
12432 const unsigned char *addr;
12433 int len;
12434
12435 addr = of_get_property(dp, "local-mac-address", &len);
12436 if (addr && len == 6) {
12437 memcpy(dev->dev_addr, addr, 6);
12438 memcpy(dev->perm_addr, dev->dev_addr, 6);
12439 return 0;
12440 }
12441 return -ENODEV;
12442 }
12443
12444 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12445 {
12446 struct net_device *dev = tp->dev;
12447
12448 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12449 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12450 return 0;
12451 }
12452 #endif
12453
12454 static int __devinit tg3_get_device_address(struct tg3 *tp)
12455 {
12456 struct net_device *dev = tp->dev;
12457 u32 hi, lo, mac_offset;
12458 int addr_ok = 0;
12459
12460 #ifdef CONFIG_SPARC
12461 if (!tg3_get_macaddr_sparc(tp))
12462 return 0;
12463 #endif
12464
12465 mac_offset = 0x7c;
12466 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12467 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12468 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12469 mac_offset = 0xcc;
12470 if (tg3_nvram_lock(tp))
12471 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12472 else
12473 tg3_nvram_unlock(tp);
12474 }
12475 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12476 mac_offset = 0x10;
12477
12478 /* First try to get it from MAC address mailbox. */
12479 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12480 if ((hi >> 16) == 0x484b) {
12481 dev->dev_addr[0] = (hi >> 8) & 0xff;
12482 dev->dev_addr[1] = (hi >> 0) & 0xff;
12483
12484 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12485 dev->dev_addr[2] = (lo >> 24) & 0xff;
12486 dev->dev_addr[3] = (lo >> 16) & 0xff;
12487 dev->dev_addr[4] = (lo >> 8) & 0xff;
12488 dev->dev_addr[5] = (lo >> 0) & 0xff;
12489
12490 /* Some old bootcode may report a 0 MAC address in SRAM */
12491 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12492 }
12493 if (!addr_ok) {
12494 /* Next, try NVRAM. */
12495 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
12496 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
12497 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
12498 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
12499 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
12500 }
12501 /* Finally just fetch it out of the MAC control regs. */
12502 else {
12503 hi = tr32(MAC_ADDR_0_HIGH);
12504 lo = tr32(MAC_ADDR_0_LOW);
12505
12506 dev->dev_addr[5] = lo & 0xff;
12507 dev->dev_addr[4] = (lo >> 8) & 0xff;
12508 dev->dev_addr[3] = (lo >> 16) & 0xff;
12509 dev->dev_addr[2] = (lo >> 24) & 0xff;
12510 dev->dev_addr[1] = hi & 0xff;
12511 dev->dev_addr[0] = (hi >> 8) & 0xff;
12512 }
12513 }
12514
12515 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12516 #ifdef CONFIG_SPARC
12517 if (!tg3_get_default_macaddr_sparc(tp))
12518 return 0;
12519 #endif
12520 return -EINVAL;
12521 }
12522 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12523 return 0;
12524 }
12525
12526 #define BOUNDARY_SINGLE_CACHELINE 1
12527 #define BOUNDARY_MULTI_CACHELINE 2
12528
12529 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12530 {
12531 int cacheline_size;
12532 u8 byte;
12533 int goal;
12534
12535 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12536 if (byte == 0)
12537 cacheline_size = 1024;
12538 else
12539 cacheline_size = (int) byte * 4;
12540
12541 /* On 5703 and later chips, the boundary bits have no
12542 * effect.
12543 */
12544 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12545 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12546 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12547 goto out;
12548
12549 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12550 goal = BOUNDARY_MULTI_CACHELINE;
12551 #else
12552 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12553 goal = BOUNDARY_SINGLE_CACHELINE;
12554 #else
12555 goal = 0;
12556 #endif
12557 #endif
12558
12559 if (!goal)
12560 goto out;
12561
12562 /* PCI controllers on most RISC systems tend to disconnect
12563 * when a device tries to burst across a cache-line boundary.
12564 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12565 *
12566 * Unfortunately, for PCI-E there are only limited
12567 * write-side controls for this, and thus for reads
12568 * we will still get the disconnects. We'll also waste
12569 * these PCI cycles for both read and write for chips
12570 * other than 5700 and 5701 which do not implement the
12571 * boundary bits.
12572 */
12573 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12574 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12575 switch (cacheline_size) {
12576 case 16:
12577 case 32:
12578 case 64:
12579 case 128:
12580 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12581 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12582 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12583 } else {
12584 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12585 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12586 }
12587 break;
12588
12589 case 256:
12590 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12591 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12592 break;
12593
12594 default:
12595 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12596 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12597 break;
12598 }
12599 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12600 switch (cacheline_size) {
12601 case 16:
12602 case 32:
12603 case 64:
12604 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12605 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12606 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12607 break;
12608 }
12609 /* fallthrough */
12610 case 128:
12611 default:
12612 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12613 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12614 break;
12615 }
12616 } else {
12617 switch (cacheline_size) {
12618 case 16:
12619 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12620 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12621 DMA_RWCTRL_WRITE_BNDRY_16);
12622 break;
12623 }
12624 /* fallthrough */
12625 case 32:
12626 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12627 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12628 DMA_RWCTRL_WRITE_BNDRY_32);
12629 break;
12630 }
12631 /* fallthrough */
12632 case 64:
12633 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12634 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12635 DMA_RWCTRL_WRITE_BNDRY_64);
12636 break;
12637 }
12638 /* fallthrough */
12639 case 128:
12640 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12641 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12642 DMA_RWCTRL_WRITE_BNDRY_128);
12643 break;
12644 }
12645 /* fallthrough */
12646 case 256:
12647 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12648 DMA_RWCTRL_WRITE_BNDRY_256);
12649 break;
12650 case 512:
12651 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12652 DMA_RWCTRL_WRITE_BNDRY_512);
12653 break;
12654 case 1024:
12655 default:
12656 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12657 DMA_RWCTRL_WRITE_BNDRY_1024);
12658 break;
12659 }
12660 }
12661
12662 out:
12663 return val;
12664 }
12665
12666 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12667 {
12668 struct tg3_internal_buffer_desc test_desc;
12669 u32 sram_dma_descs;
12670 int i, ret;
12671
12672 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12673
12674 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12675 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12676 tw32(RDMAC_STATUS, 0);
12677 tw32(WDMAC_STATUS, 0);
12678
12679 tw32(BUFMGR_MODE, 0);
12680 tw32(FTQ_RESET, 0);
12681
12682 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12683 test_desc.addr_lo = buf_dma & 0xffffffff;
12684 test_desc.nic_mbuf = 0x00002100;
12685 test_desc.len = size;
12686
12687 /*
12688 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12689 * the *second* time the tg3 driver was getting loaded after an
12690 * initial scan.
12691 *
12692 * Broadcom tells me:
12693 * ...the DMA engine is connected to the GRC block and a DMA
12694 * reset may affect the GRC block in some unpredictable way...
12695 * The behavior of resets to individual blocks has not been tested.
12696 *
12697 * Broadcom noted the GRC reset will also reset all sub-components.
12698 */
12699 if (to_device) {
12700 test_desc.cqid_sqid = (13 << 8) | 2;
12701
12702 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12703 udelay(40);
12704 } else {
12705 test_desc.cqid_sqid = (16 << 8) | 7;
12706
12707 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12708 udelay(40);
12709 }
12710 test_desc.flags = 0x00000005;
12711
12712 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12713 u32 val;
12714
12715 val = *(((u32 *)&test_desc) + i);
12716 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12717 sram_dma_descs + (i * sizeof(u32)));
12718 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12719 }
12720 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12721
12722 if (to_device) {
12723 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12724 } else {
12725 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12726 }
12727
12728 ret = -ENODEV;
12729 for (i = 0; i < 40; i++) {
12730 u32 val;
12731
12732 if (to_device)
12733 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12734 else
12735 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12736 if ((val & 0xffff) == sram_dma_descs) {
12737 ret = 0;
12738 break;
12739 }
12740
12741 udelay(100);
12742 }
12743
12744 return ret;
12745 }
12746
12747 #define TEST_BUFFER_SIZE 0x2000
12748
12749 static int __devinit tg3_test_dma(struct tg3 *tp)
12750 {
12751 dma_addr_t buf_dma;
12752 u32 *buf, saved_dma_rwctrl;
12753 int ret;
12754
12755 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12756 if (!buf) {
12757 ret = -ENOMEM;
12758 goto out_nofree;
12759 }
12760
12761 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12762 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12763
12764 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12765
12766 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12767 /* DMA read watermark not used on PCIE */
12768 tp->dma_rwctrl |= 0x00180000;
12769 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12770 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12771 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12772 tp->dma_rwctrl |= 0x003f0000;
12773 else
12774 tp->dma_rwctrl |= 0x003f000f;
12775 } else {
12776 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12777 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12778 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12779 u32 read_water = 0x7;
12780
12781 /* If the 5704 is behind the EPB bridge, we can
12782 * do the less restrictive ONE_DMA workaround for
12783 * better performance.
12784 */
12785 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12786 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12787 tp->dma_rwctrl |= 0x8000;
12788 else if (ccval == 0x6 || ccval == 0x7)
12789 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12790
12791 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12792 read_water = 4;
12793 /* Set bit 23 to enable PCIX hw bug fix */
12794 tp->dma_rwctrl |=
12795 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12796 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12797 (1 << 23);
12798 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12799 /* 5780 always in PCIX mode */
12800 tp->dma_rwctrl |= 0x00144000;
12801 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12802 /* 5714 always in PCIX mode */
12803 tp->dma_rwctrl |= 0x00148000;
12804 } else {
12805 tp->dma_rwctrl |= 0x001b000f;
12806 }
12807 }
12808
12809 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12810 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12811 tp->dma_rwctrl &= 0xfffffff0;
12812
12813 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12814 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12815 /* Remove this if it causes problems for some boards. */
12816 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12817
12818 /* On 5700/5701 chips, we need to set this bit.
12819 * Otherwise the chip will issue cacheline transactions
12820 * to streamable DMA memory with not all the byte
12821 * enables turned on. This is an error on several
12822 * RISC PCI controllers, in particular sparc64.
12823 *
12824 * On 5703/5704 chips, this bit has been reassigned
12825 * a different meaning. In particular, it is used
12826 * on those chips to enable a PCI-X workaround.
12827 */
12828 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12829 }
12830
12831 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12832
12833 #if 0
12834 /* Unneeded, already done by tg3_get_invariants. */
12835 tg3_switch_clocks(tp);
12836 #endif
12837
12838 ret = 0;
12839 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12840 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12841 goto out;
12842
12843 /* It is best to perform DMA test with maximum write burst size
12844 * to expose the 5700/5701 write DMA bug.
12845 */
12846 saved_dma_rwctrl = tp->dma_rwctrl;
12847 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12848 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12849
12850 while (1) {
12851 u32 *p = buf, i;
12852
12853 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12854 p[i] = i;
12855
12856 /* Send the buffer to the chip. */
12857 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12858 if (ret) {
12859 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12860 break;
12861 }
12862
12863 #if 0
12864 /* validate data reached card RAM correctly. */
12865 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12866 u32 val;
12867 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12868 if (le32_to_cpu(val) != p[i]) {
12869 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12870 /* ret = -ENODEV here? */
12871 }
12872 p[i] = 0;
12873 }
12874 #endif
12875 /* Now read it back. */
12876 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12877 if (ret) {
12878 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12879
12880 break;
12881 }
12882
12883 /* Verify it. */
12884 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12885 if (p[i] == i)
12886 continue;
12887
12888 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12889 DMA_RWCTRL_WRITE_BNDRY_16) {
12890 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12891 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12892 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12893 break;
12894 } else {
12895 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12896 ret = -ENODEV;
12897 goto out;
12898 }
12899 }
12900
12901 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12902 /* Success. */
12903 ret = 0;
12904 break;
12905 }
12906 }
12907 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12908 DMA_RWCTRL_WRITE_BNDRY_16) {
12909 static struct pci_device_id dma_wait_state_chipsets[] = {
12910 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12911 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12912 { },
12913 };
12914
12915 /* DMA test passed without adjusting DMA boundary,
12916 * now look for chipsets that are known to expose the
12917 * DMA bug without failing the test.
12918 */
12919 if (pci_dev_present(dma_wait_state_chipsets)) {
12920 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12921 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12922 }
12923 else
12924 /* Safe to use the calculated DMA boundary. */
12925 tp->dma_rwctrl = saved_dma_rwctrl;
12926
12927 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12928 }
12929
12930 out:
12931 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12932 out_nofree:
12933 return ret;
12934 }
12935
12936 static void __devinit tg3_init_link_config(struct tg3 *tp)
12937 {
12938 tp->link_config.advertising =
12939 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12940 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12941 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12942 ADVERTISED_Autoneg | ADVERTISED_MII);
12943 tp->link_config.speed = SPEED_INVALID;
12944 tp->link_config.duplex = DUPLEX_INVALID;
12945 tp->link_config.autoneg = AUTONEG_ENABLE;
12946 tp->link_config.active_speed = SPEED_INVALID;
12947 tp->link_config.active_duplex = DUPLEX_INVALID;
12948 tp->link_config.phy_is_low_power = 0;
12949 tp->link_config.orig_speed = SPEED_INVALID;
12950 tp->link_config.orig_duplex = DUPLEX_INVALID;
12951 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12952 }
12953
12954 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12955 {
12956 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12957 tp->bufmgr_config.mbuf_read_dma_low_water =
12958 DEFAULT_MB_RDMA_LOW_WATER_5705;
12959 tp->bufmgr_config.mbuf_mac_rx_low_water =
12960 DEFAULT_MB_MACRX_LOW_WATER_5705;
12961 tp->bufmgr_config.mbuf_high_water =
12962 DEFAULT_MB_HIGH_WATER_5705;
12963 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12964 tp->bufmgr_config.mbuf_mac_rx_low_water =
12965 DEFAULT_MB_MACRX_LOW_WATER_5906;
12966 tp->bufmgr_config.mbuf_high_water =
12967 DEFAULT_MB_HIGH_WATER_5906;
12968 }
12969
12970 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12971 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12972 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12973 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12974 tp->bufmgr_config.mbuf_high_water_jumbo =
12975 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12976 } else {
12977 tp->bufmgr_config.mbuf_read_dma_low_water =
12978 DEFAULT_MB_RDMA_LOW_WATER;
12979 tp->bufmgr_config.mbuf_mac_rx_low_water =
12980 DEFAULT_MB_MACRX_LOW_WATER;
12981 tp->bufmgr_config.mbuf_high_water =
12982 DEFAULT_MB_HIGH_WATER;
12983
12984 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12985 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12986 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12987 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12988 tp->bufmgr_config.mbuf_high_water_jumbo =
12989 DEFAULT_MB_HIGH_WATER_JUMBO;
12990 }
12991
12992 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12993 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12994 }
12995
12996 static char * __devinit tg3_phy_string(struct tg3 *tp)
12997 {
12998 switch (tp->phy_id & PHY_ID_MASK) {
12999 case PHY_ID_BCM5400: return "5400";
13000 case PHY_ID_BCM5401: return "5401";
13001 case PHY_ID_BCM5411: return "5411";
13002 case PHY_ID_BCM5701: return "5701";
13003 case PHY_ID_BCM5703: return "5703";
13004 case PHY_ID_BCM5704: return "5704";
13005 case PHY_ID_BCM5705: return "5705";
13006 case PHY_ID_BCM5750: return "5750";
13007 case PHY_ID_BCM5752: return "5752";
13008 case PHY_ID_BCM5714: return "5714";
13009 case PHY_ID_BCM5780: return "5780";
13010 case PHY_ID_BCM5755: return "5755";
13011 case PHY_ID_BCM5787: return "5787";
13012 case PHY_ID_BCM5784: return "5784";
13013 case PHY_ID_BCM5756: return "5722/5756";
13014 case PHY_ID_BCM5906: return "5906";
13015 case PHY_ID_BCM5761: return "5761";
13016 case PHY_ID_BCM8002: return "8002/serdes";
13017 case 0: return "serdes";
13018 default: return "unknown";
13019 }
13020 }
13021
13022 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13023 {
13024 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13025 strcpy(str, "PCI Express");
13026 return str;
13027 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13028 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13029
13030 strcpy(str, "PCIX:");
13031
13032 if ((clock_ctrl == 7) ||
13033 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13034 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13035 strcat(str, "133MHz");
13036 else if (clock_ctrl == 0)
13037 strcat(str, "33MHz");
13038 else if (clock_ctrl == 2)
13039 strcat(str, "50MHz");
13040 else if (clock_ctrl == 4)
13041 strcat(str, "66MHz");
13042 else if (clock_ctrl == 6)
13043 strcat(str, "100MHz");
13044 } else {
13045 strcpy(str, "PCI:");
13046 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13047 strcat(str, "66MHz");
13048 else
13049 strcat(str, "33MHz");
13050 }
13051 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13052 strcat(str, ":32-bit");
13053 else
13054 strcat(str, ":64-bit");
13055 return str;
13056 }
13057
13058 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13059 {
13060 struct pci_dev *peer;
13061 unsigned int func, devnr = tp->pdev->devfn & ~7;
13062
13063 for (func = 0; func < 8; func++) {
13064 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13065 if (peer && peer != tp->pdev)
13066 break;
13067 pci_dev_put(peer);
13068 }
13069 /* 5704 can be configured in single-port mode, set peer to
13070 * tp->pdev in that case.
13071 */
13072 if (!peer) {
13073 peer = tp->pdev;
13074 return peer;
13075 }
13076
13077 /*
13078 * We don't need to keep the refcount elevated; there's no way
13079 * to remove one half of this device without removing the other
13080 */
13081 pci_dev_put(peer);
13082
13083 return peer;
13084 }
13085
13086 static void __devinit tg3_init_coal(struct tg3 *tp)
13087 {
13088 struct ethtool_coalesce *ec = &tp->coal;
13089
13090 memset(ec, 0, sizeof(*ec));
13091 ec->cmd = ETHTOOL_GCOALESCE;
13092 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13093 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13094 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13095 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13096 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13097 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13098 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13099 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13100 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13101
13102 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13103 HOSTCC_MODE_CLRTICK_TXBD)) {
13104 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13105 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13106 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13107 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13108 }
13109
13110 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13111 ec->rx_coalesce_usecs_irq = 0;
13112 ec->tx_coalesce_usecs_irq = 0;
13113 ec->stats_block_coalesce_usecs = 0;
13114 }
13115 }
13116
13117 static const struct net_device_ops tg3_netdev_ops = {
13118 .ndo_open = tg3_open,
13119 .ndo_stop = tg3_close,
13120 .ndo_start_xmit = tg3_start_xmit,
13121 .ndo_get_stats = tg3_get_stats,
13122 .ndo_validate_addr = eth_validate_addr,
13123 .ndo_set_multicast_list = tg3_set_rx_mode,
13124 .ndo_set_mac_address = tg3_set_mac_addr,
13125 .ndo_do_ioctl = tg3_ioctl,
13126 .ndo_tx_timeout = tg3_tx_timeout,
13127 .ndo_change_mtu = tg3_change_mtu,
13128 #if TG3_VLAN_TAG_USED
13129 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13130 #endif
13131 #ifdef CONFIG_NET_POLL_CONTROLLER
13132 .ndo_poll_controller = tg3_poll_controller,
13133 #endif
13134 };
13135
13136 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13137 .ndo_open = tg3_open,
13138 .ndo_stop = tg3_close,
13139 .ndo_start_xmit = tg3_start_xmit_dma_bug,
13140 .ndo_get_stats = tg3_get_stats,
13141 .ndo_validate_addr = eth_validate_addr,
13142 .ndo_set_multicast_list = tg3_set_rx_mode,
13143 .ndo_set_mac_address = tg3_set_mac_addr,
13144 .ndo_do_ioctl = tg3_ioctl,
13145 .ndo_tx_timeout = tg3_tx_timeout,
13146 .ndo_change_mtu = tg3_change_mtu,
13147 #if TG3_VLAN_TAG_USED
13148 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13149 #endif
13150 #ifdef CONFIG_NET_POLL_CONTROLLER
13151 .ndo_poll_controller = tg3_poll_controller,
13152 #endif
13153 };
13154
13155 static int __devinit tg3_init_one(struct pci_dev *pdev,
13156 const struct pci_device_id *ent)
13157 {
13158 static int tg3_version_printed = 0;
13159 struct net_device *dev;
13160 struct tg3 *tp;
13161 int err, pm_cap;
13162 char str[40];
13163 u64 dma_mask, persist_dma_mask;
13164
13165 if (tg3_version_printed++ == 0)
13166 printk(KERN_INFO "%s", version);
13167
13168 err = pci_enable_device(pdev);
13169 if (err) {
13170 printk(KERN_ERR PFX "Cannot enable PCI device, "
13171 "aborting.\n");
13172 return err;
13173 }
13174
13175 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13176 if (err) {
13177 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13178 "aborting.\n");
13179 goto err_out_disable_pdev;
13180 }
13181
13182 pci_set_master(pdev);
13183
13184 /* Find power-management capability. */
13185 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13186 if (pm_cap == 0) {
13187 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13188 "aborting.\n");
13189 err = -EIO;
13190 goto err_out_free_res;
13191 }
13192
13193 dev = alloc_etherdev(sizeof(*tp));
13194 if (!dev) {
13195 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13196 err = -ENOMEM;
13197 goto err_out_free_res;
13198 }
13199
13200 SET_NETDEV_DEV(dev, &pdev->dev);
13201
13202 #if TG3_VLAN_TAG_USED
13203 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13204 #endif
13205
13206 tp = netdev_priv(dev);
13207 tp->pdev = pdev;
13208 tp->dev = dev;
13209 tp->pm_cap = pm_cap;
13210 tp->rx_mode = TG3_DEF_RX_MODE;
13211 tp->tx_mode = TG3_DEF_TX_MODE;
13212
13213 if (tg3_debug > 0)
13214 tp->msg_enable = tg3_debug;
13215 else
13216 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13217
13218 /* The word/byte swap controls here control register access byte
13219 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13220 * setting below.
13221 */
13222 tp->misc_host_ctrl =
13223 MISC_HOST_CTRL_MASK_PCI_INT |
13224 MISC_HOST_CTRL_WORD_SWAP |
13225 MISC_HOST_CTRL_INDIR_ACCESS |
13226 MISC_HOST_CTRL_PCISTATE_RW;
13227
13228 /* The NONFRM (non-frame) byte/word swap controls take effect
13229 * on descriptor entries, anything which isn't packet data.
13230 *
13231 * The StrongARM chips on the board (one for tx, one for rx)
13232 * are running in big-endian mode.
13233 */
13234 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13235 GRC_MODE_WSWAP_NONFRM_DATA);
13236 #ifdef __BIG_ENDIAN
13237 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13238 #endif
13239 spin_lock_init(&tp->lock);
13240 spin_lock_init(&tp->indirect_lock);
13241 INIT_WORK(&tp->reset_task, tg3_reset_task);
13242
13243 tp->regs = pci_ioremap_bar(pdev, BAR_0);
13244 if (!tp->regs) {
13245 printk(KERN_ERR PFX "Cannot map device registers, "
13246 "aborting.\n");
13247 err = -ENOMEM;
13248 goto err_out_free_dev;
13249 }
13250
13251 tg3_init_link_config(tp);
13252
13253 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13254 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13255 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13256
13257 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13258 dev->ethtool_ops = &tg3_ethtool_ops;
13259 dev->watchdog_timeo = TG3_TX_TIMEOUT;
13260 dev->irq = pdev->irq;
13261
13262 err = tg3_get_invariants(tp);
13263 if (err) {
13264 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13265 "aborting.\n");
13266 goto err_out_iounmap;
13267 }
13268
13269 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13271 dev->netdev_ops = &tg3_netdev_ops;
13272 else
13273 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13274
13275
13276 /* The EPB bridge inside 5714, 5715, and 5780 and any
13277 * device behind the EPB cannot support DMA addresses > 40-bit.
13278 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13279 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13280 * do DMA address check in tg3_start_xmit().
13281 */
13282 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13283 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
13284 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13285 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
13286 #ifdef CONFIG_HIGHMEM
13287 dma_mask = DMA_BIT_MASK(64);
13288 #endif
13289 } else
13290 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
13291
13292 /* Configure DMA attributes. */
13293 if (dma_mask > DMA_BIT_MASK(32)) {
13294 err = pci_set_dma_mask(pdev, dma_mask);
13295 if (!err) {
13296 dev->features |= NETIF_F_HIGHDMA;
13297 err = pci_set_consistent_dma_mask(pdev,
13298 persist_dma_mask);
13299 if (err < 0) {
13300 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13301 "DMA for consistent allocations\n");
13302 goto err_out_iounmap;
13303 }
13304 }
13305 }
13306 if (err || dma_mask == DMA_BIT_MASK(32)) {
13307 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
13308 if (err) {
13309 printk(KERN_ERR PFX "No usable DMA configuration, "
13310 "aborting.\n");
13311 goto err_out_iounmap;
13312 }
13313 }
13314
13315 tg3_init_bufmgr_config(tp);
13316
13317 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13318 tp->fw_needed = FIRMWARE_TG3;
13319
13320 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13321 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13322 }
13323 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13324 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13325 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13326 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13327 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13328 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13329 } else {
13330 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13331 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13332 tp->fw_needed = FIRMWARE_TG3TSO5;
13333 else
13334 tp->fw_needed = FIRMWARE_TG3TSO;
13335 }
13336
13337 /* TSO is on by default on chips that support hardware TSO.
13338 * Firmware TSO on older chips gives lower performance, so it
13339 * is off by default, but can be enabled using ethtool.
13340 */
13341 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13342 if (dev->features & NETIF_F_IP_CSUM)
13343 dev->features |= NETIF_F_TSO;
13344 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13345 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13346 dev->features |= NETIF_F_TSO6;
13347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13348 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13349 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13350 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13351 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13352 dev->features |= NETIF_F_TSO_ECN;
13353 }
13354
13355
13356 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13357 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13358 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13359 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13360 tp->rx_pending = 63;
13361 }
13362
13363 err = tg3_get_device_address(tp);
13364 if (err) {
13365 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13366 "aborting.\n");
13367 goto err_out_fw;
13368 }
13369
13370 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13371 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13372 if (!tp->aperegs) {
13373 printk(KERN_ERR PFX "Cannot map APE registers, "
13374 "aborting.\n");
13375 err = -ENOMEM;
13376 goto err_out_fw;
13377 }
13378
13379 tg3_ape_lock_init(tp);
13380
13381 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
13382 tg3_read_dash_ver(tp);
13383 }
13384
13385 /*
13386 * Reset chip in case UNDI or EFI driver did not shutdown
13387 * DMA self test will enable WDMAC and we'll see (spurious)
13388 * pending DMA on the PCI bus at that point.
13389 */
13390 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13391 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13392 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13393 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13394 }
13395
13396 err = tg3_test_dma(tp);
13397 if (err) {
13398 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13399 goto err_out_apeunmap;
13400 }
13401
13402 /* flow control autonegotiation is default behavior */
13403 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13404 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13405
13406 tg3_init_coal(tp);
13407
13408 pci_set_drvdata(pdev, dev);
13409
13410 err = register_netdev(dev);
13411 if (err) {
13412 printk(KERN_ERR PFX "Cannot register net device, "
13413 "aborting.\n");
13414 goto err_out_apeunmap;
13415 }
13416
13417 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13418 dev->name,
13419 tp->board_part_number,
13420 tp->pci_chip_rev_id,
13421 tg3_bus_string(tp, str),
13422 dev->dev_addr);
13423
13424 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13425 printk(KERN_INFO
13426 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13427 tp->dev->name,
13428 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13429 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13430 else
13431 printk(KERN_INFO
13432 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13433 tp->dev->name, tg3_phy_string(tp),
13434 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13435 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13436 "10/100/1000Base-T")),
13437 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13438
13439 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13440 dev->name,
13441 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13442 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13443 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13444 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13445 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13446 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13447 dev->name, tp->dma_rwctrl,
13448 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
13449 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
13450
13451 return 0;
13452
13453 err_out_apeunmap:
13454 if (tp->aperegs) {
13455 iounmap(tp->aperegs);
13456 tp->aperegs = NULL;
13457 }
13458
13459 err_out_fw:
13460 if (tp->fw)
13461 release_firmware(tp->fw);
13462
13463 err_out_iounmap:
13464 if (tp->regs) {
13465 iounmap(tp->regs);
13466 tp->regs = NULL;
13467 }
13468
13469 err_out_free_dev:
13470 free_netdev(dev);
13471
13472 err_out_free_res:
13473 pci_release_regions(pdev);
13474
13475 err_out_disable_pdev:
13476 pci_disable_device(pdev);
13477 pci_set_drvdata(pdev, NULL);
13478 return err;
13479 }
13480
13481 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13482 {
13483 struct net_device *dev = pci_get_drvdata(pdev);
13484
13485 if (dev) {
13486 struct tg3 *tp = netdev_priv(dev);
13487
13488 if (tp->fw)
13489 release_firmware(tp->fw);
13490
13491 flush_scheduled_work();
13492
13493 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13494 tg3_phy_fini(tp);
13495 tg3_mdio_fini(tp);
13496 }
13497
13498 unregister_netdev(dev);
13499 if (tp->aperegs) {
13500 iounmap(tp->aperegs);
13501 tp->aperegs = NULL;
13502 }
13503 if (tp->regs) {
13504 iounmap(tp->regs);
13505 tp->regs = NULL;
13506 }
13507 free_netdev(dev);
13508 pci_release_regions(pdev);
13509 pci_disable_device(pdev);
13510 pci_set_drvdata(pdev, NULL);
13511 }
13512 }
13513
13514 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13515 {
13516 struct net_device *dev = pci_get_drvdata(pdev);
13517 struct tg3 *tp = netdev_priv(dev);
13518 pci_power_t target_state;
13519 int err;
13520
13521 /* PCI register 4 needs to be saved whether netif_running() or not.
13522 * MSI address and data need to be saved if using MSI and
13523 * netif_running().
13524 */
13525 pci_save_state(pdev);
13526
13527 if (!netif_running(dev))
13528 return 0;
13529
13530 flush_scheduled_work();
13531 tg3_phy_stop(tp);
13532 tg3_netif_stop(tp);
13533
13534 del_timer_sync(&tp->timer);
13535
13536 tg3_full_lock(tp, 1);
13537 tg3_disable_ints(tp);
13538 tg3_full_unlock(tp);
13539
13540 netif_device_detach(dev);
13541
13542 tg3_full_lock(tp, 0);
13543 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13544 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13545 tg3_full_unlock(tp);
13546
13547 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13548
13549 err = tg3_set_power_state(tp, target_state);
13550 if (err) {
13551 int err2;
13552
13553 tg3_full_lock(tp, 0);
13554
13555 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13556 err2 = tg3_restart_hw(tp, 1);
13557 if (err2)
13558 goto out;
13559
13560 tp->timer.expires = jiffies + tp->timer_offset;
13561 add_timer(&tp->timer);
13562
13563 netif_device_attach(dev);
13564 tg3_netif_start(tp);
13565
13566 out:
13567 tg3_full_unlock(tp);
13568
13569 if (!err2)
13570 tg3_phy_start(tp);
13571 }
13572
13573 return err;
13574 }
13575
13576 static int tg3_resume(struct pci_dev *pdev)
13577 {
13578 struct net_device *dev = pci_get_drvdata(pdev);
13579 struct tg3 *tp = netdev_priv(dev);
13580 int err;
13581
13582 pci_restore_state(tp->pdev);
13583
13584 if (!netif_running(dev))
13585 return 0;
13586
13587 err = tg3_set_power_state(tp, PCI_D0);
13588 if (err)
13589 return err;
13590
13591 netif_device_attach(dev);
13592
13593 tg3_full_lock(tp, 0);
13594
13595 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13596 err = tg3_restart_hw(tp, 1);
13597 if (err)
13598 goto out;
13599
13600 tp->timer.expires = jiffies + tp->timer_offset;
13601 add_timer(&tp->timer);
13602
13603 tg3_netif_start(tp);
13604
13605 out:
13606 tg3_full_unlock(tp);
13607
13608 if (!err)
13609 tg3_phy_start(tp);
13610
13611 return err;
13612 }
13613
13614 static struct pci_driver tg3_driver = {
13615 .name = DRV_MODULE_NAME,
13616 .id_table = tg3_pci_tbl,
13617 .probe = tg3_init_one,
13618 .remove = __devexit_p(tg3_remove_one),
13619 .suspend = tg3_suspend,
13620 .resume = tg3_resume
13621 };
13622
13623 static int __init tg3_init(void)
13624 {
13625 return pci_register_driver(&tg3_driver);
13626 }
13627
13628 static void __exit tg3_cleanup(void)
13629 {
13630 pci_unregister_driver(&tg3_driver);
13631 }
13632
13633 module_init(tg3_init);
13634 module_exit(tg3_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree