arch/x86/kernel/cpu/cpufreq/powernow-k8.h

   1 /*
   2  *  (c) 2003-2006 Advanced Micro Devices, Inc.
   3  *  Your use of this code is subject to the terms and conditions of the
   4  *  GNU general public license version 2. See "COPYING" or
   5  *  http://www.gnu.org/licenses/gpl.html
   6  */
   7
   8
   9 enum pstate {
  10         HW_PSTATE_INVALID = 0xff,
  11         HW_PSTATE_0 = 0,
  12         HW_PSTATE_1 = 1,
  13         HW_PSTATE_2 = 2,
  14         HW_PSTATE_3 = 3,
  15         HW_PSTATE_4 = 4,
  16         HW_PSTATE_5 = 5,
  17         HW_PSTATE_6 = 6,
  18         HW_PSTATE_7 = 7,
  19 };
  20
  21 struct powernow_k8_data {
  22         unsigned int cpu;
  23
  24         u32 numps;  /* number of p-states */
  25         u32 batps;  /* number of p-states supported on battery */
  26         u32 max_hw_pstate; /* maximum legal hardware pstate */
  27
  28         /* these values are constant when the PSB is used to determine
  29          * vid/fid pairings, but are modified during the ->target() call
  30          * when ACPI is used */
  31         u32 rvo;     /* ramp voltage offset */
  32         u32 irt;     /* isochronous relief time */
  33         u32 vidmvs;  /* usable value calculated from mvs */
  34         u32 vstable; /* voltage stabilization time, units 20 us */
  35         u32 plllock; /* pll lock time, units 1 us */
  36         u32 exttype; /* extended interface = 1 */
  37
  38         /* keep track of the current fid / vid or pstate */
  39         u32 currvid;
  40         u32 currfid;
  41         enum pstate currpstate;
  42
  43         /* the powernow_table includes all frequency and vid/fid pairings:
  44          * fid are the lower 8 bits of the index, vid are the upper 8 bits.
  45          * frequency is in kHz */
  46         struct cpufreq_frequency_table  *powernow_table;
  47
  48 #ifdef CONFIG_X86_POWERNOW_K8_ACPI
  49         /* the acpi table needs to be kept. it's only available if ACPI was
  50          * used to determine valid frequency/vid/fid states */
  51         struct acpi_processor_performance acpi_data;
  52 #endif
  53         /* we need to keep track of associated cores, but let cpufreq
  54          * handle hotplug events - so just point at cpufreq pol->cpus
  55          * structure */
  56         cpumask_t *available_cores;
  57 };
  58
  59
  60 /* processor's cpuid instruction support */
  61 #define CPUID_PROCESSOR_SIGNATURE       1       /* function 1 */
  62 #define CPUID_XFAM                      0x0ff00000      /* extended family */
  63 #define CPUID_XFAM_K8                   0
  64 #define CPUID_XMOD                      0x000f0000      /* extended model */
  65 #define CPUID_XMOD_REV_MASK             0x000c0000
  66 #define CPUID_XFAM_10H                  0x00100000      /* family 0x10 */
  67 #define CPUID_USE_XFAM_XMOD             0x00000f00
  68 #define CPUID_GET_MAX_CAPABILITIES      0x80000000
  69 #define CPUID_FREQ_VOLT_CAPABILITIES    0x80000007
  70 #define P_STATE_TRANSITION_CAPABLE      6
  71
  72 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For     */
  73 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and   */
  74 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
  75 /* the register number is placed in ecx, and the data is returned in edx:eax. */
  76
  77 #define MSR_FIDVID_CTL      0xc0010041
  78 #define MSR_FIDVID_STATUS   0xc0010042
  79
  80 /* Field definitions within the FID VID Low Control MSR : */
  81 #define MSR_C_LO_INIT_FID_VID     0x00010000
  82 #define MSR_C_LO_NEW_VID          0x00003f00
  83 #define MSR_C_LO_NEW_FID          0x0000003f
  84 #define MSR_C_LO_VID_SHIFT        8
  85
  86 /* Field definitions within the FID VID High Control MSR : */
  87 #define MSR_C_HI_STP_GNT_TO       0x000fffff
  88
  89 /* Field definitions within the FID VID Low Status MSR : */
  90 #define MSR_S_LO_CHANGE_PENDING   0x80000000   /* cleared when completed */
  91 #define MSR_S_LO_MAX_RAMP_VID     0x3f000000
  92 #define MSR_S_LO_MAX_FID          0x003f0000
  93 #define MSR_S_LO_START_FID        0x00003f00
  94 #define MSR_S_LO_CURRENT_FID      0x0000003f
  95
  96 /* Field definitions within the FID VID High Status MSR : */
  97 #define MSR_S_HI_MIN_WORKING_VID  0x3f000000
  98 #define MSR_S_HI_MAX_WORKING_VID  0x003f0000
  99 #define MSR_S_HI_START_VID        0x00003f00
 100 #define MSR_S_HI_CURRENT_VID      0x0000003f
 101 #define MSR_C_HI_STP_GNT_BENIGN   0x00000001
 102
 103
 104 /* Hardware Pstate _PSS and MSR definitions */
 105 #define USE_HW_PSTATE           0x00000080
 106 #define HW_PSTATE_MASK          0x00000007
 107 #define HW_PSTATE_VALID_MASK    0x80000000
 108 #define HW_PSTATE_MAX_MASK      0x000000f0
 109 #define HW_PSTATE_MAX_SHIFT     4
 110 #define MSR_PSTATE_DEF_BASE     0xc0010064 /* base of Pstate MSRs */
 111 #define MSR_PSTATE_STATUS       0xc0010063 /* Pstate Status MSR */
 112 #define MSR_PSTATE_CTRL         0xc0010062 /* Pstate control MSR */
 113 #define MSR_PSTATE_CUR_LIMIT    0xc0010061 /* pstate current limit MSR */
 114
 115 /* define the two driver architectures */
 116 #define CPU_OPTERON 0
 117 #define CPU_HW_PSTATE 1
 118
 119
 120 /*
 121  * There are restrictions frequencies have to follow:
 122  * - only 1 entry in the low fid table ( <=1.4GHz )
 123  * - lowest entry in the high fid table must be >= 2 * the entry in the
 124  *   low fid table
 125  * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
 126  *   in the low fid table
 127  * - the parts can only step at <= 200 MHz intervals, odd fid values are
 128  *   supported in revision G and later revisions.
 129  * - lowest frequency must be >= interprocessor hypertransport link speed
 130  *   (only applies to MP systems obviously)
 131  */
 132
 133 /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
 134 #define LO_FID_TABLE_TOP     7  /* fid values marking the boundary    */
 135 #define HI_FID_TABLE_BOTTOM  8  /* between the low and high tables    */
 136
 137 #define LO_VCOFREQ_TABLE_TOP    1400    /* corresponding vco frequency values */
 138 #define HI_VCOFREQ_TABLE_BOTTOM 1600
 139
 140 #define MIN_FREQ_RESOLUTION  200 /* fids jump by 2 matching freq jumps by 200 */
 141
 142 #define MAX_FID 0x2a    /* Spec only gives FID values as far as 5 GHz */
 143 #define LEAST_VID 0x3e  /* Lowest (numerically highest) useful vid value */
 144
 145 #define MIN_FREQ 800    /* Min and max freqs, per spec */
 146 #define MAX_FREQ 5000
 147
 148 #define INVALID_FID_MASK 0xffffffc0  /* not a valid fid if these bits are set */
 149 #define INVALID_VID_MASK 0xffffffc0  /* not a valid vid if these bits are set */
 150
 151 #define VID_OFF 0x3f
 152
 153 #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
 154
 155 #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
 156
 157 #define MAXIMUM_VID_STEPS 1  /* Current cpus only allow a single step of 25mV */
 158 #define VST_UNITS_20US 20   /* Voltage Stabilization Time is in units of 20us */
 159
 160 /*
 161  * Most values of interest are encoded in a single field of the _PSS
 162  * entries: the "control" value.
 163  */
 164
 165 #define IRT_SHIFT      30
 166 #define RVO_SHIFT      28
 167 #define EXT_TYPE_SHIFT 27
 168 #define PLL_L_SHIFT    20
 169 #define MVS_SHIFT      18
 170 #define VST_SHIFT      11
 171 #define VID_SHIFT       6
 172 #define IRT_MASK        3
 173 #define RVO_MASK        3
 174 #define EXT_TYPE_MASK   1
 175 #define PLL_L_MASK   0x7f
 176 #define MVS_MASK        3
 177 #define VST_MASK     0x7f
 178 #define VID_MASK     0x1f
 179 #define FID_MASK     0x1f
 180 #define EXT_VID_MASK 0x3f
 181 #define EXT_FID_MASK 0x3f
 182
 183
 184 /*
 185  * Version 1.4 of the PSB table. This table is constructed by BIOS and is
 186  * to tell the OS's power management driver which VIDs and FIDs are
 187  * supported by this particular processor.
 188  * If the data in the PSB / PST is wrong, then this driver will program the
 189  * wrong values into hardware, which is very likely to lead to a crash.
 190  */
 191
 192 #define PSB_ID_STRING      "AMDK7PNOW!"
 193 #define PSB_ID_STRING_LEN  10
 194
 195 #define PSB_VERSION_1_4  0x14
 196
 197 struct psb_s {
 198         u8 signature[10];
 199         u8 tableversion;
 200         u8 flags1;
 201         u16 vstable;
 202         u8 flags2;
 203         u8 num_tables;
 204         u32 cpuid;
 205         u8 plllocktime;
 206         u8 maxfid;
 207         u8 maxvid;
 208         u8 numps;
 209 };
 210
 211 /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
 212 struct pst_s {
 213         u8 fid;
 214         u8 vid;
 215 };
 216
 217 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "powernow-k8", msg)
 218
 219 static int core_voltage_pre_transition(struct powernow_k8_data *data, u32 reqvid);
 220 static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
 221 static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
 222
 223 static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);
 224
 225 #ifdef CONFIG_X86_POWERNOW_K8_ACPI
 226 static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
 227 static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
 228 #endif
 229
 230 #ifdef CONFIG_SMP
 231 static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
 232 {
 233 }
 234 #else
 235 static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
 236 {
 237         cpu_set(0, cpu_sharedcore_mask[0]);
 238 }
 239 #endif