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staging: brcm80211: replaced BCME_OK by 0
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / brcm80211 / brcmfmac / dhd_sdio.c
blob40d6de3b162b68893b19a96dd1e610951c151bd5
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/pci_ids.h>
19 #include <bcmdefs.h>
20 #include <linux/netdevice.h>
21 #include <bcmsdh.h>
22
23 #ifdef BCMEMBEDIMAGE
24 #include BCMEMBEDIMAGE
25 #endif /* BCMEMBEDIMAGE */
26
27 #include <bcmdefs.h>
28 #include <bcmutils.h>
29 #include <bcmdevs.h>
30
31 #include <siutils.h>
32 #include <hndpmu.h>
33 #include <hndsoc.h>
34 #ifdef DHD_DEBUG
35 #include <hndrte_armtrap.h>
36 #include <hndrte_cons.h>
37 #endif /* DHD_DEBUG */
38 #include <sbchipc.h>
39 #include <sbhnddma.h>
40
41 #include <sdio.h>
42 #include <sbsdio.h>
43 #include <sbsdpcmdev.h>
44 #include <bcmsdpcm.h>
45
46 #include <proto/802.11.h>
47
48 #include <dngl_stats.h>
49 #include <dhd.h>
50 #include <dhd_bus.h>
51 #include <dhd_proto.h>
52 #include <dhd_dbg.h>
53 #include <dhdioctl.h>
54 #include <sdiovar.h>
55 #include <siutils_priv.h>
56
57 #ifndef DHDSDIO_MEM_DUMP_FNAME
58 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
59 #endif
60
61 #define TXQLEN 2048 /* bulk tx queue length */
62 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
63 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
64 #define PRIOMASK 7
65
66 #define TXRETRIES 2 /* # of retries for tx frames */
67
68 #if defined(CONFIG_MACH_SANDGATE2G)
69 #define DHD_RXBOUND 250 /* Default for max rx frames in
70 one scheduling */
71 #else
72 #define DHD_RXBOUND 50 /* Default for max rx frames in
73 one scheduling */
74 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
75
76 #define DHD_TXBOUND 20 /* Default for max tx frames in
77 one scheduling */
78
79 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
80
81 #define MEMBLOCK 2048 /* Block size used for downloading
82 of dongle image */
83 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
84 biggest possible glom */
85
86 /* Packet alignment for most efficient SDIO (can change based on platform) */
87 #ifndef DHD_SDALIGN
88 #define DHD_SDALIGN 32
89 #endif
90 #if !ISPOWEROF2(DHD_SDALIGN)
91 #error DHD_SDALIGN is not a power of 2!
92 #endif
93
94 #ifndef DHD_FIRSTREAD
95 #define DHD_FIRSTREAD 32
96 #endif
97 #if !ISPOWEROF2(DHD_FIRSTREAD)
98 #error DHD_FIRSTREAD is not a power of 2!
99 #endif
100
101 /* Total length of frame header for dongle protocol */
102 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
103 #ifdef SDTEST
104 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
105 #else
106 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
107 #endif
108
109 /* Space for header read, limit for data packets */
110 #ifndef MAX_HDR_READ
111 #define MAX_HDR_READ 32
112 #endif
113 #if !ISPOWEROF2(MAX_HDR_READ)
114 #error MAX_HDR_READ is not a power of 2!
115 #endif
116
117 #define MAX_RX_DATASZ 2048
118
119 /* Maximum milliseconds to wait for F2 to come up */
120 #define DHD_WAIT_F2RDY 3000
121
122 /* Bump up limit on waiting for HT to account for first startup;
123 * if the image is doing a CRC calculation before programming the PMU
124 * for HT availability, it could take a couple hundred ms more, so
125 * max out at a 1 second (1000000us).
126 */
127 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
128 #undef PMU_MAX_TRANSITION_DLY
129 #define PMU_MAX_TRANSITION_DLY 1000000
130 #endif
131
132 /* Value for ChipClockCSR during initial setup */
133 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
134 SBSDIO_ALP_AVAIL_REQ)
135 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
136
137 /* Flags for SDH calls */
138 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
139
140 /* Packet free applicable unconditionally for sdio and sdspi. Conditional if
141 * bufpool was present for gspi bus.
142 */
143 #define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
144 pkt_buf_free_skb(pkt);
145
146 /*
147 * Conversion of 802.1D priority to precedence level
148 */
149 #define PRIO2PREC(prio) \
150 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
151 ((prio^2)) : (prio))
152
153 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
154 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
155 uint len);
156
157 #ifdef DHD_DEBUG
158 /* Device console log buffer state */
159 typedef struct dhd_console {
160 uint count; /* Poll interval msec counter */
161 uint log_addr; /* Log struct address (fixed) */
162 hndrte_log_t log; /* Log struct (host copy) */
163 uint bufsize; /* Size of log buffer */
164 u8 *buf; /* Log buffer (host copy) */
165 uint last; /* Last buffer read index */
166 } dhd_console_t;
167 #endif /* DHD_DEBUG */
168
169 /* Private data for SDIO bus interaction */
170 typedef struct dhd_bus {
171 dhd_pub_t *dhd;
172
173 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
174 si_t *sih; /* Handle for SI calls */
175 char *vars; /* Variables (from CIS and/or other) */
176 uint varsz; /* Size of variables buffer */
177 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
178
179 sdpcmd_regs_t *regs; /* Registers for SDIO core */
180 uint sdpcmrev; /* SDIO core revision */
181 uint armrev; /* CPU core revision */
182 uint ramrev; /* SOCRAM core revision */
183 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
184 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
185
186 u32 bus; /* gSPI or SDIO bus */
187 u32 hostintmask; /* Copy of Host Interrupt Mask */
188 u32 intstatus; /* Intstatus bits (events) pending */
189 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
190 bool fcstate; /* State of dongle flow-control */
191
192 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
193 char *fw_path; /* module_param: path to firmware image */
194 char *nv_path; /* module_param: path to nvram vars file */
195 const char *nvram_params; /* user specified nvram params. */
196
197 uint blocksize; /* Block size of SDIO transfers */
198 uint roundup; /* Max roundup limit */
199
200 struct pktq txq; /* Queue length used for flow-control */
201 u8 flowcontrol; /* per prio flow control bitmask */
202 u8 tx_seq; /* Transmit sequence number (next) */
203 u8 tx_max; /* Maximum transmit sequence allowed */
204
205 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
206 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
207 u16 nextlen; /* Next Read Len from last header */
208 u8 rx_seq; /* Receive sequence number (expected) */
209 bool rxskip; /* Skip receive (awaiting NAK ACK) */
210
211 struct sk_buff *glomd; /* Packet containing glomming descriptor */
212 struct sk_buff *glom; /* Packet chain for glommed superframe */
213 uint glomerr; /* Glom packet read errors */
214
215 u8 *rxbuf; /* Buffer for receiving control packets */
216 uint rxblen; /* Allocated length of rxbuf */
217 u8 *rxctl; /* Aligned pointer into rxbuf */
218 u8 *databuf; /* Buffer for receiving big glom packet */
219 u8 *dataptr; /* Aligned pointer into databuf */
220 uint rxlen; /* Length of valid data in buffer */
221
222 u8 sdpcm_ver; /* Bus protocol reported by dongle */
223
224 bool intr; /* Use interrupts */
225 bool poll; /* Use polling */
226 bool ipend; /* Device interrupt is pending */
227 bool intdis; /* Interrupts disabled by isr */
228 uint intrcount; /* Count of device interrupt callbacks */
229 uint lastintrs; /* Count as of last watchdog timer */
230 uint spurious; /* Count of spurious interrupts */
231 uint pollrate; /* Ticks between device polls */
232 uint polltick; /* Tick counter */
233 uint pollcnt; /* Count of active polls */
234
235 #ifdef DHD_DEBUG
236 dhd_console_t console; /* Console output polling support */
237 uint console_addr; /* Console address from shared struct */
238 #endif /* DHD_DEBUG */
239
240 uint regfails; /* Count of R_REG/W_REG failures */
241
242 uint clkstate; /* State of sd and backplane clock(s) */
243 bool activity; /* Activity flag for clock down */
244 s32 idletime; /* Control for activity timeout */
245 s32 idlecount; /* Activity timeout counter */
246 s32 idleclock; /* How to set bus driver when idle */
247 s32 sd_divisor; /* Speed control to bus driver */
248 s32 sd_mode; /* Mode control to bus driver */
249 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
250 bool use_rxchain; /* If dhd should use PKT chains */
251 bool sleeping; /* Is SDIO bus sleeping? */
252 bool rxflow_mode; /* Rx flow control mode */
253 bool rxflow; /* Is rx flow control on */
254 uint prev_rxlim_hit; /* Is prev rx limit exceeded
255 (per dpc schedule) */
256 bool alp_only; /* Don't use HT clock (ALP only) */
257 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
258 bool usebufpool;
259
260 #ifdef SDTEST
261 /* external loopback */
262 bool ext_loop;
263 u8 loopid;
264
265 /* pktgen configuration */
266 uint pktgen_freq; /* Ticks between bursts */
267 uint pktgen_count; /* Packets to send each burst */
268 uint pktgen_print; /* Bursts between count displays */
269 uint pktgen_total; /* Stop after this many */
270 uint pktgen_minlen; /* Minimum packet data len */
271 uint pktgen_maxlen; /* Maximum packet data len */
272 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
273 uint pktgen_stop; /* Number of tx failures causing stop */
274
275 /* active pktgen fields */
276 uint pktgen_tick; /* Tick counter for bursts */
277 uint pktgen_ptick; /* Burst counter for printing */
278 uint pktgen_sent; /* Number of test packets generated */
279 uint pktgen_rcvd; /* Number of test packets received */
280 uint pktgen_fail; /* Number of failed send attempts */
281 u16 pktgen_len; /* Length of next packet to send */
282 #endif /* SDTEST */
283
284 /* Some additional counters */
285 uint tx_sderrs; /* Count of tx attempts with sd errors */
286 uint fcqueued; /* Tx packets that got queued */
287 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
288 uint rx_toolong; /* Receive frames too long to receive */
289 uint rxc_errors; /* SDIO errors when reading control frames */
290 uint rx_hdrfail; /* SDIO errors on header reads */
291 uint rx_badhdr; /* Bad received headers (roosync?) */
292 uint rx_badseq; /* Mismatched rx sequence number */
293 uint fc_rcvd; /* Number of flow-control events received */
294 uint fc_xoff; /* Number which turned on flow-control */
295 uint fc_xon; /* Number which turned off flow-control */
296 uint rxglomfail; /* Failed deglom attempts */
297 uint rxglomframes; /* Number of glom frames (superframes) */
298 uint rxglompkts; /* Number of packets from glom frames */
299 uint f2rxhdrs; /* Number of header reads */
300 uint f2rxdata; /* Number of frame data reads */
301 uint f2txdata; /* Number of f2 frame writes */
302 uint f1regdata; /* Number of f1 register accesses */
303
304 u8 *ctrl_frame_buf;
305 u32 ctrl_frame_len;
306 bool ctrl_frame_stat;
307 } dhd_bus_t;
308
309 /* clkstate */
310 #define CLK_NONE 0
311 #define CLK_SDONLY 1
312 #define CLK_PENDING 2 /* Not used yet */
313 #define CLK_AVAIL 3
314
315 #define DHD_NOPMU(dhd) (false)
316
317 #ifdef DHD_DEBUG
318 static int qcount[NUMPRIO];
319 static int tx_packets[NUMPRIO];
320 #endif /* DHD_DEBUG */
321
322 /* Deferred transmit */
323 const uint dhd_deferred_tx = 1;
324
325 extern uint dhd_watchdog_ms;
326 extern void dhd_os_wd_timer(void *bus, uint wdtick);
327
328 /* Tx/Rx bounds */
329 uint dhd_txbound;
330 uint dhd_rxbound;
331 uint dhd_txminmax;
332
333 /* override the RAM size if possible */
334 #define DONGLE_MIN_MEMSIZE (128 * 1024)
335 int dhd_dongle_memsize;
336
337 static bool dhd_alignctl;
338
339 static bool sd1idle;
340
341 static bool retrydata;
342 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
343
344 static const uint watermark = 8;
345 static const uint firstread = DHD_FIRSTREAD;
346
347 #define HDATLEN (firstread - (SDPCM_HDRLEN))
348
349 /* Retry count for register access failures */
350 static const uint retry_limit = 2;
351
352 /* Force even SD lengths (some host controllers mess up on odd bytes) */
353 static bool forcealign;
354
355 #define ALIGNMENT 4
356
357 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
358 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
359 #endif
360
361 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
362 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
363 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
364 #define PKTALIGN(_p, _len, _align) \
365 do { \
366 uint datalign; \
367 datalign = (unsigned long)((_p)->data); \
368 datalign = roundup(datalign, (_align)) - datalign; \
369 ASSERT(datalign < (_align)); \
370 ASSERT((_p)->len >= ((_len) + datalign)); \
371 if (datalign) \
372 skb_pull((_p), datalign); \
373 __skb_trim((_p), (_len)); \
374 } while (0)
375
376 /* Limit on rounding up frames */
377 static const uint max_roundup = 512;
378
379 /* Try doing readahead */
380 static bool dhd_readahead;
381
382 /* To check if there's window offered */
383 #define DATAOK(bus) \
384 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
385 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
386
387 /* Macros to get register read/write status */
388 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
389 #define R_SDREG(regvar, regaddr, retryvar) \
390 do { \
391 retryvar = 0; \
392 do { \
393 regvar = R_REG(regaddr); \
394 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
395 if (retryvar) { \
396 bus->regfails += (retryvar-1); \
397 if (retryvar > retry_limit) { \
398 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
399 __func__, __LINE__)); \
400 regvar = 0; \
401 } \
402 } \
403 } while (0)
404
405 #define W_SDREG(regval, regaddr, retryvar) \
406 do { \
407 retryvar = 0; \
408 do { \
409 W_REG(regaddr, regval); \
410 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
411 if (retryvar) { \
412 bus->regfails += (retryvar-1); \
413 if (retryvar > retry_limit) \
414 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
415 __func__, __LINE__)); \
416 } \
417 } while (0)
418
419 #define DHD_BUS SDIO_BUS
420
421 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
422
423 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
424
425 #define GSPI_PR55150_BAILOUT
426
427 #ifdef SDTEST
428 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
429 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
430 #endif
431
432 #ifdef DHD_DEBUG
433 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
434 static int dhdsdio_mem_dump(dhd_bus_t *bus);
435 #endif /* DHD_DEBUG */
436 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
437
438 static void dhdsdio_release(dhd_bus_t *bus);
439 static void dhdsdio_release_malloc(dhd_bus_t *bus);
440 static void dhdsdio_disconnect(void *ptr);
441 static bool dhdsdio_chipmatch(u16 chipid);
442 static bool dhdsdio_probe_attach(dhd_bus_t *bus, void *sdh,
443 void *regsva, u16 devid);
444 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh);
445 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh);
446 static void dhdsdio_release_dongle(dhd_bus_t *bus);
447
448 static uint process_nvram_vars(char *varbuf, uint len);
449
450 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
451 static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn,
452 uint flags, u8 *buf, uint nbytes,
453 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
454 void *handle);
455 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
456 uint flags, u8 *buf, uint nbytes,
457 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
458 void *handle);
459
460 static bool dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh);
461 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
462
463 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
464 static int dhdsdio_download_nvram(struct dhd_bus *bus);
465 #ifdef BCMEMBEDIMAGE
466 static int dhdsdio_download_code_array(struct dhd_bus *bus);
467 #endif
468
469 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
470 {
471 s32 min_size = DONGLE_MIN_MEMSIZE;
472 /* Restrict the memsize to user specified limit */
473 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
474 dhd_dongle_memsize, min_size));
475 if ((dhd_dongle_memsize > min_size) &&
476 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
477 bus->ramsize = dhd_dongle_memsize;
478 }
479
480 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
481 {
482 int err = 0;
483 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
484 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
485 if (!err)
486 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
487 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
488 if (!err)
489 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
490 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
491 &err);
492 return err;
493 }
494
495 /* Turn backplane clock on or off */
496 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
497 {
498 int err;
499 u8 clkctl, clkreq, devctl;
500 bcmsdh_info_t *sdh;
501
502 DHD_TRACE(("%s: Enter\n", __func__));
503
504 #if defined(OOB_INTR_ONLY)
505 pendok = false;
506 #endif
507 clkctl = 0;
508 sdh = bus->sdh;
509
510 if (on) {
511 /* Request HT Avail */
512 clkreq =
513 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
514
515 if ((bus->sih->chip == BCM4329_CHIP_ID)
516 && (bus->sih->chiprev == 0))
517 clkreq |= SBSDIO_FORCE_ALP;
518
519 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
520 clkreq, &err);
521 if (err) {
522 DHD_ERROR(("%s: HT Avail request error: %d\n",
523 __func__, err));
524 return BCME_ERROR;
525 }
526
527 if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
528 && (bus->sih->buscorerev == 9))) {
529 u32 dummy, retries;
530 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
531 }
532
533 /* Check current status */
534 clkctl =
535 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
536 &err);
537 if (err) {
538 DHD_ERROR(("%s: HT Avail read error: %d\n",
539 __func__, err));
540 return BCME_ERROR;
541 }
542
543 /* Go to pending and await interrupt if appropriate */
544 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
545 /* Allow only clock-available interrupt */
546 devctl =
547 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
548 &err);
549 if (err) {
550 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
551 __func__, err));
552 return BCME_ERROR;
553 }
554
555 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
556 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
557 devctl, &err);
558 DHD_INFO(("CLKCTL: set PENDING\n"));
559 bus->clkstate = CLK_PENDING;
560
561 return 0;
562 } else if (bus->clkstate == CLK_PENDING) {
563 /* Cancel CA-only interrupt filter */
564 devctl =
565 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
566 &err);
567 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
568 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
569 devctl, &err);
570 }
571
572 /* Otherwise, wait here (polling) for HT Avail */
573 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
574 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
575 ((clkctl =
576 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
577 SBSDIO_FUNC1_CHIPCLKCSR,
578 &err)),
579 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
580 PMU_MAX_TRANSITION_DLY);
581 }
582 if (err) {
583 DHD_ERROR(("%s: HT Avail request error: %d\n",
584 __func__, err));
585 return BCME_ERROR;
586 }
587 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
588 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
589 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
590 return BCME_ERROR;
591 }
592
593 /* Mark clock available */
594 bus->clkstate = CLK_AVAIL;
595 DHD_INFO(("CLKCTL: turned ON\n"));
596
597 #if defined(DHD_DEBUG)
598 if (bus->alp_only == true) {
599 #if !defined(BCMLXSDMMC)
600 if (!SBSDIO_ALPONLY(clkctl)) {
601 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
602 __func__));
603 }
604 #endif /* !defined(BCMLXSDMMC) */
605 } else {
606 if (SBSDIO_ALPONLY(clkctl)) {
607 DHD_ERROR(("%s: HT Clock should be on.\n",
608 __func__));
609 }
610 }
611 #endif /* defined (DHD_DEBUG) */
612
613 bus->activity = true;
614 } else {
615 clkreq = 0;
616
617 if (bus->clkstate == CLK_PENDING) {
618 /* Cancel CA-only interrupt filter */
619 devctl =
620 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
621 &err);
622 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
623 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
624 devctl, &err);
625 }
626
627 bus->clkstate = CLK_SDONLY;
628 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
629 clkreq, &err);
630 DHD_INFO(("CLKCTL: turned OFF\n"));
631 if (err) {
632 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
633 __func__, err));
634 return BCME_ERROR;
635 }
636 }
637 return 0;
638 }
639
640 /* Change idle/active SD state */
641 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
642 {
643 int err;
644 s32 iovalue;
645
646 DHD_TRACE(("%s: Enter\n", __func__));
647
648 if (on) {
649 if (bus->idleclock == DHD_IDLE_STOP) {
650 /* Turn on clock and restore mode */
651 iovalue = 1;
652 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
653 &iovalue, sizeof(iovalue), true);
654 if (err) {
655 DHD_ERROR(("%s: error enabling sd_clock: %d\n",
656 __func__, err));
657 return BCME_ERROR;
658 }
659
660 iovalue = bus->sd_mode;
661 err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
662 &iovalue, sizeof(iovalue), true);
663 if (err) {
664 DHD_ERROR(("%s: error changing sd_mode: %d\n",
665 __func__, err));
666 return BCME_ERROR;
667 }
668 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
669 /* Restore clock speed */
670 iovalue = bus->sd_divisor;
671 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
672 &iovalue, sizeof(iovalue), true);
673 if (err) {
674 DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
675 __func__, err));
676 return BCME_ERROR;
677 }
678 }
679 bus->clkstate = CLK_SDONLY;
680 } else {
681 /* Stop or slow the SD clock itself */
682 if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
683 DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
684 __func__, bus->sd_divisor, bus->sd_mode));
685 return BCME_ERROR;
686 }
687 if (bus->idleclock == DHD_IDLE_STOP) {
688 if (sd1idle) {
689 /* Change to SD1 mode and turn off clock */
690 iovalue = 1;
691 err =
692 bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL,
693 0, &iovalue,
694 sizeof(iovalue), true);
695 if (err) {
696 DHD_ERROR(("%s: error changing sd_clock: %d\n",
697 __func__, err));
698 return BCME_ERROR;
699 }
700 }
701
702 iovalue = 0;
703 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
704 &iovalue, sizeof(iovalue), true);
705 if (err) {
706 DHD_ERROR(("%s: error disabling sd_clock: %d\n",
707 __func__, err));
708 return BCME_ERROR;
709 }
710 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
711 /* Set divisor to idle value */
712 iovalue = bus->idleclock;
713 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
714 &iovalue, sizeof(iovalue), true);
715 if (err) {
716 DHD_ERROR(("%s: error changing sd_divisor: %d\n",
717 __func__, err));
718 return BCME_ERROR;
719 }
720 }
721 bus->clkstate = CLK_NONE;
722 }
723
724 return 0;
725 }
726
727 /* Transition SD and backplane clock readiness */
728 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
729 {
730 #ifdef DHD_DEBUG
731 uint oldstate = bus->clkstate;
732 #endif /* DHD_DEBUG */
733
734 DHD_TRACE(("%s: Enter\n", __func__));
735
736 /* Early exit if we're already there */
737 if (bus->clkstate == target) {
738 if (target == CLK_AVAIL) {
739 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
740 bus->activity = true;
741 }
742 return 0;
743 }
744
745 switch (target) {
746 case CLK_AVAIL:
747 /* Make sure SD clock is available */
748 if (bus->clkstate == CLK_NONE)
749 dhdsdio_sdclk(bus, true);
750 /* Now request HT Avail on the backplane */
751 dhdsdio_htclk(bus, true, pendok);
752 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
753 bus->activity = true;
754 break;
755
756 case CLK_SDONLY:
757 /* Remove HT request, or bring up SD clock */
758 if (bus->clkstate == CLK_NONE)
759 dhdsdio_sdclk(bus, true);
760 else if (bus->clkstate == CLK_AVAIL)
761 dhdsdio_htclk(bus, false, false);
762 else
763 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
764 bus->clkstate, target));
765 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
766 break;
767
768 case CLK_NONE:
769 /* Make sure to remove HT request */
770 if (bus->clkstate == CLK_AVAIL)
771 dhdsdio_htclk(bus, false, false);
772 /* Now remove the SD clock */
773 dhdsdio_sdclk(bus, false);
774 dhd_os_wd_timer(bus->dhd, 0);
775 break;
776 }
777 #ifdef DHD_DEBUG
778 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
779 #endif /* DHD_DEBUG */
780
781 return 0;
782 }
783
784 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
785 {
786 bcmsdh_info_t *sdh = bus->sdh;
787 sdpcmd_regs_t *regs = bus->regs;
788 uint retries = 0;
789
790 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
791 (sleep ? "SLEEP" : "WAKE"),
792 (bus->sleeping ? "SLEEP" : "WAKE")));
793
794 /* Done if we're already in the requested state */
795 if (sleep == bus->sleeping)
796 return 0;
797
798 /* Going to sleep: set the alarm and turn off the lights... */
799 if (sleep) {
800 /* Don't sleep if something is pending */
801 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
802 return BCME_BUSY;
803
804 /* Disable SDIO interrupts (no longer interested) */
805 bcmsdh_intr_disable(bus->sdh);
806
807 /* Make sure the controller has the bus up */
808 dhdsdio_clkctl(bus, CLK_AVAIL, false);
809
810 /* Tell device to start using OOB wakeup */
811 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
812 if (retries > retry_limit)
813 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
814
815 /* Turn off our contribution to the HT clock request */
816 dhdsdio_clkctl(bus, CLK_SDONLY, false);
817
818 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
819 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
820
821 /* Isolate the bus */
822 if (bus->sih->chip != BCM4329_CHIP_ID
823 && bus->sih->chip != BCM4319_CHIP_ID) {
824 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
825 SBSDIO_DEVCTL_PADS_ISO, NULL);
826 }
827
828 /* Change state */
829 bus->sleeping = true;
830
831 } else {
832 /* Waking up: bus power up is ok, set local state */
833
834 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
835 0, NULL);
836
837 /* Force pad isolation off if possible
838 (in case power never toggled) */
839 if ((bus->sih->buscoretype == PCMCIA_CORE_ID)
840 && (bus->sih->buscorerev >= 10))
841 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
842 NULL);
843
844 /* Make sure the controller has the bus up */
845 dhdsdio_clkctl(bus, CLK_AVAIL, false);
846
847 /* Send misc interrupt to indicate OOB not needed */
848 W_SDREG(0, &regs->tosbmailboxdata, retries);
849 if (retries <= retry_limit)
850 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
851
852 if (retries > retry_limit)
853 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
854
855 /* Make sure we have SD bus access */
856 dhdsdio_clkctl(bus, CLK_SDONLY, false);
857
858 /* Change state */
859 bus->sleeping = false;
860
861 /* Enable interrupts again */
862 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
863 bus->intdis = false;
864 bcmsdh_intr_enable(bus->sdh);
865 }
866 }
867
868 return 0;
869 }
870
871 #if defined(OOB_INTR_ONLY)
872 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
873 {
874 #if defined(HW_OOB)
875 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
876 #else
877 sdpcmd_regs_t *regs = bus->regs;
878 uint retries = 0;
879
880 dhdsdio_clkctl(bus, CLK_AVAIL, false);
881 if (enable == true) {
882
883 /* Tell device to start using OOB wakeup */
884 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
885 if (retries > retry_limit)
886 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
887
888 } else {
889 /* Send misc interrupt to indicate OOB not needed */
890 W_SDREG(0, &regs->tosbmailboxdata, retries);
891 if (retries <= retry_limit)
892 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
893 }
894
895 /* Turn off our contribution to the HT clock request */
896 dhdsdio_clkctl(bus, CLK_SDONLY, false);
897 #endif /* !defined(HW_OOB) */
898 }
899 #endif /* defined(OOB_INTR_ONLY) */
900
901 #define BUS_WAKE(bus) \
902 do { \
903 if ((bus)->sleeping) \
904 dhdsdio_bussleep((bus), false); \
905 } while (0);
906
907 /* Writes a HW/SW header into the packet and sends it. */
908 /* Assumes: (a) header space already there, (b) caller holds lock */
909 static int dhdsdio_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
910 bool free_pkt)
911 {
912 int ret;
913 u8 *frame;
914 u16 len, pad = 0;
915 u32 swheader;
916 uint retries = 0;
917 bcmsdh_info_t *sdh;
918 struct sk_buff *new;
919 int i;
920
921 DHD_TRACE(("%s: Enter\n", __func__));
922
923 sdh = bus->sdh;
924
925 if (bus->dhd->dongle_reset) {
926 ret = BCME_NOTREADY;
927 goto done;
928 }
929
930 frame = (u8 *) (pkt->data);
931
932 /* Add alignment padding, allocate new packet if needed */
933 pad = ((unsigned long)frame % DHD_SDALIGN);
934 if (pad) {
935 if (skb_headroom(pkt) < pad) {
936 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
937 __func__, skb_headroom(pkt), pad));
938 bus->dhd->tx_realloc++;
939 new = pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
940 if (!new) {
941 DHD_ERROR(("%s: couldn't allocate new %d-byte "
942 "packet\n",
943 __func__, pkt->len + DHD_SDALIGN));
944 ret = BCME_NOMEM;
945 goto done;
946 }
947
948 PKTALIGN(new, pkt->len, DHD_SDALIGN);
949 memcpy(new->data, pkt->data, pkt->len);
950 if (free_pkt)
951 pkt_buf_free_skb(pkt);
952 /* free the pkt if canned one is not used */
953 free_pkt = true;
954 pkt = new;
955 frame = (u8 *) (pkt->data);
956 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
957 pad = 0;
958 } else {
959 skb_push(pkt, pad);
960 frame = (u8 *) (pkt->data);
961
962 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
963 memset(frame, 0, pad + SDPCM_HDRLEN);
964 }
965 }
966 ASSERT(pad < DHD_SDALIGN);
967
968 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
969 len = (u16) (pkt->len);
970 *(u16 *) frame = cpu_to_le16(len);
971 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
972
973 /* Software tag: channel, sequence number, data offset */
974 swheader =
975 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
976 (((pad +
977 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
978
979 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
980 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
981
982 #ifdef DHD_DEBUG
983 tx_packets[pkt->priority]++;
984 if (DHD_BYTES_ON() &&
985 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
986 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
987 prhex("Tx Frame", frame, len);
988 } else if (DHD_HDRS_ON()) {
989 prhex("TxHdr", frame, min_t(u16, len, 16));
990 }
991 #endif
992
993 /* Raise len to next SDIO block to eliminate tail command */
994 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
995 u16 pad = bus->blocksize - (len % bus->blocksize);
996 if ((pad <= bus->roundup) && (pad < bus->blocksize))
997 #ifdef NOTUSED
998 if (pad <= skb_tailroom(pkt))
999 #endif /* NOTUSED */
1000 len += pad;
1001 } else if (len % DHD_SDALIGN) {
1002 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1003 }
1004
1005 /* Some controllers have trouble with odd bytes -- round to even */
1006 if (forcealign && (len & (ALIGNMENT - 1))) {
1007 #ifdef NOTUSED
1008 if (skb_tailroom(pkt))
1009 #endif
1010 len = roundup(len, ALIGNMENT);
1011 #ifdef NOTUSED
1012 else
1013 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1014 __func__, len));
1015 #endif
1016 }
1017
1018 do {
1019 ret =
1020 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1021 F2SYNC, frame, len, pkt, NULL, NULL);
1022 bus->f2txdata++;
1023 ASSERT(ret != BCME_PENDING);
1024
1025 if (ret < 0) {
1026 /* On failure, abort the command
1027 and terminate the frame */
1028 DHD_INFO(("%s: sdio error %d, abort command and "
1029 "terminate frame.\n", __func__, ret));
1030 bus->tx_sderrs++;
1031
1032 bcmsdh_abort(sdh, SDIO_FUNC_2);
1033 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1034 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1035 NULL);
1036 bus->f1regdata++;
1037
1038 for (i = 0; i < 3; i++) {
1039 u8 hi, lo;
1040 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1041 SBSDIO_FUNC1_WFRAMEBCHI,
1042 NULL);
1043 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1044 SBSDIO_FUNC1_WFRAMEBCLO,
1045 NULL);
1046 bus->f1regdata += 2;
1047 if ((hi == 0) && (lo == 0))
1048 break;
1049 }
1050
1051 }
1052 if (ret == 0)
1053 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1054
1055 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1056
1057 done:
1058 /* restore pkt buffer pointer before calling tx complete routine */
1059 skb_pull(pkt, SDPCM_HDRLEN + pad);
1060 dhd_os_sdunlock(bus->dhd);
1061 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1062 dhd_os_sdlock(bus->dhd);
1063
1064 if (free_pkt)
1065 pkt_buf_free_skb(pkt);
1066
1067 return ret;
1068 }
1069
1070 int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1071 {
1072 int ret = BCME_ERROR;
1073 uint datalen, prec;
1074
1075 DHD_TRACE(("%s: Enter\n", __func__));
1076
1077 datalen = pkt->len;
1078
1079 #ifdef SDTEST
1080 /* Push the test header if doing loopback */
1081 if (bus->ext_loop) {
1082 u8 *data;
1083 skb_push(pkt, SDPCM_TEST_HDRLEN);
1084 data = pkt->data;
1085 *data++ = SDPCM_TEST_ECHOREQ;
1086 *data++ = (u8) bus->loopid++;
1087 *data++ = (datalen >> 0);
1088 *data++ = (datalen >> 8);
1089 datalen += SDPCM_TEST_HDRLEN;
1090 }
1091 #endif /* SDTEST */
1092
1093 /* Add space for the header */
1094 skb_push(pkt, SDPCM_HDRLEN);
1095 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1096
1097 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1098
1099 /* Check for existing queue, current flow-control,
1100 pending event, or pending clock */
1101 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1102 || bus->dpc_sched || (!DATAOK(bus))
1103 || (bus->flowcontrol & NBITVAL(prec))
1104 || (bus->clkstate != CLK_AVAIL)) {
1105 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1106 pktq_len(&bus->txq)));
1107 bus->fcqueued++;
1108
1109 /* Priority based enq */
1110 dhd_os_sdlock_txq(bus->dhd);
1111 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1112 skb_pull(pkt, SDPCM_HDRLEN);
1113 dhd_txcomplete(bus->dhd, pkt, false);
1114 pkt_buf_free_skb(pkt);
1115 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1116 ret = BCME_NORESOURCE;
1117 } else {
1118 ret = 0;
1119 }
1120 dhd_os_sdunlock_txq(bus->dhd);
1121
1122 if (pktq_len(&bus->txq) >= TXHI)
1123 dhd_txflowcontrol(bus->dhd, 0, ON);
1124
1125 #ifdef DHD_DEBUG
1126 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1127 qcount[prec] = pktq_plen(&bus->txq, prec);
1128 #endif
1129 /* Schedule DPC if needed to send queued packet(s) */
1130 if (dhd_deferred_tx && !bus->dpc_sched) {
1131 bus->dpc_sched = true;
1132 dhd_sched_dpc(bus->dhd);
1133 }
1134 } else {
1135 /* Lock: we're about to use shared data/code (and SDIO) */
1136 dhd_os_sdlock(bus->dhd);
1137
1138 /* Otherwise, send it now */
1139 BUS_WAKE(bus);
1140 /* Make sure back plane ht clk is on, no pending allowed */
1141 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1142
1143 #ifndef SDTEST
1144 DHD_TRACE(("%s: calling txpkt\n", __func__));
1145 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1146 #else
1147 ret = dhdsdio_txpkt(bus, pkt,
1148 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1149 SDPCM_DATA_CHANNEL), true);
1150 #endif
1151 if (ret)
1152 bus->dhd->tx_errors++;
1153 else
1154 bus->dhd->dstats.tx_bytes += datalen;
1155
1156 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1157 bus->activity = false;
1158 dhdsdio_clkctl(bus, CLK_NONE, true);
1159 }
1160
1161 dhd_os_sdunlock(bus->dhd);
1162 }
1163
1164 return ret;
1165 }
1166
1167 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1168 {
1169 struct sk_buff *pkt;
1170 u32 intstatus = 0;
1171 uint retries = 0;
1172 int ret = 0, prec_out;
1173 uint cnt = 0;
1174 uint datalen;
1175 u8 tx_prec_map;
1176
1177 dhd_pub_t *dhd = bus->dhd;
1178 sdpcmd_regs_t *regs = bus->regs;
1179
1180 DHD_TRACE(("%s: Enter\n", __func__));
1181
1182 tx_prec_map = ~bus->flowcontrol;
1183
1184 /* Send frames until the limit or some other event */
1185 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1186 dhd_os_sdlock_txq(bus->dhd);
1187 pkt = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1188 if (pkt == NULL) {
1189 dhd_os_sdunlock_txq(bus->dhd);
1190 break;
1191 }
1192 dhd_os_sdunlock_txq(bus->dhd);
1193 datalen = pkt->len - SDPCM_HDRLEN;
1194
1195 #ifndef SDTEST
1196 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1197 #else
1198 ret = dhdsdio_txpkt(bus, pkt,
1199 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1200 SDPCM_DATA_CHANNEL), true);
1201 #endif
1202 if (ret)
1203 bus->dhd->tx_errors++;
1204 else
1205 bus->dhd->dstats.tx_bytes += datalen;
1206
1207 /* In poll mode, need to check for other events */
1208 if (!bus->intr && cnt) {
1209 /* Check device status, signal pending interrupt */
1210 R_SDREG(intstatus, &regs->intstatus, retries);
1211 bus->f2txdata++;
1212 if (bcmsdh_regfail(bus->sdh))
1213 break;
1214 if (intstatus & bus->hostintmask)
1215 bus->ipend = true;
1216 }
1217 }
1218
1219 /* Deflow-control stack if needed */
1220 if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1221 dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1222 dhd_txflowcontrol(dhd, 0, OFF);
1223
1224 return cnt;
1225 }
1226
1227 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1228 {
1229 u8 *frame;
1230 u16 len;
1231 u32 swheader;
1232 uint retries = 0;
1233 bcmsdh_info_t *sdh = bus->sdh;
1234 u8 doff = 0;
1235 int ret = -1;
1236 int i;
1237
1238 DHD_TRACE(("%s: Enter\n", __func__));
1239
1240 if (bus->dhd->dongle_reset)
1241 return -EIO;
1242
1243 /* Back the pointer to make a room for bus header */
1244 frame = msg - SDPCM_HDRLEN;
1245 len = (msglen += SDPCM_HDRLEN);
1246
1247 /* Add alignment padding (optional for ctl frames) */
1248 if (dhd_alignctl) {
1249 doff = ((unsigned long)frame % DHD_SDALIGN);
1250 if (doff) {
1251 frame -= doff;
1252 len += doff;
1253 msglen += doff;
1254 memset(frame, 0, doff + SDPCM_HDRLEN);
1255 }
1256 ASSERT(doff < DHD_SDALIGN);
1257 }
1258 doff += SDPCM_HDRLEN;
1259
1260 /* Round send length to next SDIO block */
1261 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1262 u16 pad = bus->blocksize - (len % bus->blocksize);
1263 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1264 len += pad;
1265 } else if (len % DHD_SDALIGN) {
1266 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1267 }
1268
1269 /* Satisfy length-alignment requirements */
1270 if (forcealign && (len & (ALIGNMENT - 1)))
1271 len = roundup(len, ALIGNMENT);
1272
1273 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1274
1275 /* Need to lock here to protect txseq and SDIO tx calls */
1276 dhd_os_sdlock(bus->dhd);
1277
1278 BUS_WAKE(bus);
1279
1280 /* Make sure backplane clock is on */
1281 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1282
1283 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1284 *(u16 *) frame = cpu_to_le16((u16) msglen);
1285 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1286
1287 /* Software tag: channel, sequence number, data offset */
1288 swheader =
1289 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1290 SDPCM_CHANNEL_MASK)
1291 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1292 SDPCM_DOFFSET_MASK);
1293 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1294 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1295
1296 if (!DATAOK(bus)) {
1297 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1298 __func__, bus->tx_max, bus->tx_seq));
1299 bus->ctrl_frame_stat = true;
1300 /* Send from dpc */
1301 bus->ctrl_frame_buf = frame;
1302 bus->ctrl_frame_len = len;
1303
1304 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1305
1306 if (bus->ctrl_frame_stat == false) {
1307 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1308 ret = 0;
1309 } else {
1310 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1311 ret = -1;
1312 }
1313 }
1314
1315 if (ret == -1) {
1316 #ifdef DHD_DEBUG
1317 if (DHD_BYTES_ON() && DHD_CTL_ON())
1318 prhex("Tx Frame", frame, len);
1319 else if (DHD_HDRS_ON())
1320 prhex("TxHdr", frame, min_t(u16, len, 16));
1321 #endif
1322
1323 do {
1324 bus->ctrl_frame_stat = false;
1325 ret =
1326 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1327 SDIO_FUNC_2, F2SYNC, frame, len,
1328 NULL, NULL, NULL);
1329
1330 ASSERT(ret != BCME_PENDING);
1331
1332 if (ret < 0) {
1333 /* On failure, abort the command and
1334 terminate the frame */
1335 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1336 __func__, ret));
1337 bus->tx_sderrs++;
1338
1339 bcmsdh_abort(sdh, SDIO_FUNC_2);
1340
1341 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1342 SBSDIO_FUNC1_FRAMECTRL,
1343 SFC_WF_TERM, NULL);
1344 bus->f1regdata++;
1345
1346 for (i = 0; i < 3; i++) {
1347 u8 hi, lo;
1348 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1349 SBSDIO_FUNC1_WFRAMEBCHI,
1350 NULL);
1351 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1352 SBSDIO_FUNC1_WFRAMEBCLO,
1353 NULL);
1354 bus->f1regdata += 2;
1355 if ((hi == 0) && (lo == 0))
1356 break;
1357 }
1358
1359 }
1360 if (ret == 0) {
1361 bus->tx_seq =
1362 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1363 }
1364 } while ((ret < 0) && retries++ < TXRETRIES);
1365 }
1366
1367 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1368 bus->activity = false;
1369 dhdsdio_clkctl(bus, CLK_NONE, true);
1370 }
1371
1372 dhd_os_sdunlock(bus->dhd);
1373
1374 if (ret)
1375 bus->dhd->tx_ctlerrs++;
1376 else
1377 bus->dhd->tx_ctlpkts++;
1378
1379 return ret ? -EIO : 0;
1380 }
1381
1382 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1383 {
1384 int timeleft;
1385 uint rxlen = 0;
1386 bool pending;
1387
1388 DHD_TRACE(("%s: Enter\n", __func__));
1389
1390 if (bus->dhd->dongle_reset)
1391 return -EIO;
1392
1393 /* Wait until control frame is available */
1394 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1395
1396 dhd_os_sdlock(bus->dhd);
1397 rxlen = bus->rxlen;
1398 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1399 bus->rxlen = 0;
1400 dhd_os_sdunlock(bus->dhd);
1401
1402 if (rxlen) {
1403 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1404 __func__, rxlen, msglen));
1405 } else if (timeleft == 0) {
1406 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1407 #ifdef DHD_DEBUG
1408 dhd_os_sdlock(bus->dhd);
1409 dhdsdio_checkdied(bus, NULL, 0);
1410 dhd_os_sdunlock(bus->dhd);
1411 #endif /* DHD_DEBUG */
1412 } else if (pending == true) {
1413 DHD_CTL(("%s: cancelled\n", __func__));
1414 return -ERESTARTSYS;
1415 } else {
1416 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1417 #ifdef DHD_DEBUG
1418 dhd_os_sdlock(bus->dhd);
1419 dhdsdio_checkdied(bus, NULL, 0);
1420 dhd_os_sdunlock(bus->dhd);
1421 #endif /* DHD_DEBUG */
1422 }
1423
1424 if (rxlen)
1425 bus->dhd->rx_ctlpkts++;
1426 else
1427 bus->dhd->rx_ctlerrs++;
1428
1429 return rxlen ? (int)rxlen : -ETIMEDOUT;
1430 }
1431
1432 /* IOVar table */
1433 enum {
1434 IOV_INTR = 1,
1435 IOV_POLLRATE,
1436 IOV_SDREG,
1437 IOV_SBREG,
1438 IOV_SDCIS,
1439 IOV_MEMBYTES,
1440 IOV_MEMSIZE,
1441 #ifdef DHD_DEBUG
1442 IOV_CHECKDIED,
1443 #endif
1444 IOV_DOWNLOAD,
1445 IOV_FORCEEVEN,
1446 IOV_SDIOD_DRIVE,
1447 IOV_READAHEAD,
1448 IOV_SDRXCHAIN,
1449 IOV_ALIGNCTL,
1450 IOV_SDALIGN,
1451 IOV_DEVRESET,
1452 IOV_CPU,
1453 #ifdef SDTEST
1454 IOV_PKTGEN,
1455 IOV_EXTLOOP,
1456 #endif /* SDTEST */
1457 IOV_SPROM,
1458 IOV_TXBOUND,
1459 IOV_RXBOUND,
1460 IOV_TXMINMAX,
1461 IOV_IDLETIME,
1462 IOV_IDLECLOCK,
1463 IOV_SD1IDLE,
1464 IOV_SLEEP,
1465 IOV_VARS
1466 };
1467
1468 const bcm_iovar_t dhdsdio_iovars[] = {
1469 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1470 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1471 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1472 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1473 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1474 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1475 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1476 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1477 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1478 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1479 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1480 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1481 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1482 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1483 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1484 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1485 #ifdef DHD_DEBUG
1486 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1487 ,
1488 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1489 ,
1490 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1491 ,
1492 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1493 ,
1494 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1495 ,
1496 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1497 ,
1498 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1499 ,
1500 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1501 ,
1502 #ifdef DHD_DEBUG
1503 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1504 ,
1505 #endif /* DHD_DEBUG */
1506 #endif /* DHD_DEBUG */
1507 #ifdef SDTEST
1508 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1509 ,
1510 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1511 ,
1512 #endif /* SDTEST */
1513
1514 {NULL, 0, 0, 0, 0}
1515 };
1516
1517 static void
1518 dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1519 {
1520 uint q1, q2;
1521
1522 if (!div) {
1523 bcm_bprintf(strbuf, "%s N/A", desc);
1524 } else {
1525 q1 = num / div;
1526 q2 = (100 * (num - (q1 * div))) / div;
1527 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1528 }
1529 }
1530
1531 void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1532 {
1533 dhd_bus_t *bus = dhdp->bus;
1534
1535 bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1536 bcm_bprintf(strbuf,
1537 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1538 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1539 bcm_bprintf(strbuf,
1540 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1541 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1542 bus->rxskip, bus->rxlen, bus->rx_seq);
1543 bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1544 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1545 bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1546 bus->pollrate, bus->pollcnt, bus->regfails);
1547
1548 bcm_bprintf(strbuf, "\nAdditional counters:\n");
1549 bcm_bprintf(strbuf,
1550 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1551 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1552 bus->rxc_errors);
1553 bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1554 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1555 bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus->fc_rcvd,
1556 bus->fc_xoff, bus->fc_xon);
1557 bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1558 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1559 bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1560 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1561 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1562 {
1563 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1564 (bus->f2rxhdrs + bus->f2rxdata));
1565 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1566 bus->f1regdata);
1567 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1568 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1569 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1570 bus->intrcount);
1571 bcm_bprintf(strbuf, "\n");
1572
1573 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1574 bus->dhd->rx_packets);
1575 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1576 bus->rxglomframes);
1577 bcm_bprintf(strbuf, "\n");
1578
1579 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1580 bus->f2txdata);
1581 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1582 bus->f1regdata);
1583 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1584 (bus->f2txdata + bus->f1regdata));
1585 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1586 bus->intrcount);
1587 bcm_bprintf(strbuf, "\n");
1588
1589 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1590 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1591 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1592 dhd_dump_pct(strbuf, ", pkts/f1sd",
1593 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1594 bus->f1regdata);
1595 dhd_dump_pct(strbuf, ", pkts/sd",
1596 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1597 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1598 bus->f1regdata));
1599 dhd_dump_pct(strbuf, ", pkts/int",
1600 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1601 bus->intrcount);
1602 bcm_bprintf(strbuf, "\n\n");
1603 }
1604
1605 #ifdef SDTEST
1606 if (bus->pktgen_count) {
1607 bcm_bprintf(strbuf, "pktgen config and count:\n");
1608 bcm_bprintf(strbuf,
1609 "freq %d count %d print %d total %d min %d len %d\n",
1610 bus->pktgen_freq, bus->pktgen_count,
1611 bus->pktgen_print, bus->pktgen_total,
1612 bus->pktgen_minlen, bus->pktgen_maxlen);
1613 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1614 bus->pktgen_sent, bus->pktgen_rcvd,
1615 bus->pktgen_fail);
1616 }
1617 #endif /* SDTEST */
1618 #ifdef DHD_DEBUG
1619 bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1620 bus->dpc_sched,
1621 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1622 bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1623 bus->roundup);
1624 #endif /* DHD_DEBUG */
1625 bcm_bprintf(strbuf,
1626 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1627 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1628 bus->sleeping);
1629 }
1630
1631 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1632 {
1633 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1634
1635 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1636 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1637 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1638 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1639 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1640 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1641 }
1642
1643 #ifdef SDTEST
1644 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1645 {
1646 dhd_pktgen_t pktgen;
1647
1648 pktgen.version = DHD_PKTGEN_VERSION;
1649 pktgen.freq = bus->pktgen_freq;
1650 pktgen.count = bus->pktgen_count;
1651 pktgen.print = bus->pktgen_print;
1652 pktgen.total = bus->pktgen_total;
1653 pktgen.minlen = bus->pktgen_minlen;
1654 pktgen.maxlen = bus->pktgen_maxlen;
1655 pktgen.numsent = bus->pktgen_sent;
1656 pktgen.numrcvd = bus->pktgen_rcvd;
1657 pktgen.numfail = bus->pktgen_fail;
1658 pktgen.mode = bus->pktgen_mode;
1659 pktgen.stop = bus->pktgen_stop;
1660
1661 memcpy(arg, &pktgen, sizeof(pktgen));
1662
1663 return 0;
1664 }
1665
1666 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1667 {
1668 dhd_pktgen_t pktgen;
1669 uint oldcnt, oldmode;
1670
1671 memcpy(&pktgen, arg, sizeof(pktgen));
1672 if (pktgen.version != DHD_PKTGEN_VERSION)
1673 return BCME_BADARG;
1674
1675 oldcnt = bus->pktgen_count;
1676 oldmode = bus->pktgen_mode;
1677
1678 bus->pktgen_freq = pktgen.freq;
1679 bus->pktgen_count = pktgen.count;
1680 bus->pktgen_print = pktgen.print;
1681 bus->pktgen_total = pktgen.total;
1682 bus->pktgen_minlen = pktgen.minlen;
1683 bus->pktgen_maxlen = pktgen.maxlen;
1684 bus->pktgen_mode = pktgen.mode;
1685 bus->pktgen_stop = pktgen.stop;
1686
1687 bus->pktgen_tick = bus->pktgen_ptick = 0;
1688 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1689 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1690
1691 /* Clear counts for a new pktgen (mode change, or was stopped) */
1692 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1693 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1694
1695 return 0;
1696 }
1697 #endif /* SDTEST */
1698
1699 static int
1700 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1701 uint size)
1702 {
1703 int bcmerror = 0;
1704 u32 sdaddr;
1705 uint dsize;
1706
1707 /* Determine initial transfer parameters */
1708 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1709 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1710 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1711 else
1712 dsize = size;
1713
1714 /* Set the backplane window to include the start address */
1715 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1716 if (bcmerror) {
1717 DHD_ERROR(("%s: window change failed\n", __func__));
1718 goto xfer_done;
1719 }
1720
1721 /* Do the transfer(s) */
1722 while (size) {
1723 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1724 __func__, (write ? "write" : "read"), dsize,
1725 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1726 bcmerror =
1727 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1728 if (bcmerror) {
1729 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1730 break;
1731 }
1732
1733 /* Adjust for next transfer (if any) */
1734 size -= dsize;
1735 if (size) {
1736 data += dsize;
1737 address += dsize;
1738 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1739 if (bcmerror) {
1740 DHD_ERROR(("%s: window change failed\n",
1741 __func__));
1742 break;
1743 }
1744 sdaddr = 0;
1745 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1746 }
1747 }
1748
1749 xfer_done:
1750 /* Return the window to backplane enumeration space for core access */
1751 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1752 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1753 __func__, bcmsdh_cur_sbwad(bus->sdh)));
1754 }
1755
1756 return bcmerror;
1757 }
1758
1759 #ifdef DHD_DEBUG
1760 static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1761 {
1762 u32 addr;
1763 int rv;
1764
1765 /* Read last word in memory to determine address of
1766 sdpcm_shared structure */
1767 rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
1768 if (rv < 0)
1769 return rv;
1770
1771 addr = le32_to_cpu(addr);
1772
1773 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1774
1775 /*
1776 * Check if addr is valid.
1777 * NVRAM length at the end of memory should have been overwritten.
1778 */
1779 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1780 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1781 __func__, addr));
1782 return BCME_ERROR;
1783 }
1784
1785 /* Read hndrte_shared structure */
1786 rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
1787 sizeof(sdpcm_shared_t));
1788 if (rv < 0)
1789 return rv;
1790
1791 /* Endianness */
1792 sh->flags = le32_to_cpu(sh->flags);
1793 sh->trap_addr = le32_to_cpu(sh->trap_addr);
1794 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
1795 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
1796 sh->assert_line = le32_to_cpu(sh->assert_line);
1797 sh->console_addr = le32_to_cpu(sh->console_addr);
1798 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
1799
1800 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1801 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1802 "is different than sdpcm_shared version %d in dongle\n",
1803 __func__, SDPCM_SHARED_VERSION,
1804 sh->flags & SDPCM_SHARED_VERSION_MASK));
1805 return BCME_ERROR;
1806 }
1807
1808 return 0;
1809 }
1810
1811 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
1812 {
1813 int bcmerror = 0;
1814 uint msize = 512;
1815 char *mbuffer = NULL;
1816 uint maxstrlen = 256;
1817 char *str = NULL;
1818 trap_t tr;
1819 sdpcm_shared_t sdpcm_shared;
1820 struct bcmstrbuf strbuf;
1821
1822 DHD_TRACE(("%s: Enter\n", __func__));
1823
1824 if (data == NULL) {
1825 /*
1826 * Called after a rx ctrl timeout. "data" is NULL.
1827 * allocate memory to trace the trap or assert.
1828 */
1829 size = msize;
1830 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
1831 if (mbuffer == NULL) {
1832 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
1833 msize));
1834 bcmerror = BCME_NOMEM;
1835 goto done;
1836 }
1837 }
1838
1839 str = kmalloc(maxstrlen, GFP_ATOMIC);
1840 if (str == NULL) {
1841 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
1842 bcmerror = BCME_NOMEM;
1843 goto done;
1844 }
1845
1846 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
1847 if (bcmerror < 0)
1848 goto done;
1849
1850 bcm_binit(&strbuf, data, size);
1851
1852 bcm_bprintf(&strbuf,
1853 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1854 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1855
1856 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
1857 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1858 * (Avoids conflict with real asserts for programmatic
1859 * parsing of output.)
1860 */
1861 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
1862 }
1863
1864 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
1865 0) {
1866 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1867 * (Avoids conflict with real asserts for programmatic
1868 * parsing of output.)
1869 */
1870 bcm_bprintf(&strbuf, "No trap%s in dongle",
1871 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
1872 ? "/assrt" : "");
1873 } else {
1874 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
1875 /* Download assert */
1876 bcm_bprintf(&strbuf, "Dongle assert");
1877 if (sdpcm_shared.assert_exp_addr != 0) {
1878 str[0] = '\0';
1879 bcmerror = dhdsdio_membytes(bus, false,
1880 sdpcm_shared.assert_exp_addr,
1881 (u8 *) str, maxstrlen);
1882 if (bcmerror < 0)
1883 goto done;
1884
1885 str[maxstrlen - 1] = '\0';
1886 bcm_bprintf(&strbuf, " expr \"%s\"", str);
1887 }
1888
1889 if (sdpcm_shared.assert_file_addr != 0) {
1890 str[0] = '\0';
1891 bcmerror = dhdsdio_membytes(bus, false,
1892 sdpcm_shared.assert_file_addr,
1893 (u8 *) str, maxstrlen);
1894 if (bcmerror < 0)
1895 goto done;
1896
1897 str[maxstrlen - 1] = '\0';
1898 bcm_bprintf(&strbuf, " file \"%s\"", str);
1899 }
1900
1901 bcm_bprintf(&strbuf, " line %d ",
1902 sdpcm_shared.assert_line);
1903 }
1904
1905 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1906 bcmerror = dhdsdio_membytes(bus, false,
1907 sdpcm_shared.trap_addr, (u8 *)&tr,
1908 sizeof(trap_t));
1909 if (bcmerror < 0)
1910 goto done;
1911
1912 bcm_bprintf(&strbuf,
1913 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
1914 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
1915 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
1916 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
1917 tr.r14, tr.pc, sdpcm_shared.trap_addr,
1918 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
1919 tr.r6, tr.r7);
1920 }
1921 }
1922
1923 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
1924 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
1925
1926 #ifdef DHD_DEBUG
1927 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1928 /* Mem dump to a file on device */
1929 dhdsdio_mem_dump(bus);
1930 }
1931 #endif /* DHD_DEBUG */
1932
1933 done:
1934 kfree(mbuffer);
1935 kfree(str);
1936
1937 return bcmerror;
1938 }
1939
1940 static int dhdsdio_mem_dump(dhd_bus_t *bus)
1941 {
1942 int ret = 0;
1943 int size; /* Full mem size */
1944 int start = 0; /* Start address */
1945 int read_size = 0; /* Read size of each iteration */
1946 u8 *buf = NULL, *databuf = NULL;
1947
1948 /* Get full mem size */
1949 size = bus->ramsize;
1950 buf = kmalloc(size, GFP_ATOMIC);
1951 if (!buf) {
1952 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
1953 return -1;
1954 }
1955
1956 /* Read mem content */
1957 printk(KERN_DEBUG "Dump dongle memory");
1958 databuf = buf;
1959 while (size) {
1960 read_size = min(MEMBLOCK, size);
1961 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
1962 if (ret) {
1963 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
1964 kfree(buf);
1965 return -1;
1966 }
1967 printk(".");
1968
1969 /* Decrement size and increment start address */
1970 size -= read_size;
1971 start += read_size;
1972 databuf += read_size;
1973 }
1974 printk(KERN_DEBUG "Done\n");
1975
1976 /* free buf before return !!! */
1977 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
1978 DHD_ERROR(("%s: Error writing to files\n", __func__));
1979 return -1;
1980 }
1981
1982 /* buf free handled in write_to_file, not here */
1983 return 0;
1984 }
1985
1986 #define CONSOLE_LINE_MAX 192
1987
1988 static int dhdsdio_readconsole(dhd_bus_t *bus)
1989 {
1990 dhd_console_t *c = &bus->console;
1991 u8 line[CONSOLE_LINE_MAX], ch;
1992 u32 n, idx, addr;
1993 int rv;
1994
1995 /* Don't do anything until FWREADY updates console address */
1996 if (bus->console_addr == 0)
1997 return 0;
1998
1999 /* Read console log struct */
2000 addr = bus->console_addr + offsetof(hndrte_cons_t, log);
2001 rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2002 sizeof(c->log));
2003 if (rv < 0)
2004 return rv;
2005
2006 /* Allocate console buffer (one time only) */
2007 if (c->buf == NULL) {
2008 c->bufsize = le32_to_cpu(c->log.buf_size);
2009 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2010 if (c->buf == NULL)
2011 return BCME_NOMEM;
2012 }
2013
2014 idx = le32_to_cpu(c->log.idx);
2015
2016 /* Protect against corrupt value */
2017 if (idx > c->bufsize)
2018 return BCME_ERROR;
2019
2020 /* Skip reading the console buffer if the index pointer
2021 has not moved */
2022 if (idx == c->last)
2023 return 0;
2024
2025 /* Read the console buffer */
2026 addr = le32_to_cpu(c->log.buf);
2027 rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2028 if (rv < 0)
2029 return rv;
2030
2031 while (c->last != idx) {
2032 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2033 if (c->last == idx) {
2034 /* This would output a partial line.
2035 * Instead, back up
2036 * the buffer pointer and output this
2037 * line next time around.
2038 */
2039 if (c->last >= n)
2040 c->last -= n;
2041 else
2042 c->last = c->bufsize - n;
2043 goto break2;
2044 }
2045 ch = c->buf[c->last];
2046 c->last = (c->last + 1) % c->bufsize;
2047 if (ch == '\n')
2048 break;
2049 line[n] = ch;
2050 }
2051
2052 if (n > 0) {
2053 if (line[n - 1] == '\r')
2054 n--;
2055 line[n] = 0;
2056 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2057 }
2058 }
2059 break2:
2060
2061 return 0;
2062 }
2063 #endif /* DHD_DEBUG */
2064
2065 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2066 {
2067 int bcmerror = 0;
2068
2069 DHD_TRACE(("%s: Enter\n", __func__));
2070
2071 /* Basic sanity checks */
2072 if (bus->dhd->up) {
2073 bcmerror = BCME_NOTDOWN;
2074 goto err;
2075 }
2076 if (!len) {
2077 bcmerror = BCME_BUFTOOSHORT;
2078 goto err;
2079 }
2080
2081 /* Free the old ones and replace with passed variables */
2082 kfree(bus->vars);
2083
2084 bus->vars = kmalloc(len, GFP_ATOMIC);
2085 bus->varsz = bus->vars ? len : 0;
2086 if (bus->vars == NULL) {
2087 bcmerror = BCME_NOMEM;
2088 goto err;
2089 }
2090
2091 /* Copy the passed variables, which should include the
2092 terminating double-null */
2093 memcpy(bus->vars, arg, bus->varsz);
2094 err:
2095 return bcmerror;
2096 }
2097
2098 static int
2099 dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
2100 const char *name, void *params, int plen, void *arg, int len,
2101 int val_size)
2102 {
2103 int bcmerror = 0;
2104 s32 int_val = 0;
2105 bool bool_val = 0;
2106
2107 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2108 "len %d val_size %d\n",
2109 __func__, actionid, name, params, plen, arg, len, val_size));
2110
2111 bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2112 if (bcmerror != 0)
2113 goto exit;
2114
2115 if (plen >= (int)sizeof(int_val))
2116 memcpy(&int_val, params, sizeof(int_val));
2117
2118 bool_val = (int_val != 0) ? true : false;
2119
2120 /* Some ioctls use the bus */
2121 dhd_os_sdlock(bus->dhd);
2122
2123 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2124 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2125 actionid == IOV_GVAL(IOV_DEVRESET))) {
2126 bcmerror = BCME_NOTREADY;
2127 goto exit;
2128 }
2129
2130 /* Handle sleep stuff before any clock mucking */
2131 if (vi->varid == IOV_SLEEP) {
2132 if (IOV_ISSET(actionid)) {
2133 bcmerror = dhdsdio_bussleep(bus, bool_val);
2134 } else {
2135 int_val = (s32) bus->sleeping;
2136 memcpy(arg, &int_val, val_size);
2137 }
2138 goto exit;
2139 }
2140
2141 /* Request clock to allow SDIO accesses */
2142 if (!bus->dhd->dongle_reset) {
2143 BUS_WAKE(bus);
2144 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2145 }
2146
2147 switch (actionid) {
2148 case IOV_GVAL(IOV_INTR):
2149 int_val = (s32) bus->intr;
2150 memcpy(arg, &int_val, val_size);
2151 break;
2152
2153 case IOV_SVAL(IOV_INTR):
2154 bus->intr = bool_val;
2155 bus->intdis = false;
2156 if (bus->dhd->up) {
2157 if (bus->intr) {
2158 DHD_INTR(("%s: enable SDIO device interrupts\n",
2159 __func__));
2160 bcmsdh_intr_enable(bus->sdh);
2161 } else {
2162 DHD_INTR(("%s: disable SDIO interrupts\n",
2163 __func__));
2164 bcmsdh_intr_disable(bus->sdh);
2165 }
2166 }
2167 break;
2168
2169 case IOV_GVAL(IOV_POLLRATE):
2170 int_val = (s32) bus->pollrate;
2171 memcpy(arg, &int_val, val_size);
2172 break;
2173
2174 case IOV_SVAL(IOV_POLLRATE):
2175 bus->pollrate = (uint) int_val;
2176 bus->poll = (bus->pollrate != 0);
2177 break;
2178
2179 case IOV_GVAL(IOV_IDLETIME):
2180 int_val = bus->idletime;
2181 memcpy(arg, &int_val, val_size);
2182 break;
2183
2184 case IOV_SVAL(IOV_IDLETIME):
2185 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2186 bcmerror = BCME_BADARG;
2187 else
2188 bus->idletime = int_val;
2189 break;
2190
2191 case IOV_GVAL(IOV_IDLECLOCK):
2192 int_val = (s32) bus->idleclock;
2193 memcpy(arg, &int_val, val_size);
2194 break;
2195
2196 case IOV_SVAL(IOV_IDLECLOCK):
2197 bus->idleclock = int_val;
2198 break;
2199
2200 case IOV_GVAL(IOV_SD1IDLE):
2201 int_val = (s32) sd1idle;
2202 memcpy(arg, &int_val, val_size);
2203 break;
2204
2205 case IOV_SVAL(IOV_SD1IDLE):
2206 sd1idle = bool_val;
2207 break;
2208
2209 case IOV_SVAL(IOV_MEMBYTES):
2210 case IOV_GVAL(IOV_MEMBYTES):
2211 {
2212 u32 address;
2213 uint size, dsize;
2214 u8 *data;
2215
2216 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2217
2218 ASSERT(plen >= 2 * sizeof(int));
2219
2220 address = (u32) int_val;
2221 memcpy(&int_val, (char *)params + sizeof(int_val),
2222 sizeof(int_val));
2223 size = (uint) int_val;
2224
2225 /* Do some validation */
2226 dsize = set ? plen - (2 * sizeof(int)) : len;
2227 if (dsize < size) {
2228 DHD_ERROR(("%s: error on %s membytes, addr "
2229 "0x%08x size %d dsize %d\n",
2230 __func__, (set ? "set" : "get"),
2231 address, size, dsize));
2232 bcmerror = BCME_BADARG;
2233 break;
2234 }
2235
2236 DHD_INFO(("%s: Request to %s %d bytes at address "
2237 "0x%08x\n",
2238 __func__, (set ? "write" : "read"), size, address));
2239
2240 /* If we know about SOCRAM, check for a fit */
2241 if ((bus->orig_ramsize) &&
2242 ((address > bus->orig_ramsize)
2243 || (address + size > bus->orig_ramsize))) {
2244 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2245 "bytes at 0x%08x\n",
2246 __func__, bus->orig_ramsize, size, address));
2247 bcmerror = BCME_BADARG;
2248 break;
2249 }
2250
2251 /* Generate the actual data pointer */
2252 data =
2253 set ? (u8 *) params +
2254 2 * sizeof(int) : (u8 *) arg;
2255
2256 /* Call to do the transfer */
2257 bcmerror =
2258 dhdsdio_membytes(bus, set, address, data, size);
2259
2260 break;
2261 }
2262
2263 case IOV_GVAL(IOV_MEMSIZE):
2264 int_val = (s32) bus->ramsize;
2265 memcpy(arg, &int_val, val_size);
2266 break;
2267
2268 case IOV_GVAL(IOV_SDIOD_DRIVE):
2269 int_val = (s32) dhd_sdiod_drive_strength;
2270 memcpy(arg, &int_val, val_size);
2271 break;
2272
2273 case IOV_SVAL(IOV_SDIOD_DRIVE):
2274 dhd_sdiod_drive_strength = int_val;
2275 si_sdiod_drive_strength_init(bus->sih,
2276 dhd_sdiod_drive_strength);
2277 break;
2278
2279 case IOV_SVAL(IOV_DOWNLOAD):
2280 bcmerror = dhdsdio_download_state(bus, bool_val);
2281 break;
2282
2283 case IOV_SVAL(IOV_VARS):
2284 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2285 break;
2286
2287 case IOV_GVAL(IOV_READAHEAD):
2288 int_val = (s32) dhd_readahead;
2289 memcpy(arg, &int_val, val_size);
2290 break;
2291
2292 case IOV_SVAL(IOV_READAHEAD):
2293 if (bool_val && !dhd_readahead)
2294 bus->nextlen = 0;
2295 dhd_readahead = bool_val;
2296 break;
2297
2298 case IOV_GVAL(IOV_SDRXCHAIN):
2299 int_val = (s32) bus->use_rxchain;
2300 memcpy(arg, &int_val, val_size);
2301 break;
2302
2303 case IOV_SVAL(IOV_SDRXCHAIN):
2304 if (bool_val && !bus->sd_rxchain)
2305 bcmerror = BCME_UNSUPPORTED;
2306 else
2307 bus->use_rxchain = bool_val;
2308 break;
2309 case IOV_GVAL(IOV_ALIGNCTL):
2310 int_val = (s32) dhd_alignctl;
2311 memcpy(arg, &int_val, val_size);
2312 break;
2313
2314 case IOV_SVAL(IOV_ALIGNCTL):
2315 dhd_alignctl = bool_val;
2316 break;
2317
2318 case IOV_GVAL(IOV_SDALIGN):
2319 int_val = DHD_SDALIGN;
2320 memcpy(arg, &int_val, val_size);
2321 break;
2322
2323 #ifdef DHD_DEBUG
2324 case IOV_GVAL(IOV_VARS):
2325 if (bus->varsz < (uint) len)
2326 memcpy(arg, bus->vars, bus->varsz);
2327 else
2328 bcmerror = BCME_BUFTOOSHORT;
2329 break;
2330 #endif /* DHD_DEBUG */
2331
2332 #ifdef DHD_DEBUG
2333 case IOV_GVAL(IOV_SDREG):
2334 {
2335 sdreg_t *sd_ptr;
2336 u32 addr, size;
2337
2338 sd_ptr = (sdreg_t *) params;
2339
2340 addr = (unsigned long)bus->regs + sd_ptr->offset;
2341 size = sd_ptr->func;
2342 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2343 if (bcmsdh_regfail(bus->sdh))
2344 bcmerror = BCME_SDIO_ERROR;
2345 memcpy(arg, &int_val, sizeof(s32));
2346 break;
2347 }
2348
2349 case IOV_SVAL(IOV_SDREG):
2350 {
2351 sdreg_t *sd_ptr;
2352 u32 addr, size;
2353
2354 sd_ptr = (sdreg_t *) params;
2355
2356 addr = (unsigned long)bus->regs + sd_ptr->offset;
2357 size = sd_ptr->func;
2358 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2359 if (bcmsdh_regfail(bus->sdh))
2360 bcmerror = BCME_SDIO_ERROR;
2361 break;
2362 }
2363
2364 /* Same as above, but offset is not backplane
2365 (not SDIO core) */
2366 case IOV_GVAL(IOV_SBREG):
2367 {
2368 sdreg_t sdreg;
2369 u32 addr, size;
2370
2371 memcpy(&sdreg, params, sizeof(sdreg));
2372
2373 addr = SI_ENUM_BASE + sdreg.offset;
2374 size = sdreg.func;
2375 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2376 if (bcmsdh_regfail(bus->sdh))
2377 bcmerror = BCME_SDIO_ERROR;
2378 memcpy(arg, &int_val, sizeof(s32));
2379 break;
2380 }
2381
2382 case IOV_SVAL(IOV_SBREG):
2383 {
2384 sdreg_t sdreg;
2385 u32 addr, size;
2386
2387 memcpy(&sdreg, params, sizeof(sdreg));
2388
2389 addr = SI_ENUM_BASE + sdreg.offset;
2390 size = sdreg.func;
2391 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2392 if (bcmsdh_regfail(bus->sdh))
2393 bcmerror = BCME_SDIO_ERROR;
2394 break;
2395 }
2396
2397 case IOV_GVAL(IOV_SDCIS):
2398 {
2399 *(char *)arg = 0;
2400
2401 strcat(arg, "\nFunc 0\n");
2402 bcmsdh_cis_read(bus->sdh, 0x10,
2403 (u8 *) arg + strlen(arg),
2404 SBSDIO_CIS_SIZE_LIMIT);
2405 strcat(arg, "\nFunc 1\n");
2406 bcmsdh_cis_read(bus->sdh, 0x11,
2407 (u8 *) arg + strlen(arg),
2408 SBSDIO_CIS_SIZE_LIMIT);
2409 strcat(arg, "\nFunc 2\n");
2410 bcmsdh_cis_read(bus->sdh, 0x12,
2411 (u8 *) arg + strlen(arg),
2412 SBSDIO_CIS_SIZE_LIMIT);
2413 break;
2414 }
2415
2416 case IOV_GVAL(IOV_FORCEEVEN):
2417 int_val = (s32) forcealign;
2418 memcpy(arg, &int_val, val_size);
2419 break;
2420
2421 case IOV_SVAL(IOV_FORCEEVEN):
2422 forcealign = bool_val;
2423 break;
2424
2425 case IOV_GVAL(IOV_TXBOUND):
2426 int_val = (s32) dhd_txbound;
2427 memcpy(arg, &int_val, val_size);
2428 break;
2429
2430 case IOV_SVAL(IOV_TXBOUND):
2431 dhd_txbound = (uint) int_val;
2432 break;
2433
2434 case IOV_GVAL(IOV_RXBOUND):
2435 int_val = (s32) dhd_rxbound;
2436 memcpy(arg, &int_val, val_size);
2437 break;
2438
2439 case IOV_SVAL(IOV_RXBOUND):
2440 dhd_rxbound = (uint) int_val;
2441 break;
2442
2443 case IOV_GVAL(IOV_TXMINMAX):
2444 int_val = (s32) dhd_txminmax;
2445 memcpy(arg, &int_val, val_size);
2446 break;
2447
2448 case IOV_SVAL(IOV_TXMINMAX):
2449 dhd_txminmax = (uint) int_val;
2450 break;
2451 #endif /* DHD_DEBUG */
2452
2453 #ifdef SDTEST
2454 case IOV_GVAL(IOV_EXTLOOP):
2455 int_val = (s32) bus->ext_loop;
2456 memcpy(arg, &int_val, val_size);
2457 break;
2458
2459 case IOV_SVAL(IOV_EXTLOOP):
2460 bus->ext_loop = bool_val;
2461 break;
2462
2463 case IOV_GVAL(IOV_PKTGEN):
2464 bcmerror = dhdsdio_pktgen_get(bus, arg);
2465 break;
2466
2467 case IOV_SVAL(IOV_PKTGEN):
2468 bcmerror = dhdsdio_pktgen_set(bus, arg);
2469 break;
2470 #endif /* SDTEST */
2471
2472 case IOV_SVAL(IOV_DEVRESET):
2473 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2474 "busstate=%d\n",
2475 __func__, bool_val, bus->dhd->dongle_reset,
2476 bus->dhd->busstate));
2477
2478 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2479
2480 break;
2481
2482 case IOV_GVAL(IOV_DEVRESET):
2483 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2484
2485 /* Get its status */
2486 int_val = (bool) bus->dhd->dongle_reset;
2487 memcpy(arg, &int_val, val_size);
2488
2489 break;
2490
2491 default:
2492 bcmerror = BCME_UNSUPPORTED;
2493 break;
2494 }
2495
2496 exit:
2497 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2498 bus->activity = false;
2499 dhdsdio_clkctl(bus, CLK_NONE, true);
2500 }
2501
2502 dhd_os_sdunlock(bus->dhd);
2503
2504 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2505 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2506
2507 return bcmerror;
2508 }
2509
2510 static int dhdsdio_write_vars(dhd_bus_t *bus)
2511 {
2512 int bcmerror = 0;
2513 u32 varsize;
2514 u32 varaddr;
2515 u8 *vbuffer;
2516 u32 varsizew;
2517 #ifdef DHD_DEBUG
2518 char *nvram_ularray;
2519 #endif /* DHD_DEBUG */
2520
2521 /* Even if there are no vars are to be written, we still
2522 need to set the ramsize. */
2523 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2524 varaddr = (bus->ramsize - 4) - varsize;
2525
2526 if (bus->vars) {
2527 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2528 if (!vbuffer)
2529 return BCME_NOMEM;
2530
2531 memcpy(vbuffer, bus->vars, bus->varsz);
2532
2533 /* Write the vars list */
2534 bcmerror =
2535 dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2536 #ifdef DHD_DEBUG
2537 /* Verify NVRAM bytes */
2538 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2539 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2540 if (!nvram_ularray)
2541 return BCME_NOMEM;
2542
2543 /* Upload image to verify downloaded contents. */
2544 memset(nvram_ularray, 0xaa, varsize);
2545
2546 /* Read the vars list to temp buffer for comparison */
2547 bcmerror =
2548 dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2549 varsize);
2550 if (bcmerror) {
2551 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2552 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2553 }
2554 /* Compare the org NVRAM with the one read from RAM */
2555 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2556 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2557 __func__));
2558 } else
2559 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2560 __func__));
2561
2562 kfree(nvram_ularray);
2563 #endif /* DHD_DEBUG */
2564
2565 kfree(vbuffer);
2566 }
2567
2568 /* adjust to the user specified RAM */
2569 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2570 bus->orig_ramsize, bus->ramsize));
2571 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2572 varsize = ((bus->orig_ramsize - 4) - varaddr);
2573
2574 /*
2575 * Determine the length token:
2576 * Varsize, converted to words, in lower 16-bits, checksum
2577 * in upper 16-bits.
2578 */
2579 if (bcmerror) {
2580 varsizew = 0;
2581 } else {
2582 varsizew = varsize / 4;
2583 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2584 varsizew = cpu_to_le32(varsizew);
2585 }
2586
2587 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2588 varsizew));
2589
2590 /* Write the length token to the last word */
2591 bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2592 (u8 *)&varsizew, 4);
2593
2594 return bcmerror;
2595 }
2596
2597 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2598 {
2599 uint retries;
2600 int bcmerror = 0;
2601
2602 /* To enter download state, disable ARM and reset SOCRAM.
2603 * To exit download state, simply reset ARM (default is RAM boot).
2604 */
2605 if (enter) {
2606
2607 bus->alp_only = true;
2608
2609 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2610 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2611 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2612 bcmerror = BCME_ERROR;
2613 goto fail;
2614 }
2615
2616 si_core_disable(bus->sih, 0);
2617 if (bcmsdh_regfail(bus->sdh)) {
2618 bcmerror = BCME_SDIO_ERROR;
2619 goto fail;
2620 }
2621
2622 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2623 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2624 __func__));
2625 bcmerror = BCME_ERROR;
2626 goto fail;
2627 }
2628
2629 si_core_reset(bus->sih, 0, 0);
2630 if (bcmsdh_regfail(bus->sdh)) {
2631 DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
2632 __func__));
2633 bcmerror = BCME_SDIO_ERROR;
2634 goto fail;
2635 }
2636
2637 /* Clear the top bit of memory */
2638 if (bus->ramsize) {
2639 u32 zeros = 0;
2640 dhdsdio_membytes(bus, true, bus->ramsize - 4,
2641 (u8 *)&zeros, 4);
2642 }
2643 } else {
2644 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2645 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2646 __func__));
2647 bcmerror = BCME_ERROR;
2648 goto fail;
2649 }
2650
2651 if (!si_iscoreup(bus->sih)) {
2652 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2653 __func__));
2654 bcmerror = BCME_ERROR;
2655 goto fail;
2656 }
2657
2658 bcmerror = dhdsdio_write_vars(bus);
2659 if (bcmerror) {
2660 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2661 bcmerror = 0;
2662 }
2663
2664 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
2665 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
2666 DHD_ERROR(("%s: Can't change back to SDIO core?\n",
2667 __func__));
2668 bcmerror = BCME_ERROR;
2669 goto fail;
2670 }
2671 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2672
2673 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2674 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2675 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2676 bcmerror = BCME_ERROR;
2677 goto fail;
2678 }
2679
2680 si_core_reset(bus->sih, 0, 0);
2681 if (bcmsdh_regfail(bus->sdh)) {
2682 DHD_ERROR(("%s: Failure trying to reset ARM core?\n",
2683 __func__));
2684 bcmerror = BCME_SDIO_ERROR;
2685 goto fail;
2686 }
2687
2688 /* Allow HT Clock now that the ARM is running. */
2689 bus->alp_only = false;
2690
2691 bus->dhd->busstate = DHD_BUS_LOAD;
2692 }
2693
2694 fail:
2695 /* Always return to SDIOD core */
2696 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
2697 si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2698
2699 return bcmerror;
2700 }
2701
2702 int
2703 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2704 void *params, int plen, void *arg, int len, bool set)
2705 {
2706 dhd_bus_t *bus = dhdp->bus;
2707 const bcm_iovar_t *vi = NULL;
2708 int bcmerror = 0;
2709 int val_size;
2710 u32 actionid;
2711
2712 DHD_TRACE(("%s: Enter\n", __func__));
2713
2714 ASSERT(name);
2715 ASSERT(len >= 0);
2716
2717 /* Get MUST have return space */
2718 ASSERT(set || (arg && len));
2719
2720 /* Set does NOT take qualifiers */
2721 ASSERT(!set || (!params && !plen));
2722
2723 /* Look up var locally; if not found pass to host driver */
2724 vi = bcm_iovar_lookup(dhdsdio_iovars, name);
2725 if (vi == NULL) {
2726 dhd_os_sdlock(bus->dhd);
2727
2728 BUS_WAKE(bus);
2729
2730 /* Turn on clock in case SD command needs backplane */
2731 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2732
2733 bcmerror =
2734 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2735 set);
2736
2737 /* Check for bus configuration changes of interest */
2738
2739 /* If it was divisor change, read the new one */
2740 if (set && strcmp(name, "sd_divisor") == 0) {
2741 if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
2742 &bus->sd_divisor, sizeof(s32),
2743 false) != 0) {
2744 bus->sd_divisor = -1;
2745 DHD_ERROR(("%s: fail on %s get\n", __func__,
2746 name));
2747 } else {
2748 DHD_INFO(("%s: noted %s update, value now %d\n",
2749 __func__, name, bus->sd_divisor));
2750 }
2751 }
2752 /* If it was a mode change, read the new one */
2753 if (set && strcmp(name, "sd_mode") == 0) {
2754 if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
2755 &bus->sd_mode, sizeof(s32),
2756 false) != 0) {
2757 bus->sd_mode = -1;
2758 DHD_ERROR(("%s: fail on %s get\n", __func__,
2759 name));
2760 } else {
2761 DHD_INFO(("%s: noted %s update, value now %d\n",
2762 __func__, name, bus->sd_mode));
2763 }
2764 }
2765 /* Similar check for blocksize change */
2766 if (set && strcmp(name, "sd_blocksize") == 0) {
2767 s32 fnum = 2;
2768 if (bcmsdh_iovar_op
2769 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2770 &bus->blocksize, sizeof(s32),
2771 false) != 0) {
2772 bus->blocksize = 0;
2773 DHD_ERROR(("%s: fail on %s get\n", __func__,
2774 "sd_blocksize"));
2775 } else {
2776 DHD_INFO(("%s: noted %s update, value now %d\n",
2777 __func__, "sd_blocksize",
2778 bus->blocksize));
2779 }
2780 }
2781 bus->roundup = min(max_roundup, bus->blocksize);
2782
2783 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2784 bus->activity = false;
2785 dhdsdio_clkctl(bus, CLK_NONE, true);
2786 }
2787
2788 dhd_os_sdunlock(bus->dhd);
2789 goto exit;
2790 }
2791
2792 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2793 name, (set ? "set" : "get"), len, plen));
2794
2795 /* set up 'params' pointer in case this is a set command so that
2796 * the convenience int and bool code can be common to set and get
2797 */
2798 if (params == NULL) {
2799 params = arg;
2800 plen = len;
2801 }
2802
2803 if (vi->type == IOVT_VOID)
2804 val_size = 0;
2805 else if (vi->type == IOVT_BUFFER)
2806 val_size = len;
2807 else
2808 /* all other types are integer sized */
2809 val_size = sizeof(int);
2810
2811 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2812 bcmerror =
2813 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2814 val_size);
2815
2816 exit:
2817 return bcmerror;
2818 }
2819
2820 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2821 {
2822 u32 local_hostintmask;
2823 u8 saveclk;
2824 uint retries;
2825 int err;
2826
2827 DHD_TRACE(("%s: Enter\n", __func__));
2828
2829 if (enforce_mutex)
2830 dhd_os_sdlock(bus->dhd);
2831
2832 BUS_WAKE(bus);
2833
2834 /* Enable clock for device interrupts */
2835 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2836
2837 /* Disable and clear interrupts at the chip level also */
2838 W_SDREG(0, &bus->regs->hostintmask, retries);
2839 local_hostintmask = bus->hostintmask;
2840 bus->hostintmask = 0;
2841
2842 /* Change our idea of bus state */
2843 bus->dhd->busstate = DHD_BUS_DOWN;
2844
2845 /* Force clocks on backplane to be sure F2 interrupt propagates */
2846 saveclk =
2847 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2848 &err);
2849 if (!err) {
2850 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2851 (saveclk | SBSDIO_FORCE_HT), &err);
2852 }
2853 if (err) {
2854 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2855 __func__, err));
2856 }
2857
2858 /* Turn off the bus (F2), free any pending packets */
2859 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2860 bcmsdh_intr_disable(bus->sdh);
2861 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
2862 SDIO_FUNC_ENABLE_1, NULL);
2863
2864 /* Clear any pending interrupts now that F2 is disabled */
2865 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
2866
2867 /* Turn off the backplane clock (only) */
2868 dhdsdio_clkctl(bus, CLK_SDONLY, false);
2869
2870 /* Clear the data packet queues */
2871 pktq_flush(&bus->txq, true);
2872
2873 /* Clear any held glomming stuff */
2874 if (bus->glomd)
2875 pkt_buf_free_skb(bus->glomd);
2876
2877 if (bus->glom)
2878 pkt_buf_free_skb(bus->glom);
2879
2880 bus->glom = bus->glomd = NULL;
2881
2882 /* Clear rx control and wake any waiters */
2883 bus->rxlen = 0;
2884 dhd_os_ioctl_resp_wake(bus->dhd);
2885
2886 /* Reset some F2 state stuff */
2887 bus->rxskip = false;
2888 bus->tx_seq = bus->rx_seq = 0;
2889
2890 if (enforce_mutex)
2891 dhd_os_sdunlock(bus->dhd);
2892 }
2893
2894 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
2895 {
2896 dhd_bus_t *bus = dhdp->bus;
2897 dhd_timeout_t tmo;
2898 uint retries = 0;
2899 u8 ready, enable;
2900 int err, ret = 0;
2901 u8 saveclk;
2902
2903 DHD_TRACE(("%s: Enter\n", __func__));
2904
2905 ASSERT(bus->dhd);
2906 if (!bus->dhd)
2907 return 0;
2908
2909 if (enforce_mutex)
2910 dhd_os_sdlock(bus->dhd);
2911
2912 /* Make sure backplane clock is on, needed to generate F2 interrupt */
2913 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2914 if (bus->clkstate != CLK_AVAIL)
2915 goto exit;
2916
2917 /* Force clocks on backplane to be sure F2 interrupt propagates */
2918 saveclk =
2919 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2920 &err);
2921 if (!err) {
2922 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2923 (saveclk | SBSDIO_FORCE_HT), &err);
2924 }
2925 if (err) {
2926 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2927 __func__, err));
2928 goto exit;
2929 }
2930
2931 /* Enable function 2 (frame transfers) */
2932 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
2933 &bus->regs->tosbmailboxdata, retries);
2934 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
2935
2936 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
2937
2938 /* Give the dongle some time to do its thing and set IOR2 */
2939 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
2940
2941 ready = 0;
2942 while (ready != enable && !dhd_timeout_expired(&tmo))
2943 ready =
2944 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY,
2945 NULL);
2946
2947 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
2948 __func__, enable, ready, tmo.elapsed));
2949
2950 /* If F2 successfully enabled, set core and enable interrupts */
2951 if (ready == enable) {
2952 /* Make sure we're talking to the core. */
2953 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
2954 if (!(bus->regs))
2955 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2956
2957 /* Set up the interrupt mask and enable interrupts */
2958 bus->hostintmask = HOSTINTMASK;
2959 W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
2960
2961 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
2962 (u8) watermark, &err);
2963
2964 /* Set bus state according to enable result */
2965 dhdp->busstate = DHD_BUS_DATA;
2966
2967 /* bcmsdh_intr_unmask(bus->sdh); */
2968
2969 bus->intdis = false;
2970 if (bus->intr) {
2971 DHD_INTR(("%s: enable SDIO device interrupts\n",
2972 __func__));
2973 bcmsdh_intr_enable(bus->sdh);
2974 } else {
2975 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2976 bcmsdh_intr_disable(bus->sdh);
2977 }
2978
2979 }
2980
2981 else {
2982 /* Disable F2 again */
2983 enable = SDIO_FUNC_ENABLE_1;
2984 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable,
2985 NULL);
2986 }
2987
2988 /* Restore previous clock setting */
2989 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2990 saveclk, &err);
2991
2992 /* If we didn't come up, turn off backplane clock */
2993 if (dhdp->busstate != DHD_BUS_DATA)
2994 dhdsdio_clkctl(bus, CLK_NONE, false);
2995
2996 exit:
2997 if (enforce_mutex)
2998 dhd_os_sdunlock(bus->dhd);
2999
3000 return ret;
3001 }
3002
3003 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3004 {
3005 bcmsdh_info_t *sdh = bus->sdh;
3006 sdpcmd_regs_t *regs = bus->regs;
3007 uint retries = 0;
3008 u16 lastrbc;
3009 u8 hi, lo;
3010 int err;
3011
3012 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3013 (abort ? "abort command, " : ""),
3014 (rtx ? ", send NAK" : "")));
3015
3016 if (abort)
3017 bcmsdh_abort(sdh, SDIO_FUNC_2);
3018
3019 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3020 &err);
3021 bus->f1regdata++;
3022
3023 /* Wait until the packet has been flushed (device/FIFO stable) */
3024 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3025 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3026 NULL);
3027 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3028 NULL);
3029 bus->f1regdata += 2;
3030
3031 if ((hi == 0) && (lo == 0))
3032 break;
3033
3034 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3035 DHD_ERROR(("%s: count growing: last 0x%04x now "
3036 "0x%04x\n",
3037 __func__, lastrbc, ((hi << 8) + lo)));
3038 }
3039 lastrbc = (hi << 8) + lo;
3040 }
3041
3042 if (!retries) {
3043 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3044 __func__, lastrbc));
3045 } else {
3046 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3047 (0xffff - retries)));
3048 }
3049
3050 if (rtx) {
3051 bus->rxrtx++;
3052 W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
3053 bus->f1regdata++;
3054 if (retries <= retry_limit)
3055 bus->rxskip = true;
3056 }
3057
3058 /* Clear partial in any case */
3059 bus->nextlen = 0;
3060
3061 /* If we can't reach the device, signal failure */
3062 if (err || bcmsdh_regfail(sdh))
3063 bus->dhd->busstate = DHD_BUS_DOWN;
3064 }
3065
3066 static void
3067 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3068 {
3069 bcmsdh_info_t *sdh = bus->sdh;
3070 uint rdlen, pad;
3071
3072 int sdret;
3073
3074 DHD_TRACE(("%s: Enter\n", __func__));
3075
3076 /* Control data already received in aligned rxctl */
3077 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3078 goto gotpkt;
3079
3080 ASSERT(bus->rxbuf);
3081 /* Set rxctl for frame (w/optional alignment) */
3082 bus->rxctl = bus->rxbuf;
3083 if (dhd_alignctl) {
3084 bus->rxctl += firstread;
3085 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3086 if (pad)
3087 bus->rxctl += (DHD_SDALIGN - pad);
3088 bus->rxctl -= firstread;
3089 }
3090 ASSERT(bus->rxctl >= bus->rxbuf);
3091
3092 /* Copy the already-read portion over */
3093 memcpy(bus->rxctl, hdr, firstread);
3094 if (len <= firstread)
3095 goto gotpkt;
3096
3097 /* Copy the full data pkt in gSPI case and process ioctl. */
3098 if (bus->bus == SPI_BUS) {
3099 memcpy(bus->rxctl, hdr, len);
3100 goto gotpkt;
3101 }
3102
3103 /* Raise rdlen to next SDIO block to avoid tail command */
3104 rdlen = len - firstread;
3105 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3106 pad = bus->blocksize - (rdlen % bus->blocksize);
3107 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3108 ((len + pad) < bus->dhd->maxctl))
3109 rdlen += pad;
3110 } else if (rdlen % DHD_SDALIGN) {
3111 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3112 }
3113
3114 /* Satisfy length-alignment requirements */
3115 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3116 rdlen = roundup(rdlen, ALIGNMENT);
3117
3118 /* Drop if the read is too big or it exceeds our maximum */
3119 if ((rdlen + firstread) > bus->dhd->maxctl) {
3120 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3121 __func__, rdlen, bus->dhd->maxctl));
3122 bus->dhd->rx_errors++;
3123 dhdsdio_rxfail(bus, false, false);
3124 goto done;
3125 }
3126
3127 if ((len - doff) > bus->dhd->maxctl) {
3128 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3129 "%d-byte limit\n",
3130 __func__, len, (len - doff), bus->dhd->maxctl));
3131 bus->dhd->rx_errors++;
3132 bus->rx_toolong++;
3133 dhdsdio_rxfail(bus, false, false);
3134 goto done;
3135 }
3136
3137 /* Read remainder of frame body into the rxctl buffer */
3138 sdret =
3139 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
3140 (bus->rxctl + firstread), rdlen, NULL, NULL,
3141 NULL);
3142 bus->f2rxdata++;
3143 ASSERT(sdret != BCME_PENDING);
3144
3145 /* Control frame failures need retransmission */
3146 if (sdret < 0) {
3147 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3148 __func__, rdlen, sdret));
3149 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3150 dhdsdio_rxfail(bus, true, true);
3151 goto done;
3152 }
3153
3154 gotpkt:
3155
3156 #ifdef DHD_DEBUG
3157 if (DHD_BYTES_ON() && DHD_CTL_ON())
3158 prhex("RxCtrl", bus->rxctl, len);
3159 #endif
3160
3161 /* Point to valid data and indicate its length */
3162 bus->rxctl += doff;
3163 bus->rxlen = len - doff;
3164
3165 done:
3166 /* Awake any waiters */
3167 dhd_os_ioctl_resp_wake(bus->dhd);
3168 }
3169
3170 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3171 {
3172 u16 dlen, totlen;
3173 u8 *dptr, num = 0;
3174
3175 u16 sublen, check;
3176 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3177
3178 int errcode;
3179 u8 chan, seq, doff, sfdoff;
3180 u8 txmax;
3181
3182 int ifidx = 0;
3183 bool usechain = bus->use_rxchain;
3184
3185 /* If packets, issue read(s) and send up packet chain */
3186 /* Return sequence numbers consumed? */
3187
3188 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3189 bus->glom));
3190
3191 /* If there's a descriptor, generate the packet chain */
3192 if (bus->glomd) {
3193 dhd_os_sdlock_rxq(bus->dhd);
3194
3195 pfirst = plast = pnext = NULL;
3196 dlen = (u16) (bus->glomd->len);
3197 dptr = bus->glomd->data;
3198 if (!dlen || (dlen & 1)) {
3199 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3200 __func__, dlen));
3201 dlen = 0;
3202 }
3203
3204 for (totlen = num = 0; dlen; num++) {
3205 /* Get (and move past) next length */
3206 sublen = get_unaligned_le16(dptr);
3207 dlen -= sizeof(u16);
3208 dptr += sizeof(u16);
3209 if ((sublen < SDPCM_HDRLEN) ||
3210 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3211 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3212 __func__, num, sublen));
3213 pnext = NULL;
3214 break;
3215 }
3216 if (sublen % DHD_SDALIGN) {
3217 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3218 __func__, sublen, DHD_SDALIGN));
3219 usechain = false;
3220 }
3221 totlen += sublen;
3222
3223 /* For last frame, adjust read len so total
3224 is a block multiple */
3225 if (!dlen) {
3226 sublen +=
3227 (roundup(totlen, bus->blocksize) - totlen);
3228 totlen = roundup(totlen, bus->blocksize);
3229 }
3230
3231 /* Allocate/chain packet for next subframe */
3232 pnext = pkt_buf_get_skb(sublen + DHD_SDALIGN);
3233 if (pnext == NULL) {
3234 DHD_ERROR(("%s: pkt_buf_get_skb failed, num %d len %d\n",
3235 __func__, num, sublen));
3236 break;
3237 }
3238 ASSERT(!(pnext->prev));
3239 if (!pfirst) {
3240 ASSERT(!plast);
3241 pfirst = plast = pnext;
3242 } else {
3243 ASSERT(plast);
3244 plast->next = pnext;
3245 plast = pnext;
3246 }
3247
3248 /* Adhere to start alignment requirements */
3249 PKTALIGN(pnext, sublen, DHD_SDALIGN);
3250 }
3251
3252 /* If all allocations succeeded, save packet chain
3253 in bus structure */
3254 if (pnext) {
3255 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3256 "subframes\n", __func__, totlen, num));
3257 if (DHD_GLOM_ON() && bus->nextlen) {
3258 if (totlen != bus->nextlen) {
3259 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3260 __func__, bus->nextlen,
3261 totlen, rxseq));
3262 }
3263 }
3264 bus->glom = pfirst;
3265 pfirst = pnext = NULL;
3266 } else {
3267 if (pfirst)
3268 pkt_buf_free_skb(pfirst);
3269 bus->glom = NULL;
3270 num = 0;
3271 }
3272
3273 /* Done with descriptor packet */
3274 pkt_buf_free_skb(bus->glomd);
3275 bus->glomd = NULL;
3276 bus->nextlen = 0;
3277
3278 dhd_os_sdunlock_rxq(bus->dhd);
3279 }
3280
3281 /* Ok -- either we just generated a packet chain,
3282 or had one from before */
3283 if (bus->glom) {
3284 if (DHD_GLOM_ON()) {
3285 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3286 __func__));
3287 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3288 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3289 pnext, (u8 *) (pnext->data),
3290 pnext->len, pnext->len));
3291 }
3292 }
3293
3294 pfirst = bus->glom;
3295 dlen = (u16) pkttotlen(pfirst);
3296
3297 /* Do an SDIO read for the superframe. Configurable iovar to
3298 * read directly into the chained packet, or allocate a large
3299 * packet and and copy into the chain.
3300 */
3301 if (usechain) {
3302 errcode = dhd_bcmsdh_recv_buf(bus,
3303 bcmsdh_cur_sbwad
3304 (bus->sdh), SDIO_FUNC_2,
3305 F2SYNC,
3306 (u8 *) pfirst->data,
3307 dlen, pfirst, NULL, NULL);
3308 } else if (bus->dataptr) {
3309 errcode = dhd_bcmsdh_recv_buf(bus,
3310 bcmsdh_cur_sbwad
3311 (bus->sdh), SDIO_FUNC_2,
3312 F2SYNC, bus->dataptr,
3313 dlen, NULL, NULL, NULL);
3314 sublen =
3315 (u16) pktfrombuf(pfirst, 0, dlen,
3316 bus->dataptr);
3317 if (sublen != dlen) {
3318 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3319 __func__, dlen, sublen));
3320 errcode = -1;
3321 }
3322 pnext = NULL;
3323 } else {
3324 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3325 dlen));
3326 errcode = -1;
3327 }
3328 bus->f2rxdata++;
3329 ASSERT(errcode != BCME_PENDING);
3330
3331 /* On failure, kill the superframe, allow a couple retries */
3332 if (errcode < 0) {
3333 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3334 __func__, dlen, errcode));
3335 bus->dhd->rx_errors++;
3336
3337 if (bus->glomerr++ < 3) {
3338 dhdsdio_rxfail(bus, true, true);
3339 } else {
3340 bus->glomerr = 0;
3341 dhdsdio_rxfail(bus, true, false);
3342 dhd_os_sdlock_rxq(bus->dhd);
3343 pkt_buf_free_skb(bus->glom);
3344 dhd_os_sdunlock_rxq(bus->dhd);
3345 bus->rxglomfail++;
3346 bus->glom = NULL;
3347 }
3348 return 0;
3349 }
3350 #ifdef DHD_DEBUG
3351 if (DHD_GLOM_ON()) {
3352 prhex("SUPERFRAME", pfirst->data,
3353 min_t(int, pfirst->len, 48));
3354 }
3355 #endif
3356
3357 /* Validate the superframe header */
3358 dptr = (u8 *) (pfirst->data);
3359 sublen = get_unaligned_le16(dptr);
3360 check = get_unaligned_le16(dptr + sizeof(u16));
3361
3362 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3363 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3364 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3365 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3366 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3367 __func__, bus->nextlen, seq));
3368 bus->nextlen = 0;
3369 }
3370 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3371 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3372
3373 errcode = 0;
3374 if ((u16)~(sublen ^ check)) {
3375 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3376 "0x%04x/0x%04x\n", __func__, sublen, check));
3377 errcode = -1;
3378 } else if (roundup(sublen, bus->blocksize) != dlen) {
3379 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3380 "0x%04x, expect 0x%04x\n",
3381 __func__, sublen,
3382 roundup(sublen, bus->blocksize), dlen));
3383 errcode = -1;
3384 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3385 SDPCM_GLOM_CHANNEL) {
3386 DHD_ERROR(("%s (superframe): bad channel %d\n",
3387 __func__,
3388 SDPCM_PACKET_CHANNEL(&dptr
3389 [SDPCM_FRAMETAG_LEN])));
3390 errcode = -1;
3391 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3392 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3393 __func__));
3394 errcode = -1;
3395 } else if ((doff < SDPCM_HDRLEN) ||
3396 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3397 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3398 "pkt %d min %d\n",
3399 __func__, doff, sublen,
3400 pfirst->len, SDPCM_HDRLEN));
3401 errcode = -1;
3402 }
3403
3404 /* Check sequence number of superframe SW header */
3405 if (rxseq != seq) {
3406 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3407 __func__, seq, rxseq));
3408 bus->rx_badseq++;
3409 rxseq = seq;
3410 }
3411
3412 /* Check window for sanity */
3413 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3414 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3415 __func__, txmax, bus->tx_seq));
3416 txmax = bus->tx_seq + 2;
3417 }
3418 bus->tx_max = txmax;
3419
3420 /* Remove superframe header, remember offset */
3421 skb_pull(pfirst, doff);
3422 sfdoff = doff;
3423
3424 /* Validate all the subframe headers */
3425 for (num = 0, pnext = pfirst; pnext && !errcode;
3426 num++, pnext = pnext->next) {
3427 dptr = (u8 *) (pnext->data);
3428 dlen = (u16) (pnext->len);
3429 sublen = get_unaligned_le16(dptr);
3430 check = get_unaligned_le16(dptr + sizeof(u16));
3431 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3432 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3433 #ifdef DHD_DEBUG
3434 if (DHD_GLOM_ON())
3435 prhex("subframe", dptr, 32);
3436 #endif
3437
3438 if ((u16)~(sublen ^ check)) {
3439 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3440 "len/check 0x%04x/0x%04x\n",
3441 __func__, num, sublen, check));
3442 errcode = -1;
3443 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3444 DHD_ERROR(("%s (subframe %d): length mismatch: "
3445 "len 0x%04x, expect 0x%04x\n",
3446 __func__, num, sublen, dlen));
3447 errcode = -1;
3448 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3449 (chan != SDPCM_EVENT_CHANNEL)) {
3450 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3451 __func__, num, chan));
3452 errcode = -1;
3453 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3454 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3455 __func__, num, doff, sublen,
3456 SDPCM_HDRLEN));
3457 errcode = -1;
3458 }
3459 }
3460
3461 if (errcode) {
3462 /* Terminate frame on error, request
3463 a couple retries */
3464 if (bus->glomerr++ < 3) {
3465 /* Restore superframe header space */
3466 skb_push(pfirst, sfdoff);
3467 dhdsdio_rxfail(bus, true, true);
3468 } else {
3469 bus->glomerr = 0;
3470 dhdsdio_rxfail(bus, true, false);
3471 dhd_os_sdlock_rxq(bus->dhd);
3472 pkt_buf_free_skb(bus->glom);
3473 dhd_os_sdunlock_rxq(bus->dhd);
3474 bus->rxglomfail++;
3475 bus->glom = NULL;
3476 }
3477 bus->nextlen = 0;
3478 return 0;
3479 }
3480
3481 /* Basic SD framing looks ok - process each packet (header) */
3482 save_pfirst = pfirst;
3483 bus->glom = NULL;
3484 plast = NULL;
3485
3486 dhd_os_sdlock_rxq(bus->dhd);
3487 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3488 pnext = pfirst->next;
3489 pfirst->next = NULL;
3490
3491 dptr = (u8 *) (pfirst->data);
3492 sublen = get_unaligned_le16(dptr);
3493 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3494 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3495 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3496
3497 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3498 "chan %d seq %d\n",
3499 __func__, num, pfirst, pfirst->data,
3500 pfirst->len, sublen, chan, seq));
3501
3502 ASSERT((chan == SDPCM_DATA_CHANNEL)
3503 || (chan == SDPCM_EVENT_CHANNEL));
3504
3505 if (rxseq != seq) {
3506 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3507 __func__, seq, rxseq));
3508 bus->rx_badseq++;
3509 rxseq = seq;
3510 }
3511 #ifdef DHD_DEBUG
3512 if (DHD_BYTES_ON() && DHD_DATA_ON())
3513 prhex("Rx Subframe Data", dptr, dlen);
3514 #endif
3515
3516 __skb_trim(pfirst, sublen);
3517 skb_pull(pfirst, doff);
3518
3519 if (pfirst->len == 0) {
3520 pkt_buf_free_skb(pfirst);
3521 if (plast) {
3522 plast->next = pnext;
3523 } else {
3524 ASSERT(save_pfirst == pfirst);
3525 save_pfirst = pnext;
3526 }
3527 continue;
3528 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3529 0) {
3530 DHD_ERROR(("%s: rx protocol error\n",
3531 __func__));
3532 bus->dhd->rx_errors++;
3533 pkt_buf_free_skb(pfirst);
3534 if (plast) {
3535 plast->next = pnext;
3536 } else {
3537 ASSERT(save_pfirst == pfirst);
3538 save_pfirst = pnext;
3539 }
3540 continue;
3541 }
3542
3543 /* this packet will go up, link back into
3544 chain and count it */
3545 pfirst->next = pnext;
3546 plast = pfirst;
3547 num++;
3548
3549 #ifdef DHD_DEBUG
3550 if (DHD_GLOM_ON()) {
3551 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3552 "nxt/lnk %p/%p\n",
3553 __func__, num, pfirst, pfirst->data,
3554 pfirst->len, pfirst->next,
3555 pfirst->prev));
3556 prhex("", (u8 *) pfirst->data,
3557 min_t(int, pfirst->len, 32));
3558 }
3559 #endif /* DHD_DEBUG */
3560 }
3561 dhd_os_sdunlock_rxq(bus->dhd);
3562 if (num) {
3563 dhd_os_sdunlock(bus->dhd);
3564 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3565 dhd_os_sdlock(bus->dhd);
3566 }
3567
3568 bus->rxglomframes++;
3569 bus->rxglompkts += num;
3570 }
3571 return num;
3572 }
3573
3574 /* Return true if there may be more frames to read */
3575 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3576 {
3577 bcmsdh_info_t *sdh = bus->sdh;
3578
3579 u16 len, check; /* Extracted hardware header fields */
3580 u8 chan, seq, doff; /* Extracted software header fields */
3581 u8 fcbits; /* Extracted fcbits from software header */
3582 u8 delta;
3583
3584 struct sk_buff *pkt; /* Packet for event or data frames */
3585 u16 pad; /* Number of pad bytes to read */
3586 u16 rdlen; /* Total number of bytes to read */
3587 u8 rxseq; /* Next sequence number to expect */
3588 uint rxleft = 0; /* Remaining number of frames allowed */
3589 int sdret; /* Return code from bcmsdh calls */
3590 u8 txmax; /* Maximum tx sequence offered */
3591 bool len_consistent; /* Result of comparing readahead len and
3592 len from hw-hdr */
3593 u8 *rxbuf;
3594 int ifidx = 0;
3595 uint rxcount = 0; /* Total frames read */
3596
3597 #if defined(DHD_DEBUG) || defined(SDTEST)
3598 bool sdtest = false; /* To limit message spew from test mode */
3599 #endif
3600
3601 DHD_TRACE(("%s: Enter\n", __func__));
3602
3603 ASSERT(maxframes);
3604
3605 #ifdef SDTEST
3606 /* Allow pktgen to override maxframes */
3607 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3608 maxframes = bus->pktgen_count;
3609 sdtest = true;
3610 }
3611 #endif
3612
3613 /* Not finished unless we encounter no more frames indication */
3614 *finished = false;
3615
3616 for (rxseq = bus->rx_seq, rxleft = maxframes;
3617 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3618 rxseq++, rxleft--) {
3619
3620 /* Handle glomming separately */
3621 if (bus->glom || bus->glomd) {
3622 u8 cnt;
3623 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3624 __func__, bus->glomd, bus->glom));
3625 cnt = dhdsdio_rxglom(bus, rxseq);
3626 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3627 rxseq += cnt - 1;
3628 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3629 continue;
3630 }
3631
3632 /* Try doing single read if we can */
3633 if (dhd_readahead && bus->nextlen) {
3634 u16 nextlen = bus->nextlen;
3635 bus->nextlen = 0;
3636
3637 if (bus->bus == SPI_BUS) {
3638 rdlen = len = nextlen;
3639 } else {
3640 rdlen = len = nextlen << 4;
3641
3642 /* Pad read to blocksize for efficiency */
3643 if (bus->roundup && bus->blocksize
3644 && (rdlen > bus->blocksize)) {
3645 pad =
3646 bus->blocksize -
3647 (rdlen % bus->blocksize);
3648 if ((pad <= bus->roundup)
3649 && (pad < bus->blocksize)
3650 && ((rdlen + pad + firstread) <
3651 MAX_RX_DATASZ))
3652 rdlen += pad;
3653 } else if (rdlen % DHD_SDALIGN) {
3654 rdlen +=
3655 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3656 }
3657 }
3658
3659 /* We use bus->rxctl buffer in WinXP for initial
3660 * control pkt receives.
3661 * Later we use buffer-poll for data as well
3662 * as control packets.
3663 * This is required because dhd receives full
3664 * frame in gSPI unlike SDIO.
3665 * After the frame is received we have to
3666 * distinguish whether it is data
3667 * or non-data frame.
3668 */
3669 /* Allocate a packet buffer */
3670 dhd_os_sdlock_rxq(bus->dhd);
3671 pkt = pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3672 if (!pkt) {
3673 if (bus->bus == SPI_BUS) {
3674 bus->usebufpool = false;
3675 bus->rxctl = bus->rxbuf;
3676 if (dhd_alignctl) {
3677 bus->rxctl += firstread;
3678 pad = ((unsigned long)bus->rxctl %
3679 DHD_SDALIGN);
3680 if (pad)
3681 bus->rxctl +=
3682 (DHD_SDALIGN - pad);
3683 bus->rxctl -= firstread;
3684 }
3685 ASSERT(bus->rxctl >= bus->rxbuf);
3686 rxbuf = bus->rxctl;
3687 /* Read the entire frame */
3688 sdret = dhd_bcmsdh_recv_buf(bus,
3689 bcmsdh_cur_sbwad
3690 (sdh),
3691 SDIO_FUNC_2,
3692 F2SYNC,
3693 rxbuf,
3694 rdlen, NULL,
3695 NULL, NULL);
3696 bus->f2rxdata++;
3697 ASSERT(sdret != BCME_PENDING);
3698
3699 /* Control frame failures need
3700 retransmission */
3701 if (sdret < 0) {
3702 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3703 __func__,
3704 rdlen, sdret));
3705 /* dhd.rx_ctlerrs is higher */
3706 bus->rxc_errors++;
3707 dhd_os_sdunlock_rxq(bus->dhd);
3708 dhdsdio_rxfail(bus, true,
3709 (bus->bus ==
3710 SPI_BUS) ? false
3711 : true);
3712 continue;
3713 }
3714 } else {
3715 /* Give up on data,
3716 request rtx of events */
3717 DHD_ERROR(("%s (nextlen): pkt_buf_get_skb failed: len %d rdlen %d " "expected rxseq %d\n",
3718 __func__, len, rdlen, rxseq));
3719 /* Just go try again w/normal
3720 header read */
3721 dhd_os_sdunlock_rxq(bus->dhd);
3722 continue;
3723 }
3724 } else {
3725 if (bus->bus == SPI_BUS)
3726 bus->usebufpool = true;
3727
3728 ASSERT(!(pkt->prev));
3729 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3730 rxbuf = (u8 *) (pkt->data);
3731 /* Read the entire frame */
3732 sdret =
3733 dhd_bcmsdh_recv_buf(bus,
3734 bcmsdh_cur_sbwad(sdh),
3735 SDIO_FUNC_2, F2SYNC,
3736 rxbuf, rdlen, pkt, NULL,
3737 NULL);
3738 bus->f2rxdata++;
3739 ASSERT(sdret != BCME_PENDING);
3740
3741 if (sdret < 0) {
3742 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3743 __func__, rdlen, sdret));
3744 pkt_buf_free_skb(pkt);
3745 bus->dhd->rx_errors++;
3746 dhd_os_sdunlock_rxq(bus->dhd);
3747 /* Force retry w/normal header read.
3748 * Don't attempt NAK for
3749 * gSPI
3750 */
3751 dhdsdio_rxfail(bus, true,
3752 (bus->bus ==
3753 SPI_BUS) ? false :
3754 true);
3755 continue;
3756 }
3757 }
3758 dhd_os_sdunlock_rxq(bus->dhd);
3759
3760 /* Now check the header */
3761 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3762
3763 /* Extract hardware header fields */
3764 len = get_unaligned_le16(bus->rxhdr);
3765 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3766
3767 /* All zeros means readahead info was bad */
3768 if (!(len | check)) {
3769 DHD_INFO(("%s (nextlen): read zeros in HW "
3770 "header???\n", __func__));
3771 dhd_os_sdlock_rxq(bus->dhd);
3772 PKTFREE2();
3773 dhd_os_sdunlock_rxq(bus->dhd);
3774 GSPI_PR55150_BAILOUT;
3775 continue;
3776 }
3777
3778 /* Validate check bytes */
3779 if ((u16)~(len ^ check)) {
3780 DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n",
3781 __func__, nextlen, len, check));
3782 dhd_os_sdlock_rxq(bus->dhd);
3783 PKTFREE2();
3784 dhd_os_sdunlock_rxq(bus->dhd);
3785 bus->rx_badhdr++;
3786 dhdsdio_rxfail(bus, false, false);
3787 GSPI_PR55150_BAILOUT;
3788 continue;
3789 }
3790
3791 /* Validate frame length */
3792 if (len < SDPCM_HDRLEN) {
3793 DHD_ERROR(("%s (nextlen): HW hdr length "
3794 "invalid: %d\n", __func__, len));
3795 dhd_os_sdlock_rxq(bus->dhd);
3796 PKTFREE2();
3797 dhd_os_sdunlock_rxq(bus->dhd);
3798 GSPI_PR55150_BAILOUT;
3799 continue;
3800 }
3801
3802 /* Check for consistency withreadahead info */
3803 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3804 if (len_consistent) {
3805 /* Mismatch, force retry w/normal
3806 header (may be >4K) */
3807 DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " "expected rxseq %d\n",
3808 __func__, nextlen,
3809 len, roundup(len, 16), rxseq));
3810 dhd_os_sdlock_rxq(bus->dhd);
3811 PKTFREE2();
3812 dhd_os_sdunlock_rxq(bus->dhd);
3813 dhdsdio_rxfail(bus, true,
3814 (bus->bus ==
3815 SPI_BUS) ? false : true);
3816 GSPI_PR55150_BAILOUT;
3817 continue;
3818 }
3819
3820 /* Extract software header fields */
3821 chan =
3822 SDPCM_PACKET_CHANNEL(&bus->rxhdr
3823 [SDPCM_FRAMETAG_LEN]);
3824 seq =
3825 SDPCM_PACKET_SEQUENCE(&bus->rxhdr
3826 [SDPCM_FRAMETAG_LEN]);
3827 doff =
3828 SDPCM_DOFFSET_VALUE(&bus->rxhdr
3829 [SDPCM_FRAMETAG_LEN]);
3830 txmax =
3831 SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3832
3833 bus->nextlen =
3834 bus->rxhdr[SDPCM_FRAMETAG_LEN +
3835 SDPCM_NEXTLEN_OFFSET];
3836 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3837 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3838 __func__, bus->nextlen, seq));
3839 bus->nextlen = 0;
3840 }
3841
3842 bus->dhd->rx_readahead_cnt++;
3843 /* Handle Flow Control */
3844 fcbits =
3845 SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3846
3847 delta = 0;
3848 if (~bus->flowcontrol & fcbits) {
3849 bus->fc_xoff++;
3850 delta = 1;
3851 }
3852 if (bus->flowcontrol & ~fcbits) {
3853 bus->fc_xon++;
3854 delta = 1;
3855 }
3856
3857 if (delta) {
3858 bus->fc_rcvd++;
3859 bus->flowcontrol = fcbits;
3860 }
3861
3862 /* Check and update sequence number */
3863 if (rxseq != seq) {
3864 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
3865 "%d\n", __func__, seq, rxseq));
3866 bus->rx_badseq++;
3867 rxseq = seq;
3868 }
3869
3870 /* Check window for sanity */
3871 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3872 DHD_ERROR(("%s: got unlikely tx max %d with "
3873 "tx_seq %d\n",
3874 __func__, txmax, bus->tx_seq));
3875 txmax = bus->tx_seq + 2;
3876 }
3877 bus->tx_max = txmax;
3878
3879 #ifdef DHD_DEBUG
3880 if (DHD_BYTES_ON() && DHD_DATA_ON())
3881 prhex("Rx Data", rxbuf, len);
3882 else if (DHD_HDRS_ON())
3883 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3884 #endif
3885
3886 if (chan == SDPCM_CONTROL_CHANNEL) {
3887 if (bus->bus == SPI_BUS) {
3888 dhdsdio_read_control(bus, rxbuf, len,
3889 doff);
3890 if (bus->usebufpool) {
3891 dhd_os_sdlock_rxq(bus->dhd);
3892 pkt_buf_free_skb(pkt);
3893 dhd_os_sdunlock_rxq(bus->dhd);
3894 }
3895 continue;
3896 } else {
3897 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3898 __func__, seq));
3899 /* Force retry w/normal header read */
3900 bus->nextlen = 0;
3901 dhdsdio_rxfail(bus, false, true);
3902 dhd_os_sdlock_rxq(bus->dhd);
3903 PKTFREE2();
3904 dhd_os_sdunlock_rxq(bus->dhd);
3905 continue;
3906 }
3907 }
3908
3909 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
3910 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
3911 len, chan));
3912 continue;
3913 }
3914
3915 /* Validate data offset */
3916 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3917 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3918 __func__, doff, len, SDPCM_HDRLEN));
3919 dhd_os_sdlock_rxq(bus->dhd);
3920 PKTFREE2();
3921 dhd_os_sdunlock_rxq(bus->dhd);
3922 ASSERT(0);
3923 dhdsdio_rxfail(bus, false, false);
3924 continue;
3925 }
3926
3927 /* All done with this one -- now deliver the packet */
3928 goto deliver;
3929 }
3930 /* gSPI frames should not be handled in fractions */
3931 if (bus->bus == SPI_BUS)
3932 break;
3933
3934 /* Read frame header (hardware and software) */
3935 sdret =
3936 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3937 F2SYNC, bus->rxhdr, firstread, NULL,
3938 NULL, NULL);
3939 bus->f2rxhdrs++;
3940 ASSERT(sdret != BCME_PENDING);
3941
3942 if (sdret < 0) {
3943 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
3944 sdret));
3945 bus->rx_hdrfail++;
3946 dhdsdio_rxfail(bus, true, true);
3947 continue;
3948 }
3949 #ifdef DHD_DEBUG
3950 if (DHD_BYTES_ON() || DHD_HDRS_ON())
3951 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3952 #endif
3953
3954 /* Extract hardware header fields */
3955 len = get_unaligned_le16(bus->rxhdr);
3956 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3957
3958 /* All zeros means no more frames */
3959 if (!(len | check)) {
3960 *finished = true;
3961 break;
3962 }
3963
3964 /* Validate check bytes */
3965 if ((u16) ~(len ^ check)) {
3966 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
3967 __func__, len, check));
3968 bus->rx_badhdr++;
3969 dhdsdio_rxfail(bus, false, false);
3970 continue;
3971 }
3972
3973 /* Validate frame length */
3974 if (len < SDPCM_HDRLEN) {
3975 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
3976 __func__, len));
3977 continue;
3978 }
3979
3980 /* Extract software header fields */
3981 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3982 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3983 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3984 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3985
3986 /* Validate data offset */
3987 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3988 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
3989 "seq %d\n",
3990 __func__, doff, len, SDPCM_HDRLEN, seq));
3991 bus->rx_badhdr++;
3992 ASSERT(0);
3993 dhdsdio_rxfail(bus, false, false);
3994 continue;
3995 }
3996
3997 /* Save the readahead length if there is one */
3998 bus->nextlen =
3999 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4000 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4001 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4002 "(%d), seq %d\n",
4003 __func__, bus->nextlen, seq));
4004 bus->nextlen = 0;
4005 }
4006
4007 /* Handle Flow Control */
4008 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4009
4010 delta = 0;
4011 if (~bus->flowcontrol & fcbits) {
4012 bus->fc_xoff++;
4013 delta = 1;
4014 }
4015 if (bus->flowcontrol & ~fcbits) {
4016 bus->fc_xon++;
4017 delta = 1;
4018 }
4019
4020 if (delta) {
4021 bus->fc_rcvd++;
4022 bus->flowcontrol = fcbits;
4023 }
4024
4025 /* Check and update sequence number */
4026 if (rxseq != seq) {
4027 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4028 seq, rxseq));
4029 bus->rx_badseq++;
4030 rxseq = seq;
4031 }
4032
4033 /* Check window for sanity */
4034 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4035 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4036 __func__, txmax, bus->tx_seq));
4037 txmax = bus->tx_seq + 2;
4038 }
4039 bus->tx_max = txmax;
4040
4041 /* Call a separate function for control frames */
4042 if (chan == SDPCM_CONTROL_CHANNEL) {
4043 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4044 continue;
4045 }
4046
4047 ASSERT((chan == SDPCM_DATA_CHANNEL)
4048 || (chan == SDPCM_EVENT_CHANNEL)
4049 || (chan == SDPCM_TEST_CHANNEL)
4050 || (chan == SDPCM_GLOM_CHANNEL));
4051
4052 /* Length to read */
4053 rdlen = (len > firstread) ? (len - firstread) : 0;
4054
4055 /* May pad read to blocksize for efficiency */
4056 if (bus->roundup && bus->blocksize &&
4057 (rdlen > bus->blocksize)) {
4058 pad = bus->blocksize - (rdlen % bus->blocksize);
4059 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4060 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4061 rdlen += pad;
4062 } else if (rdlen % DHD_SDALIGN) {
4063 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4064 }
4065
4066 /* Satisfy length-alignment requirements */
4067 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4068 rdlen = roundup(rdlen, ALIGNMENT);
4069
4070 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4071 /* Too long -- skip this frame */
4072 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4073 __func__, len, rdlen));
4074 bus->dhd->rx_errors++;
4075 bus->rx_toolong++;
4076 dhdsdio_rxfail(bus, false, false);
4077 continue;
4078 }
4079
4080 dhd_os_sdlock_rxq(bus->dhd);
4081 pkt = pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4082 if (!pkt) {
4083 /* Give up on data, request rtx of events */
4084 DHD_ERROR(("%s: pkt_buf_get_skb failed: rdlen %d chan %d\n",
4085 __func__, rdlen, chan));
4086 bus->dhd->rx_dropped++;
4087 dhd_os_sdunlock_rxq(bus->dhd);
4088 dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4089 continue;
4090 }
4091 dhd_os_sdunlock_rxq(bus->dhd);
4092
4093 ASSERT(!(pkt->prev));
4094
4095 /* Leave room for what we already read, and align remainder */
4096 ASSERT(firstread < pkt->len);
4097 skb_pull(pkt, firstread);
4098 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4099
4100 /* Read the remaining frame data */
4101 sdret =
4102 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4103 F2SYNC, ((u8 *) (pkt->data)), rdlen,
4104 pkt, NULL, NULL);
4105 bus->f2rxdata++;
4106 ASSERT(sdret != BCME_PENDING);
4107
4108 if (sdret < 0) {
4109 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4110 __func__, rdlen,
4111 ((chan ==
4112 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4113 SDPCM_DATA_CHANNEL)
4114 ? "data" : "test")),
4115 sdret));
4116 dhd_os_sdlock_rxq(bus->dhd);
4117 pkt_buf_free_skb(pkt);
4118 dhd_os_sdunlock_rxq(bus->dhd);
4119 bus->dhd->rx_errors++;
4120 dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4121 continue;
4122 }
4123
4124 /* Copy the already-read portion */
4125 skb_push(pkt, firstread);
4126 memcpy(pkt->data, bus->rxhdr, firstread);
4127
4128 #ifdef DHD_DEBUG
4129 if (DHD_BYTES_ON() && DHD_DATA_ON())
4130 prhex("Rx Data", pkt->data, len);
4131 #endif
4132
4133 deliver:
4134 /* Save superframe descriptor and allocate packet frame */
4135 if (chan == SDPCM_GLOM_CHANNEL) {
4136 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4137 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4138 __func__, len));
4139 #ifdef DHD_DEBUG
4140 if (DHD_GLOM_ON()) {
4141 prhex("Glom Data", pkt->data, len);
4142 }
4143 #endif
4144 __skb_trim(pkt, len);
4145 ASSERT(doff == SDPCM_HDRLEN);
4146 skb_pull(pkt, SDPCM_HDRLEN);
4147 bus->glomd = pkt;
4148 } else {
4149 DHD_ERROR(("%s: glom superframe w/o "
4150 "descriptor!\n", __func__));
4151 dhdsdio_rxfail(bus, false, false);
4152 }
4153 continue;
4154 }
4155
4156 /* Fill in packet len and prio, deliver upward */
4157 __skb_trim(pkt, len);
4158 skb_pull(pkt, doff);
4159
4160 #ifdef SDTEST
4161 /* Test channel packets are processed separately */
4162 if (chan == SDPCM_TEST_CHANNEL) {
4163 dhdsdio_testrcv(bus, pkt, seq);
4164 continue;
4165 }
4166 #endif /* SDTEST */
4167
4168 if (pkt->len == 0) {
4169 dhd_os_sdlock_rxq(bus->dhd);
4170 pkt_buf_free_skb(pkt);
4171 dhd_os_sdunlock_rxq(bus->dhd);
4172 continue;
4173 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4174 DHD_ERROR(("%s: rx protocol error\n", __func__));
4175 dhd_os_sdlock_rxq(bus->dhd);
4176 pkt_buf_free_skb(pkt);
4177 dhd_os_sdunlock_rxq(bus->dhd);
4178 bus->dhd->rx_errors++;
4179 continue;
4180 }
4181
4182 /* Unlock during rx call */
4183 dhd_os_sdunlock(bus->dhd);
4184 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4185 dhd_os_sdlock(bus->dhd);
4186 }
4187 rxcount = maxframes - rxleft;
4188 #ifdef DHD_DEBUG
4189 /* Message if we hit the limit */
4190 if (!rxleft && !sdtest)
4191 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4192 maxframes));
4193 else
4194 #endif /* DHD_DEBUG */
4195 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4196 /* Back off rxseq if awaiting rtx, update rx_seq */
4197 if (bus->rxskip)
4198 rxseq--;
4199 bus->rx_seq = rxseq;
4200
4201 return rxcount;
4202 }
4203
4204 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4205 {
4206 sdpcmd_regs_t *regs = bus->regs;
4207 u32 intstatus = 0;
4208 u32 hmb_data;
4209 u8 fcbits;
4210 uint retries = 0;
4211
4212 DHD_TRACE(("%s: Enter\n", __func__));
4213
4214 /* Read mailbox data and ack that we did so */
4215 R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
4216 if (retries <= retry_limit)
4217 W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
4218 bus->f1regdata += 2;
4219
4220 /* Dongle recomposed rx frames, accept them again */
4221 if (hmb_data & HMB_DATA_NAKHANDLED) {
4222 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4223 bus->rx_seq));
4224 if (!bus->rxskip)
4225 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4226
4227 bus->rxskip = false;
4228 intstatus |= I_HMB_FRAME_IND;
4229 }
4230
4231 /*
4232 * DEVREADY does not occur with gSPI.
4233 */
4234 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4235 bus->sdpcm_ver =
4236 (hmb_data & HMB_DATA_VERSION_MASK) >>
4237 HMB_DATA_VERSION_SHIFT;
4238 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4239 DHD_ERROR(("Version mismatch, dongle reports %d, "
4240 "expecting %d\n",
4241 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4242 else
4243 DHD_INFO(("Dongle ready, protocol version %d\n",
4244 bus->sdpcm_ver));
4245 }
4246
4247 /*
4248 * Flow Control has been moved into the RX headers and this out of band
4249 * method isn't used any more. Leae this here for possibly
4250 * remaining backward
4251 * compatible with older dongles
4252 */
4253 if (hmb_data & HMB_DATA_FC) {
4254 fcbits =
4255 (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
4256
4257 if (fcbits & ~bus->flowcontrol)
4258 bus->fc_xoff++;
4259 if (bus->flowcontrol & ~fcbits)
4260 bus->fc_xon++;
4261
4262 bus->fc_rcvd++;
4263 bus->flowcontrol = fcbits;
4264 }
4265
4266 /* Shouldn't be any others */
4267 if (hmb_data & ~(HMB_DATA_DEVREADY |
4268 HMB_DATA_NAKHANDLED |
4269 HMB_DATA_FC |
4270 HMB_DATA_FWREADY |
4271 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4272 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4273 }
4274
4275 return intstatus;
4276 }
4277
4278 bool dhdsdio_dpc(dhd_bus_t *bus)
4279 {
4280 bcmsdh_info_t *sdh = bus->sdh;
4281 sdpcmd_regs_t *regs = bus->regs;
4282 u32 intstatus, newstatus = 0;
4283 uint retries = 0;
4284 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4285 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4286 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4287 bool rxdone = true; /* Flag for no more read data */
4288 bool resched = false; /* Flag indicating resched wanted */
4289
4290 DHD_TRACE(("%s: Enter\n", __func__));
4291
4292 /* Start with leftover status bits */
4293 intstatus = bus->intstatus;
4294
4295 dhd_os_sdlock(bus->dhd);
4296
4297 /* If waiting for HTAVAIL, check status */
4298 if (bus->clkstate == CLK_PENDING) {
4299 int err;
4300 u8 clkctl, devctl = 0;
4301
4302 #ifdef DHD_DEBUG
4303 /* Check for inconsistent device control */
4304 devctl =
4305 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4306 if (err) {
4307 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4308 __func__, err));
4309 bus->dhd->busstate = DHD_BUS_DOWN;
4310 } else {
4311 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4312 }
4313 #endif /* DHD_DEBUG */
4314
4315 /* Read CSR, if clock on switch to AVAIL, else ignore */
4316 clkctl =
4317 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4318 &err);
4319 if (err) {
4320 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4321 err));
4322 bus->dhd->busstate = DHD_BUS_DOWN;
4323 }
4324
4325 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4326 clkctl));
4327
4328 if (SBSDIO_HTAV(clkctl)) {
4329 devctl =
4330 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4331 &err);
4332 if (err) {
4333 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4334 __func__, err));
4335 bus->dhd->busstate = DHD_BUS_DOWN;
4336 }
4337 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4338 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4339 devctl, &err);
4340 if (err) {
4341 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4342 __func__, err));
4343 bus->dhd->busstate = DHD_BUS_DOWN;
4344 }
4345 bus->clkstate = CLK_AVAIL;
4346 } else {
4347 goto clkwait;
4348 }
4349 }
4350
4351 BUS_WAKE(bus);
4352
4353 /* Make sure backplane clock is on */
4354 dhdsdio_clkctl(bus, CLK_AVAIL, true);
4355 if (bus->clkstate == CLK_PENDING)
4356 goto clkwait;
4357
4358 /* Pending interrupt indicates new device status */
4359 if (bus->ipend) {
4360 bus->ipend = false;
4361 R_SDREG(newstatus, &regs->intstatus, retries);
4362 bus->f1regdata++;
4363 if (bcmsdh_regfail(bus->sdh))
4364 newstatus = 0;
4365 newstatus &= bus->hostintmask;
4366 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4367 if (newstatus) {
4368 W_SDREG(newstatus, &regs->intstatus, retries);
4369 bus->f1regdata++;
4370 }
4371 }
4372
4373 /* Merge new bits with previous */
4374 intstatus |= newstatus;
4375 bus->intstatus = 0;
4376
4377 /* Handle flow-control change: read new state in case our ack
4378 * crossed another change interrupt. If change still set, assume
4379 * FC ON for safety, let next loop through do the debounce.
4380 */
4381 if (intstatus & I_HMB_FC_CHANGE) {
4382 intstatus &= ~I_HMB_FC_CHANGE;
4383 W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
4384 R_SDREG(newstatus, &regs->intstatus, retries);
4385 bus->f1regdata += 2;
4386 bus->fcstate =
4387 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4388 intstatus |= (newstatus & bus->hostintmask);
4389 }
4390
4391 /* Handle host mailbox indication */
4392 if (intstatus & I_HMB_HOST_INT) {
4393 intstatus &= ~I_HMB_HOST_INT;
4394 intstatus |= dhdsdio_hostmail(bus);
4395 }
4396
4397 /* Generally don't ask for these, can get CRC errors... */
4398 if (intstatus & I_WR_OOSYNC) {
4399 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4400 intstatus &= ~I_WR_OOSYNC;
4401 }
4402
4403 if (intstatus & I_RD_OOSYNC) {
4404 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4405 intstatus &= ~I_RD_OOSYNC;
4406 }
4407
4408 if (intstatus & I_SBINT) {
4409 DHD_ERROR(("Dongle reports SBINT\n"));
4410 intstatus &= ~I_SBINT;
4411 }
4412
4413 /* Would be active due to wake-wlan in gSPI */
4414 if (intstatus & I_CHIPACTIVE) {
4415 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4416 intstatus &= ~I_CHIPACTIVE;
4417 }
4418
4419 /* Ignore frame indications if rxskip is set */
4420 if (bus->rxskip)
4421 intstatus &= ~I_HMB_FRAME_IND;
4422
4423 /* On frame indication, read available frames */
4424 if (PKT_AVAILABLE()) {
4425 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4426 if (rxdone || bus->rxskip)
4427 intstatus &= ~I_HMB_FRAME_IND;
4428 rxlimit -= min(framecnt, rxlimit);
4429 }
4430
4431 /* Keep still-pending events for next scheduling */
4432 bus->intstatus = intstatus;
4433
4434 clkwait:
4435 #if defined(OOB_INTR_ONLY)
4436 bcmsdh_oob_intr_set(1);
4437 #endif /* (OOB_INTR_ONLY) */
4438 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4439 * or clock availability. (Allows tx loop to check ipend if desired.)
4440 * (Unless register access seems hosed, as we may not be able to ACK...)
4441 */
4442 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4443 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4444 __func__, rxdone, framecnt));
4445 bus->intdis = false;
4446 bcmsdh_intr_enable(sdh);
4447 }
4448
4449 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4450 (bus->clkstate == CLK_AVAIL)) {
4451 int ret, i;
4452
4453 ret =
4454 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4455 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4456 (u32) bus->ctrl_frame_len, NULL,
4457 NULL, NULL);
4458 ASSERT(ret != BCME_PENDING);
4459
4460 if (ret < 0) {
4461 /* On failure, abort the command and
4462 terminate the frame */
4463 DHD_INFO(("%s: sdio error %d, abort command and "
4464 "terminate frame.\n", __func__, ret));
4465 bus->tx_sderrs++;
4466
4467 bcmsdh_abort(sdh, SDIO_FUNC_2);
4468
4469 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4470 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4471 NULL);
4472 bus->f1regdata++;
4473
4474 for (i = 0; i < 3; i++) {
4475 u8 hi, lo;
4476 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4477 SBSDIO_FUNC1_WFRAMEBCHI,
4478 NULL);
4479 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4480 SBSDIO_FUNC1_WFRAMEBCLO,
4481 NULL);
4482 bus->f1regdata += 2;
4483 if ((hi == 0) && (lo == 0))
4484 break;
4485 }
4486
4487 }
4488 if (ret == 0)
4489 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4490
4491 DHD_INFO(("Return_dpc value is : %d\n", ret));
4492 bus->ctrl_frame_stat = false;
4493 dhd_wait_event_wakeup(bus->dhd);
4494 }
4495 /* Send queued frames (limit 1 if rx may still be pending) */
4496 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4497 pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4498 && DATAOK(bus)) {
4499 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4500 framecnt = dhdsdio_sendfromq(bus, framecnt);
4501 txlimit -= framecnt;
4502 }
4503
4504 /* Resched if events or tx frames are pending,
4505 else await next interrupt */
4506 /* On failed register access, all bets are off:
4507 no resched or interrupts */
4508 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4509 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4510 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4511 bus->dhd->busstate = DHD_BUS_DOWN;
4512 bus->intstatus = 0;
4513 } else if (bus->clkstate == CLK_PENDING) {
4514 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4515 "I_CHIPACTIVE interrupt\n", __func__));
4516 resched = true;
4517 } else if (bus->intstatus || bus->ipend ||
4518 (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4519 DATAOK(bus)) || PKT_AVAILABLE()) {
4520 resched = true;
4521 }
4522
4523 bus->dpc_sched = resched;
4524
4525 /* If we're done for now, turn off clock request. */
4526 if ((bus->clkstate != CLK_PENDING)
4527 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4528 bus->activity = false;
4529 dhdsdio_clkctl(bus, CLK_NONE, false);
4530 }
4531
4532 dhd_os_sdunlock(bus->dhd);
4533
4534 return resched;
4535 }
4536
4537 bool dhd_bus_dpc(struct dhd_bus *bus)
4538 {
4539 bool resched;
4540
4541 /* Call the DPC directly. */
4542 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4543 resched = dhdsdio_dpc(bus);
4544
4545 return resched;
4546 }
4547
4548 void dhdsdio_isr(void *arg)
4549 {
4550 dhd_bus_t *bus = (dhd_bus_t *) arg;
4551 bcmsdh_info_t *sdh;
4552
4553 DHD_TRACE(("%s: Enter\n", __func__));
4554
4555 if (!bus) {
4556 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4557 return;
4558 }
4559 sdh = bus->sdh;
4560
4561 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4562 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4563 __func__));
4564 return;
4565 }
4566 /* Count the interrupt call */
4567 bus->intrcount++;
4568 bus->ipend = true;
4569
4570 /* Shouldn't get this interrupt if we're sleeping? */
4571 if (bus->sleeping) {
4572 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4573 return;
4574 }
4575
4576 /* Disable additional interrupts (is this needed now)? */
4577 if (bus->intr)
4578 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4579 else
4580 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4581
4582 bcmsdh_intr_disable(sdh);
4583 bus->intdis = true;
4584
4585 #if defined(SDIO_ISR_THREAD)
4586 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4587 while (dhdsdio_dpc(bus))
4588 ;
4589 #else
4590 bus->dpc_sched = true;
4591 dhd_sched_dpc(bus->dhd);
4592 #endif
4593
4594 }
4595
4596 #ifdef SDTEST
4597 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4598 {
4599 /* Default to specified length, or full range */
4600 if (dhd_pktgen_len) {
4601 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4602 bus->pktgen_minlen = bus->pktgen_maxlen;
4603 } else {
4604 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4605 bus->pktgen_minlen = 0;
4606 }
4607 bus->pktgen_len = (u16) bus->pktgen_minlen;
4608
4609 /* Default to per-watchdog burst with 10s print time */
4610 bus->pktgen_freq = 1;
4611 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4612 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4613
4614 /* Default to echo mode */
4615 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4616 bus->pktgen_stop = 1;
4617 }
4618
4619 static void dhdsdio_pktgen(dhd_bus_t *bus)
4620 {
4621 struct sk_buff *pkt;
4622 u8 *data;
4623 uint pktcount;
4624 uint fillbyte;
4625 u16 len;
4626
4627 /* Display current count if appropriate */
4628 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4629 bus->pktgen_ptick = 0;
4630 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4631 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4632 }
4633
4634 /* For recv mode, just make sure dongle has started sending */
4635 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4636 if (!bus->pktgen_rcvd)
4637 dhdsdio_sdtest_set(bus, true);
4638 return;
4639 }
4640
4641 /* Otherwise, generate or request the specified number of packets */
4642 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4643 /* Stop if total has been reached */
4644 if (bus->pktgen_total
4645 && (bus->pktgen_sent >= bus->pktgen_total)) {
4646 bus->pktgen_count = 0;
4647 break;
4648 }
4649
4650 /* Allocate an appropriate-sized packet */
4651 len = bus->pktgen_len;
4652 pkt = pkt_buf_get_skb(
4653 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4654 true);
4655 if (!pkt) {
4656 DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
4657 break;
4658 }
4659 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4660 DHD_SDALIGN);
4661 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4662
4663 /* Write test header cmd and extra based on mode */
4664 switch (bus->pktgen_mode) {
4665 case DHD_PKTGEN_ECHO:
4666 *data++ = SDPCM_TEST_ECHOREQ;
4667 *data++ = (u8) bus->pktgen_sent;
4668 break;
4669
4670 case DHD_PKTGEN_SEND:
4671 *data++ = SDPCM_TEST_DISCARD;
4672 *data++ = (u8) bus->pktgen_sent;
4673 break;
4674
4675 case DHD_PKTGEN_RXBURST:
4676 *data++ = SDPCM_TEST_BURST;
4677 *data++ = (u8) bus->pktgen_count;
4678 break;
4679
4680 default:
4681 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4682 bus->pktgen_mode));
4683 pkt_buf_free_skb(pkt, true);
4684 bus->pktgen_count = 0;
4685 return;
4686 }
4687
4688 /* Write test header length field */
4689 *data++ = (len >> 0);
4690 *data++ = (len >> 8);
4691
4692 /* Then fill in the remainder -- N/A for burst,
4693 but who cares... */
4694 for (fillbyte = 0; fillbyte < len; fillbyte++)
4695 *data++ =
4696 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4697
4698 #ifdef DHD_DEBUG
4699 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4700 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4701 prhex("dhdsdio_pktgen: Tx Data", data,
4702 pkt->len - SDPCM_HDRLEN);
4703 }
4704 #endif
4705
4706 /* Send it */
4707 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4708 bus->pktgen_fail++;
4709 if (bus->pktgen_stop
4710 && bus->pktgen_stop == bus->pktgen_fail)
4711 bus->pktgen_count = 0;
4712 }
4713 bus->pktgen_sent++;
4714
4715 /* Bump length if not fixed, wrap at max */
4716 if (++bus->pktgen_len > bus->pktgen_maxlen)
4717 bus->pktgen_len = (u16) bus->pktgen_minlen;
4718
4719 /* Special case for burst mode: just send one request! */
4720 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4721 break;
4722 }
4723 }
4724
4725 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4726 {
4727 struct sk_buff *pkt;
4728 u8 *data;
4729
4730 /* Allocate the packet */
4731 pkt = pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN,
4732 true);
4733 if (!pkt) {
4734 DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
4735 return;
4736 }
4737 PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4738 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4739
4740 /* Fill in the test header */
4741 *data++ = SDPCM_TEST_SEND;
4742 *data++ = start;
4743 *data++ = (bus->pktgen_maxlen >> 0);
4744 *data++ = (bus->pktgen_maxlen >> 8);
4745
4746 /* Send it */
4747 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4748 bus->pktgen_fail++;
4749 }
4750
4751 static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4752 {
4753 u8 *data;
4754 uint pktlen;
4755
4756 u8 cmd;
4757 u8 extra;
4758 u16 len;
4759 u16 offset;
4760
4761 /* Check for min length */
4762 pktlen = pkt->len;
4763 if (pktlen < SDPCM_TEST_HDRLEN) {
4764 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4765 pktlen));
4766 pkt_buf_free_skb(pkt, false);
4767 return;
4768 }
4769
4770 /* Extract header fields */
4771 data = pkt->data;
4772 cmd = *data++;
4773 extra = *data++;
4774 len = *data++;
4775 len += *data++ << 8;
4776
4777 /* Check length for relevant commands */
4778 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4779 || cmd == SDPCM_TEST_ECHORSP) {
4780 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4781 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4782 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4783 pktlen, seq, cmd, extra, len));
4784 pkt_buf_free_skb(pkt, false);
4785 return;
4786 }
4787 }
4788
4789 /* Process as per command */
4790 switch (cmd) {
4791 case SDPCM_TEST_ECHOREQ:
4792 /* Rx->Tx turnaround ok (even on NDIS w/current
4793 implementation) */
4794 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4795 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4796 bus->pktgen_sent++;
4797 } else {
4798 bus->pktgen_fail++;
4799 pkt_buf_free_skb(pkt, false);
4800 }
4801 bus->pktgen_rcvd++;
4802 break;
4803
4804 case SDPCM_TEST_ECHORSP:
4805 if (bus->ext_loop) {
4806 pkt_buf_free_skb(pkt, false);
4807 bus->pktgen_rcvd++;
4808 break;
4809 }
4810
4811 for (offset = 0; offset < len; offset++, data++) {
4812 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4813 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4814 offset, len,
4815 SDPCM_TEST_FILL(offset, extra), *data));
4816 break;
4817 }
4818 }
4819 pkt_buf_free_skb(pkt, false);
4820 bus->pktgen_rcvd++;
4821 break;
4822
4823 case SDPCM_TEST_DISCARD:
4824 pkt_buf_free_skb(pkt, false);
4825 bus->pktgen_rcvd++;
4826 break;
4827
4828 case SDPCM_TEST_BURST:
4829 case SDPCM_TEST_SEND:
4830 default:
4831 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4832 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4833 pktlen, seq, cmd, extra, len));
4834 pkt_buf_free_skb(pkt, false);
4835 break;
4836 }
4837
4838 /* For recv mode, stop at limie (and tell dongle to stop sending) */
4839 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4840 if (bus->pktgen_total
4841 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4842 bus->pktgen_count = 0;
4843 dhdsdio_sdtest_set(bus, false);
4844 }
4845 }
4846 }
4847 #endif /* SDTEST */
4848
4849 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4850 {
4851 dhd_bus_t *bus;
4852
4853 DHD_TIMER(("%s: Enter\n", __func__));
4854
4855 bus = dhdp->bus;
4856
4857 if (bus->dhd->dongle_reset)
4858 return false;
4859
4860 /* Ignore the timer if simulating bus down */
4861 if (bus->sleeping)
4862 return false;
4863
4864 dhd_os_sdlock(bus->dhd);
4865
4866 /* Poll period: check device if appropriate. */
4867 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
4868 u32 intstatus = 0;
4869
4870 /* Reset poll tick */
4871 bus->polltick = 0;
4872
4873 /* Check device if no interrupts */
4874 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
4875
4876 if (!bus->dpc_sched) {
4877 u8 devpend;
4878 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
4879 SDIOD_CCCR_INTPEND,
4880 NULL);
4881 intstatus =
4882 devpend & (INTR_STATUS_FUNC1 |
4883 INTR_STATUS_FUNC2);
4884 }
4885
4886 /* If there is something, make like the ISR and
4887 schedule the DPC */
4888 if (intstatus) {
4889 bus->pollcnt++;
4890 bus->ipend = true;
4891 if (bus->intr)
4892 bcmsdh_intr_disable(bus->sdh);
4893
4894 bus->dpc_sched = true;
4895 dhd_sched_dpc(bus->dhd);
4896
4897 }
4898 }
4899
4900 /* Update interrupt tracking */
4901 bus->lastintrs = bus->intrcount;
4902 }
4903 #ifdef DHD_DEBUG
4904 /* Poll for console output periodically */
4905 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
4906 bus->console.count += dhd_watchdog_ms;
4907 if (bus->console.count >= dhd_console_ms) {
4908 bus->console.count -= dhd_console_ms;
4909 /* Make sure backplane clock is on */
4910 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4911 if (dhdsdio_readconsole(bus) < 0)
4912 dhd_console_ms = 0; /* On error,
4913 stop trying */
4914 }
4915 }
4916 #endif /* DHD_DEBUG */
4917
4918 #ifdef SDTEST
4919 /* Generate packets if configured */
4920 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
4921 /* Make sure backplane clock is on */
4922 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4923 bus->pktgen_tick = 0;
4924 dhdsdio_pktgen(bus);
4925 }
4926 #endif
4927
4928 /* On idle timeout clear activity flag and/or turn off clock */
4929 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
4930 if (++bus->idlecount >= bus->idletime) {
4931 bus->idlecount = 0;
4932 if (bus->activity) {
4933 bus->activity = false;
4934 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
4935 } else {
4936 dhdsdio_clkctl(bus, CLK_NONE, false);
4937 }
4938 }
4939 }
4940
4941 dhd_os_sdunlock(bus->dhd);
4942
4943 return bus->ipend;
4944 }
4945
4946 #ifdef DHD_DEBUG
4947 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
4948 {
4949 dhd_bus_t *bus = dhdp->bus;
4950 u32 addr, val;
4951 int rv;
4952 struct sk_buff *pkt;
4953
4954 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4955 if (bus->console_addr == 0)
4956 return BCME_UNSUPPORTED;
4957
4958 /* Exclusive bus access */
4959 dhd_os_sdlock(bus->dhd);
4960
4961 /* Don't allow input if dongle is in reset */
4962 if (bus->dhd->dongle_reset) {
4963 dhd_os_sdunlock(bus->dhd);
4964 return BCME_NOTREADY;
4965 }
4966
4967 /* Request clock to allow SDIO accesses */
4968 BUS_WAKE(bus);
4969 /* No pend allowed since txpkt is called later, ht clk has to be on */
4970 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4971
4972 /* Zero cbuf_index */
4973 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf_idx);
4974 val = cpu_to_le32(0);
4975 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4976 if (rv < 0)
4977 goto done;
4978
4979 /* Write message into cbuf */
4980 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf);
4981 rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
4982 if (rv < 0)
4983 goto done;
4984
4985 /* Write length into vcons_in */
4986 addr = bus->console_addr + offsetof(hndrte_cons_t, vcons_in);
4987 val = cpu_to_le32(msglen);
4988 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4989 if (rv < 0)
4990 goto done;
4991
4992 /* Bump dongle by sending an empty event pkt.
4993 * sdpcm_sendup (RX) checks for virtual console input.
4994 */
4995 pkt = pkt_buf_get_skb(4 + SDPCM_RESERVE);
4996 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
4997 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
4998
4999 done:
5000 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5001 bus->activity = false;
5002 dhdsdio_clkctl(bus, CLK_NONE, true);
5003 }
5004
5005 dhd_os_sdunlock(bus->dhd);
5006
5007 return rv;
5008 }
5009 #endif /* DHD_DEBUG */
5010
5011 #ifdef DHD_DEBUG
5012 static void dhd_dump_cis(uint fn, u8 *cis)
5013 {
5014 uint byte, tag, tdata;
5015 DHD_INFO(("Function %d CIS:\n", fn));
5016
5017 for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
5018 if ((byte % 16) == 0)
5019 DHD_INFO((" "));
5020 DHD_INFO(("%02x ", cis[byte]));
5021 if ((byte % 16) == 15)
5022 DHD_INFO(("\n"));
5023 if (!tdata--) {
5024 tag = cis[byte];
5025 if (tag == 0xff)
5026 break;
5027 else if (!tag)
5028 tdata = 0;
5029 else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
5030 tdata = cis[byte + 1] + 1;
5031 else
5032 DHD_INFO(("]"));
5033 }
5034 }
5035 if ((byte % 16) != 15)
5036 DHD_INFO(("\n"));
5037 }
5038 #endif /* DHD_DEBUG */
5039
5040 static bool dhdsdio_chipmatch(u16 chipid)
5041 {
5042 if (chipid == BCM4325_CHIP_ID)
5043 return true;
5044 if (chipid == BCM4329_CHIP_ID)
5045 return true;
5046 if (chipid == BCM4319_CHIP_ID)
5047 return true;
5048 return false;
5049 }
5050
5051 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5052 u16 slot, u16 func, uint bustype, void *regsva,
5053 void *sdh)
5054 {
5055 int ret;
5056 dhd_bus_t *bus;
5057
5058 /* Init global variables at run-time, not as part of the declaration.
5059 * This is required to support init/de-init of the driver.
5060 * Initialization
5061 * of globals as part of the declaration results in non-deterministic
5062 * behavior since the value of the globals may be different on the
5063 * first time that the driver is initialized vs subsequent
5064 * initializations.
5065 */
5066 dhd_txbound = DHD_TXBOUND;
5067 dhd_rxbound = DHD_RXBOUND;
5068 dhd_alignctl = true;
5069 sd1idle = true;
5070 dhd_readahead = true;
5071 retrydata = false;
5072 dhd_dongle_memsize = 0;
5073 dhd_txminmax = DHD_TXMINMAX;
5074
5075 forcealign = true;
5076
5077 dhd_common_init();
5078
5079 DHD_TRACE(("%s: Enter\n", __func__));
5080 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5081
5082 /* We make assumptions about address window mappings */
5083 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5084
5085 /* BCMSDH passes venid and devid based on CIS parsing -- but
5086 * low-power start
5087 * means early parse could fail, so here we should get either an ID
5088 * we recognize OR (-1) indicating we must request power first.
5089 */
5090 /* Check the Vendor ID */
5091 switch (venid) {
5092 case 0x0000:
5093 case PCI_VENDOR_ID_BROADCOM:
5094 break;
5095 default:
5096 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5097 return NULL;
5098 }
5099
5100 /* Check the Device ID and make sure it's one that we support */
5101 switch (devid) {
5102 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5103 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5104 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5105 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5106 break;
5107 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5108 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5109 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5110 case 0x4329:
5111 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5112 break;
5113 case BCM4319_D11N_ID: /* 4319 802.11n id */
5114 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5115 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5116 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5117 break;
5118 case 0:
5119 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5120 __func__));
5121 break;
5122
5123 default:
5124 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5125 __func__, venid, devid));
5126 return NULL;
5127 }
5128
5129 /* Allocate private bus interface state */
5130 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5131 if (!bus) {
5132 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5133 goto fail;
5134 }
5135 bus->sdh = sdh;
5136 bus->cl_devid = (u16) devid;
5137 bus->bus = DHD_BUS;
5138 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5139 bus->usebufpool = false; /* Use bufpool if allocated,
5140 else use locally malloced rxbuf */
5141
5142 /* attempt to attach to the dongle */
5143 if (!(dhdsdio_probe_attach(bus, sdh, regsva, devid))) {
5144 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5145 goto fail;
5146 }
5147
5148 /* Attach to the dhd/OS/network interface */
5149 bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5150 if (!bus->dhd) {
5151 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5152 goto fail;
5153 }
5154
5155 /* Allocate buffers */
5156 if (!(dhdsdio_probe_malloc(bus, sdh))) {
5157 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5158 goto fail;
5159 }
5160
5161 if (!(dhdsdio_probe_init(bus, sdh))) {
5162 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5163 goto fail;
5164 }
5165
5166 /* Register interrupt callback, but mask it (not operational yet). */
5167 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5168 __func__));
5169 bcmsdh_intr_disable(sdh);
5170 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5171 if (ret != 0) {
5172 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5173 __func__, ret));
5174 goto fail;
5175 }
5176 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5177
5178 DHD_INFO(("%s: completed!!\n", __func__));
5179
5180 /* if firmware path present try to download and bring up bus */
5181 ret = dhd_bus_start(bus->dhd);
5182 if (ret != 0) {
5183 if (ret == BCME_NOTUP) {
5184 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5185 goto fail;
5186 }
5187 }
5188 /* Ok, have the per-port tell the stack we're open for business */
5189 if (dhd_net_attach(bus->dhd, 0) != 0) {
5190 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5191 goto fail;
5192 }
5193
5194 return bus;
5195
5196 fail:
5197 dhdsdio_release(bus);
5198 return NULL;
5199 }
5200
5201 static bool
5202 dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
5203 {
5204 u8 clkctl = 0;
5205 int err = 0;
5206
5207 bus->alp_only = true;
5208
5209 /* Return the window to backplane enumeration space for core access */
5210 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5211 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5212
5213 #ifdef DHD_DEBUG
5214 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5215 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5216
5217 #endif /* DHD_DEBUG */
5218
5219 /* Force PLL off until si_attach() programs PLL control regs */
5220
5221 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5222 DHD_INIT_CLKCTL1, &err);
5223 if (!err)
5224 clkctl =
5225 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5226 &err);
5227
5228 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5229 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5230 "0x%02x read 0x%02x\n",
5231 err, DHD_INIT_CLKCTL1, clkctl));
5232 goto fail;
5233 }
5234 #ifdef DHD_DEBUG
5235 if (DHD_INFO_ON()) {
5236 uint fn, numfn;
5237 u8 *cis[SDIOD_MAX_IOFUNCS];
5238 int err = 0;
5239
5240 numfn = bcmsdh_query_iofnum(sdh);
5241 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
5242
5243 /* Make sure ALP is available before trying to read CIS */
5244 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
5245 SBSDIO_FUNC1_CHIPCLKCSR,
5246 NULL)),
5247 !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
5248
5249 /* Now request ALP be put on the bus */
5250 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5251 DHD_INIT_CLKCTL2, &err);
5252 udelay(65);
5253
5254 for (fn = 0; fn <= numfn; fn++) {
5255 cis[fn] = kzalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC);
5256 if (!cis[fn]) {
5257 DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5258 "failed\n", fn));
5259 break;
5260 }
5261
5262 err = bcmsdh_cis_read(sdh, fn, cis[fn],
5263 SBSDIO_CIS_SIZE_LIMIT);
5264 if (err) {
5265 DHD_INFO(("dhdsdio_probe: fn %d cis read "
5266 "err %d\n", fn, err));
5267 kfree(cis[fn]);
5268 break;
5269 }
5270 dhd_dump_cis(fn, cis[fn]);
5271 }
5272
5273 while (fn-- > 0) {
5274 ASSERT(cis[fn]);
5275 kfree(cis[fn]);
5276 }
5277
5278 if (err) {
5279 DHD_ERROR(("dhdsdio_probe: error read/parsing CIS\n"));
5280 goto fail;
5281 }
5282 }
5283 #endif /* DHD_DEBUG */
5284
5285 /* si_attach() will provide an SI handle and scan the backplane */
5286 bus->sih = si_attach((uint) devid, regsva, DHD_BUS, sdh,
5287 &bus->vars, &bus->varsz);
5288 if (!(bus->sih)) {
5289 DHD_ERROR(("%s: si_attach failed!\n", __func__));
5290 goto fail;
5291 }
5292
5293 bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
5294
5295 if (!dhdsdio_chipmatch((u16) bus->sih->chip)) {
5296 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5297 __func__, bus->sih->chip));
5298 goto fail;
5299 }
5300
5301 si_sdiod_drive_strength_init(bus->sih, dhd_sdiod_drive_strength);
5302
5303 /* Get info on the ARM and SOCRAM cores... */
5304 if (!DHD_NOPMU(bus)) {
5305 if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
5306 (si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
5307 bus->armrev = si_corerev(bus->sih);
5308 } else {
5309 DHD_ERROR(("%s: failed to find ARM core!\n", __func__));
5310 goto fail;
5311 }
5312 bus->orig_ramsize = si_socram_size(bus->sih);
5313 if (!(bus->orig_ramsize)) {
5314 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5315 __func__));
5316 goto fail;
5317 }
5318 bus->ramsize = bus->orig_ramsize;
5319 if (dhd_dongle_memsize)
5320 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5321
5322 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5323 bus->ramsize, bus->orig_ramsize));
5324 }
5325
5326 /* ...but normally deal with the SDPCMDEV core */
5327 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
5328 if (!bus->regs) {
5329 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
5330 if (!bus->regs) {
5331 DHD_ERROR(("%s: failed to find SDIODEV core!\n",
5332 __func__));
5333 goto fail;
5334 }
5335 }
5336 bus->sdpcmrev = si_corerev(bus->sih);
5337
5338 /* Set core control so an SDIO reset does a backplane reset */
5339 OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5340
5341 pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5342
5343 /* Locate an appropriately-aligned portion of hdrbuf */
5344 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5345
5346 /* Set the poll and/or interrupt flags */
5347 bus->intr = (bool) dhd_intr;
5348 bus->poll = (bool) dhd_poll;
5349 if (bus->poll)
5350 bus->pollrate = 1;
5351
5352 return true;
5353
5354 fail:
5355 return false;
5356 }
5357
5358 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh)
5359 {
5360 DHD_TRACE(("%s: Enter\n", __func__));
5361
5362 if (bus->dhd->maxctl) {
5363 bus->rxblen =
5364 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5365 ALIGNMENT) + DHD_SDALIGN;
5366 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5367 if (!(bus->rxbuf)) {
5368 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5369 __func__, bus->rxblen));
5370 goto fail;
5371 }
5372 }
5373
5374 /* Allocate buffer to receive glomed packet */
5375 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5376 if (!(bus->databuf)) {
5377 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5378 __func__, MAX_DATA_BUF));
5379 /* release rxbuf which was already located as above */
5380 if (!bus->rxblen)
5381 kfree(bus->rxbuf);
5382 goto fail;
5383 }
5384
5385 /* Align the buffer */
5386 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5387 bus->dataptr =
5388 bus->databuf + (DHD_SDALIGN -
5389 ((unsigned long)bus->databuf % DHD_SDALIGN));
5390 else
5391 bus->dataptr = bus->databuf;
5392
5393 return true;
5394
5395 fail:
5396 return false;
5397 }
5398
5399 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh)
5400 {
5401 s32 fnum;
5402
5403 DHD_TRACE(("%s: Enter\n", __func__));
5404
5405 #ifdef SDTEST
5406 dhdsdio_pktgen_init(bus);
5407 #endif /* SDTEST */
5408
5409 /* Disable F2 to clear any intermediate frame state on the dongle */
5410 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1,
5411 NULL);
5412
5413 bus->dhd->busstate = DHD_BUS_DOWN;
5414 bus->sleeping = false;
5415 bus->rxflow = false;
5416 bus->prev_rxlim_hit = 0;
5417
5418 /* Done with backplane-dependent accesses, can drop clock... */
5419 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5420
5421 /* ...and initialize clock/power states */
5422 bus->clkstate = CLK_SDONLY;
5423 bus->idletime = (s32) dhd_idletime;
5424 bus->idleclock = DHD_IDLE_ACTIVE;
5425
5426 /* Query the SD clock speed */
5427 if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
5428 &bus->sd_divisor, sizeof(s32),
5429 false) != 0) {
5430 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_divisor"));
5431 bus->sd_divisor = -1;
5432 } else {
5433 DHD_INFO(("%s: Initial value for %s is %d\n",
5434 __func__, "sd_divisor", bus->sd_divisor));
5435 }
5436
5437 /* Query the SD bus mode */
5438 if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
5439 &bus->sd_mode, sizeof(s32), false) != 0) {
5440 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_mode"));
5441 bus->sd_mode = -1;
5442 } else {
5443 DHD_INFO(("%s: Initial value for %s is %d\n",
5444 __func__, "sd_mode", bus->sd_mode));
5445 }
5446
5447 /* Query the F2 block size, set roundup accordingly */
5448 fnum = 2;
5449 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5450 &bus->blocksize, sizeof(s32), false) != 0) {
5451 bus->blocksize = 0;
5452 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5453 } else {
5454 DHD_INFO(("%s: Initial value for %s is %d\n",
5455 __func__, "sd_blocksize", bus->blocksize));
5456 }
5457 bus->roundup = min(max_roundup, bus->blocksize);
5458
5459 /* Query if bus module supports packet chaining,
5460 default to use if supported */
5461 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5462 &bus->sd_rxchain, sizeof(s32),
5463 false) != 0) {
5464 bus->sd_rxchain = false;
5465 } else {
5466 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5467 __func__,
5468 (bus->sd_rxchain ? "supports" : "does not support")));
5469 }
5470 bus->use_rxchain = (bool) bus->sd_rxchain;
5471
5472 return true;
5473 }
5474
5475 bool
5476 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5477 {
5478 bool ret;
5479 bus->fw_path = fw_path;
5480 bus->nv_path = nv_path;
5481
5482 ret = dhdsdio_download_firmware(bus, bus->sdh);
5483
5484 return ret;
5485 }
5486
5487 static bool
5488 dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh)
5489 {
5490 bool ret;
5491
5492 /* Download the firmware */
5493 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5494
5495 ret = _dhdsdio_download_firmware(bus) == 0;
5496
5497 dhdsdio_clkctl(bus, CLK_SDONLY, false);
5498
5499 return ret;
5500 }
5501
5502 /* Detach and free everything */
5503 static void dhdsdio_release(dhd_bus_t *bus)
5504 {
5505 DHD_TRACE(("%s: Enter\n", __func__));
5506
5507 if (bus) {
5508 /* De-register interrupt handler */
5509 bcmsdh_intr_disable(bus->sdh);
5510 bcmsdh_intr_dereg(bus->sdh);
5511
5512 if (bus->dhd) {
5513
5514 dhdsdio_release_dongle(bus);
5515
5516 dhd_detach(bus->dhd);
5517 bus->dhd = NULL;
5518 }
5519
5520 dhdsdio_release_malloc(bus);
5521
5522 kfree(bus);
5523 }
5524
5525 DHD_TRACE(("%s: Disconnected\n", __func__));
5526 }
5527
5528 static void dhdsdio_release_malloc(dhd_bus_t *bus)
5529 {
5530 DHD_TRACE(("%s: Enter\n", __func__));
5531
5532 if (bus->dhd && bus->dhd->dongle_reset)
5533 return;
5534
5535 if (bus->rxbuf) {
5536 kfree(bus->rxbuf);
5537 bus->rxctl = bus->rxbuf = NULL;
5538 bus->rxlen = 0;
5539 }
5540
5541 kfree(bus->databuf);
5542 bus->databuf = NULL;
5543 }
5544
5545 static void dhdsdio_release_dongle(dhd_bus_t *bus)
5546 {
5547 DHD_TRACE(("%s: Enter\n", __func__));
5548
5549 if (bus->dhd && bus->dhd->dongle_reset)
5550 return;
5551
5552 if (bus->sih) {
5553 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5554 #if !defined(BCMLXSDMMC)
5555 si_watchdog(bus->sih, 4);
5556 #endif /* !defined(BCMLXSDMMC) */
5557 dhdsdio_clkctl(bus, CLK_NONE, false);
5558 si_detach(bus->sih);
5559 if (bus->vars && bus->varsz)
5560 kfree(bus->vars);
5561 bus->vars = NULL;
5562 }
5563
5564 DHD_TRACE(("%s: Disconnected\n", __func__));
5565 }
5566
5567 static void dhdsdio_disconnect(void *ptr)
5568 {
5569 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5570
5571 DHD_TRACE(("%s: Enter\n", __func__));
5572
5573 if (bus) {
5574 ASSERT(bus->dhd);
5575 dhdsdio_release(bus);
5576 }
5577
5578 DHD_TRACE(("%s: Disconnected\n", __func__));
5579 }
5580
5581 /* Register/Unregister functions are called by the main DHD entry
5582 * point (e.g. module insertion) to link with the bus driver, in
5583 * order to look for or await the device.
5584 */
5585
5586 static bcmsdh_driver_t dhd_sdio = {
5587 dhdsdio_probe,
5588 dhdsdio_disconnect
5589 };
5590
5591 int dhd_bus_register(void)
5592 {
5593 DHD_TRACE(("%s: Enter\n", __func__));
5594
5595 return bcmsdh_register(&dhd_sdio);
5596 }
5597
5598 void dhd_bus_unregister(void)
5599 {
5600 DHD_TRACE(("%s: Enter\n", __func__));
5601
5602 bcmsdh_unregister();
5603 }
5604
5605 #ifdef BCMEMBEDIMAGE
5606 static int dhdsdio_download_code_array(struct dhd_bus *bus)
5607 {
5608 int bcmerror = -1;
5609 int offset = 0;
5610
5611 DHD_INFO(("%s: download embedded firmware...\n", __func__));
5612
5613 /* Download image */
5614 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5615 bcmerror =
5616 dhdsdio_membytes(bus, true, offset, dlarray + offset,
5617 MEMBLOCK);
5618 if (bcmerror) {
5619 DHD_ERROR(("%s: error %d on writing %d membytes at "
5620 "0x%08x\n",
5621 __func__, bcmerror, MEMBLOCK, offset));
5622 goto err;
5623 }
5624
5625 offset += MEMBLOCK;
5626 }
5627
5628 if (offset < sizeof(dlarray)) {
5629 bcmerror = dhdsdio_membytes(bus, true, offset,
5630 dlarray + offset,
5631 sizeof(dlarray) - offset);
5632 if (bcmerror) {
5633 DHD_ERROR(("%s: error %d on writing %d membytes at "
5634 "0x%08x\n", __func__, bcmerror,
5635 sizeof(dlarray) - offset, offset));
5636 goto err;
5637 }
5638 }
5639 #ifdef DHD_DEBUG
5640 /* Upload and compare the downloaded code */
5641 {
5642 unsigned char *ularray;
5643
5644 ularray = kmalloc(bus->ramsize, GFP_ATOMIC);
5645 if (!ularray) {
5646 bcmerror = BCME_NOMEM;
5647 goto err;
5648 }
5649 /* Upload image to verify downloaded contents. */
5650 offset = 0;
5651 memset(ularray, 0xaa, bus->ramsize);
5652 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5653 bcmerror =
5654 dhdsdio_membytes(bus, false, offset,
5655 ularray + offset, MEMBLOCK);
5656 if (bcmerror) {
5657 DHD_ERROR(("%s: error %d on reading %d membytes"
5658 " at 0x%08x\n",
5659 __func__, bcmerror, MEMBLOCK, offset));
5660 goto free;
5661 }
5662
5663 offset += MEMBLOCK;
5664 }
5665
5666 if (offset < sizeof(dlarray)) {
5667 bcmerror = dhdsdio_membytes(bus, false, offset,
5668 ularray + offset,
5669 sizeof(dlarray) - offset);
5670 if (bcmerror) {
5671 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5672 __func__, bcmerror,
5673 sizeof(dlarray) - offset, offset));
5674 goto free;
5675 }
5676 }
5677
5678 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
5679 DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5680 __func__));
5681 ASSERT(0);
5682 goto free;
5683 } else
5684 DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5685 __func__));
5686 free:
5687 kfree(ularray);
5688 }
5689 #endif /* DHD_DEBUG */
5690
5691 err:
5692 return bcmerror;
5693 }
5694 #endif /* BCMEMBEDIMAGE */
5695
5696 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5697 {
5698 int bcmerror = -1;
5699 int offset = 0;
5700 uint len;
5701 void *image = NULL;
5702 u8 *memblock = NULL, *memptr;
5703
5704 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5705
5706 image = dhd_os_open_image(fw_path);
5707 if (image == NULL)
5708 goto err;
5709
5710 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5711 if (memblock == NULL) {
5712 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5713 __func__, MEMBLOCK));
5714 goto err;
5715 }
5716 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5717 memptr +=
5718 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5719
5720 /* Download image */
5721 while ((len =
5722 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5723 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5724 if (bcmerror) {
5725 DHD_ERROR(("%s: error %d on writing %d membytes at "
5726 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5727 goto err;
5728 }
5729
5730 offset += MEMBLOCK;
5731 }
5732
5733 err:
5734 kfree(memblock);
5735
5736 if (image)
5737 dhd_os_close_image(image);
5738
5739 return bcmerror;
5740 }
5741
5742 /*
5743 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5744 * and ending in a NUL.
5745 * Removes carriage returns, empty lines, comment lines, and converts
5746 * newlines to NULs.
5747 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5748 * by two NULs.
5749 */
5750
5751 static uint process_nvram_vars(char *varbuf, uint len)
5752 {
5753 char *dp;
5754 bool findNewline;
5755 int column;
5756 uint buf_len, n;
5757
5758 dp = varbuf;
5759
5760 findNewline = false;
5761 column = 0;
5762
5763 for (n = 0; n < len; n++) {
5764 if (varbuf[n] == 0)
5765 break;
5766 if (varbuf[n] == '\r')
5767 continue;
5768 if (findNewline && varbuf[n] != '\n')
5769 continue;
5770 findNewline = false;
5771 if (varbuf[n] == '#') {
5772 findNewline = true;
5773 continue;
5774 }
5775 if (varbuf[n] == '\n') {
5776 if (column == 0)
5777 continue;
5778 *dp++ = 0;
5779 column = 0;
5780 continue;
5781 }
5782 *dp++ = varbuf[n];
5783 column++;
5784 }
5785 buf_len = dp - varbuf;
5786
5787 while (dp < varbuf + n)
5788 *dp++ = 0;
5789
5790 return buf_len;
5791 }
5792
5793 /*
5794 EXAMPLE: nvram_array
5795 nvram_arry format:
5796 name=value
5797 Use carriage return at the end of each assignment,
5798 and an empty string with
5799 carriage return at the end of array.
5800
5801 For example:
5802 unsigned char nvram_array[] = {"name1=value1\n",
5803 "name2=value2\n", "\n"};
5804 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5805
5806 Search "EXAMPLE: nvram_array" to see how the array is activated.
5807 */
5808
5809 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5810 {
5811 bus->nvram_params = nvram_params;
5812 }
5813
5814 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5815 {
5816 int bcmerror = -1;
5817 uint len;
5818 void *image = NULL;
5819 char *memblock = NULL;
5820 char *bufp;
5821 char *nv_path;
5822 bool nvram_file_exists;
5823
5824 nv_path = bus->nv_path;
5825
5826 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5827 if (!nvram_file_exists && (bus->nvram_params == NULL))
5828 return 0;
5829
5830 if (nvram_file_exists) {
5831 image = dhd_os_open_image(nv_path);
5832 if (image == NULL)
5833 goto err;
5834 }
5835
5836 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5837 if (memblock == NULL) {
5838 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5839 __func__, MEMBLOCK));
5840 goto err;
5841 }
5842
5843 /* Download variables */
5844 if (nvram_file_exists) {
5845 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5846 } else {
5847 len = strlen(bus->nvram_params);
5848 ASSERT(len <= MEMBLOCK);
5849 if (len > MEMBLOCK)
5850 len = MEMBLOCK;
5851 memcpy(memblock, bus->nvram_params, len);
5852 }
5853
5854 if (len > 0 && len < MEMBLOCK) {
5855 bufp = (char *)memblock;
5856 bufp[len] = 0;
5857 len = process_nvram_vars(bufp, len);
5858 bufp += len;
5859 *bufp++ = 0;
5860 if (len)
5861 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5862 if (bcmerror) {
5863 DHD_ERROR(("%s: error downloading vars: %d\n",
5864 __func__, bcmerror));
5865 }
5866 } else {
5867 DHD_ERROR(("%s: error reading nvram file: %d\n",
5868 __func__, len));
5869 bcmerror = BCME_SDIO_ERROR;
5870 }
5871
5872 err:
5873 kfree(memblock);
5874
5875 if (image)
5876 dhd_os_close_image(image);
5877
5878 return bcmerror;
5879 }
5880
5881 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5882 {
5883 int bcmerror = -1;
5884
5885 bool embed = false; /* download embedded firmware */
5886 bool dlok = false; /* download firmware succeeded */
5887
5888 /* Out immediately if no image to download */
5889 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
5890 #ifdef BCMEMBEDIMAGE
5891 embed = true;
5892 #else
5893 return bcmerror;
5894 #endif
5895 }
5896
5897 /* Keep arm in reset */
5898 if (dhdsdio_download_state(bus, true)) {
5899 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5900 goto err;
5901 }
5902
5903 /* External image takes precedence if specified */
5904 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5905 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5906 DHD_ERROR(("%s: dongle image file download failed\n",
5907 __func__));
5908 #ifdef BCMEMBEDIMAGE
5909 embed = true;
5910 #else
5911 goto err;
5912 #endif
5913 } else {
5914 embed = false;
5915 dlok = true;
5916 }
5917 }
5918 #ifdef BCMEMBEDIMAGE
5919 if (embed) {
5920 if (dhdsdio_download_code_array(bus)) {
5921 DHD_ERROR(("%s: dongle image array download failed\n",
5922 __func__));
5923 goto err;
5924 } else {
5925 dlok = true;
5926 }
5927 }
5928 #endif
5929 if (!dlok) {
5930 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5931 goto err;
5932 }
5933
5934 /* EXAMPLE: nvram_array */
5935 /* If a valid nvram_arry is specified as above, it can be passed
5936 down to dongle */
5937 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5938
5939 /* External nvram takes precedence if specified */
5940 if (dhdsdio_download_nvram(bus)) {
5941 DHD_ERROR(("%s: dongle nvram file download failed\n",
5942 __func__));
5943 }
5944
5945 /* Take arm out of reset */
5946 if (dhdsdio_download_state(bus, false)) {
5947 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5948 __func__));
5949 goto err;
5950 }
5951
5952 bcmerror = 0;
5953
5954 err:
5955 return bcmerror;
5956 }
5957
5958 static int
5959 dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5960 u8 *buf, uint nbytes, struct sk_buff *pkt,
5961 bcmsdh_cmplt_fn_t complete, void *handle)
5962 {
5963 int status;
5964
5965 /* 4329: GSPI check */
5966 status =
5967 bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt,
5968 complete, handle);
5969 return status;
5970 }
5971
5972 static int
5973 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5974 u8 *buf, uint nbytes, struct sk_buff *pkt,
5975 bcmsdh_cmplt_fn_t complete, void *handle)
5976 {
5977 return bcmsdh_send_buf
5978 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5979 handle);
5980 }
5981
5982 uint dhd_bus_chip(struct dhd_bus *bus)
5983 {
5984 ASSERT(bus->sih != NULL);
5985 return bus->sih->chip;
5986 }
5987
5988 void *dhd_bus_pub(struct dhd_bus *bus)
5989 {
5990 return bus->dhd;
5991 }
5992
5993 void *dhd_bus_txq(struct dhd_bus *bus)
5994 {
5995 return &bus->txq;
5996 }
5997
5998 uint dhd_bus_hdrlen(struct dhd_bus *bus)
5999 {
6000 return SDPCM_HDRLEN;
6001 }
6002
6003 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
6004 {
6005 int bcmerror = 0;
6006 dhd_bus_t *bus;
6007
6008 bus = dhdp->bus;
6009
6010 if (flag == true) {
6011 if (!bus->dhd->dongle_reset) {
6012 /* Expect app to have torn down any
6013 connection before calling */
6014 /* Stop the bus, disable F2 */
6015 dhd_bus_stop(bus, false);
6016
6017 /* Clean tx/rx buffer pointers,
6018 detach from the dongle */
6019 dhdsdio_release_dongle(bus);
6020
6021 bus->dhd->dongle_reset = true;
6022 bus->dhd->up = false;
6023
6024 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
6025 /* App can now remove power from device */
6026 } else
6027 bcmerror = BCME_SDIO_ERROR;
6028 } else {
6029 /* App must have restored power to device before calling */
6030
6031 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
6032
6033 if (bus->dhd->dongle_reset) {
6034 /* Turn on WLAN */
6035 /* Reset SD client */
6036 bcmsdh_reset(bus->sdh);
6037
6038 /* Attempt to re-attach & download */
6039 if (dhdsdio_probe_attach(bus, bus->sdh,
6040 (u32 *) SI_ENUM_BASE,
6041 bus->cl_devid)) {
6042 /* Attempt to download binary to the dongle */
6043 if (dhdsdio_probe_init
6044 (bus, bus->sdh)
6045 && dhdsdio_download_firmware(bus,
6046 bus->sdh)) {
6047
6048 /* Re-init bus, enable F2 transfer */
6049 dhd_bus_init((dhd_pub_t *) bus->dhd,
6050 false);
6051
6052 #if defined(OOB_INTR_ONLY)
6053 dhd_enable_oob_intr(bus, true);
6054 #endif /* defined(OOB_INTR_ONLY) */
6055
6056 bus->dhd->dongle_reset = false;
6057 bus->dhd->up = true;
6058
6059 DHD_TRACE(("%s: WLAN ON DONE\n",
6060 __func__));
6061 } else
6062 bcmerror = BCME_SDIO_ERROR;
6063 } else
6064 bcmerror = BCME_SDIO_ERROR;
6065 } else {
6066 bcmerror = BCME_NOTDOWN;
6067 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6068 "is on\n", __func__));
6069 bcmerror = BCME_SDIO_ERROR;
6070 }
6071 }
6072 return bcmerror;
6073 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree