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xen block: remove driver_data direct access of struct device
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / parport / parport_pc.c
blob151bf5bc8afe968d196702bad526c38b2797a4f8
1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
2 *
3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell
7 * Andrea Arcangeli
8 *
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10 *
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17 */
18
19 /* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
22 * layout is:
23 *
24 * base+0 data
25 * base+1 status
26 * base+2 control
27 *
28 * In addition, there are some optional registers:
29 *
30 * base+3 EPP address
31 * base+4 EPP data
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
35 *
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
39 * accommodate this.
40 *
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
43 */
44
45 #include <linux/module.h>
46 #include <linux/init.h>
47 #include <linux/sched.h>
48 #include <linux/delay.h>
49 #include <linux/errno.h>
50 #include <linux/interrupt.h>
51 #include <linux/ioport.h>
52 #include <linux/kernel.h>
53 #include <linux/slab.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/pci.h>
56 #include <linux/pnp.h>
57 #include <linux/platform_device.h>
58 #include <linux/sysctl.h>
59 #include <linux/io.h>
60 #include <linux/uaccess.h>
61
62 #include <asm/dma.h>
63
64 #include <linux/parport.h>
65 #include <linux/parport_pc.h>
66 #include <linux/via.h>
67 #include <asm/parport.h>
68
69 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
70
71 #ifdef CONFIG_ISA_DMA_API
72 #define HAS_DMA
73 #endif
74
75 /* ECR modes */
76 #define ECR_SPP 00
77 #define ECR_PS2 01
78 #define ECR_PPF 02
79 #define ECR_ECP 03
80 #define ECR_EPP 04
81 #define ECR_VND 05
82 #define ECR_TST 06
83 #define ECR_CNF 07
84 #define ECR_MODE_MASK 0xe0
85 #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
86
87 #undef DEBUG
88
89 #ifdef DEBUG
90 #define DPRINTK printk
91 #else
92 #define DPRINTK(stuff...)
93 #endif
94
95
96 #define NR_SUPERIOS 3
97 static struct superio_struct { /* For Super-IO chips autodetection */
98 int io;
99 int irq;
100 int dma;
101 } superios[NR_SUPERIOS] = { {0,},};
102
103 static int user_specified;
104 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
105 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
106 static int verbose_probing;
107 #endif
108 static int pci_registered_parport;
109 static int pnp_registered_parport;
110
111 /* frob_control, but for ECR */
112 static void frob_econtrol(struct parport *pb, unsigned char m,
113 unsigned char v)
114 {
115 unsigned char ectr = 0;
116
117 if (m != 0xff)
118 ectr = inb(ECONTROL(pb));
119
120 DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
121 m, v, ectr, (ectr & ~m) ^ v);
122
123 outb((ectr & ~m) ^ v, ECONTROL(pb));
124 }
125
126 static inline void frob_set_mode(struct parport *p, int mode)
127 {
128 frob_econtrol(p, ECR_MODE_MASK, mode << 5);
129 }
130
131 #ifdef CONFIG_PARPORT_PC_FIFO
132 /* Safely change the mode bits in the ECR
133 Returns:
134 0 : Success
135 -EBUSY: Could not drain FIFO in some finite amount of time,
136 mode not changed!
137 */
138 static int change_mode(struct parport *p, int m)
139 {
140 const struct parport_pc_private *priv = p->physport->private_data;
141 unsigned char oecr;
142 int mode;
143
144 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m);
145
146 if (!priv->ecr) {
147 printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
148 return 0;
149 }
150
151 /* Bits <7:5> contain the mode. */
152 oecr = inb(ECONTROL(p));
153 mode = (oecr >> 5) & 0x7;
154 if (mode == m)
155 return 0;
156
157 if (mode >= 2 && !(priv->ctr & 0x20)) {
158 /* This mode resets the FIFO, so we may
159 * have to wait for it to drain first. */
160 unsigned long expire = jiffies + p->physport->cad->timeout;
161 int counter;
162 switch (mode) {
163 case ECR_PPF: /* Parallel Port FIFO mode */
164 case ECR_ECP: /* ECP Parallel Port mode */
165 /* Busy wait for 200us */
166 for (counter = 0; counter < 40; counter++) {
167 if (inb(ECONTROL(p)) & 0x01)
168 break;
169 if (signal_pending(current))
170 break;
171 udelay(5);
172 }
173
174 /* Poll slowly. */
175 while (!(inb(ECONTROL(p)) & 0x01)) {
176 if (time_after_eq(jiffies, expire))
177 /* The FIFO is stuck. */
178 return -EBUSY;
179 schedule_timeout_interruptible(
180 msecs_to_jiffies(10));
181 if (signal_pending(current))
182 break;
183 }
184 }
185 }
186
187 if (mode >= 2 && m >= 2) {
188 /* We have to go through mode 001 */
189 oecr &= ~(7 << 5);
190 oecr |= ECR_PS2 << 5;
191 ECR_WRITE(p, oecr);
192 }
193
194 /* Set the mode. */
195 oecr &= ~(7 << 5);
196 oecr |= m << 5;
197 ECR_WRITE(p, oecr);
198 return 0;
199 }
200
201 #ifdef CONFIG_PARPORT_1284
202 /* Find FIFO lossage; FIFO is reset */
203 #if 0
204 static int get_fifo_residue(struct parport *p)
205 {
206 int residue;
207 int cnfga;
208 const struct parport_pc_private *priv = p->physport->private_data;
209
210 /* Adjust for the contents of the FIFO. */
211 for (residue = priv->fifo_depth; ; residue--) {
212 if (inb(ECONTROL(p)) & 0x2)
213 /* Full up. */
214 break;
215
216 outb(0, FIFO(p));
217 }
218
219 printk(KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
220 residue);
221
222 /* Reset the FIFO. */
223 frob_set_mode(p, ECR_PS2);
224
225 /* Now change to config mode and clean up. FIXME */
226 frob_set_mode(p, ECR_CNF);
227 cnfga = inb(CONFIGA(p));
228 printk(KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
229
230 if (!(cnfga & (1<<2))) {
231 printk(KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
232 residue++;
233 }
234
235 /* Don't care about partial PWords until support is added for
236 * PWord != 1 byte. */
237
238 /* Back to PS2 mode. */
239 frob_set_mode(p, ECR_PS2);
240
241 DPRINTK(KERN_DEBUG
242 "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n",
243 inb(ECONTROL(p)));
244 return residue;
245 }
246 #endif /* 0 */
247 #endif /* IEEE 1284 support */
248 #endif /* FIFO support */
249
250 /*
251 * Clear TIMEOUT BIT in EPP MODE
252 *
253 * This is also used in SPP detection.
254 */
255 static int clear_epp_timeout(struct parport *pb)
256 {
257 unsigned char r;
258
259 if (!(parport_pc_read_status(pb) & 0x01))
260 return 1;
261
262 /* To clear timeout some chips require double read */
263 parport_pc_read_status(pb);
264 r = parport_pc_read_status(pb);
265 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */
266 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
267 r = parport_pc_read_status(pb);
268
269 return !(r & 0x01);
270 }
271
272 /*
273 * Access functions.
274 *
275 * Most of these aren't static because they may be used by the
276 * parport_xxx_yyy macros. extern __inline__ versions of several
277 * of these are in parport_pc.h.
278 */
279
280 static void parport_pc_init_state(struct pardevice *dev,
281 struct parport_state *s)
282 {
283 s->u.pc.ctr = 0xc;
284 if (dev->irq_func &&
285 dev->port->irq != PARPORT_IRQ_NONE)
286 /* Set ackIntEn */
287 s->u.pc.ctr |= 0x10;
288
289 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
290 * D.Gruszka VScom */
291 }
292
293 static void parport_pc_save_state(struct parport *p, struct parport_state *s)
294 {
295 const struct parport_pc_private *priv = p->physport->private_data;
296 s->u.pc.ctr = priv->ctr;
297 if (priv->ecr)
298 s->u.pc.ecr = inb(ECONTROL(p));
299 }
300
301 static void parport_pc_restore_state(struct parport *p,
302 struct parport_state *s)
303 {
304 struct parport_pc_private *priv = p->physport->private_data;
305 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
306 outb(c, CONTROL(p));
307 priv->ctr = c;
308 if (priv->ecr)
309 ECR_WRITE(p, s->u.pc.ecr);
310 }
311
312 #ifdef CONFIG_PARPORT_1284
313 static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
314 size_t length, int flags)
315 {
316 size_t got = 0;
317
318 if (flags & PARPORT_W91284PIC) {
319 unsigned char status;
320 size_t left = length;
321
322 /* use knowledge about data lines..:
323 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
324 * pError is 1 if there are 16 bytes in the Warp's FIFO
325 */
326 status = inb(STATUS(port));
327
328 while (!(status & 0x08) && got < length) {
329 if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
330 /* can grab 16 bytes from warp fifo */
331 if (!((long)buf & 0x03))
332 insl(EPPDATA(port), buf, 4);
333 else
334 insb(EPPDATA(port), buf, 16);
335 buf += 16;
336 got += 16;
337 left -= 16;
338 } else {
339 /* grab single byte from the warp fifo */
340 *((char *)buf) = inb(EPPDATA(port));
341 buf++;
342 got++;
343 left--;
344 }
345 status = inb(STATUS(port));
346 if (status & 0x01) {
347 /* EPP timeout should never occur... */
348 printk(KERN_DEBUG
349 "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name);
350 clear_epp_timeout(port);
351 }
352 }
353 return got;
354 }
355 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
356 if (!(((long)buf | length) & 0x03))
357 insl(EPPDATA(port), buf, (length >> 2));
358 else
359 insb(EPPDATA(port), buf, length);
360 if (inb(STATUS(port)) & 0x01) {
361 clear_epp_timeout(port);
362 return -EIO;
363 }
364 return length;
365 }
366 for (; got < length; got++) {
367 *((char *)buf) = inb(EPPDATA(port));
368 buf++;
369 if (inb(STATUS(port)) & 0x01) {
370 /* EPP timeout */
371 clear_epp_timeout(port);
372 break;
373 }
374 }
375
376 return got;
377 }
378
379 static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
380 size_t length, int flags)
381 {
382 size_t written = 0;
383
384 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
385 if (!(((long)buf | length) & 0x03))
386 outsl(EPPDATA(port), buf, (length >> 2));
387 else
388 outsb(EPPDATA(port), buf, length);
389 if (inb(STATUS(port)) & 0x01) {
390 clear_epp_timeout(port);
391 return -EIO;
392 }
393 return length;
394 }
395 for (; written < length; written++) {
396 outb(*((char *)buf), EPPDATA(port));
397 buf++;
398 if (inb(STATUS(port)) & 0x01) {
399 clear_epp_timeout(port);
400 break;
401 }
402 }
403
404 return written;
405 }
406
407 static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
408 size_t length, int flags)
409 {
410 size_t got = 0;
411
412 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
413 insb(EPPADDR(port), buf, length);
414 if (inb(STATUS(port)) & 0x01) {
415 clear_epp_timeout(port);
416 return -EIO;
417 }
418 return length;
419 }
420 for (; got < length; got++) {
421 *((char *)buf) = inb(EPPADDR(port));
422 buf++;
423 if (inb(STATUS(port)) & 0x01) {
424 clear_epp_timeout(port);
425 break;
426 }
427 }
428
429 return got;
430 }
431
432 static size_t parport_pc_epp_write_addr(struct parport *port,
433 const void *buf, size_t length,
434 int flags)
435 {
436 size_t written = 0;
437
438 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
439 outsb(EPPADDR(port), buf, length);
440 if (inb(STATUS(port)) & 0x01) {
441 clear_epp_timeout(port);
442 return -EIO;
443 }
444 return length;
445 }
446 for (; written < length; written++) {
447 outb(*((char *)buf), EPPADDR(port));
448 buf++;
449 if (inb(STATUS(port)) & 0x01) {
450 clear_epp_timeout(port);
451 break;
452 }
453 }
454
455 return written;
456 }
457
458 static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
459 size_t length, int flags)
460 {
461 size_t got;
462
463 frob_set_mode(port, ECR_EPP);
464 parport_pc_data_reverse(port);
465 parport_pc_write_control(port, 0x4);
466 got = parport_pc_epp_read_data(port, buf, length, flags);
467 frob_set_mode(port, ECR_PS2);
468
469 return got;
470 }
471
472 static size_t parport_pc_ecpepp_write_data(struct parport *port,
473 const void *buf, size_t length,
474 int flags)
475 {
476 size_t written;
477
478 frob_set_mode(port, ECR_EPP);
479 parport_pc_write_control(port, 0x4);
480 parport_pc_data_forward(port);
481 written = parport_pc_epp_write_data(port, buf, length, flags);
482 frob_set_mode(port, ECR_PS2);
483
484 return written;
485 }
486
487 static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
488 size_t length, int flags)
489 {
490 size_t got;
491
492 frob_set_mode(port, ECR_EPP);
493 parport_pc_data_reverse(port);
494 parport_pc_write_control(port, 0x4);
495 got = parport_pc_epp_read_addr(port, buf, length, flags);
496 frob_set_mode(port, ECR_PS2);
497
498 return got;
499 }
500
501 static size_t parport_pc_ecpepp_write_addr(struct parport *port,
502 const void *buf, size_t length,
503 int flags)
504 {
505 size_t written;
506
507 frob_set_mode(port, ECR_EPP);
508 parport_pc_write_control(port, 0x4);
509 parport_pc_data_forward(port);
510 written = parport_pc_epp_write_addr(port, buf, length, flags);
511 frob_set_mode(port, ECR_PS2);
512
513 return written;
514 }
515 #endif /* IEEE 1284 support */
516
517 #ifdef CONFIG_PARPORT_PC_FIFO
518 static size_t parport_pc_fifo_write_block_pio(struct parport *port,
519 const void *buf, size_t length)
520 {
521 int ret = 0;
522 const unsigned char *bufp = buf;
523 size_t left = length;
524 unsigned long expire = jiffies + port->physport->cad->timeout;
525 const int fifo = FIFO(port);
526 int poll_for = 8; /* 80 usecs */
527 const struct parport_pc_private *priv = port->physport->private_data;
528 const int fifo_depth = priv->fifo_depth;
529
530 port = port->physport;
531
532 /* We don't want to be interrupted every character. */
533 parport_pc_disable_irq(port);
534 /* set nErrIntrEn and serviceIntr */
535 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
536
537 /* Forward mode. */
538 parport_pc_data_forward(port); /* Must be in PS2 mode */
539
540 while (left) {
541 unsigned char byte;
542 unsigned char ecrval = inb(ECONTROL(port));
543 int i = 0;
544
545 if (need_resched() && time_before(jiffies, expire))
546 /* Can't yield the port. */
547 schedule();
548
549 /* Anyone else waiting for the port? */
550 if (port->waithead) {
551 printk(KERN_DEBUG "Somebody wants the port\n");
552 break;
553 }
554
555 if (ecrval & 0x02) {
556 /* FIFO is full. Wait for interrupt. */
557
558 /* Clear serviceIntr */
559 ECR_WRITE(port, ecrval & ~(1<<2));
560 false_alarm:
561 ret = parport_wait_event(port, HZ);
562 if (ret < 0)
563 break;
564 ret = 0;
565 if (!time_before(jiffies, expire)) {
566 /* Timed out. */
567 printk(KERN_DEBUG "FIFO write timed out\n");
568 break;
569 }
570 ecrval = inb(ECONTROL(port));
571 if (!(ecrval & (1<<2))) {
572 if (need_resched() &&
573 time_before(jiffies, expire))
574 schedule();
575
576 goto false_alarm;
577 }
578
579 continue;
580 }
581
582 /* Can't fail now. */
583 expire = jiffies + port->cad->timeout;
584
585 poll:
586 if (signal_pending(current))
587 break;
588
589 if (ecrval & 0x01) {
590 /* FIFO is empty. Blast it full. */
591 const int n = left < fifo_depth ? left : fifo_depth;
592 outsb(fifo, bufp, n);
593 bufp += n;
594 left -= n;
595
596 /* Adjust the poll time. */
597 if (i < (poll_for - 2))
598 poll_for--;
599 continue;
600 } else if (i++ < poll_for) {
601 udelay(10);
602 ecrval = inb(ECONTROL(port));
603 goto poll;
604 }
605
606 /* Half-full(call me an optimist) */
607 byte = *bufp++;
608 outb(byte, fifo);
609 left--;
610 }
611 dump_parport_state("leave fifo_write_block_pio", port);
612 return length - left;
613 }
614
615 #ifdef HAS_DMA
616 static size_t parport_pc_fifo_write_block_dma(struct parport *port,
617 const void *buf, size_t length)
618 {
619 int ret = 0;
620 unsigned long dmaflag;
621 size_t left = length;
622 const struct parport_pc_private *priv = port->physport->private_data;
623 struct device *dev = port->physport->dev;
624 dma_addr_t dma_addr, dma_handle;
625 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
626 unsigned long start = (unsigned long) buf;
627 unsigned long end = (unsigned long) buf + length - 1;
628
629 dump_parport_state("enter fifo_write_block_dma", port);
630 if (end < MAX_DMA_ADDRESS) {
631 /* If it would cross a 64k boundary, cap it at the end. */
632 if ((start ^ end) & ~0xffffUL)
633 maxlen = 0x10000 - (start & 0xffff);
634
635 dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
636 DMA_TO_DEVICE);
637 } else {
638 /* above 16 MB we use a bounce buffer as ISA-DMA
639 is not possible */
640 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
641 dma_addr = priv->dma_handle;
642 dma_handle = 0;
643 }
644
645 port = port->physport;
646
647 /* We don't want to be interrupted every character. */
648 parport_pc_disable_irq(port);
649 /* set nErrIntrEn and serviceIntr */
650 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
651
652 /* Forward mode. */
653 parport_pc_data_forward(port); /* Must be in PS2 mode */
654
655 while (left) {
656 unsigned long expire = jiffies + port->physport->cad->timeout;
657
658 size_t count = left;
659
660 if (count > maxlen)
661 count = maxlen;
662
663 if (!dma_handle) /* bounce buffer ! */
664 memcpy(priv->dma_buf, buf, count);
665
666 dmaflag = claim_dma_lock();
667 disable_dma(port->dma);
668 clear_dma_ff(port->dma);
669 set_dma_mode(port->dma, DMA_MODE_WRITE);
670 set_dma_addr(port->dma, dma_addr);
671 set_dma_count(port->dma, count);
672
673 /* Set DMA mode */
674 frob_econtrol(port, 1<<3, 1<<3);
675
676 /* Clear serviceIntr */
677 frob_econtrol(port, 1<<2, 0);
678
679 enable_dma(port->dma);
680 release_dma_lock(dmaflag);
681
682 /* assume DMA will be successful */
683 left -= count;
684 buf += count;
685 if (dma_handle)
686 dma_addr += count;
687
688 /* Wait for interrupt. */
689 false_alarm:
690 ret = parport_wait_event(port, HZ);
691 if (ret < 0)
692 break;
693 ret = 0;
694 if (!time_before(jiffies, expire)) {
695 /* Timed out. */
696 printk(KERN_DEBUG "DMA write timed out\n");
697 break;
698 }
699 /* Is serviceIntr set? */
700 if (!(inb(ECONTROL(port)) & (1<<2))) {
701 cond_resched();
702
703 goto false_alarm;
704 }
705
706 dmaflag = claim_dma_lock();
707 disable_dma(port->dma);
708 clear_dma_ff(port->dma);
709 count = get_dma_residue(port->dma);
710 release_dma_lock(dmaflag);
711
712 cond_resched(); /* Can't yield the port. */
713
714 /* Anyone else waiting for the port? */
715 if (port->waithead) {
716 printk(KERN_DEBUG "Somebody wants the port\n");
717 break;
718 }
719
720 /* update for possible DMA residue ! */
721 buf -= count;
722 left += count;
723 if (dma_handle)
724 dma_addr -= count;
725 }
726
727 /* Maybe got here through break, so adjust for DMA residue! */
728 dmaflag = claim_dma_lock();
729 disable_dma(port->dma);
730 clear_dma_ff(port->dma);
731 left += get_dma_residue(port->dma);
732 release_dma_lock(dmaflag);
733
734 /* Turn off DMA mode */
735 frob_econtrol(port, 1<<3, 0);
736
737 if (dma_handle)
738 dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
739
740 dump_parport_state("leave fifo_write_block_dma", port);
741 return length - left;
742 }
743 #endif
744
745 static inline size_t parport_pc_fifo_write_block(struct parport *port,
746 const void *buf, size_t length)
747 {
748 #ifdef HAS_DMA
749 if (port->dma != PARPORT_DMA_NONE)
750 return parport_pc_fifo_write_block_dma(port, buf, length);
751 #endif
752 return parport_pc_fifo_write_block_pio(port, buf, length);
753 }
754
755 /* Parallel Port FIFO mode (ECP chipsets) */
756 static size_t parport_pc_compat_write_block_pio(struct parport *port,
757 const void *buf, size_t length,
758 int flags)
759 {
760 size_t written;
761 int r;
762 unsigned long expire;
763 const struct parport_pc_private *priv = port->physport->private_data;
764
765 /* Special case: a timeout of zero means we cannot call schedule().
766 * Also if O_NONBLOCK is set then use the default implementation. */
767 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
768 return parport_ieee1284_write_compat(port, buf,
769 length, flags);
770
771 /* Set up parallel port FIFO mode.*/
772 parport_pc_data_forward(port); /* Must be in PS2 mode */
773 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
774 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
775 if (r)
776 printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
777 port->name);
778
779 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
780
781 /* Write the data to the FIFO. */
782 written = parport_pc_fifo_write_block(port, buf, length);
783
784 /* Finish up. */
785 /* For some hardware we don't want to touch the mode until
786 * the FIFO is empty, so allow 4 seconds for each position
787 * in the fifo.
788 */
789 expire = jiffies + (priv->fifo_depth * HZ * 4);
790 do {
791 /* Wait for the FIFO to empty */
792 r = change_mode(port, ECR_PS2);
793 if (r != -EBUSY)
794 break;
795 } while (time_before(jiffies, expire));
796 if (r == -EBUSY) {
797
798 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
799
800 /* Prevent further data transfer. */
801 frob_set_mode(port, ECR_TST);
802
803 /* Adjust for the contents of the FIFO. */
804 for (written -= priv->fifo_depth; ; written++) {
805 if (inb(ECONTROL(port)) & 0x2) {
806 /* Full up. */
807 break;
808 }
809 outb(0, FIFO(port));
810 }
811
812 /* Reset the FIFO and return to PS2 mode. */
813 frob_set_mode(port, ECR_PS2);
814 }
815
816 r = parport_wait_peripheral(port,
817 PARPORT_STATUS_BUSY,
818 PARPORT_STATUS_BUSY);
819 if (r)
820 printk(KERN_DEBUG
821 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
822 port->name, r);
823
824 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
825
826 return written;
827 }
828
829 /* ECP */
830 #ifdef CONFIG_PARPORT_1284
831 static size_t parport_pc_ecp_write_block_pio(struct parport *port,
832 const void *buf, size_t length,
833 int flags)
834 {
835 size_t written;
836 int r;
837 unsigned long expire;
838 const struct parport_pc_private *priv = port->physport->private_data;
839
840 /* Special case: a timeout of zero means we cannot call schedule().
841 * Also if O_NONBLOCK is set then use the default implementation. */
842 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
843 return parport_ieee1284_ecp_write_data(port, buf,
844 length, flags);
845
846 /* Switch to forward mode if necessary. */
847 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
848 /* Event 47: Set nInit high. */
849 parport_frob_control(port,
850 PARPORT_CONTROL_INIT
851 | PARPORT_CONTROL_AUTOFD,
852 PARPORT_CONTROL_INIT
853 | PARPORT_CONTROL_AUTOFD);
854
855 /* Event 49: PError goes high. */
856 r = parport_wait_peripheral(port,
857 PARPORT_STATUS_PAPEROUT,
858 PARPORT_STATUS_PAPEROUT);
859 if (r) {
860 printk(KERN_DEBUG "%s: PError timeout (%d) "
861 "in ecp_write_block_pio\n", port->name, r);
862 }
863 }
864
865 /* Set up ECP parallel port mode.*/
866 parport_pc_data_forward(port); /* Must be in PS2 mode */
867 parport_pc_frob_control(port,
868 PARPORT_CONTROL_STROBE |
869 PARPORT_CONTROL_AUTOFD,
870 0);
871 r = change_mode(port, ECR_ECP); /* ECP FIFO */
872 if (r)
873 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
874 port->name);
875 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
876
877 /* Write the data to the FIFO. */
878 written = parport_pc_fifo_write_block(port, buf, length);
879
880 /* Finish up. */
881 /* For some hardware we don't want to touch the mode until
882 * the FIFO is empty, so allow 4 seconds for each position
883 * in the fifo.
884 */
885 expire = jiffies + (priv->fifo_depth * (HZ * 4));
886 do {
887 /* Wait for the FIFO to empty */
888 r = change_mode(port, ECR_PS2);
889 if (r != -EBUSY)
890 break;
891 } while (time_before(jiffies, expire));
892 if (r == -EBUSY) {
893
894 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
895
896 /* Prevent further data transfer. */
897 frob_set_mode(port, ECR_TST);
898
899 /* Adjust for the contents of the FIFO. */
900 for (written -= priv->fifo_depth; ; written++) {
901 if (inb(ECONTROL(port)) & 0x2) {
902 /* Full up. */
903 break;
904 }
905 outb(0, FIFO(port));
906 }
907
908 /* Reset the FIFO and return to PS2 mode. */
909 frob_set_mode(port, ECR_PS2);
910
911 /* Host transfer recovery. */
912 parport_pc_data_reverse(port); /* Must be in PS2 mode */
913 udelay(5);
914 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
915 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
916 if (r)
917 printk(KERN_DEBUG "%s: PE,1 timeout (%d) "
918 "in ecp_write_block_pio\n", port->name, r);
919
920 parport_frob_control(port,
921 PARPORT_CONTROL_INIT,
922 PARPORT_CONTROL_INIT);
923 r = parport_wait_peripheral(port,
924 PARPORT_STATUS_PAPEROUT,
925 PARPORT_STATUS_PAPEROUT);
926 if (r)
927 printk(KERN_DEBUG "%s: PE,2 timeout (%d) "
928 "in ecp_write_block_pio\n", port->name, r);
929 }
930
931 r = parport_wait_peripheral(port,
932 PARPORT_STATUS_BUSY,
933 PARPORT_STATUS_BUSY);
934 if (r)
935 printk(KERN_DEBUG
936 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
937 port->name, r);
938
939 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
940
941 return written;
942 }
943
944 #if 0
945 static size_t parport_pc_ecp_read_block_pio(struct parport *port,
946 void *buf, size_t length,
947 int flags)
948 {
949 size_t left = length;
950 size_t fifofull;
951 int r;
952 const int fifo = FIFO(port);
953 const struct parport_pc_private *priv = port->physport->private_data;
954 const int fifo_depth = priv->fifo_depth;
955 char *bufp = buf;
956
957 port = port->physport;
958 DPRINTK(KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
959 dump_parport_state("enter fcn", port);
960
961 /* Special case: a timeout of zero means we cannot call schedule().
962 * Also if O_NONBLOCK is set then use the default implementation. */
963 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
964 return parport_ieee1284_ecp_read_data(port, buf,
965 length, flags);
966
967 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
968 /* If the peripheral is allowed to send RLE compressed
969 * data, it is possible for a byte to expand to 128
970 * bytes in the FIFO. */
971 fifofull = 128;
972 } else {
973 fifofull = fifo_depth;
974 }
975
976 /* If the caller wants less than a full FIFO's worth of data,
977 * go through software emulation. Otherwise we may have to throw
978 * away data. */
979 if (length < fifofull)
980 return parport_ieee1284_ecp_read_data(port, buf,
981 length, flags);
982
983 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
984 /* change to reverse-idle phase (must be in forward-idle) */
985
986 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
987 parport_frob_control(port,
988 PARPORT_CONTROL_AUTOFD
989 | PARPORT_CONTROL_STROBE,
990 PARPORT_CONTROL_AUTOFD);
991 parport_pc_data_reverse(port); /* Must be in PS2 mode */
992 udelay(5);
993 /* Event 39: Set nInit low to initiate bus reversal */
994 parport_frob_control(port,
995 PARPORT_CONTROL_INIT,
996 0);
997 /* Event 40: Wait for nAckReverse (PError) to go low */
998 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
999 if (r) {
1000 printk(KERN_DEBUG "%s: PE timeout Event 40 (%d) "
1001 "in ecp_read_block_pio\n", port->name, r);
1002 return 0;
1003 }
1004 }
1005
1006 /* Set up ECP FIFO mode.*/
1007 /* parport_pc_frob_control(port,
1008 PARPORT_CONTROL_STROBE |
1009 PARPORT_CONTROL_AUTOFD,
1010 PARPORT_CONTROL_AUTOFD); */
1011 r = change_mode(port, ECR_ECP); /* ECP FIFO */
1012 if (r)
1013 printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
1014 port->name);
1015
1016 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
1017
1018 /* the first byte must be collected manually */
1019 dump_parport_state("pre 43", port);
1020 /* Event 43: Wait for nAck to go low */
1021 r = parport_wait_peripheral(port, PARPORT_STATUS_ACK, 0);
1022 if (r) {
1023 /* timed out while reading -- no data */
1024 printk(KERN_DEBUG "PIO read timed out (initial byte)\n");
1025 goto out_no_data;
1026 }
1027 /* read byte */
1028 *bufp++ = inb(DATA(port));
1029 left--;
1030 dump_parport_state("43-44", port);
1031 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1032 parport_pc_frob_control(port,
1033 PARPORT_CONTROL_AUTOFD,
1034 0);
1035 dump_parport_state("pre 45", port);
1036 /* Event 45: Wait for nAck to go high */
1037 /* r = parport_wait_peripheral(port, PARPORT_STATUS_ACK,
1038 PARPORT_STATUS_ACK); */
1039 dump_parport_state("post 45", port);
1040 r = 0;
1041 if (r) {
1042 /* timed out while waiting for peripheral to respond to ack */
1043 printk(KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1044
1045 /* keep hold of the byte we've got already */
1046 goto out_no_data;
1047 }
1048 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1049 parport_pc_frob_control(port,
1050 PARPORT_CONTROL_AUTOFD,
1051 PARPORT_CONTROL_AUTOFD);
1052
1053
1054 dump_parport_state("rev idle", port);
1055 /* Do the transfer. */
1056 while (left > fifofull) {
1057 int ret;
1058 unsigned long expire = jiffies + port->cad->timeout;
1059 unsigned char ecrval = inb(ECONTROL(port));
1060
1061 if (need_resched() && time_before(jiffies, expire))
1062 /* Can't yield the port. */
1063 schedule();
1064
1065 /* At this point, the FIFO may already be full. In
1066 * that case ECP is already holding back the
1067 * peripheral (assuming proper design) with a delayed
1068 * handshake. Work fast to avoid a peripheral
1069 * timeout. */
1070
1071 if (ecrval & 0x01) {
1072 /* FIFO is empty. Wait for interrupt. */
1073 dump_parport_state("FIFO empty", port);
1074
1075 /* Anyone else waiting for the port? */
1076 if (port->waithead) {
1077 printk(KERN_DEBUG "Somebody wants the port\n");
1078 break;
1079 }
1080
1081 /* Clear serviceIntr */
1082 ECR_WRITE(port, ecrval & ~(1<<2));
1083 false_alarm:
1084 dump_parport_state("waiting", port);
1085 ret = parport_wait_event(port, HZ);
1086 DPRINTK(KERN_DEBUG "parport_wait_event returned %d\n",
1087 ret);
1088 if (ret < 0)
1089 break;
1090 ret = 0;
1091 if (!time_before(jiffies, expire)) {
1092 /* Timed out. */
1093 dump_parport_state("timeout", port);
1094 printk(KERN_DEBUG "PIO read timed out\n");
1095 break;
1096 }
1097 ecrval = inb(ECONTROL(port));
1098 if (!(ecrval & (1<<2))) {
1099 if (need_resched() &&
1100 time_before(jiffies, expire)) {
1101 schedule();
1102 }
1103 goto false_alarm;
1104 }
1105
1106 /* Depending on how the FIFO threshold was
1107 * set, how long interrupt service took, and
1108 * how fast the peripheral is, we might be
1109 * lucky and have a just filled FIFO. */
1110 continue;
1111 }
1112
1113 if (ecrval & 0x02) {
1114 /* FIFO is full. */
1115 dump_parport_state("FIFO full", port);
1116 insb(fifo, bufp, fifo_depth);
1117 bufp += fifo_depth;
1118 left -= fifo_depth;
1119 continue;
1120 }
1121
1122 DPRINTK(KERN_DEBUG
1123 "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1124
1125 /* FIFO not filled. We will cycle this loop for a while
1126 * and either the peripheral will fill it faster,
1127 * tripping a fast empty with insb, or we empty it. */
1128 *bufp++ = inb(fifo);
1129 left--;
1130 }
1131
1132 /* scoop up anything left in the FIFO */
1133 while (left && !(inb(ECONTROL(port) & 0x01))) {
1134 *bufp++ = inb(fifo);
1135 left--;
1136 }
1137
1138 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1139 dump_parport_state("rev idle2", port);
1140
1141 out_no_data:
1142
1143 /* Go to forward idle mode to shut the peripheral up (event 47). */
1144 parport_frob_control(port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1145
1146 /* event 49: PError goes high */
1147 r = parport_wait_peripheral(port,
1148 PARPORT_STATUS_PAPEROUT,
1149 PARPORT_STATUS_PAPEROUT);
1150 if (r) {
1151 printk(KERN_DEBUG
1152 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1153 port->name, r);
1154 }
1155
1156 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1157
1158 /* Finish up. */
1159 {
1160 int lost = get_fifo_residue(port);
1161 if (lost)
1162 /* Shouldn't happen with compliant peripherals. */
1163 printk(KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1164 port->name, lost);
1165 }
1166
1167 dump_parport_state("fwd idle", port);
1168 return length - left;
1169 }
1170 #endif /* 0 */
1171 #endif /* IEEE 1284 support */
1172 #endif /* Allowed to use FIFO/DMA */
1173
1174
1175 /*
1176 * ******************************************
1177 * INITIALISATION AND MODULE STUFF BELOW HERE
1178 * ******************************************
1179 */
1180
1181 /* GCC is not inlining extern inline function later overwriten to non-inline,
1182 so we use outlined_ variants here. */
1183 static const struct parport_operations parport_pc_ops = {
1184 .write_data = parport_pc_write_data,
1185 .read_data = parport_pc_read_data,
1186
1187 .write_control = parport_pc_write_control,
1188 .read_control = parport_pc_read_control,
1189 .frob_control = parport_pc_frob_control,
1190
1191 .read_status = parport_pc_read_status,
1192
1193 .enable_irq = parport_pc_enable_irq,
1194 .disable_irq = parport_pc_disable_irq,
1195
1196 .data_forward = parport_pc_data_forward,
1197 .data_reverse = parport_pc_data_reverse,
1198
1199 .init_state = parport_pc_init_state,
1200 .save_state = parport_pc_save_state,
1201 .restore_state = parport_pc_restore_state,
1202
1203 .epp_write_data = parport_ieee1284_epp_write_data,
1204 .epp_read_data = parport_ieee1284_epp_read_data,
1205 .epp_write_addr = parport_ieee1284_epp_write_addr,
1206 .epp_read_addr = parport_ieee1284_epp_read_addr,
1207
1208 .ecp_write_data = parport_ieee1284_ecp_write_data,
1209 .ecp_read_data = parport_ieee1284_ecp_read_data,
1210 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1211
1212 .compat_write_data = parport_ieee1284_write_compat,
1213 .nibble_read_data = parport_ieee1284_read_nibble,
1214 .byte_read_data = parport_ieee1284_read_byte,
1215
1216 .owner = THIS_MODULE,
1217 };
1218
1219 #ifdef CONFIG_PARPORT_PC_SUPERIO
1220
1221 static struct superio_struct *find_free_superio(void)
1222 {
1223 int i;
1224 for (i = 0; i < NR_SUPERIOS; i++)
1225 if (superios[i].io == 0)
1226 return &superios[i];
1227 return NULL;
1228 }
1229
1230
1231 /* Super-IO chipset detection, Winbond, SMSC */
1232 static void __devinit show_parconfig_smsc37c669(int io, int key)
1233 {
1234 int cr1, cr4, cra, cr23, cr26, cr27;
1235 struct superio_struct *s;
1236
1237 static const char *const modes[] = {
1238 "SPP and Bidirectional (PS/2)",
1239 "EPP and SPP",
1240 "ECP",
1241 "ECP and EPP" };
1242
1243 outb(key, io);
1244 outb(key, io);
1245 outb(1, io);
1246 cr1 = inb(io + 1);
1247 outb(4, io);
1248 cr4 = inb(io + 1);
1249 outb(0x0a, io);
1250 cra = inb(io + 1);
1251 outb(0x23, io);
1252 cr23 = inb(io + 1);
1253 outb(0x26, io);
1254 cr26 = inb(io + 1);
1255 outb(0x27, io);
1256 cr27 = inb(io + 1);
1257 outb(0xaa, io);
1258
1259 if (verbose_probing) {
1260 printk(KERN_INFO
1261 "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1262 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1263 cr1, cr4, cra, cr23, cr26, cr27);
1264
1265 /* The documentation calls DMA and IRQ-Lines by letters, so
1266 the board maker can/will wire them
1267 appropriately/randomly... G=reserved H=IDE-irq, */
1268 printk(KERN_INFO
1269 "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
1270 cr23 * 4,
1271 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
1272 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
1273 cra & 0x0f);
1274 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1275 (cr23 * 4 >= 0x100) ? "yes" : "no",
1276 (cr1 & 4) ? "yes" : "no");
1277 printk(KERN_INFO
1278 "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1279 (cr1 & 0x08) ? "Standard mode only (SPP)"
1280 : modes[cr4 & 0x03],
1281 (cr4 & 0x40) ? "1.7" : "1.9");
1282 }
1283
1284 /* Heuristics ! BIOS setup for this mainboard device limits
1285 the choices to standard settings, i.e. io-address and IRQ
1286 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1287 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1288 if (cr23 * 4 >= 0x100) { /* if active */
1289 s = find_free_superio();
1290 if (s == NULL)
1291 printk(KERN_INFO "Super-IO: too many chips!\n");
1292 else {
1293 int d;
1294 switch (cr23 * 4) {
1295 case 0x3bc:
1296 s->io = 0x3bc;
1297 s->irq = 7;
1298 break;
1299 case 0x378:
1300 s->io = 0x378;
1301 s->irq = 7;
1302 break;
1303 case 0x278:
1304 s->io = 0x278;
1305 s->irq = 5;
1306 }
1307 d = (cr26 & 0x0f);
1308 if (d == 1 || d == 3)
1309 s->dma = d;
1310 else
1311 s->dma = PARPORT_DMA_NONE;
1312 }
1313 }
1314 }
1315
1316
1317 static void __devinit show_parconfig_winbond(int io, int key)
1318 {
1319 int cr30, cr60, cr61, cr70, cr74, crf0;
1320 struct superio_struct *s;
1321 static const char *const modes[] = {
1322 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1323 "EPP-1.9 and SPP",
1324 "ECP",
1325 "ECP and EPP-1.9",
1326 "Standard (SPP)",
1327 "EPP-1.7 and SPP", /* 5 */
1328 "undefined!",
1329 "ECP and EPP-1.7" };
1330 static char *const irqtypes[] = {
1331 "pulsed low, high-Z",
1332 "follows nACK" };
1333
1334 /* The registers are called compatible-PnP because the
1335 register layout is modelled after ISA-PnP, the access
1336 method is just another ... */
1337 outb(key, io);
1338 outb(key, io);
1339 outb(0x07, io); /* Register 7: Select Logical Device */
1340 outb(0x01, io + 1); /* LD1 is Parallel Port */
1341 outb(0x30, io);
1342 cr30 = inb(io + 1);
1343 outb(0x60, io);
1344 cr60 = inb(io + 1);
1345 outb(0x61, io);
1346 cr61 = inb(io + 1);
1347 outb(0x70, io);
1348 cr70 = inb(io + 1);
1349 outb(0x74, io);
1350 cr74 = inb(io + 1);
1351 outb(0xf0, io);
1352 crf0 = inb(io + 1);
1353 outb(0xaa, io);
1354
1355 if (verbose_probing) {
1356 printk(KERN_INFO
1357 "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1358 cr30, cr60, cr61, cr70, cr74, crf0);
1359 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1360 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1361 if ((cr74 & 0x07) > 3)
1362 printk("dma=none\n");
1363 else
1364 printk("dma=%d\n", cr74 & 0x07);
1365 printk(KERN_INFO
1366 "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1367 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1368 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n",
1369 modes[crf0 & 0x07]);
1370 }
1371
1372 if (cr30 & 0x01) { /* the settings can be interrogated later ... */
1373 s = find_free_superio();
1374 if (s == NULL)
1375 printk(KERN_INFO "Super-IO: too many chips!\n");
1376 else {
1377 s->io = (cr60 << 8) | cr61;
1378 s->irq = cr70 & 0x0f;
1379 s->dma = (((cr74 & 0x07) > 3) ?
1380 PARPORT_DMA_NONE : (cr74 & 0x07));
1381 }
1382 }
1383 }
1384
1385 static void __devinit decode_winbond(int efer, int key, int devid,
1386 int devrev, int oldid)
1387 {
1388 const char *type = "unknown";
1389 int id, progif = 2;
1390
1391 if (devid == devrev)
1392 /* simple heuristics, we happened to read some
1393 non-winbond register */
1394 return;
1395
1396 id = (devid << 8) | devrev;
1397
1398 /* Values are from public data sheets pdf files, I can just
1399 confirm 83977TF is correct :-) */
1400 if (id == 0x9771)
1401 type = "83977F/AF";
1402 else if (id == 0x9773)
1403 type = "83977TF / SMSC 97w33x/97w34x";
1404 else if (id == 0x9774)
1405 type = "83977ATF";
1406 else if ((id & ~0x0f) == 0x5270)
1407 type = "83977CTF / SMSC 97w36x";
1408 else if ((id & ~0x0f) == 0x52f0)
1409 type = "83977EF / SMSC 97w35x";
1410 else if ((id & ~0x0f) == 0x5210)
1411 type = "83627";
1412 else if ((id & ~0x0f) == 0x6010)
1413 type = "83697HF";
1414 else if ((oldid & 0x0f) == 0x0a) {
1415 type = "83877F";
1416 progif = 1;
1417 } else if ((oldid & 0x0f) == 0x0b) {
1418 type = "83877AF";
1419 progif = 1;
1420 } else if ((oldid & 0x0f) == 0x0c) {
1421 type = "83877TF";
1422 progif = 1;
1423 } else if ((oldid & 0x0f) == 0x0d) {
1424 type = "83877ATF";
1425 progif = 1;
1426 } else
1427 progif = 0;
1428
1429 if (verbose_probing)
1430 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1431 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1432 efer, key, devid, devrev, oldid, type);
1433
1434 if (progif == 2)
1435 show_parconfig_winbond(efer, key);
1436 }
1437
1438 static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1439 {
1440 const char *type = "unknown";
1441 void (*func)(int io, int key);
1442 int id;
1443
1444 if (devid == devrev)
1445 /* simple heuristics, we happened to read some
1446 non-smsc register */
1447 return;
1448
1449 func = NULL;
1450 id = (devid << 8) | devrev;
1451
1452 if (id == 0x0302) {
1453 type = "37c669";
1454 func = show_parconfig_smsc37c669;
1455 } else if (id == 0x6582)
1456 type = "37c665IR";
1457 else if (devid == 0x65)
1458 type = "37c665GT";
1459 else if (devid == 0x66)
1460 type = "37c666GT";
1461
1462 if (verbose_probing)
1463 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1464 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1465 efer, key, devid, devrev, type);
1466
1467 if (func)
1468 func(efer, key);
1469 }
1470
1471
1472 static void __devinit winbond_check(int io, int key)
1473 {
1474 int devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1475
1476 if (!request_region(io, 3, __func__))
1477 return;
1478
1479 /* First probe without key */
1480 outb(0x20, io);
1481 x_devid = inb(io + 1);
1482 outb(0x21, io);
1483 x_devrev = inb(io + 1);
1484 outb(0x09, io);
1485 x_oldid = inb(io + 1);
1486
1487 outb(key, io);
1488 outb(key, io); /* Write Magic Sequence to EFER, extended
1489 funtion enable register */
1490 outb(0x20, io); /* Write EFIR, extended function index register */
1491 devid = inb(io + 1); /* Read EFDR, extended function data register */
1492 outb(0x21, io);
1493 devrev = inb(io + 1);
1494 outb(0x09, io);
1495 oldid = inb(io + 1);
1496 outb(0xaa, io); /* Magic Seal */
1497
1498 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1499 goto out; /* protection against false positives */
1500
1501 decode_winbond(io, key, devid, devrev, oldid);
1502 out:
1503 release_region(io, 3);
1504 }
1505
1506 static void __devinit winbond_check2(int io, int key)
1507 {
1508 int devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1509
1510 if (!request_region(io, 3, __func__))
1511 return;
1512
1513 /* First probe without the key */
1514 outb(0x20, io + 2);
1515 x_devid = inb(io + 2);
1516 outb(0x21, io + 1);
1517 x_devrev = inb(io + 2);
1518 outb(0x09, io + 1);
1519 x_oldid = inb(io + 2);
1520
1521 outb(key, io); /* Write Magic Byte to EFER, extended
1522 funtion enable register */
1523 outb(0x20, io + 2); /* Write EFIR, extended function index register */
1524 devid = inb(io + 2); /* Read EFDR, extended function data register */
1525 outb(0x21, io + 1);
1526 devrev = inb(io + 2);
1527 outb(0x09, io + 1);
1528 oldid = inb(io + 2);
1529 outb(0xaa, io); /* Magic Seal */
1530
1531 if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1532 goto out; /* protection against false positives */
1533
1534 decode_winbond(io, key, devid, devrev, oldid);
1535 out:
1536 release_region(io, 3);
1537 }
1538
1539 static void __devinit smsc_check(int io, int key)
1540 {
1541 int id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1542
1543 if (!request_region(io, 3, __func__))
1544 return;
1545
1546 /* First probe without the key */
1547 outb(0x0d, io);
1548 x_oldid = inb(io + 1);
1549 outb(0x0e, io);
1550 x_oldrev = inb(io + 1);
1551 outb(0x20, io);
1552 x_id = inb(io + 1);
1553 outb(0x21, io);
1554 x_rev = inb(io + 1);
1555
1556 outb(key, io);
1557 outb(key, io); /* Write Magic Sequence to EFER, extended
1558 funtion enable register */
1559 outb(0x0d, io); /* Write EFIR, extended function index register */
1560 oldid = inb(io + 1); /* Read EFDR, extended function data register */
1561 outb(0x0e, io);
1562 oldrev = inb(io + 1);
1563 outb(0x20, io);
1564 id = inb(io + 1);
1565 outb(0x21, io);
1566 rev = inb(io + 1);
1567 outb(0xaa, io); /* Magic Seal */
1568
1569 if (x_id == id && x_oldrev == oldrev &&
1570 x_oldid == oldid && x_rev == rev)
1571 goto out; /* protection against false positives */
1572
1573 decode_smsc(io, key, oldid, oldrev);
1574 out:
1575 release_region(io, 3);
1576 }
1577
1578
1579 static void __devinit detect_and_report_winbond(void)
1580 {
1581 if (verbose_probing)
1582 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1583 winbond_check(0x3f0, 0x87);
1584 winbond_check(0x370, 0x87);
1585 winbond_check(0x2e , 0x87);
1586 winbond_check(0x4e , 0x87);
1587 winbond_check(0x3f0, 0x86);
1588 winbond_check2(0x250, 0x88);
1589 winbond_check2(0x250, 0x89);
1590 }
1591
1592 static void __devinit detect_and_report_smsc(void)
1593 {
1594 if (verbose_probing)
1595 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1596 smsc_check(0x3f0, 0x55);
1597 smsc_check(0x370, 0x55);
1598 smsc_check(0x3f0, 0x44);
1599 smsc_check(0x370, 0x44);
1600 }
1601
1602 static void __devinit detect_and_report_it87(void)
1603 {
1604 u16 dev;
1605 u8 r;
1606 if (verbose_probing)
1607 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1608 if (!request_region(0x2e, 1, __func__))
1609 return;
1610 outb(0x87, 0x2e);
1611 outb(0x01, 0x2e);
1612 outb(0x55, 0x2e);
1613 outb(0x55, 0x2e);
1614 outb(0x20, 0x2e);
1615 dev = inb(0x2f) << 8;
1616 outb(0x21, 0x2e);
1617 dev |= inb(0x2f);
1618 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 ||
1619 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) {
1620 printk(KERN_INFO "IT%04X SuperIO detected.\n", dev);
1621 outb(0x07, 0x2E); /* Parallel Port */
1622 outb(0x03, 0x2F);
1623 outb(0xF0, 0x2E); /* BOOT 0x80 off */
1624 r = inb(0x2f);
1625 outb(0xF0, 0x2E);
1626 outb(r | 8, 0x2F);
1627 outb(0x02, 0x2E); /* Lock */
1628 outb(0x02, 0x2F);
1629 }
1630 release_region(0x2e, 1);
1631 }
1632 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1633
1634 static struct superio_struct *find_superio(struct parport *p)
1635 {
1636 int i;
1637 for (i = 0; i < NR_SUPERIOS; i++)
1638 if (superios[i].io != p->base)
1639 return &superios[i];
1640 return NULL;
1641 }
1642
1643 static int get_superio_dma(struct parport *p)
1644 {
1645 struct superio_struct *s = find_superio(p);
1646 if (s)
1647 return s->dma;
1648 return PARPORT_DMA_NONE;
1649 }
1650
1651 static int get_superio_irq(struct parport *p)
1652 {
1653 struct superio_struct *s = find_superio(p);
1654 if (s)
1655 return s->irq;
1656 return PARPORT_IRQ_NONE;
1657 }
1658
1659
1660 /* --- Mode detection ------------------------------------- */
1661
1662 /*
1663 * Checks for port existence, all ports support SPP MODE
1664 * Returns:
1665 * 0 : No parallel port at this address
1666 * PARPORT_MODE_PCSPP : SPP port detected
1667 * (if the user specified an ioport himself,
1668 * this shall always be the case!)
1669 *
1670 */
1671 static int parport_SPP_supported(struct parport *pb)
1672 {
1673 unsigned char r, w;
1674
1675 /*
1676 * first clear an eventually pending EPP timeout
1677 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1678 * that does not even respond to SPP cycles if an EPP
1679 * timeout is pending
1680 */
1681 clear_epp_timeout(pb);
1682
1683 /* Do a simple read-write test to make sure the port exists. */
1684 w = 0xc;
1685 outb(w, CONTROL(pb));
1686
1687 /* Is there a control register that we can read from? Some
1688 * ports don't allow reads, so read_control just returns a
1689 * software copy. Some ports _do_ allow reads, so bypass the
1690 * software copy here. In addition, some bits aren't
1691 * writable. */
1692 r = inb(CONTROL(pb));
1693 if ((r & 0xf) == w) {
1694 w = 0xe;
1695 outb(w, CONTROL(pb));
1696 r = inb(CONTROL(pb));
1697 outb(0xc, CONTROL(pb));
1698 if ((r & 0xf) == w)
1699 return PARPORT_MODE_PCSPP;
1700 }
1701
1702 if (user_specified)
1703 /* That didn't work, but the user thinks there's a
1704 * port here. */
1705 printk(KERN_INFO "parport 0x%lx (WARNING): CTR: "
1706 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1707
1708 /* Try the data register. The data lines aren't tri-stated at
1709 * this stage, so we expect back what we wrote. */
1710 w = 0xaa;
1711 parport_pc_write_data(pb, w);
1712 r = parport_pc_read_data(pb);
1713 if (r == w) {
1714 w = 0x55;
1715 parport_pc_write_data(pb, w);
1716 r = parport_pc_read_data(pb);
1717 if (r == w)
1718 return PARPORT_MODE_PCSPP;
1719 }
1720
1721 if (user_specified) {
1722 /* Didn't work, but the user is convinced this is the
1723 * place. */
1724 printk(KERN_INFO "parport 0x%lx (WARNING): DATA: "
1725 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1726 printk(KERN_INFO "parport 0x%lx: You gave this address, "
1727 "but there is probably no parallel port there!\n",
1728 pb->base);
1729 }
1730
1731 /* It's possible that we can't read the control register or
1732 * the data register. In that case just believe the user. */
1733 if (user_specified)
1734 return PARPORT_MODE_PCSPP;
1735
1736 return 0;
1737 }
1738
1739 /* Check for ECR
1740 *
1741 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1742 * on these cards actually accesses the CTR.
1743 *
1744 * Modern cards don't do this but reading from ECR will return 0xff
1745 * regardless of what is written here if the card does NOT support
1746 * ECP.
1747 *
1748 * We first check to see if ECR is the same as CTR. If not, the low
1749 * two bits of ECR aren't writable, so we check by writing ECR and
1750 * reading it back to see if it's what we expect.
1751 */
1752 static int parport_ECR_present(struct parport *pb)
1753 {
1754 struct parport_pc_private *priv = pb->private_data;
1755 unsigned char r = 0xc;
1756
1757 outb(r, CONTROL(pb));
1758 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1759 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1760
1761 r = inb(CONTROL(pb));
1762 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1763 goto no_reg; /* Sure that no ECR register exists */
1764 }
1765
1766 if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1767 goto no_reg;
1768
1769 ECR_WRITE(pb, 0x34);
1770 if (inb(ECONTROL(pb)) != 0x35)
1771 goto no_reg;
1772
1773 priv->ecr = 1;
1774 outb(0xc, CONTROL(pb));
1775
1776 /* Go to mode 000 */
1777 frob_set_mode(pb, ECR_SPP);
1778
1779 return 1;
1780
1781 no_reg:
1782 outb(0xc, CONTROL(pb));
1783 return 0;
1784 }
1785
1786 #ifdef CONFIG_PARPORT_1284
1787 /* Detect PS/2 support.
1788 *
1789 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1790 * allows us to read data from the data lines. In theory we would get back
1791 * 0xff but any peripheral attached to the port may drag some or all of the
1792 * lines down to zero. So if we get back anything that isn't the contents
1793 * of the data register we deem PS/2 support to be present.
1794 *
1795 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1796 * drivers, but an external peripheral with sufficiently beefy drivers of
1797 * its own can overpower them and assert its own levels onto the bus, from
1798 * where they can then be read back as normal. Ports with this property
1799 * and the right type of device attached are likely to fail the SPP test,
1800 * (as they will appear to have stuck bits) and so the fact that they might
1801 * be misdetected here is rather academic.
1802 */
1803
1804 static int parport_PS2_supported(struct parport *pb)
1805 {
1806 int ok = 0;
1807
1808 clear_epp_timeout(pb);
1809
1810 /* try to tri-state the buffer */
1811 parport_pc_data_reverse(pb);
1812
1813 parport_pc_write_data(pb, 0x55);
1814 if (parport_pc_read_data(pb) != 0x55)
1815 ok++;
1816
1817 parport_pc_write_data(pb, 0xaa);
1818 if (parport_pc_read_data(pb) != 0xaa)
1819 ok++;
1820
1821 /* cancel input mode */
1822 parport_pc_data_forward(pb);
1823
1824 if (ok) {
1825 pb->modes |= PARPORT_MODE_TRISTATE;
1826 } else {
1827 struct parport_pc_private *priv = pb->private_data;
1828 priv->ctr_writable &= ~0x20;
1829 }
1830
1831 return ok;
1832 }
1833
1834 #ifdef CONFIG_PARPORT_PC_FIFO
1835 static int parport_ECP_supported(struct parport *pb)
1836 {
1837 int i;
1838 int config, configb;
1839 int pword;
1840 struct parport_pc_private *priv = pb->private_data;
1841 /* Translate ECP intrLine to ISA irq value */
1842 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1843
1844 /* If there is no ECR, we have no hope of supporting ECP. */
1845 if (!priv->ecr)
1846 return 0;
1847
1848 /* Find out FIFO depth */
1849 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1850 ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1851 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1852 outb(0xaa, FIFO(pb));
1853
1854 /*
1855 * Using LGS chipset it uses ECR register, but
1856 * it doesn't support ECP or FIFO MODE
1857 */
1858 if (i == 1024) {
1859 ECR_WRITE(pb, ECR_SPP << 5);
1860 return 0;
1861 }
1862
1863 priv->fifo_depth = i;
1864 if (verbose_probing)
1865 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1866
1867 /* Find out writeIntrThreshold */
1868 frob_econtrol(pb, 1<<2, 1<<2);
1869 frob_econtrol(pb, 1<<2, 0);
1870 for (i = 1; i <= priv->fifo_depth; i++) {
1871 inb(FIFO(pb));
1872 udelay(50);
1873 if (inb(ECONTROL(pb)) & (1<<2))
1874 break;
1875 }
1876
1877 if (i <= priv->fifo_depth) {
1878 if (verbose_probing)
1879 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1880 pb->base, i);
1881 } else
1882 /* Number of bytes we know we can write if we get an
1883 interrupt. */
1884 i = 0;
1885
1886 priv->writeIntrThreshold = i;
1887
1888 /* Find out readIntrThreshold */
1889 frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1890 parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1891 frob_set_mode(pb, ECR_TST); /* Test FIFO */
1892 frob_econtrol(pb, 1<<2, 1<<2);
1893 frob_econtrol(pb, 1<<2, 0);
1894 for (i = 1; i <= priv->fifo_depth; i++) {
1895 outb(0xaa, FIFO(pb));
1896 if (inb(ECONTROL(pb)) & (1<<2))
1897 break;
1898 }
1899
1900 if (i <= priv->fifo_depth) {
1901 if (verbose_probing)
1902 printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1903 pb->base, i);
1904 } else
1905 /* Number of bytes we can read if we get an interrupt. */
1906 i = 0;
1907
1908 priv->readIntrThreshold = i;
1909
1910 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1911 ECR_WRITE(pb, 0xf4); /* Configuration mode */
1912 config = inb(CONFIGA(pb));
1913 pword = (config >> 4) & 0x7;
1914 switch (pword) {
1915 case 0:
1916 pword = 2;
1917 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1918 pb->base);
1919 break;
1920 case 2:
1921 pword = 4;
1922 printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1923 pb->base);
1924 break;
1925 default:
1926 printk(KERN_WARNING "0x%lx: Unknown implementation ID\n",
1927 pb->base);
1928 /* Assume 1 */
1929 case 1:
1930 pword = 1;
1931 }
1932 priv->pword = pword;
1933
1934 if (verbose_probing) {
1935 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1936 pb->base, 8 * pword);
1937
1938 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1939 config & 0x80 ? "Level" : "Pulses");
1940
1941 configb = inb(CONFIGB(pb));
1942 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1943 pb->base, config, configb);
1944 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1945 if ((configb >> 3) & 0x07)
1946 printk("%d", intrline[(configb >> 3) & 0x07]);
1947 else
1948 printk("<none or set by other means>");
1949 printk(" dma=");
1950 if ((configb & 0x03) == 0x00)
1951 printk("<none or set by other means>\n");
1952 else
1953 printk("%d\n", configb & 0x07);
1954 }
1955
1956 /* Go back to mode 000 */
1957 frob_set_mode(pb, ECR_SPP);
1958
1959 return 1;
1960 }
1961 #endif
1962
1963 static int parport_ECPPS2_supported(struct parport *pb)
1964 {
1965 const struct parport_pc_private *priv = pb->private_data;
1966 int result;
1967 unsigned char oecr;
1968
1969 if (!priv->ecr)
1970 return 0;
1971
1972 oecr = inb(ECONTROL(pb));
1973 ECR_WRITE(pb, ECR_PS2 << 5);
1974 result = parport_PS2_supported(pb);
1975 ECR_WRITE(pb, oecr);
1976 return result;
1977 }
1978
1979 /* EPP mode detection */
1980
1981 static int parport_EPP_supported(struct parport *pb)
1982 {
1983 const struct parport_pc_private *priv = pb->private_data;
1984
1985 /*
1986 * Theory:
1987 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1988 * when EPP is possible and is set high when an EPP timeout
1989 * occurs (EPP uses the HALT line to stop the CPU while it does
1990 * the byte transfer, an EPP timeout occurs if the attached
1991 * device fails to respond after 10 micro seconds).
1992 *
1993 * This bit is cleared by either reading it (National Semi)
1994 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1995 * This bit is always high in non EPP modes.
1996 */
1997
1998 /* If EPP timeout bit clear then EPP available */
1999 if (!clear_epp_timeout(pb))
2000 return 0; /* No way to clear timeout */
2001
2002 /* Check for Intel bug. */
2003 if (priv->ecr) {
2004 unsigned char i;
2005 for (i = 0x00; i < 0x80; i += 0x20) {
2006 ECR_WRITE(pb, i);
2007 if (clear_epp_timeout(pb)) {
2008 /* Phony EPP in ECP. */
2009 return 0;
2010 }
2011 }
2012 }
2013
2014 pb->modes |= PARPORT_MODE_EPP;
2015
2016 /* Set up access functions to use EPP hardware. */
2017 pb->ops->epp_read_data = parport_pc_epp_read_data;
2018 pb->ops->epp_write_data = parport_pc_epp_write_data;
2019 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
2020 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
2021
2022 return 1;
2023 }
2024
2025 static int parport_ECPEPP_supported(struct parport *pb)
2026 {
2027 struct parport_pc_private *priv = pb->private_data;
2028 int result;
2029 unsigned char oecr;
2030
2031 if (!priv->ecr)
2032 return 0;
2033
2034 oecr = inb(ECONTROL(pb));
2035 /* Search for SMC style EPP+ECP mode */
2036 ECR_WRITE(pb, 0x80);
2037 outb(0x04, CONTROL(pb));
2038 result = parport_EPP_supported(pb);
2039
2040 ECR_WRITE(pb, oecr);
2041
2042 if (result) {
2043 /* Set up access functions to use ECP+EPP hardware. */
2044 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
2045 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
2046 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
2047 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
2048 }
2049
2050 return result;
2051 }
2052
2053 #else /* No IEEE 1284 support */
2054
2055 /* Don't bother probing for modes we know we won't use. */
2056 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
2057 #ifdef CONFIG_PARPORT_PC_FIFO
2058 static int parport_ECP_supported(struct parport *pb)
2059 {
2060 return 0;
2061 }
2062 #endif
2063 static int __devinit parport_EPP_supported(struct parport *pb)
2064 {
2065 return 0;
2066 }
2067
2068 static int __devinit parport_ECPEPP_supported(struct parport *pb)
2069 {
2070 return 0;
2071 }
2072
2073 static int __devinit parport_ECPPS2_supported(struct parport *pb)
2074 {
2075 return 0;
2076 }
2077
2078 #endif /* No IEEE 1284 support */
2079
2080 /* --- IRQ detection -------------------------------------- */
2081
2082 /* Only if supports ECP mode */
2083 static int programmable_irq_support(struct parport *pb)
2084 {
2085 int irq, intrLine;
2086 unsigned char oecr = inb(ECONTROL(pb));
2087 static const int lookup[8] = {
2088 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
2089 };
2090
2091 ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
2092
2093 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
2094 irq = lookup[intrLine];
2095
2096 ECR_WRITE(pb, oecr);
2097 return irq;
2098 }
2099
2100 static int irq_probe_ECP(struct parport *pb)
2101 {
2102 int i;
2103 unsigned long irqs;
2104
2105 irqs = probe_irq_on();
2106
2107 ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
2108 ECR_WRITE(pb, (ECR_TST << 5) | 0x04);
2109 ECR_WRITE(pb, ECR_TST << 5);
2110
2111 /* If Full FIFO sure that writeIntrThreshold is generated */
2112 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
2113 outb(0xaa, FIFO(pb));
2114
2115 pb->irq = probe_irq_off(irqs);
2116 ECR_WRITE(pb, ECR_SPP << 5);
2117
2118 if (pb->irq <= 0)
2119 pb->irq = PARPORT_IRQ_NONE;
2120
2121 return pb->irq;
2122 }
2123
2124 /*
2125 * This detection seems that only works in National Semiconductors
2126 * This doesn't work in SMC, LGS, and Winbond
2127 */
2128 static int irq_probe_EPP(struct parport *pb)
2129 {
2130 #ifndef ADVANCED_DETECT
2131 return PARPORT_IRQ_NONE;
2132 #else
2133 int irqs;
2134 unsigned char oecr;
2135
2136 if (pb->modes & PARPORT_MODE_PCECR)
2137 oecr = inb(ECONTROL(pb));
2138
2139 irqs = probe_irq_on();
2140
2141 if (pb->modes & PARPORT_MODE_PCECR)
2142 frob_econtrol(pb, 0x10, 0x10);
2143
2144 clear_epp_timeout(pb);
2145 parport_pc_frob_control(pb, 0x20, 0x20);
2146 parport_pc_frob_control(pb, 0x10, 0x10);
2147 clear_epp_timeout(pb);
2148
2149 /* Device isn't expecting an EPP read
2150 * and generates an IRQ.
2151 */
2152 parport_pc_read_epp(pb);
2153 udelay(20);
2154
2155 pb->irq = probe_irq_off(irqs);
2156 if (pb->modes & PARPORT_MODE_PCECR)
2157 ECR_WRITE(pb, oecr);
2158 parport_pc_write_control(pb, 0xc);
2159
2160 if (pb->irq <= 0)
2161 pb->irq = PARPORT_IRQ_NONE;
2162
2163 return pb->irq;
2164 #endif /* Advanced detection */
2165 }
2166
2167 static int irq_probe_SPP(struct parport *pb)
2168 {
2169 /* Don't even try to do this. */
2170 return PARPORT_IRQ_NONE;
2171 }
2172
2173 /* We will attempt to share interrupt requests since other devices
2174 * such as sound cards and network cards seem to like using the
2175 * printer IRQs.
2176 *
2177 * When ECP is available we can autoprobe for IRQs.
2178 * NOTE: If we can autoprobe it, we can register the IRQ.
2179 */
2180 static int parport_irq_probe(struct parport *pb)
2181 {
2182 struct parport_pc_private *priv = pb->private_data;
2183
2184 if (priv->ecr) {
2185 pb->irq = programmable_irq_support(pb);
2186
2187 if (pb->irq == PARPORT_IRQ_NONE)
2188 pb->irq = irq_probe_ECP(pb);
2189 }
2190
2191 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2192 (pb->modes & PARPORT_MODE_EPP))
2193 pb->irq = irq_probe_EPP(pb);
2194
2195 clear_epp_timeout(pb);
2196
2197 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2198 pb->irq = irq_probe_EPP(pb);
2199
2200 clear_epp_timeout(pb);
2201
2202 if (pb->irq == PARPORT_IRQ_NONE)
2203 pb->irq = irq_probe_SPP(pb);
2204
2205 if (pb->irq == PARPORT_IRQ_NONE)
2206 pb->irq = get_superio_irq(pb);
2207
2208 return pb->irq;
2209 }
2210
2211 /* --- DMA detection -------------------------------------- */
2212
2213 /* Only if chipset conforms to ECP ISA Interface Standard */
2214 static int programmable_dma_support(struct parport *p)
2215 {
2216 unsigned char oecr = inb(ECONTROL(p));
2217 int dma;
2218
2219 frob_set_mode(p, ECR_CNF);
2220
2221 dma = inb(CONFIGB(p)) & 0x07;
2222 /* 000: Indicates jumpered 8-bit DMA if read-only.
2223 100: Indicates jumpered 16-bit DMA if read-only. */
2224 if ((dma & 0x03) == 0)
2225 dma = PARPORT_DMA_NONE;
2226
2227 ECR_WRITE(p, oecr);
2228 return dma;
2229 }
2230
2231 static int parport_dma_probe(struct parport *p)
2232 {
2233 const struct parport_pc_private *priv = p->private_data;
2234 if (priv->ecr) /* ask ECP chipset first */
2235 p->dma = programmable_dma_support(p);
2236 if (p->dma == PARPORT_DMA_NONE) {
2237 /* ask known Super-IO chips proper, although these
2238 claim ECP compatible, some don't report their DMA
2239 conforming to ECP standards */
2240 p->dma = get_superio_dma(p);
2241 }
2242
2243 return p->dma;
2244 }
2245
2246 /* --- Initialisation code -------------------------------- */
2247
2248 static LIST_HEAD(ports_list);
2249 static DEFINE_SPINLOCK(ports_lock);
2250
2251 struct parport *parport_pc_probe_port(unsigned long int base,
2252 unsigned long int base_hi,
2253 int irq, int dma,
2254 struct device *dev,
2255 int irqflags)
2256 {
2257 struct parport_pc_private *priv;
2258 struct parport_operations *ops;
2259 struct parport *p;
2260 int probedirq = PARPORT_IRQ_NONE;
2261 struct resource *base_res;
2262 struct resource *ECR_res = NULL;
2263 struct resource *EPP_res = NULL;
2264 struct platform_device *pdev = NULL;
2265
2266 if (!dev) {
2267 /* We need a physical device to attach to, but none was
2268 * provided. Create our own. */
2269 pdev = platform_device_register_simple("parport_pc",
2270 base, NULL, 0);
2271 if (IS_ERR(pdev))
2272 return NULL;
2273 dev = &pdev->dev;
2274 }
2275
2276 ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2277 if (!ops)
2278 goto out1;
2279
2280 priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
2281 if (!priv)
2282 goto out2;
2283
2284 /* a misnomer, actually - it's allocate and reserve parport number */
2285 p = parport_register_port(base, irq, dma, ops);
2286 if (!p)
2287 goto out3;
2288
2289 base_res = request_region(base, 3, p->name);
2290 if (!base_res)
2291 goto out4;
2292
2293 memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
2294 priv->ctr = 0xc;
2295 priv->ctr_writable = ~0x10;
2296 priv->ecr = 0;
2297 priv->fifo_depth = 0;
2298 priv->dma_buf = NULL;
2299 priv->dma_handle = 0;
2300 INIT_LIST_HEAD(&priv->list);
2301 priv->port = p;
2302
2303 p->dev = dev;
2304 p->base_hi = base_hi;
2305 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2306 p->private_data = priv;
2307
2308 if (base_hi) {
2309 ECR_res = request_region(base_hi, 3, p->name);
2310 if (ECR_res)
2311 parport_ECR_present(p);
2312 }
2313
2314 if (base != 0x3bc) {
2315 EPP_res = request_region(base+0x3, 5, p->name);
2316 if (EPP_res)
2317 if (!parport_EPP_supported(p))
2318 parport_ECPEPP_supported(p);
2319 }
2320 if (!parport_SPP_supported(p))
2321 /* No port. */
2322 goto out5;
2323 if (priv->ecr)
2324 parport_ECPPS2_supported(p);
2325 else
2326 parport_PS2_supported(p);
2327
2328 p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
2329
2330 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2331 if (p->base_hi && priv->ecr)
2332 printk(" (0x%lx)", p->base_hi);
2333 if (p->irq == PARPORT_IRQ_AUTO) {
2334 p->irq = PARPORT_IRQ_NONE;
2335 parport_irq_probe(p);
2336 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2337 p->irq = PARPORT_IRQ_NONE;
2338 parport_irq_probe(p);
2339 probedirq = p->irq;
2340 p->irq = PARPORT_IRQ_NONE;
2341 }
2342 if (p->irq != PARPORT_IRQ_NONE) {
2343 printk(", irq %d", p->irq);
2344 priv->ctr_writable |= 0x10;
2345
2346 if (p->dma == PARPORT_DMA_AUTO) {
2347 p->dma = PARPORT_DMA_NONE;
2348 parport_dma_probe(p);
2349 }
2350 }
2351 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2352 is mandatory (see above) */
2353 p->dma = PARPORT_DMA_NONE;
2354
2355 #ifdef CONFIG_PARPORT_PC_FIFO
2356 if (parport_ECP_supported(p) &&
2357 p->dma != PARPORT_DMA_NOFIFO &&
2358 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2359 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2360 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2361 #ifdef CONFIG_PARPORT_1284
2362 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2363 /* currently broken, but working on it.. (FB) */
2364 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2365 #endif /* IEEE 1284 support */
2366 if (p->dma != PARPORT_DMA_NONE) {
2367 printk(", dma %d", p->dma);
2368 p->modes |= PARPORT_MODE_DMA;
2369 } else
2370 printk(", using FIFO");
2371 } else
2372 /* We can't use the DMA channel after all. */
2373 p->dma = PARPORT_DMA_NONE;
2374 #endif /* Allowed to use FIFO/DMA */
2375
2376 printk(" [");
2377
2378 #define printmode(x) \
2379 {\
2380 if (p->modes & PARPORT_MODE_##x) {\
2381 printk("%s%s", f ? "," : "", #x);\
2382 f++;\
2383 } \
2384 }
2385
2386 {
2387 int f = 0;
2388 printmode(PCSPP);
2389 printmode(TRISTATE);
2390 printmode(COMPAT)
2391 printmode(EPP);
2392 printmode(ECP);
2393 printmode(DMA);
2394 }
2395 #undef printmode
2396 #ifndef CONFIG_PARPORT_1284
2397 printk("(,...)");
2398 #endif /* CONFIG_PARPORT_1284 */
2399 printk("]\n");
2400 if (probedirq != PARPORT_IRQ_NONE)
2401 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2402
2403 /* If No ECP release the ports grabbed above. */
2404 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2405 release_region(base_hi, 3);
2406 ECR_res = NULL;
2407 }
2408 /* Likewise for EEP ports */
2409 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2410 release_region(base+3, 5);
2411 EPP_res = NULL;
2412 }
2413 if (p->irq != PARPORT_IRQ_NONE) {
2414 if (request_irq(p->irq, parport_irq_handler,
2415 irqflags, p->name, p)) {
2416 printk(KERN_WARNING "%s: irq %d in use, "
2417 "resorting to polled operation\n",
2418 p->name, p->irq);
2419 p->irq = PARPORT_IRQ_NONE;
2420 p->dma = PARPORT_DMA_NONE;
2421 }
2422
2423 #ifdef CONFIG_PARPORT_PC_FIFO
2424 #ifdef HAS_DMA
2425 if (p->dma != PARPORT_DMA_NONE) {
2426 if (request_dma(p->dma, p->name)) {
2427 printk(KERN_WARNING "%s: dma %d in use, "
2428 "resorting to PIO operation\n",
2429 p->name, p->dma);
2430 p->dma = PARPORT_DMA_NONE;
2431 } else {
2432 priv->dma_buf =
2433 dma_alloc_coherent(dev,
2434 PAGE_SIZE,
2435 &priv->dma_handle,
2436 GFP_KERNEL);
2437 if (!priv->dma_buf) {
2438 printk(KERN_WARNING "%s: "
2439 "cannot get buffer for DMA, "
2440 "resorting to PIO operation\n",
2441 p->name);
2442 free_dma(p->dma);
2443 p->dma = PARPORT_DMA_NONE;
2444 }
2445 }
2446 }
2447 #endif
2448 #endif
2449 }
2450
2451 /* Done probing. Now put the port into a sensible start-up state. */
2452 if (priv->ecr)
2453 /*
2454 * Put the ECP detected port in PS2 mode.
2455 * Do this also for ports that have ECR but don't do ECP.
2456 */
2457 ECR_WRITE(p, 0x34);
2458
2459 parport_pc_write_data(p, 0);
2460 parport_pc_data_forward(p);
2461
2462 /* Now that we've told the sharing engine about the port, and
2463 found out its characteristics, let the high-level drivers
2464 know about it. */
2465 spin_lock(&ports_lock);
2466 list_add(&priv->list, &ports_list);
2467 spin_unlock(&ports_lock);
2468 parport_announce_port(p);
2469
2470 return p;
2471
2472 out5:
2473 if (ECR_res)
2474 release_region(base_hi, 3);
2475 if (EPP_res)
2476 release_region(base+0x3, 5);
2477 release_region(base, 3);
2478 out4:
2479 parport_put_port(p);
2480 out3:
2481 kfree(priv);
2482 out2:
2483 kfree(ops);
2484 out1:
2485 if (pdev)
2486 platform_device_unregister(pdev);
2487 return NULL;
2488 }
2489 EXPORT_SYMBOL(parport_pc_probe_port);
2490
2491 void parport_pc_unregister_port(struct parport *p)
2492 {
2493 struct parport_pc_private *priv = p->private_data;
2494 struct parport_operations *ops = p->ops;
2495
2496 parport_remove_port(p);
2497 spin_lock(&ports_lock);
2498 list_del_init(&priv->list);
2499 spin_unlock(&ports_lock);
2500 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2501 if (p->dma != PARPORT_DMA_NONE)
2502 free_dma(p->dma);
2503 #endif
2504 if (p->irq != PARPORT_IRQ_NONE)
2505 free_irq(p->irq, p);
2506 release_region(p->base, 3);
2507 if (p->size > 3)
2508 release_region(p->base + 3, p->size - 3);
2509 if (p->modes & PARPORT_MODE_ECP)
2510 release_region(p->base_hi, 3);
2511 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2512 if (priv->dma_buf)
2513 dma_free_coherent(p->physport->dev, PAGE_SIZE,
2514 priv->dma_buf,
2515 priv->dma_handle);
2516 #endif
2517 kfree(p->private_data);
2518 parport_put_port(p);
2519 kfree(ops); /* hope no-one cached it */
2520 }
2521 EXPORT_SYMBOL(parport_pc_unregister_port);
2522
2523 #ifdef CONFIG_PCI
2524
2525 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
2526 static int __devinit sio_ite_8872_probe(struct pci_dev *pdev, int autoirq,
2527 int autodma,
2528 const struct parport_pc_via_data *via)
2529 {
2530 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2531 struct resource *base_res;
2532 u32 ite8872set;
2533 u32 ite8872_lpt, ite8872_lpthi;
2534 u8 ite8872_irq, type;
2535 int irq;
2536 int i;
2537
2538 DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n");
2539
2540 /* make sure which one chip */
2541 for (i = 0; i < 5; i++) {
2542 base_res = request_region(inta_addr[i], 32, "it887x");
2543 if (base_res) {
2544 int test;
2545 pci_write_config_dword(pdev, 0x60,
2546 0xe5000000 | inta_addr[i]);
2547 pci_write_config_dword(pdev, 0x78,
2548 0x00000000 | inta_addr[i]);
2549 test = inb(inta_addr[i]);
2550 if (test != 0xff)
2551 break;
2552 release_region(inta_addr[i], 0x8);
2553 }
2554 }
2555 if (i >= 5) {
2556 printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2557 return 0;
2558 }
2559
2560 type = inb(inta_addr[i] + 0x18);
2561 type &= 0x0f;
2562
2563 switch (type) {
2564 case 0x2:
2565 printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2566 ite8872set = 0x64200000;
2567 break;
2568 case 0xa:
2569 printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2570 ite8872set = 0x64200000;
2571 break;
2572 case 0xe:
2573 printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2574 ite8872set = 0x64e00000;
2575 break;
2576 case 0x6:
2577 printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2578 return 0;
2579 case 0x8:
2580 DPRINTK(KERN_DEBUG "parport_pc: ITE8874 found (2S)\n");
2581 return 0;
2582 default:
2583 printk(KERN_INFO "parport_pc: unknown ITE887x\n");
2584 printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2585 "output to Rich.Liu@ite.com.tw\n");
2586 return 0;
2587 }
2588
2589 pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2590 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
2591 ite8872_lpt &= 0x0000ff00;
2592 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
2593 ite8872_lpthi &= 0x0000ff00;
2594 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2595 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2596 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2597 /* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2598 /* SET Parallel IRQ */
2599 pci_write_config_dword(pdev, 0x9c,
2600 ite8872set | (ite8872_irq * 0x11111));
2601
2602 DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2603 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2604 ite8872_lpt);
2605 DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2606 ite8872_lpthi);
2607
2608 /* Let the user (or defaults) steer us away from interrupts */
2609 irq = ite8872_irq;
2610 if (autoirq != PARPORT_IRQ_AUTO)
2611 irq = PARPORT_IRQ_NONE;
2612
2613 /*
2614 * Release the resource so that parport_pc_probe_port can get it.
2615 */
2616 release_resource(base_res);
2617 if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
2618 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
2619 printk(KERN_INFO
2620 "parport_pc: ITE 8872 parallel port: io=0x%X",
2621 ite8872_lpt);
2622 if (irq != PARPORT_IRQ_NONE)
2623 printk(", irq=%d", irq);
2624 printk("\n");
2625 return 1;
2626 }
2627
2628 return 0;
2629 }
2630
2631 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2632 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2633 static int __devinitdata parport_init_mode;
2634
2635 /* Data for two known VIA chips */
2636 static struct parport_pc_via_data via_686a_data __devinitdata = {
2637 0x51,
2638 0x50,
2639 0x85,
2640 0x02,
2641 0xE2,
2642 0xF0,
2643 0xE6
2644 };
2645 static struct parport_pc_via_data via_8231_data __devinitdata = {
2646 0x45,
2647 0x44,
2648 0x50,
2649 0x04,
2650 0xF2,
2651 0xFA,
2652 0xF6
2653 };
2654
2655 static int __devinit sio_via_probe(struct pci_dev *pdev, int autoirq,
2656 int autodma,
2657 const struct parport_pc_via_data *via)
2658 {
2659 u8 tmp, tmp2, siofunc;
2660 u8 ppcontrol = 0;
2661 int dma, irq;
2662 unsigned port1, port2;
2663 unsigned have_epp = 0;
2664
2665 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2666
2667 switch (parport_init_mode) {
2668 case 1:
2669 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2670 siofunc = VIA_FUNCTION_PARPORT_SPP;
2671 break;
2672 case 2:
2673 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2674 siofunc = VIA_FUNCTION_PARPORT_SPP;
2675 ppcontrol = VIA_PARPORT_BIDIR;
2676 break;
2677 case 3:
2678 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2679 siofunc = VIA_FUNCTION_PARPORT_EPP;
2680 ppcontrol = VIA_PARPORT_BIDIR;
2681 have_epp = 1;
2682 break;
2683 case 4:
2684 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2685 siofunc = VIA_FUNCTION_PARPORT_ECP;
2686 ppcontrol = VIA_PARPORT_BIDIR;
2687 break;
2688 case 5:
2689 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2690 siofunc = VIA_FUNCTION_PARPORT_ECP;
2691 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2692 have_epp = 1;
2693 break;
2694 default:
2695 printk(KERN_DEBUG
2696 "parport_pc: probing current configuration\n");
2697 siofunc = VIA_FUNCTION_PROBE;
2698 break;
2699 }
2700 /*
2701 * unlock super i/o configuration
2702 */
2703 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2704 tmp |= via->via_pci_superio_config_data;
2705 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2706
2707 /* Bits 1-0: Parallel Port Mode / Enable */
2708 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2709 tmp = inb(VIA_CONFIG_DATA);
2710 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2711 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2712 tmp2 = inb(VIA_CONFIG_DATA);
2713 if (siofunc == VIA_FUNCTION_PROBE) {
2714 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2715 ppcontrol = tmp2;
2716 } else {
2717 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2718 tmp |= siofunc;
2719 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2720 outb(tmp, VIA_CONFIG_DATA);
2721 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2722 tmp2 |= ppcontrol;
2723 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2724 outb(tmp2, VIA_CONFIG_DATA);
2725 }
2726
2727 /* Parallel Port I/O Base Address, bits 9-2 */
2728 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2729 port1 = inb(VIA_CONFIG_DATA) << 2;
2730
2731 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2732 port1);
2733 if (port1 == 0x3BC && have_epp) {
2734 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2735 outb((0x378 >> 2), VIA_CONFIG_DATA);
2736 printk(KERN_DEBUG
2737 "parport_pc: Parallel port base changed to 0x378\n");
2738 port1 = 0x378;
2739 }
2740
2741 /*
2742 * lock super i/o configuration
2743 */
2744 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2745 tmp &= ~via->via_pci_superio_config_data;
2746 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2747
2748 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2749 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2750 return 0;
2751 }
2752
2753 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2754 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2755 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2756
2757 if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2758 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2759 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2760 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2761 } else
2762 /* if ECP not enabled, DMA is not enabled, assumed
2763 bogus 'dma' value */
2764 dma = PARPORT_DMA_NONE;
2765
2766 /* Let the user (or defaults) steer us away from interrupts and DMA */
2767 if (autoirq == PARPORT_IRQ_NONE) {
2768 irq = PARPORT_IRQ_NONE;
2769 dma = PARPORT_DMA_NONE;
2770 }
2771 if (autodma == PARPORT_DMA_NONE)
2772 dma = PARPORT_DMA_NONE;
2773
2774 switch (port1) {
2775 case 0x3bc:
2776 port2 = 0x7bc; break;
2777 case 0x378:
2778 port2 = 0x778; break;
2779 case 0x278:
2780 port2 = 0x678; break;
2781 default:
2782 printk(KERN_INFO
2783 "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2784 port1);
2785 return 0;
2786 }
2787
2788 /* filter bogus IRQs */
2789 switch (irq) {
2790 case 0:
2791 case 2:
2792 case 8:
2793 case 13:
2794 irq = PARPORT_IRQ_NONE;
2795 break;
2796
2797 default: /* do nothing */
2798 break;
2799 }
2800
2801 /* finally, do the probe with values obtained */
2802 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2803 printk(KERN_INFO
2804 "parport_pc: VIA parallel port: io=0x%X", port1);
2805 if (irq != PARPORT_IRQ_NONE)
2806 printk(", irq=%d", irq);
2807 if (dma != PARPORT_DMA_NONE)
2808 printk(", dma=%d", dma);
2809 printk("\n");
2810 return 1;
2811 }
2812
2813 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2814 port1, irq, dma);
2815 return 0;
2816 }
2817
2818
2819 enum parport_pc_sio_types {
2820 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2821 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2822 sio_ite_8872,
2823 last_sio
2824 };
2825
2826 /* each element directly indexed from enum list, above */
2827 static struct parport_pc_superio {
2828 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma,
2829 const struct parport_pc_via_data *via);
2830 const struct parport_pc_via_data *via;
2831 } parport_pc_superio_info[] __devinitdata = {
2832 { sio_via_probe, &via_686a_data, },
2833 { sio_via_probe, &via_8231_data, },
2834 { sio_ite_8872_probe, NULL, },
2835 };
2836
2837 enum parport_pc_pci_cards {
2838 siig_1p_10x = last_sio,
2839 siig_2p_10x,
2840 siig_1p_20x,
2841 siig_2p_20x,
2842 lava_parallel,
2843 lava_parallel_dual_a,
2844 lava_parallel_dual_b,
2845 boca_ioppar,
2846 plx_9050,
2847 timedia_4078a,
2848 timedia_4079h,
2849 timedia_4085h,
2850 timedia_4088a,
2851 timedia_4089a,
2852 timedia_4095a,
2853 timedia_4096a,
2854 timedia_4078u,
2855 timedia_4079a,
2856 timedia_4085u,
2857 timedia_4079r,
2858 timedia_4079s,
2859 timedia_4079d,
2860 timedia_4079e,
2861 timedia_4079f,
2862 timedia_9079a,
2863 timedia_9079b,
2864 timedia_9079c,
2865 timedia_4006a,
2866 timedia_4014,
2867 timedia_4008a,
2868 timedia_4018,
2869 timedia_9018a,
2870 syba_2p_epp,
2871 syba_1p_ecp,
2872 titan_010l,
2873 titan_1284p1,
2874 titan_1284p2,
2875 avlab_1p,
2876 avlab_2p,
2877 oxsemi_952,
2878 oxsemi_954,
2879 oxsemi_840,
2880 oxsemi_pcie_pport,
2881 aks_0100,
2882 mobility_pp,
2883 netmos_9705,
2884 netmos_9715,
2885 netmos_9755,
2886 netmos_9805,
2887 netmos_9815,
2888 quatech_sppxp100,
2889 };
2890
2891
2892 /* each element directly indexed from enum list, above
2893 * (but offset by last_sio) */
2894 static struct parport_pc_pci {
2895 int numports;
2896 struct { /* BAR (base address registers) numbers in the config
2897 space header */
2898 int lo;
2899 int hi;
2900 /* -1 if not there, >6 for offset-method (max BAR is 6) */
2901 } addr[4];
2902
2903 /* If set, this is called immediately after pci_enable_device.
2904 * If it returns non-zero, no probing will take place and the
2905 * ports will not be used. */
2906 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2907
2908 /* If set, this is called after probing for ports. If 'failed'
2909 * is non-zero we couldn't use any of the ports. */
2910 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2911 } cards[] = {
2912 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2913 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2914 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2915 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2916 /* lava_parallel */ { 1, { { 0, -1 }, } },
2917 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2918 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2919 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2920 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2921 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2922 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2923 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2924 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2925 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2926 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2927 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2928 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2929 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2930 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2931 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2932 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2933 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2934 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2935 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2936 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2937 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2938 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2939 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2940 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2941 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2942 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2943 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2944 /* SYBA uses fixed offsets in
2945 a 1K io window */
2946 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2947 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2948 /* titan_010l */ { 1, { { 3, -1 }, } },
2949 /* titan_1284p1 */ { 1, { { 0, 1 }, } },
2950 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2951 /* avlab_1p */ { 1, { { 0, 1}, } },
2952 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2953 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2954 * and 840 locks up if you write 1 to bit 2! */
2955 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
2956 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2957 /* oxsemi_840 */ { 1, { { 0, 1 }, } },
2958 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
2959 /* aks_0100 */ { 1, { { 0, -1 }, } },
2960 /* mobility_pp */ { 1, { { 0, 1 }, } },
2961
2962 /* The netmos entries below are untested */
2963 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2964 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2965 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2966 /* netmos_9805 */ { 1, { { 0, -1 }, } },
2967 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2968
2969 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2970 };
2971
2972 static const struct pci_device_id parport_pc_pci_tbl[] = {
2973 /* Super-IO onboard chips */
2974 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2975 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2976 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2977 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2978
2979 /* PCI cards */
2980 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2981 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2982 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2983 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2984 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2985 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2986 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2987 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2988 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2989 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2990 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2991 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2992 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2993 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2994 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2995 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2996 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2997 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2998 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2999 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
3000 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
3001 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
3002 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
3003 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
3004 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
3005 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
3006 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
3007 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
3008 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
3009 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
3010 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
3011 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
3012 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
3013 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
3014 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
3015 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
3016 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
3017 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
3018 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
3019 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
3020 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
3021 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
3022 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
3023 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
3024 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
3025 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
3026 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
3027 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
3028 { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 },
3029 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
3030 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
3031 /* AFAVLAB_TK9902 */
3032 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
3033 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
3034 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
3035 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
3036 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
3037 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
3038 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
3039 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
3040 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
3041 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3042 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
3043 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3044 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
3045 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3046 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
3047 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3048 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
3049 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3050 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
3051 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3052 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
3053 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3054 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
3055 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
3056 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
3057 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
3058 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
3059 /* NetMos communication controllers */
3060 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
3061 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
3062 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
3063 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
3064 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
3065 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
3066 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
3067 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
3068 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
3069 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
3070 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
3071 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
3072 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
3073 { 0, } /* terminate list */
3074 };
3075 MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
3076
3077 struct pci_parport_data {
3078 int num;
3079 struct parport *ports[2];
3080 };
3081
3082 static int parport_pc_pci_probe(struct pci_dev *dev,
3083 const struct pci_device_id *id)
3084 {
3085 int err, count, n, i = id->driver_data;
3086 struct pci_parport_data *data;
3087
3088 if (i < last_sio)
3089 /* This is an onboard Super-IO and has already been probed */
3090 return 0;
3091
3092 /* This is a PCI card */
3093 i -= last_sio;
3094 count = 0;
3095 err = pci_enable_device(dev);
3096 if (err)
3097 return err;
3098
3099 data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
3100 if (!data)
3101 return -ENOMEM;
3102
3103 if (cards[i].preinit_hook &&
3104 cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
3105 kfree(data);
3106 return -ENODEV;
3107 }
3108
3109 for (n = 0; n < cards[i].numports; n++) {
3110 int lo = cards[i].addr[n].lo;
3111 int hi = cards[i].addr[n].hi;
3112 int irq;
3113 unsigned long io_lo, io_hi;
3114 io_lo = pci_resource_start(dev, lo);
3115 io_hi = 0;
3116 if ((hi >= 0) && (hi <= 6))
3117 io_hi = pci_resource_start(dev, hi);
3118 else if (hi > 6)
3119 io_lo += hi; /* Reinterpret the meaning of
3120 "hi" as an offset (see SYBA
3121 def.) */
3122 /* TODO: test if sharing interrupts works */
3123 irq = dev->irq;
3124 if (irq == IRQ_NONE) {
3125 printk(KERN_DEBUG
3126 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
3127 parport_pc_pci_tbl[i + last_sio].vendor,
3128 parport_pc_pci_tbl[i + last_sio].device,
3129 io_lo, io_hi);
3130 irq = PARPORT_IRQ_NONE;
3131 } else {
3132 printk(KERN_DEBUG
3133 "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
3134 parport_pc_pci_tbl[i + last_sio].vendor,
3135 parport_pc_pci_tbl[i + last_sio].device,
3136 io_lo, io_hi, irq);
3137 }
3138 data->ports[count] =
3139 parport_pc_probe_port(io_lo, io_hi, irq,
3140 PARPORT_DMA_NONE, &dev->dev,
3141 IRQF_SHARED);
3142 if (data->ports[count])
3143 count++;
3144 }
3145
3146 data->num = count;
3147
3148 if (cards[i].postinit_hook)
3149 cards[i].postinit_hook(dev, count == 0);
3150
3151 if (count) {
3152 pci_set_drvdata(dev, data);
3153 return 0;
3154 }
3155
3156 kfree(data);
3157
3158 return -ENODEV;
3159 }
3160
3161 static void __devexit parport_pc_pci_remove(struct pci_dev *dev)
3162 {
3163 struct pci_parport_data *data = pci_get_drvdata(dev);
3164 int i;
3165
3166 pci_set_drvdata(dev, NULL);
3167
3168 if (data) {
3169 for (i = data->num - 1; i >= 0; i--)
3170 parport_pc_unregister_port(data->ports[i]);
3171
3172 kfree(data);
3173 }
3174 }
3175
3176 static struct pci_driver parport_pc_pci_driver = {
3177 .name = "parport_pc",
3178 .id_table = parport_pc_pci_tbl,
3179 .probe = parport_pc_pci_probe,
3180 .remove = __devexit_p(parport_pc_pci_remove),
3181 };
3182
3183 static int __init parport_pc_init_superio(int autoirq, int autodma)
3184 {
3185 const struct pci_device_id *id;
3186 struct pci_dev *pdev = NULL;
3187 int ret = 0;
3188
3189 for_each_pci_dev(pdev) {
3190 id = pci_match_id(parport_pc_pci_tbl, pdev);
3191 if (id == NULL || id->driver_data >= last_sio)
3192 continue;
3193
3194 if (parport_pc_superio_info[id->driver_data].probe(
3195 pdev, autoirq, autodma,
3196 parport_pc_superio_info[id->driver_data].via)) {
3197 ret++;
3198 }
3199 }
3200
3201 return ret; /* number of devices found */
3202 }
3203 #else
3204 static struct pci_driver parport_pc_pci_driver;
3205 static int __init parport_pc_init_superio(int autoirq, int autodma)
3206 {
3207 return 0;
3208 }
3209 #endif /* CONFIG_PCI */
3210
3211 #ifdef CONFIG_PNP
3212
3213 static const struct pnp_device_id parport_pc_pnp_tbl[] = {
3214 /* Standard LPT Printer Port */
3215 {.id = "PNP0400", .driver_data = 0},
3216 /* ECP Printer Port */
3217 {.id = "PNP0401", .driver_data = 0},
3218 { }
3219 };
3220
3221 MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
3222
3223 static int parport_pc_pnp_probe(struct pnp_dev *dev,
3224 const struct pnp_device_id *id)
3225 {
3226 struct parport *pdata;
3227 unsigned long io_lo, io_hi;
3228 int dma, irq;
3229
3230 if (pnp_port_valid(dev, 0) &&
3231 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
3232 io_lo = pnp_port_start(dev, 0);
3233 } else
3234 return -EINVAL;
3235
3236 if (pnp_port_valid(dev, 1) &&
3237 !(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
3238 io_hi = pnp_port_start(dev, 1);
3239 } else
3240 io_hi = 0;
3241
3242 if (pnp_irq_valid(dev, 0) &&
3243 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
3244 irq = pnp_irq(dev, 0);
3245 } else
3246 irq = PARPORT_IRQ_NONE;
3247
3248 if (pnp_dma_valid(dev, 0) &&
3249 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
3250 dma = pnp_dma(dev, 0);
3251 } else
3252 dma = PARPORT_DMA_NONE;
3253
3254 dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
3255 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
3256 if (pdata == NULL)
3257 return -ENODEV;
3258
3259 pnp_set_drvdata(dev, pdata);
3260 return 0;
3261 }
3262
3263 static void parport_pc_pnp_remove(struct pnp_dev *dev)
3264 {
3265 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
3266 if (!pdata)
3267 return;
3268
3269 parport_pc_unregister_port(pdata);
3270 }
3271
3272 /* we only need the pnp layer to activate the device, at least for now */
3273 static struct pnp_driver parport_pc_pnp_driver = {
3274 .name = "parport_pc",
3275 .id_table = parport_pc_pnp_tbl,
3276 .probe = parport_pc_pnp_probe,
3277 .remove = parport_pc_pnp_remove,
3278 };
3279
3280 #else
3281 static struct pnp_driver parport_pc_pnp_driver;
3282 #endif /* CONFIG_PNP */
3283
3284 static int __devinit parport_pc_platform_probe(struct platform_device *pdev)
3285 {
3286 /* Always succeed, the actual probing is done in
3287 * parport_pc_probe_port(). */
3288 return 0;
3289 }
3290
3291 static struct platform_driver parport_pc_platform_driver = {
3292 .driver = {
3293 .owner = THIS_MODULE,
3294 .name = "parport_pc",
3295 },
3296 .probe = parport_pc_platform_probe,
3297 };
3298
3299 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3300 static int __devinit __attribute__((unused))
3301 parport_pc_find_isa_ports(int autoirq, int autodma)
3302 {
3303 int count = 0;
3304
3305 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
3306 count++;
3307 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
3308 count++;
3309 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
3310 count++;
3311
3312 return count;
3313 }
3314
3315 /* This function is called by parport_pc_init if the user didn't
3316 * specify any ports to probe. Its job is to find some ports. Order
3317 * is important here -- we want ISA ports to be registered first,
3318 * followed by PCI cards (for least surprise), but before that we want
3319 * to do chipset-specific tests for some onboard ports that we know
3320 * about.
3321 *
3322 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3323 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3324 */
3325 static void __init parport_pc_find_ports(int autoirq, int autodma)
3326 {
3327 int count = 0, err;
3328
3329 #ifdef CONFIG_PARPORT_PC_SUPERIO
3330 detect_and_report_it87();
3331 detect_and_report_winbond();
3332 detect_and_report_smsc();
3333 #endif
3334
3335 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3336 count += parport_pc_init_superio(autoirq, autodma);
3337
3338 /* PnP ports, skip detection if SuperIO already found them */
3339 if (!count) {
3340 err = pnp_register_driver(&parport_pc_pnp_driver);
3341 if (!err)
3342 pnp_registered_parport = 1;
3343 }
3344
3345 /* ISA ports and whatever (see asm/parport.h). */
3346 parport_pc_find_nonpci_ports(autoirq, autodma);
3347
3348 err = pci_register_driver(&parport_pc_pci_driver);
3349 if (!err)
3350 pci_registered_parport = 1;
3351 }
3352
3353 /*
3354 * Piles of crap below pretend to be a parser for module and kernel
3355 * parameters. Say "thank you" to whoever had come up with that
3356 * syntax and keep in mind that code below is a cleaned up version.
3357 */
3358
3359 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3360 [0 ... PARPORT_PC_MAX_PORTS] = 0
3361 };
3362 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3363 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3364 };
3365 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3366 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3367 };
3368 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3369 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3370 };
3371
3372 static int __init parport_parse_param(const char *s, int *val,
3373 int automatic, int none, int nofifo)
3374 {
3375 if (!s)
3376 return 0;
3377 if (!strncmp(s, "auto", 4))
3378 *val = automatic;
3379 else if (!strncmp(s, "none", 4))
3380 *val = none;
3381 else if (nofifo && !strncmp(s, "nofifo", 4))
3382 *val = nofifo;
3383 else {
3384 char *ep;
3385 unsigned long r = simple_strtoul(s, &ep, 0);
3386 if (ep != s)
3387 *val = r;
3388 else {
3389 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3390 return -1;
3391 }
3392 }
3393 return 0;
3394 }
3395
3396 static int __init parport_parse_irq(const char *irqstr, int *val)
3397 {
3398 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3399 PARPORT_IRQ_NONE, 0);
3400 }
3401
3402 static int __init parport_parse_dma(const char *dmastr, int *val)
3403 {
3404 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3405 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3406 }
3407
3408 #ifdef CONFIG_PCI
3409 static int __init parport_init_mode_setup(char *str)
3410 {
3411 printk(KERN_DEBUG
3412 "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3413
3414 if (!strcmp(str, "spp"))
3415 parport_init_mode = 1;
3416 if (!strcmp(str, "ps2"))
3417 parport_init_mode = 2;
3418 if (!strcmp(str, "epp"))
3419 parport_init_mode = 3;
3420 if (!strcmp(str, "ecp"))
3421 parport_init_mode = 4;
3422 if (!strcmp(str, "ecpepp"))
3423 parport_init_mode = 5;
3424 return 1;
3425 }
3426 #endif
3427
3428 #ifdef MODULE
3429 static const char *irq[PARPORT_PC_MAX_PORTS];
3430 static const char *dma[PARPORT_PC_MAX_PORTS];
3431
3432 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3433 module_param_array(io, int, NULL, 0);
3434 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3435 module_param_array(io_hi, int, NULL, 0);
3436 MODULE_PARM_DESC(irq, "IRQ line");
3437 module_param_array(irq, charp, NULL, 0);
3438 MODULE_PARM_DESC(dma, "DMA channel");
3439 module_param_array(dma, charp, NULL, 0);
3440 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3441 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3442 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3443 module_param(verbose_probing, int, 0644);
3444 #endif
3445 #ifdef CONFIG_PCI
3446 static char *init_mode;
3447 MODULE_PARM_DESC(init_mode,
3448 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3449 module_param(init_mode, charp, 0);
3450 #endif
3451
3452 static int __init parse_parport_params(void)
3453 {
3454 unsigned int i;
3455 int val;
3456
3457 #ifdef CONFIG_PCI
3458 if (init_mode)
3459 parport_init_mode_setup(init_mode);
3460 #endif
3461
3462 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3463 if (parport_parse_irq(irq[i], &val))
3464 return 1;
3465 irqval[i] = val;
3466 if (parport_parse_dma(dma[i], &val))
3467 return 1;
3468 dmaval[i] = val;
3469 }
3470 if (!io[0]) {
3471 /* The user can make us use any IRQs or DMAs we find. */
3472 if (irq[0] && !parport_parse_irq(irq[0], &val))
3473 switch (val) {
3474 case PARPORT_IRQ_NONE:
3475 case PARPORT_IRQ_AUTO:
3476 irqval[0] = val;
3477 break;
3478 default:
3479 printk(KERN_WARNING
3480 "parport_pc: irq specified "
3481 "without base address. Use 'io=' "
3482 "to specify one\n");
3483 }
3484
3485 if (dma[0] && !parport_parse_dma(dma[0], &val))
3486 switch (val) {
3487 case PARPORT_DMA_NONE:
3488 case PARPORT_DMA_AUTO:
3489 dmaval[0] = val;
3490 break;
3491 default:
3492 printk(KERN_WARNING
3493 "parport_pc: dma specified "
3494 "without base address. Use 'io=' "
3495 "to specify one\n");
3496 }
3497 }
3498 return 0;
3499 }
3500
3501 #else
3502
3503 static int parport_setup_ptr __initdata;
3504
3505 /*
3506 * Acceptable parameters:
3507 *
3508 * parport=0
3509 * parport=auto
3510 * parport=0xBASE[,IRQ[,DMA]]
3511 *
3512 * IRQ/DMA may be numeric or 'auto' or 'none'
3513 */
3514 static int __init parport_setup(char *str)
3515 {
3516 char *endptr;
3517 char *sep;
3518 int val;
3519
3520 if (!str || !*str || (*str == '0' && !*(str+1))) {
3521 /* Disable parport if "parport=0" in cmdline */
3522 io[0] = PARPORT_DISABLE;
3523 return 1;
3524 }
3525
3526 if (!strncmp(str, "auto", 4)) {
3527 irqval[0] = PARPORT_IRQ_AUTO;
3528 dmaval[0] = PARPORT_DMA_AUTO;
3529 return 1;
3530 }
3531
3532 val = simple_strtoul(str, &endptr, 0);
3533 if (endptr == str) {
3534 printk(KERN_WARNING "parport=%s not understood\n", str);
3535 return 1;
3536 }
3537
3538 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3539 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3540 return 1;
3541 }
3542
3543 io[parport_setup_ptr] = val;
3544 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3545 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3546
3547 sep = strchr(str, ',');
3548 if (sep++) {
3549 if (parport_parse_irq(sep, &val))
3550 return 1;
3551 irqval[parport_setup_ptr] = val;
3552 sep = strchr(sep, ',');
3553 if (sep++) {
3554 if (parport_parse_dma(sep, &val))
3555 return 1;
3556 dmaval[parport_setup_ptr] = val;
3557 }
3558 }
3559 parport_setup_ptr++;
3560 return 1;
3561 }
3562
3563 static int __init parse_parport_params(void)
3564 {
3565 return io[0] == PARPORT_DISABLE;
3566 }
3567
3568 __setup("parport=", parport_setup);
3569
3570 /*
3571 * Acceptable parameters:
3572 *
3573 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3574 */
3575 #ifdef CONFIG_PCI
3576 __setup("parport_init_mode=", parport_init_mode_setup);
3577 #endif
3578 #endif
3579
3580 /* "Parser" ends here */
3581
3582 static int __init parport_pc_init(void)
3583 {
3584 int err;
3585
3586 if (parse_parport_params())
3587 return -EINVAL;
3588
3589 err = platform_driver_register(&parport_pc_platform_driver);
3590 if (err)
3591 return err;
3592
3593 if (io[0]) {
3594 int i;
3595 /* Only probe the ports we were given. */
3596 user_specified = 1;
3597 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3598 if (!io[i])
3599 break;
3600 if (io_hi[i] == PARPORT_IOHI_AUTO)
3601 io_hi[i] = 0x400 + io[i];
3602 parport_pc_probe_port(io[i], io_hi[i],
3603 irqval[i], dmaval[i], NULL, 0);
3604 }
3605 } else
3606 parport_pc_find_ports(irqval[0], dmaval[0]);
3607
3608 return 0;
3609 }
3610
3611 static void __exit parport_pc_exit(void)
3612 {
3613 if (pci_registered_parport)
3614 pci_unregister_driver(&parport_pc_pci_driver);
3615 if (pnp_registered_parport)
3616 pnp_unregister_driver(&parport_pc_pnp_driver);
3617 platform_driver_unregister(&parport_pc_platform_driver);
3618
3619 while (!list_empty(&ports_list)) {
3620 struct parport_pc_private *priv;
3621 struct parport *port;
3622 priv = list_entry(ports_list.next,
3623 struct parport_pc_private, list);
3624 port = priv->port;
3625 if (port->dev && port->dev->bus == &platform_bus_type)
3626 platform_device_unregister(
3627 to_platform_device(port->dev));
3628 parport_pc_unregister_port(port);
3629 }
3630 }
3631
3632 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3633 MODULE_DESCRIPTION("PC-style parallel port driver");
3634 MODULE_LICENSE("GPL");
3635 module_init(parport_pc_init)
3636 module_exit(parport_pc_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree