2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
36 struct change_domains
{
37 uint32_t invalidate_domains
;
38 uint32_t flush_domains
;
43 * Set the next domain for the specified object. This
44 * may not actually perform the necessary flushing/invaliding though,
45 * as that may want to be batched with other set_domain operations
47 * This is (we hope) the only really tricky part of gem. The goal
48 * is fairly simple -- track which caches hold bits of the object
49 * and make sure they remain coherent. A few concrete examples may
50 * help to explain how it works. For shorthand, we use the notation
51 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
52 * a pair of read and write domain masks.
54 * Case 1: the batch buffer
60 * 5. Unmapped from GTT
63 * Let's take these a step at a time
66 * Pages allocated from the kernel may still have
67 * cache contents, so we set them to (CPU, CPU) always.
68 * 2. Written by CPU (using pwrite)
69 * The pwrite function calls set_domain (CPU, CPU) and
70 * this function does nothing (as nothing changes)
72 * This function asserts that the object is not
73 * currently in any GPU-based read or write domains
75 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
76 * As write_domain is zero, this function adds in the
77 * current read domains (CPU+COMMAND, 0).
78 * flush_domains is set to CPU.
79 * invalidate_domains is set to COMMAND
80 * clflush is run to get data out of the CPU caches
81 * then i915_dev_set_domain calls i915_gem_flush to
82 * emit an MI_FLUSH and drm_agp_chipset_flush
83 * 5. Unmapped from GTT
84 * i915_gem_object_unbind calls set_domain (CPU, CPU)
85 * flush_domains and invalidate_domains end up both zero
86 * so no flushing/invalidating happens
90 * Case 2: The shared render buffer
94 * 3. Read/written by GPU
95 * 4. set_domain to (CPU,CPU)
96 * 5. Read/written by CPU
97 * 6. Read/written by GPU
100 * Same as last example, (CPU, CPU)
102 * Nothing changes (assertions find that it is not in the GPU)
103 * 3. Read/written by GPU
104 * execbuffer calls set_domain (RENDER, RENDER)
105 * flush_domains gets CPU
106 * invalidate_domains gets GPU
108 * MI_FLUSH and drm_agp_chipset_flush
109 * 4. set_domain (CPU, CPU)
110 * flush_domains gets GPU
111 * invalidate_domains gets CPU
112 * wait_rendering (obj) to make sure all drawing is complete.
113 * This will include an MI_FLUSH to get the data from GPU
115 * clflush (obj) to invalidate the CPU cache
116 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
117 * 5. Read/written by CPU
118 * cache lines are loaded and dirtied
119 * 6. Read written by GPU
120 * Same as last GPU access
122 * Case 3: The constant buffer
127 * 4. Updated (written) by CPU again
136 * flush_domains = CPU
137 * invalidate_domains = RENDER
140 * drm_agp_chipset_flush
141 * 4. Updated (written) by CPU again
143 * flush_domains = 0 (no previous write domain)
144 * invalidate_domains = 0 (no new read domains)
147 * flush_domains = CPU
148 * invalidate_domains = RENDER
151 * drm_agp_chipset_flush
154 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object
*obj
,
155 struct intel_ring_buffer
*ring
,
156 struct change_domains
*cd
)
158 uint32_t invalidate_domains
= 0, flush_domains
= 0;
161 * If the object isn't moving to a new write domain,
162 * let the object stay in multiple read domains
164 if (obj
->base
.pending_write_domain
== 0)
165 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
168 * Flush the current write domain if
169 * the new read domains don't match. Invalidate
170 * any read domains which differ from the old
173 if (obj
->base
.write_domain
&&
174 (((obj
->base
.write_domain
!= obj
->base
.pending_read_domains
||
175 obj
->ring
!= ring
)) ||
176 (obj
->fenced_gpu_access
&& !obj
->pending_fenced_gpu_access
))) {
177 flush_domains
|= obj
->base
.write_domain
;
178 invalidate_domains
|=
179 obj
->base
.pending_read_domains
& ~obj
->base
.write_domain
;
182 * Invalidate any read caches which may have
183 * stale data. That is, any new read domains.
185 invalidate_domains
|= obj
->base
.pending_read_domains
& ~obj
->base
.read_domains
;
186 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
187 i915_gem_clflush_object(obj
);
189 /* blow away mappings if mapped through GTT */
190 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_GTT
)
191 i915_gem_release_mmap(obj
);
193 /* The actual obj->write_domain will be updated with
194 * pending_write_domain after we emit the accumulated flush for all
195 * of our domain changes in execbuffers (which clears objects'
196 * write_domains). So if we have a current write domain that we
197 * aren't changing, set pending_write_domain to that.
199 if (flush_domains
== 0 && obj
->base
.pending_write_domain
== 0)
200 obj
->base
.pending_write_domain
= obj
->base
.write_domain
;
202 cd
->invalidate_domains
|= invalidate_domains
;
203 cd
->flush_domains
|= flush_domains
;
204 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
205 cd
->flush_rings
|= obj
->ring
->id
;
206 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
207 cd
->flush_rings
|= ring
->id
;
212 struct hlist_head buckets
[0];
215 static struct eb_objects
*
218 struct eb_objects
*eb
;
219 int count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
222 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
223 sizeof(struct eb_objects
),
233 eb_reset(struct eb_objects
*eb
)
235 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
239 eb_add_object(struct eb_objects
*eb
, struct drm_i915_gem_object
*obj
)
241 hlist_add_head(&obj
->exec_node
,
242 &eb
->buckets
[obj
->exec_handle
& eb
->and]);
245 static struct drm_i915_gem_object
*
246 eb_get_object(struct eb_objects
*eb
, unsigned long handle
)
248 struct hlist_head
*head
;
249 struct hlist_node
*node
;
250 struct drm_i915_gem_object
*obj
;
252 head
= &eb
->buckets
[handle
& eb
->and];
253 hlist_for_each(node
, head
) {
254 obj
= hlist_entry(node
, struct drm_i915_gem_object
, exec_node
);
255 if (obj
->exec_handle
== handle
)
263 eb_destroy(struct eb_objects
*eb
)
269 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
270 struct eb_objects
*eb
,
271 struct drm_i915_gem_relocation_entry
*reloc
)
273 struct drm_device
*dev
= obj
->base
.dev
;
274 struct drm_gem_object
*target_obj
;
275 uint32_t target_offset
;
278 /* we've already hold a reference to all valid objects */
279 target_obj
= &eb_get_object(eb
, reloc
->target_handle
)->base
;
280 if (unlikely(target_obj
== NULL
))
283 target_offset
= to_intel_bo(target_obj
)->gtt_offset
;
286 DRM_INFO("%s: obj %p offset %08x target %d "
287 "read %08x write %08x gtt %08x "
288 "presumed %08x delta %08x\n",
292 (int) reloc
->target_handle
,
293 (int) reloc
->read_domains
,
294 (int) reloc
->write_domain
,
296 (int) reloc
->presumed_offset
,
300 /* The target buffer should have appeared before us in the
301 * exec_object list, so it should have a GTT space bound by now.
303 if (unlikely(target_offset
== 0)) {
304 DRM_ERROR("No GTT space found for object %d\n",
305 reloc
->target_handle
);
309 /* Validate that the target is in a valid r/w GPU domain */
310 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
311 DRM_ERROR("reloc with multiple write domains: "
312 "obj %p target %d offset %d "
313 "read %08x write %08x",
314 obj
, reloc
->target_handle
,
317 reloc
->write_domain
);
320 if (unlikely((reloc
->write_domain
| reloc
->read_domains
) & I915_GEM_DOMAIN_CPU
)) {
321 DRM_ERROR("reloc with read/write CPU domains: "
322 "obj %p target %d offset %d "
323 "read %08x write %08x",
324 obj
, reloc
->target_handle
,
327 reloc
->write_domain
);
330 if (unlikely(reloc
->write_domain
&& target_obj
->pending_write_domain
&&
331 reloc
->write_domain
!= target_obj
->pending_write_domain
)) {
332 DRM_ERROR("Write domain conflict: "
333 "obj %p target %d offset %d "
334 "new %08x old %08x\n",
335 obj
, reloc
->target_handle
,
338 target_obj
->pending_write_domain
);
342 target_obj
->pending_read_domains
|= reloc
->read_domains
;
343 target_obj
->pending_write_domain
|= reloc
->write_domain
;
345 /* If the relocation already has the right value in it, no
346 * more work needs to be done.
348 if (target_offset
== reloc
->presumed_offset
)
351 /* Check that the relocation address is valid... */
352 if (unlikely(reloc
->offset
> obj
->base
.size
- 4)) {
353 DRM_ERROR("Relocation beyond object bounds: "
354 "obj %p target %d offset %d size %d.\n",
355 obj
, reloc
->target_handle
,
357 (int) obj
->base
.size
);
360 if (unlikely(reloc
->offset
& 3)) {
361 DRM_ERROR("Relocation not 4-byte aligned: "
362 "obj %p target %d offset %d.\n",
363 obj
, reloc
->target_handle
,
364 (int) reloc
->offset
);
368 /* and points to somewhere within the target object. */
369 if (unlikely(reloc
->delta
>= target_obj
->size
)) {
370 DRM_ERROR("Relocation beyond target object bounds: "
371 "obj %p target %d delta %d size %d.\n",
372 obj
, reloc
->target_handle
,
374 (int) target_obj
->size
);
378 reloc
->delta
+= target_offset
;
379 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
380 uint32_t page_offset
= reloc
->offset
& ~PAGE_MASK
;
383 vaddr
= kmap_atomic(obj
->pages
[reloc
->offset
>> PAGE_SHIFT
]);
384 *(uint32_t *)(vaddr
+ page_offset
) = reloc
->delta
;
385 kunmap_atomic(vaddr
);
387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
388 uint32_t __iomem
*reloc_entry
;
389 void __iomem
*reloc_page
;
391 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
395 /* Map the page containing the relocation we're going to perform. */
396 reloc
->offset
+= obj
->gtt_offset
;
397 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
398 reloc
->offset
& PAGE_MASK
);
399 reloc_entry
= (uint32_t __iomem
*)
400 (reloc_page
+ (reloc
->offset
& ~PAGE_MASK
));
401 iowrite32(reloc
->delta
, reloc_entry
);
402 io_mapping_unmap_atomic(reloc_page
);
405 /* and update the user's relocation entry */
406 reloc
->presumed_offset
= target_offset
;
412 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object
*obj
,
413 struct eb_objects
*eb
)
415 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
416 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
419 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
420 for (i
= 0; i
< entry
->relocation_count
; i
++) {
421 struct drm_i915_gem_relocation_entry reloc
;
423 if (__copy_from_user_inatomic(&reloc
,
428 ret
= i915_gem_execbuffer_relocate_entry(obj
, eb
, &reloc
);
432 if (__copy_to_user_inatomic(&user_relocs
[i
].presumed_offset
,
433 &reloc
.presumed_offset
,
434 sizeof(reloc
.presumed_offset
)))
442 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object
*obj
,
443 struct eb_objects
*eb
,
444 struct drm_i915_gem_relocation_entry
*relocs
)
446 const struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
449 for (i
= 0; i
< entry
->relocation_count
; i
++) {
450 ret
= i915_gem_execbuffer_relocate_entry(obj
, eb
, &relocs
[i
]);
459 i915_gem_execbuffer_relocate(struct drm_device
*dev
,
460 struct eb_objects
*eb
,
461 struct list_head
*objects
)
463 struct drm_i915_gem_object
*obj
;
466 list_for_each_entry(obj
, objects
, exec_list
) {
467 ret
= i915_gem_execbuffer_relocate_object(obj
, eb
);
476 i915_gem_execbuffer_reserve(struct intel_ring_buffer
*ring
,
477 struct drm_file
*file
,
478 struct list_head
*objects
)
480 struct drm_i915_gem_object
*obj
;
482 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
483 struct list_head ordered_objects
;
485 INIT_LIST_HEAD(&ordered_objects
);
486 while (!list_empty(objects
)) {
487 struct drm_i915_gem_exec_object2
*entry
;
488 bool need_fence
, need_mappable
;
490 obj
= list_first_entry(objects
,
491 struct drm_i915_gem_object
,
493 entry
= obj
->exec_entry
;
496 has_fenced_gpu_access
&&
497 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
498 obj
->tiling_mode
!= I915_TILING_NONE
;
500 entry
->relocation_count
? true : need_fence
;
503 list_move(&obj
->exec_list
, &ordered_objects
);
505 list_move_tail(&obj
->exec_list
, &ordered_objects
);
507 obj
->base
.pending_read_domains
= 0;
508 obj
->base
.pending_write_domain
= 0;
510 list_splice(&ordered_objects
, objects
);
512 /* Attempt to pin all of the buffers into the GTT.
513 * This is done in 3 phases:
515 * 1a. Unbind all objects that do not match the GTT constraints for
516 * the execbuffer (fenceable, mappable, alignment etc).
517 * 1b. Increment pin count for already bound objects.
518 * 2. Bind new objects.
519 * 3. Decrement pin count.
521 * This avoid unnecessary unbinding of later objects in order to makr
522 * room for the earlier objects *unless* we need to defragment.
528 /* Unbind any ill-fitting objects or pin. */
529 list_for_each_entry(obj
, objects
, exec_list
) {
530 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
531 bool need_fence
, need_mappable
;
536 has_fenced_gpu_access
&&
537 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
538 obj
->tiling_mode
!= I915_TILING_NONE
;
540 entry
->relocation_count
? true : need_fence
;
542 if ((entry
->alignment
&& obj
->gtt_offset
& (entry
->alignment
- 1)) ||
543 (need_mappable
&& !obj
->map_and_fenceable
))
544 ret
= i915_gem_object_unbind(obj
);
546 ret
= i915_gem_object_pin(obj
,
555 /* Bind fresh objects */
556 list_for_each_entry(obj
, objects
, exec_list
) {
557 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
561 has_fenced_gpu_access
&&
562 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
563 obj
->tiling_mode
!= I915_TILING_NONE
;
565 if (!obj
->gtt_space
) {
567 entry
->relocation_count
? true : need_fence
;
569 ret
= i915_gem_object_pin(obj
,
576 if (has_fenced_gpu_access
) {
578 ret
= i915_gem_object_get_fence(obj
, ring
, 1);
581 } else if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
582 obj
->tiling_mode
== I915_TILING_NONE
) {
584 ret
= i915_gem_object_put_fence(obj
);
588 obj
->pending_fenced_gpu_access
= need_fence
;
591 entry
->offset
= obj
->gtt_offset
;
594 /* Decrement pin count for bound objects */
595 list_for_each_entry(obj
, objects
, exec_list
) {
597 i915_gem_object_unpin(obj
);
600 if (ret
!= -ENOSPC
|| retry
> 1)
603 /* First attempt, just clear anything that is purgeable.
604 * Second attempt, clear the entire GTT.
606 ret
= i915_gem_evict_everything(ring
->dev
, retry
== 0);
614 obj
= list_entry(obj
->exec_list
.prev
,
615 struct drm_i915_gem_object
,
617 while (objects
!= &obj
->exec_list
) {
619 i915_gem_object_unpin(obj
);
621 obj
= list_entry(obj
->exec_list
.prev
,
622 struct drm_i915_gem_object
,
630 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
631 struct drm_file
*file
,
632 struct intel_ring_buffer
*ring
,
633 struct list_head
*objects
,
634 struct eb_objects
*eb
,
635 struct drm_i915_gem_exec_object2
*exec
,
638 struct drm_i915_gem_relocation_entry
*reloc
;
639 struct drm_i915_gem_object
*obj
;
643 /* We may process another execbuffer during the unlock... */
644 while (!list_empty(objects
)) {
645 obj
= list_first_entry(objects
,
646 struct drm_i915_gem_object
,
648 list_del_init(&obj
->exec_list
);
649 drm_gem_object_unreference(&obj
->base
);
652 mutex_unlock(&dev
->struct_mutex
);
655 for (i
= 0; i
< count
; i
++)
656 total
+= exec
[i
].relocation_count
;
658 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
659 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
660 if (reloc
== NULL
|| reloc_offset
== NULL
) {
661 drm_free_large(reloc
);
662 drm_free_large(reloc_offset
);
663 mutex_lock(&dev
->struct_mutex
);
668 for (i
= 0; i
< count
; i
++) {
669 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
671 user_relocs
= (void __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
673 if (copy_from_user(reloc
+total
, user_relocs
,
674 exec
[i
].relocation_count
* sizeof(*reloc
))) {
676 mutex_lock(&dev
->struct_mutex
);
680 reloc_offset
[i
] = total
;
681 total
+= exec
[i
].relocation_count
;
684 ret
= i915_mutex_lock_interruptible(dev
);
686 mutex_lock(&dev
->struct_mutex
);
690 /* reacquire the objects */
692 for (i
= 0; i
< count
; i
++) {
693 struct drm_i915_gem_object
*obj
;
695 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
,
698 DRM_ERROR("Invalid object handle %d at index %d\n",
704 list_add_tail(&obj
->exec_list
, objects
);
705 obj
->exec_handle
= exec
[i
].handle
;
706 obj
->exec_entry
= &exec
[i
];
707 eb_add_object(eb
, obj
);
710 ret
= i915_gem_execbuffer_reserve(ring
, file
, objects
);
714 list_for_each_entry(obj
, objects
, exec_list
) {
715 int offset
= obj
->exec_entry
- exec
;
716 ret
= i915_gem_execbuffer_relocate_object_slow(obj
, eb
,
717 reloc
+ reloc_offset
[offset
]);
722 /* Leave the user relocations as are, this is the painfully slow path,
723 * and we want to avoid the complication of dropping the lock whilst
724 * having buffers reserved in the aperture and so causing spurious
725 * ENOSPC for random operations.
729 drm_free_large(reloc
);
730 drm_free_large(reloc_offset
);
735 i915_gem_execbuffer_flush(struct drm_device
*dev
,
736 uint32_t invalidate_domains
,
737 uint32_t flush_domains
,
738 uint32_t flush_rings
)
740 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
743 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
744 intel_gtt_chipset_flush();
746 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
749 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
750 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
751 if (flush_rings
& (1 << i
)) {
752 ret
= i915_gem_flush_ring(dev
,
765 i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object
*obj
,
766 struct intel_ring_buffer
*to
)
768 struct intel_ring_buffer
*from
= obj
->ring
;
772 if (from
== NULL
|| to
== from
)
775 /* XXX gpu semaphores are implicated in various hard hangs on SNB */
776 if (INTEL_INFO(obj
->base
.dev
)->gen
< 6 || !i915_semaphores
)
777 return i915_gem_object_wait_rendering(obj
, true);
779 idx
= intel_ring_sync_index(from
, to
);
781 seqno
= obj
->last_rendering_seqno
;
782 if (seqno
<= from
->sync_seqno
[idx
])
785 if (seqno
== from
->outstanding_lazy_request
) {
786 struct drm_i915_gem_request
*request
;
788 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
792 ret
= i915_add_request(obj
->base
.dev
, NULL
, request
, from
);
798 seqno
= request
->seqno
;
801 from
->sync_seqno
[idx
] = seqno
;
802 return intel_ring_sync(to
, from
, seqno
- 1);
806 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer
*ring
,
807 struct list_head
*objects
)
809 struct drm_i915_gem_object
*obj
;
810 struct change_domains cd
;
813 cd
.invalidate_domains
= 0;
814 cd
.flush_domains
= 0;
816 list_for_each_entry(obj
, objects
, exec_list
)
817 i915_gem_object_set_to_gpu_domain(obj
, ring
, &cd
);
819 if (cd
.invalidate_domains
| cd
.flush_domains
) {
821 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
823 cd
.invalidate_domains
,
826 ret
= i915_gem_execbuffer_flush(ring
->dev
,
827 cd
.invalidate_domains
,
834 list_for_each_entry(obj
, objects
, exec_list
) {
835 ret
= i915_gem_execbuffer_sync_rings(obj
, ring
);
844 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
846 return ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7) == 0;
850 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
855 for (i
= 0; i
< count
; i
++) {
856 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
857 int length
; /* limited by fault_in_pages_readable() */
859 /* First check for malicious input causing overflow */
860 if (exec
[i
].relocation_count
>
861 INT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
))
864 length
= exec
[i
].relocation_count
*
865 sizeof(struct drm_i915_gem_relocation_entry
);
866 if (!access_ok(VERIFY_READ
, ptr
, length
))
869 /* we may also need to update the presumed offsets */
870 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
873 if (fault_in_pages_readable(ptr
, length
))
881 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer
*ring
,
882 struct list_head
*objects
)
884 struct drm_i915_gem_object
*obj
;
887 /* Check for any pending flips. As we only maintain a flip queue depth
888 * of 1, we can simply insert a WAIT for the next display flip prior
889 * to executing the batch and avoid stalling the CPU.
892 list_for_each_entry(obj
, objects
, exec_list
) {
893 if (obj
->base
.write_domain
)
894 flips
|= atomic_read(&obj
->pending_flip
);
897 int plane
, flip_mask
, ret
;
899 for (plane
= 0; flips
>> plane
; plane
++) {
900 if (((flips
>> plane
) & 1) == 0)
904 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
906 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
908 ret
= intel_ring_begin(ring
, 2);
912 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
913 intel_ring_emit(ring
, MI_NOOP
);
914 intel_ring_advance(ring
);
922 i915_gem_execbuffer_move_to_active(struct list_head
*objects
,
923 struct intel_ring_buffer
*ring
,
926 struct drm_i915_gem_object
*obj
;
928 list_for_each_entry(obj
, objects
, exec_list
) {
929 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
930 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
931 obj
->fenced_gpu_access
= obj
->pending_fenced_gpu_access
;
933 i915_gem_object_move_to_active(obj
, ring
, seqno
);
934 if (obj
->base
.write_domain
) {
936 obj
->pending_gpu_write
= true;
937 list_move_tail(&obj
->gpu_write_list
,
938 &ring
->gpu_write_list
);
939 intel_mark_busy(ring
->dev
, obj
);
942 trace_i915_gem_object_change_domain(obj
,
943 obj
->base
.read_domains
,
944 obj
->base
.write_domain
);
949 i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
950 struct drm_file
*file
,
951 struct intel_ring_buffer
*ring
)
953 struct drm_i915_gem_request
*request
;
957 * Ensure that the commands in the batch buffer are
958 * finished before the interrupt fires.
960 * The sampler always gets flushed on i965 (sigh).
962 invalidate
= I915_GEM_DOMAIN_COMMAND
;
963 if (INTEL_INFO(dev
)->gen
>= 4)
964 invalidate
|= I915_GEM_DOMAIN_SAMPLER
;
965 if (ring
->flush(ring
, invalidate
, 0)) {
966 i915_gem_next_request_seqno(dev
, ring
);
970 /* Add a breadcrumb for the completion of the batch buffer */
971 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
972 if (request
== NULL
|| i915_add_request(dev
, file
, request
, ring
)) {
973 i915_gem_next_request_seqno(dev
, ring
);
979 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
980 struct drm_file
*file
,
981 struct drm_i915_gem_execbuffer2
*args
,
982 struct drm_i915_gem_exec_object2
*exec
)
984 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
985 struct list_head objects
;
986 struct eb_objects
*eb
;
987 struct drm_i915_gem_object
*batch_obj
;
988 struct drm_clip_rect
*cliprects
= NULL
;
989 struct intel_ring_buffer
*ring
;
990 u32 exec_start
, exec_len
;
994 if (!i915_gem_check_execbuffer(args
)) {
995 DRM_ERROR("execbuf with invalid offset/length\n");
999 ret
= validate_exec_list(exec
, args
->buffer_count
);
1004 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1005 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
1007 switch (args
->flags
& I915_EXEC_RING_MASK
) {
1008 case I915_EXEC_DEFAULT
:
1009 case I915_EXEC_RENDER
:
1010 ring
= &dev_priv
->ring
[RCS
];
1013 if (!HAS_BSD(dev
)) {
1014 DRM_ERROR("execbuf with invalid ring (BSD)\n");
1017 ring
= &dev_priv
->ring
[VCS
];
1020 if (!HAS_BLT(dev
)) {
1021 DRM_ERROR("execbuf with invalid ring (BLT)\n");
1024 ring
= &dev_priv
->ring
[BCS
];
1027 DRM_ERROR("execbuf with unknown ring: %d\n",
1028 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1032 mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1034 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1035 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1036 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1037 if (ring
== &dev_priv
->ring
[RCS
] &&
1038 mode
!= dev_priv
->relative_constants_mode
) {
1039 if (INTEL_INFO(dev
)->gen
< 4)
1042 if (INTEL_INFO(dev
)->gen
> 5 &&
1043 mode
== I915_EXEC_CONSTANTS_REL_SURFACE
)
1046 ret
= intel_ring_begin(ring
, 4);
1050 intel_ring_emit(ring
, MI_NOOP
);
1051 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1052 intel_ring_emit(ring
, INSTPM
);
1053 intel_ring_emit(ring
,
1054 I915_EXEC_CONSTANTS_MASK
<< 16 | mode
);
1055 intel_ring_advance(ring
);
1057 dev_priv
->relative_constants_mode
= mode
;
1061 DRM_ERROR("execbuf with unknown constants: %d\n", mode
);
1065 if (args
->buffer_count
< 1) {
1066 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
1070 if (args
->num_cliprects
!= 0) {
1071 if (ring
!= &dev_priv
->ring
[RCS
]) {
1072 DRM_ERROR("clip rectangles are only valid with the render ring\n");
1076 cliprects
= kmalloc(args
->num_cliprects
* sizeof(*cliprects
),
1078 if (cliprects
== NULL
) {
1083 if (copy_from_user(cliprects
,
1084 (struct drm_clip_rect __user
*)(uintptr_t)
1085 args
->cliprects_ptr
,
1086 sizeof(*cliprects
)*args
->num_cliprects
)) {
1092 ret
= i915_mutex_lock_interruptible(dev
);
1096 if (dev_priv
->mm
.suspended
) {
1097 mutex_unlock(&dev
->struct_mutex
);
1102 eb
= eb_create(args
->buffer_count
);
1104 mutex_unlock(&dev
->struct_mutex
);
1109 /* Look up object handles */
1110 INIT_LIST_HEAD(&objects
);
1111 for (i
= 0; i
< args
->buffer_count
; i
++) {
1112 struct drm_i915_gem_object
*obj
;
1114 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
,
1117 DRM_ERROR("Invalid object handle %d at index %d\n",
1119 /* prevent error path from reading uninitialized data */
1124 if (!list_empty(&obj
->exec_list
)) {
1125 DRM_ERROR("Object %p [handle %d, index %d] appears more than once in object list\n",
1126 obj
, exec
[i
].handle
, i
);
1131 list_add_tail(&obj
->exec_list
, &objects
);
1132 obj
->exec_handle
= exec
[i
].handle
;
1133 obj
->exec_entry
= &exec
[i
];
1134 eb_add_object(eb
, obj
);
1137 /* take note of the batch buffer before we might reorder the lists */
1138 batch_obj
= list_entry(objects
.prev
,
1139 struct drm_i915_gem_object
,
1142 /* Move the objects en-masse into the GTT, evicting if necessary. */
1143 ret
= i915_gem_execbuffer_reserve(ring
, file
, &objects
);
1147 /* The objects are in their final locations, apply the relocations. */
1148 ret
= i915_gem_execbuffer_relocate(dev
, eb
, &objects
);
1150 if (ret
== -EFAULT
) {
1151 ret
= i915_gem_execbuffer_relocate_slow(dev
, file
, ring
,
1154 args
->buffer_count
);
1155 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1161 /* Set the pending read domains for the batch buffer to COMMAND */
1162 if (batch_obj
->base
.pending_write_domain
) {
1163 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
1167 batch_obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1169 ret
= i915_gem_execbuffer_move_to_gpu(ring
, &objects
);
1173 ret
= i915_gem_execbuffer_wait_for_flips(ring
, &objects
);
1177 seqno
= i915_gem_next_request_seqno(dev
, ring
);
1178 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++) {
1179 if (seqno
< ring
->sync_seqno
[i
]) {
1180 /* The GPU can not handle its semaphore value wrapping,
1181 * so every billion or so execbuffers, we need to stall
1182 * the GPU in order to reset the counters.
1184 ret
= i915_gpu_idle(dev
);
1188 BUG_ON(ring
->sync_seqno
[i
]);
1192 exec_start
= batch_obj
->gtt_offset
+ args
->batch_start_offset
;
1193 exec_len
= args
->batch_len
;
1195 for (i
= 0; i
< args
->num_cliprects
; i
++) {
1196 ret
= i915_emit_box(dev
, &cliprects
[i
],
1197 args
->DR1
, args
->DR4
);
1201 ret
= ring
->dispatch_execbuffer(ring
,
1202 exec_start
, exec_len
);
1207 ret
= ring
->dispatch_execbuffer(ring
, exec_start
, exec_len
);
1212 i915_gem_execbuffer_move_to_active(&objects
, ring
, seqno
);
1213 i915_gem_execbuffer_retire_commands(dev
, file
, ring
);
1217 while (!list_empty(&objects
)) {
1218 struct drm_i915_gem_object
*obj
;
1220 obj
= list_first_entry(&objects
,
1221 struct drm_i915_gem_object
,
1223 list_del_init(&obj
->exec_list
);
1224 drm_gem_object_unreference(&obj
->base
);
1227 mutex_unlock(&dev
->struct_mutex
);
1235 * Legacy execbuffer just creates an exec2 list from the original exec object
1236 * list array and passes it to the real function.
1239 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1240 struct drm_file
*file
)
1242 struct drm_i915_gem_execbuffer
*args
= data
;
1243 struct drm_i915_gem_execbuffer2 exec2
;
1244 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1245 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1249 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1250 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
1253 if (args
->buffer_count
< 1) {
1254 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
1258 /* Copy in the exec list from userland */
1259 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1260 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1261 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1262 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1263 args
->buffer_count
);
1264 drm_free_large(exec_list
);
1265 drm_free_large(exec2_list
);
1268 ret
= copy_from_user(exec_list
,
1269 (struct drm_i915_relocation_entry __user
*)
1270 (uintptr_t) args
->buffers_ptr
,
1271 sizeof(*exec_list
) * args
->buffer_count
);
1273 DRM_ERROR("copy %d exec entries failed %d\n",
1274 args
->buffer_count
, ret
);
1275 drm_free_large(exec_list
);
1276 drm_free_large(exec2_list
);
1280 for (i
= 0; i
< args
->buffer_count
; i
++) {
1281 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1282 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1283 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1284 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1285 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1286 if (INTEL_INFO(dev
)->gen
< 4)
1287 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1289 exec2_list
[i
].flags
= 0;
1292 exec2
.buffers_ptr
= args
->buffers_ptr
;
1293 exec2
.buffer_count
= args
->buffer_count
;
1294 exec2
.batch_start_offset
= args
->batch_start_offset
;
1295 exec2
.batch_len
= args
->batch_len
;
1296 exec2
.DR1
= args
->DR1
;
1297 exec2
.DR4
= args
->DR4
;
1298 exec2
.num_cliprects
= args
->num_cliprects
;
1299 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1300 exec2
.flags
= I915_EXEC_RENDER
;
1302 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1304 /* Copy the new buffer offsets back to the user's exec list. */
1305 for (i
= 0; i
< args
->buffer_count
; i
++)
1306 exec_list
[i
].offset
= exec2_list
[i
].offset
;
1307 /* ... and back out to userspace */
1308 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
1309 (uintptr_t) args
->buffers_ptr
,
1311 sizeof(*exec_list
) * args
->buffer_count
);
1314 DRM_ERROR("failed to copy %d exec entries "
1315 "back to user (%d)\n",
1316 args
->buffer_count
, ret
);
1320 drm_free_large(exec_list
);
1321 drm_free_large(exec2_list
);
1326 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1327 struct drm_file
*file
)
1329 struct drm_i915_gem_execbuffer2
*args
= data
;
1330 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1334 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1335 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
1338 if (args
->buffer_count
< 1) {
1339 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
1343 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1344 if (exec2_list
== NULL
) {
1345 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1346 args
->buffer_count
);
1349 ret
= copy_from_user(exec2_list
,
1350 (struct drm_i915_relocation_entry __user
*)
1351 (uintptr_t) args
->buffers_ptr
,
1352 sizeof(*exec2_list
) * args
->buffer_count
);
1354 DRM_ERROR("copy %d exec entries failed %d\n",
1355 args
->buffer_count
, ret
);
1356 drm_free_large(exec2_list
);
1360 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1362 /* Copy the new buffer offsets back to the user's exec list. */
1363 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
1364 (uintptr_t) args
->buffers_ptr
,
1366 sizeof(*exec2_list
) * args
->buffer_count
);
1369 DRM_ERROR("failed to copy %d exec entries "
1370 "back to user (%d)\n",
1371 args
->buffer_count
, ret
);
1375 drm_free_large(exec2_list
);