2 * Copyright © 2006-2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include "framebuffer.h"
28 #include "psb_intel_display.h"
29 #include "mdfld_dsi_dbi.h"
30 #include "mdfld_dsi_dpi.h"
31 #include "mdfld_dsi_dbi_dpu.h"
33 #include <linux/pm_runtime.h>
39 #define MIN(x, y) (((x) < (y)) ? (x) : (y))
41 /* Hardcoded currently */
42 static int ksel
= KSEL_CRYSTAL_19
;
44 extern void mdfld_save_display(struct drm_device
*dev
);
45 extern bool gbgfxsuspended
;
47 struct psb_intel_range_t
{
51 struct mdfld_limit_t
{
52 struct psb_intel_range_t dot
, m
, p1
;
55 struct mdfld_intel_clock_t
{
69 #define COUNT_MAX 0x10000000
71 void mdfldWaitForPipeDisable(struct drm_device
*dev
, int pipe
)
74 u32 pipeconf_reg
= PIPEACONF
;
80 pipeconf_reg
= PIPEBCONF
;
83 pipeconf_reg
= PIPECCONF
;
86 DRM_ERROR("Illegal Pipe Number. \n");
91 psb_intel_wait_for_vblank(dev
);
94 /* Wait for for the pipe disable to take effect. */
95 for (count
= 0; count
< COUNT_MAX
; count
++) {
96 temp
= REG_READ(pipeconf_reg
);
97 if ((temp
& PIPEACONF_PIPE_STATE
) == 0)
102 void mdfldWaitForPipeEnable(struct drm_device
*dev
, int pipe
)
105 u32 pipeconf_reg
= PIPEACONF
;
111 pipeconf_reg
= PIPEBCONF
;
114 pipeconf_reg
= PIPECCONF
;
117 dev_err(dev
->dev
, "Illegal Pipe Number.\n");
122 psb_intel_wait_for_vblank(dev
);
125 /* Wait for for the pipe enable to take effect. */
126 for (count
= 0; count
< COUNT_MAX
; count
++) {
127 temp
= REG_READ(pipeconf_reg
);
128 if ((temp
& PIPEACONF_PIPE_STATE
) == 1)
134 static int mdfld_intel_crtc_cursor_set(struct drm_crtc
*crtc
,
135 struct drm_file
*file_priv
,
137 uint32_t width
, uint32_t height
)
139 struct drm_device
*dev
= crtc
->dev
;
140 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
141 int pipe
= psb_intel_crtc
->pipe
;
142 uint32_t control
= CURACNTR
;
143 uint32_t base
= CURABASE
;
146 struct gtt_range
*gt
;
147 struct drm_gem_object
*obj
;
162 dev_err(dev
->dev
, "Illegal Pipe Number. \n");
166 #if 1 /* FIXME_JLIU7 can't enalbe cursorB/C HW issue. need to remove after HW fix */
170 /* if we want to turn of the cursor ignore width and height */
172 dev_dbg(dev
->dev
, "cursor off\n");
173 /* turn off the cursor */
175 temp
|= CURSOR_MODE_DISABLE
;
177 if (gma_power_begin(dev
, true)) {
178 REG_WRITE(control
, temp
);
182 /* Unpin the old GEM object */
183 if (psb_intel_crtc
->cursor_obj
) {
184 gt
= container_of(psb_intel_crtc
->cursor_obj
,
185 struct gtt_range
, gem
);
187 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
188 psb_intel_crtc
->cursor_obj
= NULL
;
193 /* Currently we only support 64x64 cursors */
194 if (width
!= 64 || height
!= 64) {
195 DRM_ERROR("we currently only support 64x64 cursors\n");
199 obj
= drm_gem_object_lookup(dev
, file_priv
, handle
);
203 if (obj
->size
< width
* height
* 4) {
204 dev_dbg(dev
->dev
, "buffer is to small\n");
208 gt
= container_of(obj
, struct gtt_range
, gem
);
210 /* Pin the memory into the GTT */
211 ret
= psb_gtt_pin(gt
);
213 dev_err(dev
->dev
, "Can not pin down handle 0x%x\n", handle
);
218 addr
= gt
->offset
; /* Or resource.start ??? */
220 psb_intel_crtc
->cursor_addr
= addr
;
223 /* set the pipe for the cursor */
224 temp
|= (pipe
<< 28);
225 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
227 if (gma_power_begin(dev
, true)) {
228 REG_WRITE(control
, temp
);
229 REG_WRITE(base
, addr
);
232 /* unpin the old GEM object */
233 if (psb_intel_crtc
->cursor_obj
) {
234 gt
= container_of(psb_intel_crtc
->cursor_obj
,
235 struct gtt_range
, gem
);
237 drm_gem_object_unreference(psb_intel_crtc
->cursor_obj
);
238 psb_intel_crtc
->cursor_obj
= obj
;
243 static int mdfld_intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
245 struct drm_device
*dev
= crtc
->dev
;
246 struct drm_psb_private
* dev_priv
= (struct drm_psb_private
*)dev
->dev_private
;
247 struct mdfld_dbi_dpu_info
*dpu_info
= dev_priv
->dbi_dpu_info
;
248 struct psb_drm_dpu_rect rect
;
249 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
250 int pipe
= psb_intel_crtc
->pipe
;
251 uint32_t pos
= CURAPOS
;
252 uint32_t base
= CURABASE
;
262 mdfld_dbi_dpu_report_damage(dev
, MDFLD_CURSORA
, &rect
);
263 mdfld_dpu_exit_dsr(dev
);
264 } else if (!(dev_priv
->dsr_fb_update
& MDFLD_DSR_CURSOR_0
))
265 mdfld_dsi_dbi_exit_dsr(dev
, MDFLD_DSR_CURSOR_0
);
273 mdfld_dbi_dpu_report_damage(dev
, MDFLD_CURSORC
, &rect
);
274 mdfld_dpu_exit_dsr(dev
);
275 } else if (!(dev_priv
->dsr_fb_update
& MDFLD_DSR_CURSOR_2
))
276 mdfld_dsi_dbi_exit_dsr(dev
, MDFLD_DSR_CURSOR_2
);
281 DRM_ERROR("Illegal Pipe Number. \n");
285 #if 1 /* FIXME_JLIU7 can't enable cursorB/C HW issue. need to remove after HW fix */
290 temp
|= (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
);
294 temp
|= (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
);
298 temp
|= ((x
& CURSOR_POS_MASK
) << CURSOR_X_SHIFT
);
299 temp
|= ((y
& CURSOR_POS_MASK
) << CURSOR_Y_SHIFT
);
301 addr
= psb_intel_crtc
->cursor_addr
;
303 if (gma_power_begin(dev
, true)) {
304 REG_WRITE(pos
, temp
);
305 REG_WRITE(base
, addr
);
312 const struct drm_crtc_funcs mdfld_intel_crtc_funcs
= {
313 .cursor_set
= mdfld_intel_crtc_cursor_set
,
314 .cursor_move
= mdfld_intel_crtc_cursor_move
,
315 .gamma_set
= psb_intel_crtc_gamma_set
,
316 .set_config
= drm_crtc_helper_set_config
,
317 .destroy
= psb_intel_crtc_destroy
,
320 static struct drm_device globle_dev
;
322 void mdfld__intel_plane_set_alpha(int enable
)
324 struct drm_device
*dev
= &globle_dev
;
325 int dspcntr_reg
= DSPACNTR
;
328 dspcntr
= REG_READ(dspcntr_reg
);
331 dspcntr
&= ~DISPPLANE_32BPP_NO_ALPHA
;
332 dspcntr
|= DISPPLANE_32BPP
;
334 dspcntr
&= ~DISPPLANE_32BPP
;
335 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
338 REG_WRITE(dspcntr_reg
, dspcntr
);
341 int mdfld__intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
, struct drm_framebuffer
*old_fb
)
343 struct drm_device
*dev
= crtc
->dev
;
344 /* struct drm_i915_master_private *master_priv; */
345 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
346 struct psb_framebuffer
*psbfb
= to_psb_fb(crtc
->fb
);
347 int pipe
= psb_intel_crtc
->pipe
;
348 unsigned long start
, offset
;
349 int dsplinoff
= DSPALINOFF
;
350 int dspsurf
= DSPASURF
;
351 int dspstride
= DSPASTRIDE
;
352 int dspcntr_reg
= DSPACNTR
;
356 memcpy(&globle_dev
, dev
, sizeof(struct drm_device
));
358 if (!gma_power_begin(dev
, true))
363 dev_err(dev
->dev
, "No FB bound\n");
364 goto psb_intel_pipe_cleaner
;
369 dsplinoff
= DSPALINOFF
;
372 dsplinoff
= DSPBLINOFF
;
374 dspstride
= DSPBSTRIDE
;
375 dspcntr_reg
= DSPBCNTR
;
378 dsplinoff
= DSPCLINOFF
;
380 dspstride
= DSPCSTRIDE
;
381 dspcntr_reg
= DSPCCNTR
;
384 dev_err(dev
->dev
, "Illegal Pipe Number.\n");
388 ret
= psb_gtt_pin(psbfb
->gtt
);
390 goto psb_intel_pipe_set_base_exit
;
392 start
= psbfb
->gtt
->offset
;
393 offset
= y
* crtc
->fb
->pitches
[0] + x
* (crtc
->fb
->bits_per_pixel
/ 8);
395 REG_WRITE(dspstride
, crtc
->fb
->pitches
[0]);
396 dspcntr
= REG_READ(dspcntr_reg
);
397 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
399 switch (crtc
->fb
->bits_per_pixel
) {
401 dspcntr
|= DISPPLANE_8BPP
;
404 if (crtc
->fb
->depth
== 15)
405 dspcntr
|= DISPPLANE_15_16BPP
;
407 dspcntr
|= DISPPLANE_16BPP
;
411 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
414 dev_err(dev
->dev
, "Unknown color depth\n");
416 goto psb_intel_pipe_set_base_exit
;
418 REG_WRITE(dspcntr_reg
, dspcntr
);
420 dev_dbg(dev
->dev
, "Writing base %08lX %08lX %d %d\n",
421 start
, offset
, x
, y
);
423 REG_WRITE(dsplinoff
, offset
);
425 REG_WRITE(dspsurf
, start
);
428 psb_intel_pipe_cleaner
:
429 /* If there was a previous display we can now unpin it */
431 psb_gtt_unpin(to_psb_fb(old_fb
)->gtt
);
433 psb_intel_pipe_set_base_exit
:
439 * Disable the pipe, plane and pll.
442 void mdfld_disable_crtc (struct drm_device
*dev
, int pipe
)
444 int dpll_reg
= MRST_DPLL_A
;
445 int dspcntr_reg
= DSPACNTR
;
446 int dspbase_reg
= MRST_DSPABASE
;
447 int pipeconf_reg
= PIPEACONF
;
448 u32 gen_fifo_stat_reg
= GEN_FIFO_STAT_REG
;
455 dpll_reg
= MDFLD_DPLL_B
;
456 dspcntr_reg
= DSPBCNTR
;
457 dspbase_reg
= DSPBSURF
;
458 pipeconf_reg
= PIPEBCONF
;
461 dpll_reg
= MRST_DPLL_A
;
462 dspcntr_reg
= DSPCCNTR
;
463 dspbase_reg
= MDFLD_DSPCBASE
;
464 pipeconf_reg
= PIPECCONF
;
465 gen_fifo_stat_reg
= GEN_FIFO_STAT_REG
+ MIPIC_REG_OFFSET
;
468 dev_err(dev
->dev
, "Illegal Pipe Number. \n");
473 mdfld_dsi_gen_fifo_ready (dev
, gen_fifo_stat_reg
, HS_CTRL_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
);
475 /* Disable display plane */
476 temp
= REG_READ(dspcntr_reg
);
477 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
478 REG_WRITE(dspcntr_reg
,
479 temp
& ~DISPLAY_PLANE_ENABLE
);
480 /* Flush the plane changes */
481 REG_WRITE(dspbase_reg
, REG_READ(dspbase_reg
));
482 REG_READ(dspbase_reg
);
485 /* FIXME_JLIU7 MDFLD_PO revisit */
486 /* Wait for vblank for the disable to take effect */
487 /* MDFLD_PO_JLIU7 psb_intel_wait_for_vblank(dev); */
489 /* Next, disable display pipes */
490 temp
= REG_READ(pipeconf_reg
);
491 if ((temp
& PIPEACONF_ENABLE
) != 0) {
492 temp
&= ~PIPEACONF_ENABLE
;
493 temp
|= PIPECONF_PLANE_OFF
| PIPECONF_CURSOR_OFF
;
494 REG_WRITE(pipeconf_reg
, temp
);
495 REG_READ(pipeconf_reg
);
497 /* Wait for for the pipe disable to take effect. */
498 mdfldWaitForPipeDisable(dev
, pipe
);
501 temp
= REG_READ(dpll_reg
);
502 if (temp
& DPLL_VCO_ENABLE
) {
503 if (((pipe
!= 1) && !((REG_READ(PIPEACONF
) | REG_READ(PIPECCONF
)) & PIPEACONF_ENABLE
))
505 temp
&= ~(DPLL_VCO_ENABLE
);
506 REG_WRITE(dpll_reg
, temp
);
508 /* Wait for the clocks to turn off. */
509 /* FIXME_MDFLD PO may need more delay */
512 if (!(temp
& MDFLD_PWR_GATE_EN
)) {
513 /* gating power of DPLL */
514 REG_WRITE(dpll_reg
, temp
| MDFLD_PWR_GATE_EN
);
515 /* FIXME_MDFLD PO - change 500 to 1 after PO */
524 * Sets the power management mode of the pipe and plane.
526 * This code should probably grow support for turning the cursor off and back
527 * on appropriately at the same time as we're turning the pipe off/on.
529 static void mdfld_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
531 struct drm_device
*dev
= crtc
->dev
;
532 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
533 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
534 int pipe
= psb_intel_crtc
->pipe
;
535 int dpll_reg
= MRST_DPLL_A
;
536 int dspcntr_reg
= DSPACNTR
;
537 int dspbase_reg
= MRST_DSPABASE
;
538 int pipeconf_reg
= PIPEACONF
;
539 u32 pipestat_reg
= PIPEASTAT
;
540 u32 gen_fifo_stat_reg
= GEN_FIFO_STAT_REG
;
541 u32 pipeconf
= dev_priv
->pipeconf
;
542 u32 dspcntr
= dev_priv
->dspcntr
;
543 u32 mipi_enable_reg
= MIPIA_DEVICE_READY_REG
;
548 if (!gma_power_begin(dev
, true))
551 /* Ignore if system is already in DSR and in suspended state. */
552 if(/*gbgfxsuspended */0 && dev_priv
->dispstatus
== false && mode
== 3){
553 if(dev_priv
->rpm_enabled
&& pipe
== 1){
554 // dev_priv->is_mipi_on = false;
555 pm_request_idle(&dev
->pdev
->dev
);
558 }else if(mode
== 0) {
559 //do not need to set gbdispstatus=true in crtc.
560 //this will be set in encoder such as mdfld_dsi_dbi_dpms
561 //gbdispstatus = true;
564 /* FIXME_JLIU7 MDFLD_PO replaced w/ the following function */
565 /* mdfld_dbi_dpms (struct drm_device *dev, int pipe, bool enabled) */
572 dspcntr_reg
= DSPBCNTR
;
573 dspbase_reg
= MRST_DSPBBASE
;
574 pipeconf_reg
= PIPEBCONF
;
575 pipeconf
= dev_priv
->pipeconf1
;
576 dspcntr
= dev_priv
->dspcntr1
;
577 dpll_reg
= MDFLD_DPLL_B
;
580 dpll_reg
= MRST_DPLL_A
;
581 dspcntr_reg
= DSPCCNTR
;
582 dspbase_reg
= MDFLD_DSPCBASE
;
583 pipeconf_reg
= PIPECCONF
;
584 pipestat_reg
= PIPECSTAT
;
585 pipeconf
= dev_priv
->pipeconf2
;
586 dspcntr
= dev_priv
->dspcntr2
;
587 gen_fifo_stat_reg
= GEN_FIFO_STAT_REG
+ MIPIC_REG_OFFSET
;
588 mipi_enable_reg
= MIPIA_DEVICE_READY_REG
+ MIPIC_REG_OFFSET
;
591 dev_err(dev
->dev
, "Illegal Pipe Number.\n");
595 /* XXX: When our outputs are all unaware of DPMS modes other than off
596 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
599 case DRM_MODE_DPMS_ON
:
600 case DRM_MODE_DPMS_STANDBY
:
601 case DRM_MODE_DPMS_SUSPEND
:
602 /* Enable the DPLL */
603 temp
= REG_READ(dpll_reg
);
605 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
606 /* When ungating power of DPLL, needs to wait 0.5us before enable the VCO */
607 if (temp
& MDFLD_PWR_GATE_EN
) {
608 temp
&= ~MDFLD_PWR_GATE_EN
;
609 REG_WRITE(dpll_reg
, temp
);
610 /* FIXME_MDFLD PO - change 500 to 1 after PO */
614 REG_WRITE(dpll_reg
, temp
);
616 /* FIXME_MDFLD PO - change 500 to 1 after PO */
619 REG_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
623 * wait for DSI PLL to lock
624 * NOTE: only need to poll status of pipe 0 and pipe 1,
625 * since both MIPI pipes share the same PLL.
627 while ((pipe
!= 2) && (timeout
< 20000) && !(REG_READ(pipeconf_reg
) & PIPECONF_DSIPLL_LOCK
)) {
633 /* Enable the plane */
634 temp
= REG_READ(dspcntr_reg
);
635 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
636 REG_WRITE(dspcntr_reg
,
637 temp
| DISPLAY_PLANE_ENABLE
);
638 /* Flush the plane changes */
639 REG_WRITE(dspbase_reg
, REG_READ(dspbase_reg
));
642 /* Enable the pipe */
643 temp
= REG_READ(pipeconf_reg
);
644 if ((temp
& PIPEACONF_ENABLE
) == 0) {
645 REG_WRITE(pipeconf_reg
, pipeconf
);
647 /* Wait for for the pipe enable to take effect. */
648 mdfldWaitForPipeEnable(dev
, pipe
);
651 /*workaround for sighting 3741701 Random X blank display*/
652 /*perform w/a in video mode only on pipe A or C*/
653 if ((pipe
== 0 || pipe
== 2) &&
654 (mdfld_panel_dpi(dev
) == true)) {
655 REG_WRITE(pipestat_reg
, REG_READ(pipestat_reg
));
657 if(PIPE_VBLANK_STATUS
& REG_READ(pipestat_reg
)) {
658 printk(KERN_ALERT
"OK");
660 printk(KERN_ALERT
"STUCK!!!!");
661 /*shutdown controller*/
662 temp
= REG_READ(dspcntr_reg
);
663 REG_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
664 REG_WRITE(dspbase_reg
, REG_READ(dspbase_reg
));
665 /*mdfld_dsi_dpi_shut_down(dev, pipe);*/
666 REG_WRITE(0xb048, 1);
668 temp
= REG_READ(pipeconf_reg
);
669 temp
&= ~PIPEACONF_ENABLE
;
670 REG_WRITE(pipeconf_reg
, temp
);
671 msleep(100); /*wait for pipe disable*/
672 /*printk(KERN_ALERT "70008 is %x\n", REG_READ(0x70008));
673 printk(KERN_ALERT "b074 is %x\n", REG_READ(0xb074));*/
674 REG_WRITE(mipi_enable_reg
, 0);
676 printk(KERN_ALERT
"70008 is %x\n", REG_READ(0x70008));
677 printk(KERN_ALERT
"b074 is %x\n", REG_READ(0xb074));
678 REG_WRITE(0xb004, REG_READ(0xb004));
679 /* try to bring the controller back up again*/
680 REG_WRITE(mipi_enable_reg
, 1);
681 temp
= REG_READ(dspcntr_reg
);
682 REG_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
683 REG_WRITE(dspbase_reg
, REG_READ(dspbase_reg
));
684 /*mdfld_dsi_dpi_turn_on(dev, pipe);*/
685 REG_WRITE(0xb048, 2);
687 temp
= REG_READ(pipeconf_reg
);
688 temp
|= PIPEACONF_ENABLE
;
689 REG_WRITE(pipeconf_reg
, temp
);
693 psb_intel_crtc_load_lut(crtc
);
695 /* Give the overlay scaler a chance to enable
696 if it's on this pipe */
697 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
700 case DRM_MODE_DPMS_OFF
:
701 /* Give the overlay scaler a chance to disable
702 * if it's on this pipe */
703 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
705 mdfld_dsi_gen_fifo_ready (dev
, gen_fifo_stat_reg
, HS_CTRL_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
);
707 /* Disable the VGA plane that we never use */
708 REG_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
710 /* Disable display plane */
711 temp
= REG_READ(dspcntr_reg
);
712 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
713 REG_WRITE(dspcntr_reg
,
714 temp
& ~DISPLAY_PLANE_ENABLE
);
715 /* Flush the plane changes */
716 REG_WRITE(dspbase_reg
, REG_READ(dspbase_reg
));
717 REG_READ(dspbase_reg
);
720 /* FIXME_JLIU7 MDFLD_PO revisit */
721 /* Wait for vblank for the disable to take effect */
722 // MDFLD_PO_JLIU7 psb_intel_wait_for_vblank(dev);
724 /* Next, disable display pipes */
725 temp
= REG_READ(pipeconf_reg
);
726 if ((temp
& PIPEACONF_ENABLE
) != 0) {
727 temp
&= ~PIPEACONF_ENABLE
;
728 temp
|= PIPECONF_PLANE_OFF
| PIPECONF_CURSOR_OFF
;
729 REG_WRITE(pipeconf_reg
, temp
);
730 // REG_WRITE(pipeconf_reg, 0);
731 REG_READ(pipeconf_reg
);
733 /* Wait for for the pipe disable to take effect. */
734 mdfldWaitForPipeDisable(dev
, pipe
);
737 temp
= REG_READ(dpll_reg
);
738 if (temp
& DPLL_VCO_ENABLE
) {
739 if (((pipe
!= 1) && !((REG_READ(PIPEACONF
) | REG_READ(PIPECCONF
)) & PIPEACONF_ENABLE
))
741 temp
&= ~(DPLL_VCO_ENABLE
);
742 REG_WRITE(dpll_reg
, temp
);
744 /* Wait for the clocks to turn off. */
745 /* FIXME_MDFLD PO may need more delay */
747 #if 0 /* MDFLD_PO_JLIU7 */
748 if (!(temp
& MDFLD_PWR_GATE_EN
)) {
749 /* gating power of DPLL */
750 REG_WRITE(dpll_reg
, temp
| MDFLD_PWR_GATE_EN
);
751 /* FIXME_MDFLD PO - change 500 to 1 after PO */
754 #endif /* MDFLD_PO_JLIU7 */
760 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
762 #if 0 /* JB: Add vblank support later */
764 dev_priv
->vblank_pipe
|= (1 << pipe
);
766 dev_priv
->vblank_pipe
&= ~(1 << pipe
);
773 #define MDFLD_LIMT_DPLL_19 0
774 #define MDFLD_LIMT_DPLL_25 1
775 #define MDFLD_LIMT_DPLL_83 2
776 #define MDFLD_LIMT_DPLL_100 3
777 #define MDFLD_LIMT_DSIPLL_19 4
778 #define MDFLD_LIMT_DSIPLL_25 5
779 #define MDFLD_LIMT_DSIPLL_83 6
780 #define MDFLD_LIMT_DSIPLL_100 7
782 #define MDFLD_DOT_MIN 19750 /* FIXME_MDFLD JLIU7 need to find out min & max for MDFLD */
783 #define MDFLD_DOT_MAX 120000
784 #define MDFLD_DPLL_M_MIN_19 113
785 #define MDFLD_DPLL_M_MAX_19 155
786 #define MDFLD_DPLL_P1_MIN_19 2
787 #define MDFLD_DPLL_P1_MAX_19 10
788 #define MDFLD_DPLL_M_MIN_25 101
789 #define MDFLD_DPLL_M_MAX_25 130
790 #define MDFLD_DPLL_P1_MIN_25 2
791 #define MDFLD_DPLL_P1_MAX_25 10
792 #define MDFLD_DPLL_M_MIN_83 64
793 #define MDFLD_DPLL_M_MAX_83 64
794 #define MDFLD_DPLL_P1_MIN_83 2
795 #define MDFLD_DPLL_P1_MAX_83 2
796 #define MDFLD_DPLL_M_MIN_100 64
797 #define MDFLD_DPLL_M_MAX_100 64
798 #define MDFLD_DPLL_P1_MIN_100 2
799 #define MDFLD_DPLL_P1_MAX_100 2
800 #define MDFLD_DSIPLL_M_MIN_19 131
801 #define MDFLD_DSIPLL_M_MAX_19 175
802 #define MDFLD_DSIPLL_P1_MIN_19 3
803 #define MDFLD_DSIPLL_P1_MAX_19 8
804 #define MDFLD_DSIPLL_M_MIN_25 97
805 #define MDFLD_DSIPLL_M_MAX_25 140
806 #define MDFLD_DSIPLL_P1_MIN_25 3
807 #define MDFLD_DSIPLL_P1_MAX_25 9
808 #define MDFLD_DSIPLL_M_MIN_83 33
809 #define MDFLD_DSIPLL_M_MAX_83 92
810 #define MDFLD_DSIPLL_P1_MIN_83 2
811 #define MDFLD_DSIPLL_P1_MAX_83 3
812 #define MDFLD_DSIPLL_M_MIN_100 97
813 #define MDFLD_DSIPLL_M_MAX_100 140
814 #define MDFLD_DSIPLL_P1_MIN_100 3
815 #define MDFLD_DSIPLL_P1_MAX_100 9
817 static const struct mdfld_limit_t mdfld_limits
[] = {
818 { /* MDFLD_LIMT_DPLL_19 */
819 .dot
= {.min
= MDFLD_DOT_MIN
, .max
= MDFLD_DOT_MAX
},
820 .m
= {.min
= MDFLD_DPLL_M_MIN_19
, .max
= MDFLD_DPLL_M_MAX_19
},
821 .p1
= {.min
= MDFLD_DPLL_P1_MIN_19
, .max
= MDFLD_DPLL_P1_MAX_19
},
823 { /* MDFLD_LIMT_DPLL_25 */
824 .dot
= {.min
= MDFLD_DOT_MIN
, .max
= MDFLD_DOT_MAX
},
825 .m
= {.min
= MDFLD_DPLL_M_MIN_25
, .max
= MDFLD_DPLL_M_MAX_25
},
826 .p1
= {.min
= MDFLD_DPLL_P1_MIN_25
, .max
= MDFLD_DPLL_P1_MAX_25
},
828 { /* MDFLD_LIMT_DPLL_83 */
829 .dot
= {.min
= MDFLD_DOT_MIN
, .max
= MDFLD_DOT_MAX
},
830 .m
= {.min
= MDFLD_DPLL_M_MIN_83
, .max
= MDFLD_DPLL_M_MAX_83
},
831 .p1
= {.min
= MDFLD_DPLL_P1_MIN_83
, .max
= MDFLD_DPLL_P1_MAX_83
},
833 { /* MDFLD_LIMT_DPLL_100 */
834 .dot
= {.min
= MDFLD_DOT_MIN
, .max
= MDFLD_DOT_MAX
},
835 .m
= {.min
= MDFLD_DPLL_M_MIN_100
, .max
= MDFLD_DPLL_M_MAX_100
},
836 .p1
= {.min
= MDFLD_DPLL_P1_MIN_100
, .max
= MDFLD_DPLL_P1_MAX_100
},
838 { /* MDFLD_LIMT_DSIPLL_19 */
839 .dot
= {.min
= MDFLD_DOT_MIN
, .max
= MDFLD_DOT_MAX
},
840 .m
= {.min
= MDFLD_DSIPLL_M_MIN_19
, .max
= MDFLD_DSIPLL_M_MAX_19
},
841 .p1
= {.min
= MDFLD_DSIPLL_P1_MIN_19
, .max
= MDFLD_DSIPLL_P1_MAX_19
},
843 { /* MDFLD_LIMT_DSIPLL_25 */
844 .dot
= {.min
= MDFLD_DOT_MIN
, .max
= MDFLD_DOT_MAX
},
845 .m
= {.min
= MDFLD_DSIPLL_M_MIN_25
, .max
= MDFLD_DSIPLL_M_MAX_25
},
846 .p1
= {.min
= MDFLD_DSIPLL_P1_MIN_25
, .max
= MDFLD_DSIPLL_P1_MAX_25
},
848 { /* MDFLD_LIMT_DSIPLL_83 */
849 .dot
= {.min
= MDFLD_DOT_MIN
, .max
= MDFLD_DOT_MAX
},
850 .m
= {.min
= MDFLD_DSIPLL_M_MIN_83
, .max
= MDFLD_DSIPLL_M_MAX_83
},
851 .p1
= {.min
= MDFLD_DSIPLL_P1_MIN_83
, .max
= MDFLD_DSIPLL_P1_MAX_83
},
853 { /* MDFLD_LIMT_DSIPLL_100 */
854 .dot
= {.min
= MDFLD_DOT_MIN
, .max
= MDFLD_DOT_MAX
},
855 .m
= {.min
= MDFLD_DSIPLL_M_MIN_100
, .max
= MDFLD_DSIPLL_M_MAX_100
},
856 .p1
= {.min
= MDFLD_DSIPLL_P1_MIN_100
, .max
= MDFLD_DSIPLL_P1_MAX_100
},
860 #define MDFLD_M_MIN 21
861 #define MDFLD_M_MAX 180
862 static const u32 mdfld_m_converts
[] = {
863 /* M configuration table from 9-bit LFSR table */
864 224, 368, 440, 220, 366, 439, 219, 365, 182, 347, /* 21 - 30 */
865 173, 342, 171, 85, 298, 149, 74, 37, 18, 265, /* 31 - 40 */
866 388, 194, 353, 432, 216, 108, 310, 155, 333, 166, /* 41 - 50 */
867 83, 41, 276, 138, 325, 162, 337, 168, 340, 170, /* 51 - 60 */
868 341, 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 61 - 70 */
869 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
870 106, 53, 282, 397, 354, 227, 113, 56, 284, 142, /* 81 - 90 */
871 71, 35, 273, 136, 324, 418, 465, 488, 500, 506, /* 91 - 100 */
872 253, 126, 63, 287, 399, 455, 483, 241, 376, 444, /* 101 - 110 */
873 478, 495, 503, 251, 381, 446, 479, 239, 375, 443, /* 111 - 120 */
874 477, 238, 119, 315, 157, 78, 295, 147, 329, 420, /* 121 - 130 */
875 210, 105, 308, 154, 77, 38, 275, 137, 68, 290, /* 131 - 140 */
876 145, 328, 164, 82, 297, 404, 458, 485, 498, 249, /* 141 - 150 */
877 380, 190, 351, 431, 471, 235, 117, 314, 413, 206, /* 151 - 160 */
878 103, 51, 25, 12, 262, 387, 193, 96, 48, 280, /* 161 - 170 */
879 396, 198, 99, 305, 152, 76, 294, 403, 457, 228, /* 171 - 180 */
882 static const struct mdfld_limit_t
*mdfld_limit(struct drm_crtc
*crtc
)
884 const struct mdfld_limit_t
*limit
= NULL
;
885 struct drm_device
*dev
= crtc
->dev
;
886 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
888 if (psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_MIPI
)
889 || psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_MIPI2
)) {
890 if ((ksel
== KSEL_CRYSTAL_19
) || (ksel
== KSEL_BYPASS_19
))
891 limit
= &mdfld_limits
[MDFLD_LIMT_DSIPLL_19
];
892 else if (ksel
== KSEL_BYPASS_25
)
893 limit
= &mdfld_limits
[MDFLD_LIMT_DSIPLL_25
];
894 else if ((ksel
== KSEL_BYPASS_83_100
) && (dev_priv
->core_freq
== 166))
895 limit
= &mdfld_limits
[MDFLD_LIMT_DSIPLL_83
];
896 else if ((ksel
== KSEL_BYPASS_83_100
) &&
897 (dev_priv
->core_freq
== 100 || dev_priv
->core_freq
== 200))
898 limit
= &mdfld_limits
[MDFLD_LIMT_DSIPLL_100
];
899 } else if (psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
900 if ((ksel
== KSEL_CRYSTAL_19
) || (ksel
== KSEL_BYPASS_19
))
901 limit
= &mdfld_limits
[MDFLD_LIMT_DPLL_19
];
902 else if (ksel
== KSEL_BYPASS_25
)
903 limit
= &mdfld_limits
[MDFLD_LIMT_DPLL_25
];
904 else if ((ksel
== KSEL_BYPASS_83_100
) && (dev_priv
->core_freq
== 166))
905 limit
= &mdfld_limits
[MDFLD_LIMT_DPLL_83
];
906 else if ((ksel
== KSEL_BYPASS_83_100
) &&
907 (dev_priv
->core_freq
== 100 || dev_priv
->core_freq
== 200))
908 limit
= &mdfld_limits
[MDFLD_LIMT_DPLL_100
];
911 dev_err(dev
->dev
, "mdfld_limit Wrong display type.\n");
917 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
918 static void mdfld_clock(int refclk
, struct mdfld_intel_clock_t
*clock
)
920 clock
->dot
= (refclk
* clock
->m
) / clock
->p1
;
924 * Returns a set of divisors for the desired target clock with the given refclk,
925 * or FALSE. Divisor values are the actual divisors for
928 mdfldFindBestPLL(struct drm_crtc
*crtc
, int target
, int refclk
,
929 struct mdfld_intel_clock_t
*best_clock
)
931 struct mdfld_intel_clock_t clock
;
932 const struct mdfld_limit_t
*limit
= mdfld_limit(crtc
);
935 memset(best_clock
, 0, sizeof(*best_clock
));
937 for (clock
.m
= limit
->m
.min
; clock
.m
<= limit
->m
.max
; clock
.m
++) {
938 for (clock
.p1
= limit
->p1
.min
; clock
.p1
<= limit
->p1
.max
;
942 mdfld_clock(refclk
, &clock
);
944 this_err
= abs(clock
.dot
- target
);
945 if (this_err
< err
) {
951 return err
!= target
;
955 * Return the pipe currently connected to the panel fitter,
956 * or -1 if the panel fitter is not present or not in use
958 static int mdfld_panel_fitter_pipe(struct drm_device
*dev
)
962 pfit_control
= REG_READ(PFIT_CONTROL
);
964 /* See if the panel fitter is in use */
965 if ((pfit_control
& PFIT_ENABLE
) == 0)
967 return (pfit_control
>> 29) & 3;
970 static int mdfld_crtc_mode_set(struct drm_crtc
*crtc
,
971 struct drm_display_mode
*mode
,
972 struct drm_display_mode
*adjusted_mode
,
974 struct drm_framebuffer
*old_fb
)
976 struct drm_device
*dev
= crtc
->dev
;
977 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
978 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
979 int pipe
= psb_intel_crtc
->pipe
;
980 int fp_reg
= MRST_FPA0
;
981 int dpll_reg
= MRST_DPLL_A
;
982 int dspcntr_reg
= DSPACNTR
;
983 int pipeconf_reg
= PIPEACONF
;
984 int htot_reg
= HTOTAL_A
;
985 int hblank_reg
= HBLANK_A
;
986 int hsync_reg
= HSYNC_A
;
987 int vtot_reg
= VTOTAL_A
;
988 int vblank_reg
= VBLANK_A
;
989 int vsync_reg
= VSYNC_A
;
990 int dspsize_reg
= DSPASIZE
;
991 int dsppos_reg
= DSPAPOS
;
992 int pipesrc_reg
= PIPEASRC
;
993 u32
*pipeconf
= &dev_priv
->pipeconf
;
994 u32
*dspcntr
= &dev_priv
->dspcntr
;
996 int clk_n
= 0, clk_p2
= 0, clk_byte
= 1, clk
= 0, m_conv
= 0, clk_tmp
= 0;
997 struct mdfld_intel_clock_t clock
;
999 u32 dpll
= 0, fp
= 0;
1000 bool is_crt
= false, is_lvds
= false, is_tv
= false;
1001 bool is_mipi
= false, is_mipi2
= false, is_hdmi
= false;
1002 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
1003 struct psb_intel_output
*psb_intel_output
= NULL
;
1004 uint64_t scalingType
= DRM_MODE_SCALE_FULLSCREEN
;
1005 struct drm_encoder
*encoder
;
1006 struct drm_connector
*connector
;
1009 dev_dbg(dev
->dev
, "pipe = 0x%x \n", pipe
);
1017 dspcntr_reg
= DSPBCNTR
;
1018 pipeconf_reg
= PIPEBCONF
;
1019 htot_reg
= HTOTAL_B
;
1020 hblank_reg
= HBLANK_B
;
1021 hsync_reg
= HSYNC_B
;
1022 vtot_reg
= VTOTAL_B
;
1023 vblank_reg
= VBLANK_B
;
1024 vsync_reg
= VSYNC_B
;
1025 dspsize_reg
= DSPBSIZE
;
1026 dsppos_reg
= DSPBPOS
;
1027 pipesrc_reg
= PIPEBSRC
;
1028 pipeconf
= &dev_priv
->pipeconf1
;
1029 dspcntr
= &dev_priv
->dspcntr1
;
1030 fp_reg
= MDFLD_DPLL_DIV0
;
1031 dpll_reg
= MDFLD_DPLL_B
;
1034 dpll_reg
= MRST_DPLL_A
;
1035 dspcntr_reg
= DSPCCNTR
;
1036 pipeconf_reg
= PIPECCONF
;
1037 htot_reg
= HTOTAL_C
;
1038 hblank_reg
= HBLANK_C
;
1039 hsync_reg
= HSYNC_C
;
1040 vtot_reg
= VTOTAL_C
;
1041 vblank_reg
= VBLANK_C
;
1042 vsync_reg
= VSYNC_C
;
1043 dspsize_reg
= DSPCSIZE
;
1044 dsppos_reg
= DSPCPOS
;
1045 pipesrc_reg
= PIPECSRC
;
1046 pipeconf
= &dev_priv
->pipeconf2
;
1047 dspcntr
= &dev_priv
->dspcntr2
;
1050 DRM_ERROR("Illegal Pipe Number. \n");
1054 dev_dbg(dev
->dev
, "adjusted_hdisplay = %d\n",
1055 adjusted_mode
->hdisplay
);
1056 dev_dbg(dev
->dev
, "adjusted_vdisplay = %d\n",
1057 adjusted_mode
->vdisplay
);
1058 dev_dbg(dev
->dev
, "adjusted_hsync_start = %d\n",
1059 adjusted_mode
->hsync_start
);
1060 dev_dbg(dev
->dev
, "adjusted_hsync_end = %d\n",
1061 adjusted_mode
->hsync_end
);
1062 dev_dbg(dev
->dev
, "adjusted_htotal = %d\n",
1063 adjusted_mode
->htotal
);
1064 dev_dbg(dev
->dev
, "adjusted_vsync_start = %d\n",
1065 adjusted_mode
->vsync_start
);
1066 dev_dbg(dev
->dev
, "adjusted_vsync_end = %d\n",
1067 adjusted_mode
->vsync_end
);
1068 dev_dbg(dev
->dev
, "adjusted_vtotal = %d\n",
1069 adjusted_mode
->vtotal
);
1070 dev_dbg(dev
->dev
, "adjusted_clock = %d\n",
1071 adjusted_mode
->clock
);
1072 dev_dbg(dev
->dev
, "hdisplay = %d\n",
1074 dev_dbg(dev
->dev
, "vdisplay = %d\n",
1077 if (!gma_power_begin(dev
, true))
1080 memcpy(&psb_intel_crtc
->saved_mode
, mode
, sizeof(struct drm_display_mode
));
1081 memcpy(&psb_intel_crtc
->saved_adjusted_mode
, adjusted_mode
, sizeof(struct drm_display_mode
));
1083 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
1085 encoder
= connector
->encoder
;
1090 if (encoder
->crtc
!= crtc
)
1093 psb_intel_output
= to_psb_intel_output(connector
);
1095 dev_dbg(dev
->dev
, "output->type = 0x%x \n", psb_intel_output
->type
);
1097 switch (psb_intel_output
->type
) {
1098 case INTEL_OUTPUT_LVDS
:
1101 case INTEL_OUTPUT_TVOUT
:
1104 case INTEL_OUTPUT_ANALOG
:
1107 case INTEL_OUTPUT_MIPI
:
1110 case INTEL_OUTPUT_MIPI2
:
1113 case INTEL_OUTPUT_HDMI
:
1119 /* Disable the VGA plane that we never use */
1120 REG_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
1122 /* Disable the panel fitter if it was on our pipe */
1123 if (mdfld_panel_fitter_pipe(dev
) == pipe
)
1124 REG_WRITE(PFIT_CONTROL
, 0);
1126 /* pipesrc and dspsize control the size that is scaled from,
1127 * which should always be the user's requested size.
1130 /* FIXME: To make HDMI display with 864x480 (TPO), 480x864 (PYR) or 480x854 (TMD), set the sprite
1131 * width/height and souce image size registers with the adjusted mode for pipe B. */
1133 /* The defined sprite rectangle must always be completely contained within the displayable
1134 * area of the screen image (frame buffer). */
1135 REG_WRITE(dspsize_reg
, ((MIN(mode
->crtc_vdisplay
, adjusted_mode
->crtc_vdisplay
) - 1) << 16)
1136 | (MIN(mode
->crtc_hdisplay
, adjusted_mode
->crtc_hdisplay
) - 1));
1137 /* Set the CRTC with encoder mode. */
1138 REG_WRITE(pipesrc_reg
, ((mode
->crtc_hdisplay
- 1) << 16)
1139 | (mode
->crtc_vdisplay
- 1));
1141 REG_WRITE(dspsize_reg
, ((mode
->crtc_vdisplay
- 1) << 16) | (mode
->crtc_hdisplay
- 1));
1142 REG_WRITE(pipesrc_reg
, ((mode
->crtc_hdisplay
- 1) << 16) | (mode
->crtc_vdisplay
- 1));
1145 REG_WRITE(dsppos_reg
, 0);
1147 if (psb_intel_output
)
1148 drm_connector_property_get_value(&psb_intel_output
->base
,
1149 dev
->mode_config
.scaling_mode_property
, &scalingType
);
1151 if (scalingType
== DRM_MODE_SCALE_NO_SCALE
) {
1153 * Medfield doesn't have register support for centering so
1154 * we need to mess with the h/vblank and h/vsync start and
1155 * ends to get central
1157 int offsetX
= 0, offsetY
= 0;
1159 offsetX
= (adjusted_mode
->crtc_hdisplay
- mode
->crtc_hdisplay
) / 2;
1160 offsetY
= (adjusted_mode
->crtc_vdisplay
- mode
->crtc_vdisplay
) / 2;
1162 REG_WRITE(htot_reg
, (mode
->crtc_hdisplay
- 1) |
1163 ((adjusted_mode
->crtc_htotal
- 1) << 16));
1164 REG_WRITE(vtot_reg
, (mode
->crtc_vdisplay
- 1) |
1165 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
1166 REG_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- offsetX
- 1) |
1167 ((adjusted_mode
->crtc_hblank_end
- offsetX
- 1) << 16));
1168 REG_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- offsetX
- 1) |
1169 ((adjusted_mode
->crtc_hsync_end
- offsetX
- 1) << 16));
1170 REG_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- offsetY
- 1) |
1171 ((adjusted_mode
->crtc_vblank_end
- offsetY
- 1) << 16));
1172 REG_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- offsetY
- 1) |
1173 ((adjusted_mode
->crtc_vsync_end
- offsetY
- 1) << 16));
1175 REG_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
1176 ((adjusted_mode
->crtc_htotal
- 1) << 16));
1177 REG_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
1178 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
1179 REG_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
1180 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
1181 REG_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
1182 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
1183 REG_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
1184 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
1185 REG_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
1186 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
1189 /* Flush the plane changes */
1191 struct drm_crtc_helper_funcs
*crtc_funcs
=
1192 crtc
->helper_private
;
1193 crtc_funcs
->mode_set_base(crtc
, x
, y
, old_fb
);
1196 /* setup pipeconf */
1197 *pipeconf
= PIPEACONF_ENABLE
; /* FIXME_JLIU7 REG_READ(pipeconf_reg); */
1199 /* Set up the display plane register */
1200 *dspcntr
= REG_READ(dspcntr_reg
);
1201 *dspcntr
|= pipe
<< DISPPLANE_SEL_PIPE_POS
;
1202 *dspcntr
|= DISPLAY_PLANE_ENABLE
;
1203 /* MDFLD_PO_JLIU7 dspcntr |= DISPPLANE_BOTTOM; */
1204 /* MDFLD_PO_JLIU7 dspcntr |= DISPPLANE_GAMMA_ENABLE; */
1208 goto mrst_crtc_mode_set_exit
;
1210 /* FIXME JLIU7 Add MDFLD HDMI supports */
1211 /* FIXME_MDFLD JLIU7 DSIPLL clock *= 8? */
1212 /* FIXME_MDFLD JLIU7 need to revist for dual MIPI supports */
1213 clk
= adjusted_mode
->clock
;
1216 if ((ksel
== KSEL_CRYSTAL_19
) || (ksel
== KSEL_BYPASS_19
))
1220 if (is_mipi
|| is_mipi2
)
1222 clk_n
= 1, clk_p2
= 8;
1223 } else if (is_hdmi
) {
1224 clk_n
= 1, clk_p2
= 10;
1226 } else if (ksel
== KSEL_BYPASS_25
) {
1229 if (is_mipi
|| is_mipi2
)
1231 clk_n
= 1, clk_p2
= 8;
1232 } else if (is_hdmi
) {
1233 clk_n
= 1, clk_p2
= 10;
1235 } else if ((ksel
== KSEL_BYPASS_83_100
) && (dev_priv
->core_freq
== 166)) {
1238 if (is_mipi
|| is_mipi2
)
1240 clk_n
= 4, clk_p2
= 8;
1241 } else if (is_hdmi
) {
1242 clk_n
= 4, clk_p2
= 10;
1244 } else if ((ksel
== KSEL_BYPASS_83_100
) &&
1245 (dev_priv
->core_freq
== 100 || dev_priv
->core_freq
== 200)) {
1247 if (is_mipi
|| is_mipi2
)
1249 clk_n
= 4, clk_p2
= 8;
1250 } else if (is_hdmi
) {
1251 clk_n
= 4, clk_p2
= 10;
1256 clk_byte
= dev_priv
->bpp
/ 8;
1258 clk_byte
= dev_priv
->bpp2
/ 8;
1260 clk_tmp
= clk
* clk_n
* clk_p2
* clk_byte
;
1262 dev_dbg(dev
->dev
, "clk = %d, clk_n = %d, clk_p2 = %d. \n", clk
, clk_n
, clk_p2
);
1263 dev_dbg(dev
->dev
, "adjusted_mode->clock = %d, clk_tmp = %d. \n", adjusted_mode
->clock
, clk_tmp
);
1265 ok
= mdfldFindBestPLL(crtc
, clk_tmp
, refclk
, &clock
);
1269 "mdfldFindBestPLL fail in mdfld_crtc_mode_set. \n");
1271 m_conv
= mdfld_m_converts
[(clock
.m
- MDFLD_M_MIN
)];
1273 dev_dbg(dev
->dev
, "dot clock = %d,"
1274 "m = %d, p1 = %d, m_conv = %d. \n", clock
.dot
, clock
.m
,
1278 dpll
= REG_READ(dpll_reg
);
1280 if (dpll
& DPLL_VCO_ENABLE
) {
1281 dpll
&= ~DPLL_VCO_ENABLE
;
1282 REG_WRITE(dpll_reg
, dpll
);
1285 /* FIXME jliu7 check the DPLL lock bit PIPEACONF[29] */
1286 /* FIXME_MDFLD PO - change 500 to 1 after PO */
1289 /* reset M1, N1 & P1 */
1290 REG_WRITE(fp_reg
, 0);
1291 dpll
&= ~MDFLD_P1_MASK
;
1292 REG_WRITE(dpll_reg
, dpll
);
1293 /* FIXME_MDFLD PO - change 500 to 1 after PO */
1297 /* When ungating power of DPLL, needs to wait 0.5us before enable the VCO */
1298 if (dpll
& MDFLD_PWR_GATE_EN
) {
1299 dpll
&= ~MDFLD_PWR_GATE_EN
;
1300 REG_WRITE(dpll_reg
, dpll
);
1301 /* FIXME_MDFLD PO - change 500 to 1 after PO */
1307 #if 0 /* FIXME revisit later */
1308 if ((ksel
== KSEL_CRYSTAL_19
) || (ksel
== KSEL_BYPASS_19
) || (ksel
== KSEL_BYPASS_25
)) {
1309 dpll
&= ~MDFLD_INPUT_REF_SEL
;
1310 } else if (ksel
== KSEL_BYPASS_83_100
) {
1311 dpll
|= MDFLD_INPUT_REF_SEL
;
1313 #endif /* FIXME revisit later */
1316 dpll
|= MDFLD_VCO_SEL
;
1318 fp
= (clk_n
/ 2) << 16;
1321 /* compute bitmask from p1 value */
1322 dpll
|= (1 << (clock
.p1
- 2)) << 17;
1324 #if 0 /* 1080p30 & 720p */
1333 #if 0 /*DBI_TPO_480x864*/
1336 #endif /* DBI_TPO_480x864 */ /* get from spec. */
1342 REG_WRITE(fp_reg
, fp
);
1343 REG_WRITE(dpll_reg
, dpll
);
1344 /* FIXME_MDFLD PO - change 500 to 1 after PO */
1347 dpll
|= DPLL_VCO_ENABLE
;
1348 REG_WRITE(dpll_reg
, dpll
);
1351 /* wait for DSI PLL to lock */
1352 while ((timeout
< 20000) && !(REG_READ(pipeconf_reg
) & PIPECONF_DSIPLL_LOCK
)) {
1358 goto mrst_crtc_mode_set_exit
;
1360 dev_dbg(dev
->dev
, "is_mipi = 0x%x \n", is_mipi
);
1362 REG_WRITE(pipeconf_reg
, *pipeconf
);
1363 REG_READ(pipeconf_reg
);
1365 /* Wait for for the pipe enable to take effect. */
1366 //FIXME_JLIU7 HDMI mrstWaitForPipeEnable(dev);
1368 REG_WRITE(dspcntr_reg
, *dspcntr
);
1369 psb_intel_wait_for_vblank(dev
);
1371 mrst_crtc_mode_set_exit
:
1378 static void mdfld_crtc_prepare(struct drm_crtc
*crtc
)
1380 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1381 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
1384 static void mdfld_crtc_commit(struct drm_crtc
*crtc
)
1386 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1387 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1390 static bool mdfld_crtc_mode_fixup(struct drm_crtc
*crtc
,
1391 struct drm_display_mode
*mode
,
1392 struct drm_display_mode
*adjusted_mode
)
1397 const struct drm_crtc_helper_funcs mdfld_helper_funcs
= {
1398 .dpms
= mdfld_crtc_dpms
,
1399 .mode_fixup
= mdfld_crtc_mode_fixup
,
1400 .mode_set
= mdfld_crtc_mode_set
,
1401 .mode_set_base
= mdfld__intel_pipe_set_base
,
1402 .prepare
= mdfld_crtc_prepare
,
1403 .commit
= mdfld_crtc_commit
,