arch/sparc/kernel/sun4c_irq.c

   1 /*  sun4c_irq.c
   2  *  arch/sparc/kernel/sun4c_irq.c:
   3  *
   4  *  djhr: Hacked out of irq.c into a CPU dependent version.
   5  *
   6  *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   7  *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
   8  *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
   9  *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/linkage.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/sched.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include "irq.h"
  22
  23 #include <asm/ptrace.h>
  24 #include <asm/processor.h>
  25 #include <asm/system.h>
  26 #include <asm/psr.h>
  27 #include <asm/vaddrs.h>
  28 #include <asm/timer.h>
  29 #include <asm/openprom.h>
  30 #include <asm/oplib.h>
  31 #include <asm/traps.h>
  32 #include <asm/irq.h>
  33 #include <asm/io.h>
  34 #include <asm/sun4paddr.h>
  35 #include <asm/idprom.h>
  36 #include <asm/machines.h>
  37 #include <asm/sbus.h>
  38
  39 #if 0
  40 static struct resource sun4c_timer_eb = { "sun4c_timer" };
  41 static struct resource sun4c_intr_eb = { "sun4c_intr" };
  42 #endif
  43
  44 /*
  45  * Bit field defines for the interrupt registers on various
  46  * Sparc machines.
  47  */
  48
  49 /* The sun4c interrupt register. */
  50 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
  51 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
  52 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
  53 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
  54 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
  55 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
  56 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
  57
  58 /* Pointer to the interrupt enable byte
  59  *
  60  * Dave Redman (djhr@tadpole.co.uk)
  61  * What you may not be aware of is that entry.S requires this variable.
  62  *
  63  *  --- linux_trap_nmi_sun4c --
  64  *
  65  * so don't go making it static, like I tried. sigh.
  66  */
  67 unsigned char *interrupt_enable = NULL;
  68
  69 static int sun4c_pil_map[] = { 0, 1, 2, 3, 5, 7, 8, 9 };
  70
  71 static unsigned int sun4c_sbint_to_irq(struct sbus_dev *sdev,
  72                                        unsigned int sbint)
  73 {
  74         if (sbint >= sizeof(sun4c_pil_map)) {
  75                 printk(KERN_ERR "%s: bogus SBINT %d\n", sdev->prom_name, sbint);
  76                 BUG();
  77         }
  78         return sun4c_pil_map[sbint];
  79 }
  80
  81 static void sun4c_disable_irq(unsigned int irq_nr)
  82 {
  83         unsigned long flags;
  84         unsigned char current_mask, new_mask;
  85
  86         local_irq_save(flags);
  87         irq_nr &= (NR_IRQS - 1);
  88         current_mask = *interrupt_enable;
  89         switch(irq_nr) {
  90         case 1:
  91                 new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
  92                 break;
  93         case 8:
  94                 new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
  95                 break;
  96         case 10:
  97                 new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
  98                 break;
  99         case 14:
 100                 new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
 101                 break;
 102         default:
 103                 local_irq_restore(flags);
 104                 return;
 105         }
 106         *interrupt_enable = new_mask;
 107         local_irq_restore(flags);
 108 }
 109
 110 static void sun4c_enable_irq(unsigned int irq_nr)
 111 {
 112         unsigned long flags;
 113         unsigned char current_mask, new_mask;
 114
 115         local_irq_save(flags);
 116         irq_nr &= (NR_IRQS - 1);
 117         current_mask = *interrupt_enable;
 118         switch(irq_nr) {
 119         case 1:
 120                 new_mask = ((current_mask) | SUN4C_INT_E1);
 121                 break;
 122         case 8:
 123                 new_mask = ((current_mask) | SUN4C_INT_E8);
 124                 break;
 125         case 10:
 126                 new_mask = ((current_mask) | SUN4C_INT_E10);
 127                 break;
 128         case 14:
 129                 new_mask = ((current_mask) | SUN4C_INT_E14);
 130                 break;
 131         default:
 132                 local_irq_restore(flags);
 133                 return;
 134         }
 135         *interrupt_enable = new_mask;
 136         local_irq_restore(flags);
 137 }
 138
 139 #define TIMER_IRQ       10    /* Also at level 14, but we ignore that one. */
 140 #define PROFILE_IRQ     14    /* Level14 ticker.. used by OBP for polling */
 141
 142 volatile struct sun4c_timer_info *sun4c_timers;
 143
 144 #ifdef CONFIG_SUN4
 145 /* This is an ugly hack to work around the
 146    current timer code, and make it work with
 147    the sun4/260 intersil
 148    */
 149 volatile struct sun4c_timer_info sun4_timer;
 150 #endif
 151
 152 static void sun4c_clear_clock_irq(void)
 153 {
 154         volatile unsigned int clear_intr;
 155 #ifdef CONFIG_SUN4
 156         if (idprom->id_machtype == (SM_SUN4 | SM_4_260))
 157           clear_intr = sun4_timer.timer_limit10;
 158         else
 159 #endif
 160         clear_intr = sun4c_timers->timer_limit10;
 161 }
 162
 163 static void sun4c_clear_profile_irq(int cpu)
 164 {
 165         /* Errm.. not sure how to do this.. */
 166 }
 167
 168 static void sun4c_load_profile_irq(int cpu, unsigned int limit)
 169 {
 170         /* Errm.. not sure how to do this.. */
 171 }
 172
 173 static void __init sun4c_init_timers(irq_handler_t counter_fn)
 174 {
 175         int irq;
 176
 177         /* Map the Timer chip, this is implemented in hardware inside
 178          * the cache chip on the sun4c.
 179          */
 180 #ifdef CONFIG_SUN4
 181         if (idprom->id_machtype == (SM_SUN4 | SM_4_260))
 182                 sun4c_timers = &sun4_timer;
 183         else
 184 #endif
 185         sun4c_timers = ioremap(SUN_TIMER_PHYSADDR,
 186             sizeof(struct sun4c_timer_info));
 187
 188         /* Have the level 10 timer tick at 100HZ.  We don't touch the
 189          * level 14 timer limit since we are letting the prom handle
 190          * them until we have a real console driver so L1-A works.
 191          */
 192         sun4c_timers->timer_limit10 = (((1000000/HZ) + 1) << 10);
 193         master_l10_counter = &sun4c_timers->cur_count10;
 194         master_l10_limit = &sun4c_timers->timer_limit10;
 195
 196         irq = request_irq(TIMER_IRQ,
 197                           counter_fn,
 198                           (IRQF_DISABLED | SA_STATIC_ALLOC),
 199                           "timer", NULL);
 200         if (irq) {
 201                 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
 202                 prom_halt();
 203         }
 204
 205 #if 0
 206         /* This does not work on 4/330 */
 207         sun4c_enable_irq(10);
 208 #endif
 209         claim_ticker14(NULL, PROFILE_IRQ, 0);
 210 }
 211
 212 #ifdef CONFIG_SMP
 213 static void sun4c_nop(void) {}
 214 #endif
 215
 216 void __init sun4c_init_IRQ(void)
 217 {
 218         struct linux_prom_registers int_regs[2];
 219         int ie_node;
 220
 221         if (ARCH_SUN4) {
 222                 interrupt_enable = (char *)
 223                     ioremap(sun4_ie_physaddr, PAGE_SIZE);
 224         } else {
 225                 struct resource phyres;
 226
 227                 ie_node = prom_searchsiblings (prom_getchild(prom_root_node),
 228                                         "interrupt-enable");
 229                 if(ie_node == 0)
 230                         panic("Cannot find /interrupt-enable node");
 231
 232                 /* Depending on the "address" property is bad news... */
 233                 interrupt_enable = NULL;
 234                 if (prom_getproperty(ie_node, "reg", (char *) int_regs,
 235                                      sizeof(int_regs)) != -1) {
 236                         memset(&phyres, 0, sizeof(struct resource));
 237                         phyres.flags = int_regs[0].which_io;
 238                         phyres.start = int_regs[0].phys_addr;
 239                         interrupt_enable = (char *) sbus_ioremap(&phyres, 0,
 240                             int_regs[0].reg_size, "sun4c_intr");
 241                 }
 242         }
 243         if (!interrupt_enable)
 244                 panic("Cannot map interrupt_enable");
 245
 246         BTFIXUPSET_CALL(sbint_to_irq, sun4c_sbint_to_irq, BTFIXUPCALL_NORM);
 247         BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
 248         BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
 249         BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
 250         BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
 251         BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
 252         BTFIXUPSET_CALL(clear_profile_irq, sun4c_clear_profile_irq, BTFIXUPCALL_NOP);
 253         BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
 254         sparc_init_timers = sun4c_init_timers;
 255 #ifdef CONFIG_SMP
 256         BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
 257         BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
 258         BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
 259 #endif
 260         *interrupt_enable = (SUN4C_INT_ENABLE);
 261         /* Cannot enable interrupts until OBP ticker is disabled. */
 262 }