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ASoC: OMAP: Use DMA operating mode of McBSP
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / soc / omap / omap-mcbsp.c
blobf5387d962f5d8a91e03276bb36a326064a9c263a
1 /*
2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 *
6 * Contact: Jarkko Nikula <jhnikula@gmail.com>
7 * Peter Ujfalusi <peter.ujfalusi@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/initval.h>
32 #include <sound/soc.h>
33
34 #include <mach/control.h>
35 #include <mach/dma.h>
36 #include <mach/mcbsp.h>
37 #include "omap-mcbsp.h"
38 #include "omap-pcm.h"
39
40 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
41
42 struct omap_mcbsp_data {
43 unsigned int bus_id;
44 struct omap_mcbsp_reg_cfg regs;
45 unsigned int fmt;
46 /*
47 * Flags indicating is the bus already activated and configured by
48 * another substream
49 */
50 int active;
51 int configured;
52 };
53
54 #define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
55
56 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
57
58 /*
59 * Stream DMA parameters. DMA request line and port address are set runtime
60 * since they are different between OMAP1 and later OMAPs
61 */
62 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
63
64 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
65 static const int omap1_dma_reqs[][2] = {
66 { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
67 { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
68 { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
69 };
70 static const unsigned long omap1_mcbsp_port[][2] = {
71 { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
72 OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
73 { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
74 OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
75 { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
76 OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
77 };
78 #else
79 static const int omap1_dma_reqs[][2] = {};
80 static const unsigned long omap1_mcbsp_port[][2] = {};
81 #endif
82
83 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
84 static const int omap24xx_dma_reqs[][2] = {
85 { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
86 { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
87 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
88 { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
89 { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
90 { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
91 #endif
92 };
93 #else
94 static const int omap24xx_dma_reqs[][2] = {};
95 #endif
96
97 #if defined(CONFIG_ARCH_OMAP2420)
98 static const unsigned long omap2420_mcbsp_port[][2] = {
99 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
100 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
101 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
102 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
103 };
104 #else
105 static const unsigned long omap2420_mcbsp_port[][2] = {};
106 #endif
107
108 #if defined(CONFIG_ARCH_OMAP2430)
109 static const unsigned long omap2430_mcbsp_port[][2] = {
110 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
111 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
112 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
113 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
114 { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
115 OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
116 { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
117 OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
118 { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
119 OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
120 };
121 #else
122 static const unsigned long omap2430_mcbsp_port[][2] = {};
123 #endif
124
125 #if defined(CONFIG_ARCH_OMAP34XX)
126 static const unsigned long omap34xx_mcbsp_port[][2] = {
127 { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
128 OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
129 { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
130 OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
131 { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
132 OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
133 { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
134 OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
135 { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
136 OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
137 };
138 #else
139 static const unsigned long omap34xx_mcbsp_port[][2] = {};
140 #endif
141
142 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
143 {
144 struct snd_soc_pcm_runtime *rtd = substream->private_data;
145 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
146 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
147 int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
148 int samples;
149
150 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
151 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
152 samples = snd_pcm_lib_period_bytes(substream) >> 1;
153 else
154 samples = 1;
155
156 /* Configure McBSP internal buffer usage */
157 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
158 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1);
159 else
160 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
161 }
162
163 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
164 struct snd_soc_dai *dai)
165 {
166 struct snd_soc_pcm_runtime *rtd = substream->private_data;
167 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
168 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
169 int bus_id = mcbsp_data->bus_id;
170 int err = 0;
171
172 if (!cpu_dai->active)
173 err = omap_mcbsp_request(bus_id);
174
175 if (cpu_is_omap343x()) {
176 int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
177 int max_period;
178
179 /*
180 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
181 * Set constraint for minimum buffer size to the same than FIFO
182 * size in order to avoid underruns in playback startup because
183 * HW is keeping the DMA request active until FIFO is filled.
184 */
185 if (bus_id == 1)
186 snd_pcm_hw_constraint_minmax(substream->runtime,
187 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
188 4096, UINT_MAX);
189
190 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
191 max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
192 else
193 max_period = omap_mcbsp_get_max_rx_threshold(bus_id);
194
195 max_period++;
196 max_period <<= 1;
197
198 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
199 snd_pcm_hw_constraint_minmax(substream->runtime,
200 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
201 32, max_period);
202 }
203
204 return err;
205 }
206
207 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
208 struct snd_soc_dai *dai)
209 {
210 struct snd_soc_pcm_runtime *rtd = substream->private_data;
211 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
212 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
213
214 if (!cpu_dai->active) {
215 omap_mcbsp_free(mcbsp_data->bus_id);
216 mcbsp_data->configured = 0;
217 }
218 }
219
220 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
221 struct snd_soc_dai *dai)
222 {
223 struct snd_soc_pcm_runtime *rtd = substream->private_data;
224 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
225 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
226 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
227
228 switch (cmd) {
229 case SNDRV_PCM_TRIGGER_START:
230 case SNDRV_PCM_TRIGGER_RESUME:
231 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
232 mcbsp_data->active++;
233 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
234 /* Make sure data transfer is frame synchronized */
235 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
236 omap_mcbsp_xmit_enable(mcbsp_data->bus_id, 1);
237 else
238 omap_mcbsp_recv_enable(mcbsp_data->bus_id, 1);
239 break;
240
241 case SNDRV_PCM_TRIGGER_STOP:
242 case SNDRV_PCM_TRIGGER_SUSPEND:
243 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
244 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
245 mcbsp_data->active--;
246 break;
247 default:
248 err = -EINVAL;
249 }
250
251 return err;
252 }
253
254 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
255 struct snd_pcm_hw_params *params,
256 struct snd_soc_dai *dai)
257 {
258 struct snd_soc_pcm_runtime *rtd = substream->private_data;
259 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
260 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
261 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
262 int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
263 int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
264 unsigned long port;
265 unsigned int format;
266
267 if (cpu_class_is_omap1()) {
268 dma = omap1_dma_reqs[bus_id][substream->stream];
269 port = omap1_mcbsp_port[bus_id][substream->stream];
270 } else if (cpu_is_omap2420()) {
271 dma = omap24xx_dma_reqs[bus_id][substream->stream];
272 port = omap2420_mcbsp_port[bus_id][substream->stream];
273 } else if (cpu_is_omap2430()) {
274 dma = omap24xx_dma_reqs[bus_id][substream->stream];
275 port = omap2430_mcbsp_port[bus_id][substream->stream];
276 } else if (cpu_is_omap343x()) {
277 dma = omap24xx_dma_reqs[bus_id][substream->stream];
278 port = omap34xx_mcbsp_port[bus_id][substream->stream];
279 omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
280 omap_mcbsp_set_threshold;
281 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
282 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
283 MCBSP_DMA_MODE_THRESHOLD)
284 sync_mode = OMAP_DMA_SYNC_FRAME;
285 } else {
286 return -ENODEV;
287 }
288 omap_mcbsp_dai_dma_params[id][substream->stream].name =
289 substream->stream ? "Audio Capture" : "Audio Playback";
290 omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
291 omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
292 omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
293 cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
294
295 if (mcbsp_data->configured) {
296 /* McBSP already configured by another stream */
297 return 0;
298 }
299
300 format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
301 wpf = channels = params_channels(params);
302 switch (channels) {
303 case 2:
304 if (format == SND_SOC_DAIFMT_I2S) {
305 /* Use dual-phase frames */
306 regs->rcr2 |= RPHASE;
307 regs->xcr2 |= XPHASE;
308 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
309 wpf--;
310 regs->rcr2 |= RFRLEN2(wpf - 1);
311 regs->xcr2 |= XFRLEN2(wpf - 1);
312 }
313 case 1:
314 case 4:
315 /* Set word per (McBSP) frame for phase1 */
316 regs->rcr1 |= RFRLEN1(wpf - 1);
317 regs->xcr1 |= XFRLEN1(wpf - 1);
318 break;
319 default:
320 /* Unsupported number of channels */
321 return -EINVAL;
322 }
323
324 switch (params_format(params)) {
325 case SNDRV_PCM_FORMAT_S16_LE:
326 /* Set word lengths */
327 wlen = 16;
328 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
329 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
330 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
331 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
332 break;
333 default:
334 /* Unsupported PCM format */
335 return -EINVAL;
336 }
337
338 /* Set FS period and length in terms of bit clock periods */
339 switch (format) {
340 case SND_SOC_DAIFMT_I2S:
341 regs->srgr2 |= FPER(wlen * channels - 1);
342 regs->srgr1 |= FWID(wlen - 1);
343 break;
344 case SND_SOC_DAIFMT_DSP_A:
345 case SND_SOC_DAIFMT_DSP_B:
346 regs->srgr2 |= FPER(wlen * channels - 1);
347 regs->srgr1 |= FWID(0);
348 break;
349 }
350
351 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
352 mcbsp_data->configured = 1;
353
354 return 0;
355 }
356
357 /*
358 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
359 * cache is initialized here
360 */
361 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
362 unsigned int fmt)
363 {
364 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
365 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
366 unsigned int temp_fmt = fmt;
367
368 if (mcbsp_data->configured)
369 return 0;
370
371 mcbsp_data->fmt = fmt;
372 memset(regs, 0, sizeof(*regs));
373 /* Generic McBSP register settings */
374 regs->spcr2 |= XINTM(3) | FREE;
375 regs->spcr1 |= RINTM(3);
376 /* RFIG and XFIG are not defined in 34xx */
377 if (!cpu_is_omap34xx()) {
378 regs->rcr2 |= RFIG;
379 regs->xcr2 |= XFIG;
380 }
381 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
382 regs->xccr = DXENDLY(1) | XDMAEN;
383 regs->rccr = RFULL_CYCLE | RDMAEN;
384 }
385
386 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
387 case SND_SOC_DAIFMT_I2S:
388 /* 1-bit data delay */
389 regs->rcr2 |= RDATDLY(1);
390 regs->xcr2 |= XDATDLY(1);
391 regs->rccr |= RFULL_CYCLE | RDMAEN | RDISABLE;
392 regs->xccr |= (DXENDLY(1) | XDMAEN | XDISABLE);
393 break;
394 case SND_SOC_DAIFMT_DSP_A:
395 /* 1-bit data delay */
396 regs->rcr2 |= RDATDLY(1);
397 regs->xcr2 |= XDATDLY(1);
398 regs->rccr |= RFULL_CYCLE | RDMAEN | RDISABLE;
399 regs->xccr |= (DXENDLY(1) | XDMAEN | XDISABLE);
400 /* Invert FS polarity configuration */
401 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
402 break;
403 case SND_SOC_DAIFMT_DSP_B:
404 /* 0-bit data delay */
405 regs->rcr2 |= RDATDLY(0);
406 regs->xcr2 |= XDATDLY(0);
407 /* Invert FS polarity configuration */
408 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
409 break;
410 default:
411 /* Unsupported data format */
412 return -EINVAL;
413 }
414
415 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
416 case SND_SOC_DAIFMT_CBS_CFS:
417 /* McBSP master. Set FS and bit clocks as outputs */
418 regs->pcr0 |= FSXM | FSRM |
419 CLKXM | CLKRM;
420 /* Sample rate generator drives the FS */
421 regs->srgr2 |= FSGM;
422 break;
423 case SND_SOC_DAIFMT_CBM_CFM:
424 /* McBSP slave */
425 break;
426 default:
427 /* Unsupported master/slave configuration */
428 return -EINVAL;
429 }
430
431 /* Set bit clock (CLKX/CLKR) and FS polarities */
432 switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
433 case SND_SOC_DAIFMT_NB_NF:
434 /*
435 * Normal BCLK + FS.
436 * FS active low. TX data driven on falling edge of bit clock
437 * and RX data sampled on rising edge of bit clock.
438 */
439 regs->pcr0 |= FSXP | FSRP |
440 CLKXP | CLKRP;
441 break;
442 case SND_SOC_DAIFMT_NB_IF:
443 regs->pcr0 |= CLKXP | CLKRP;
444 break;
445 case SND_SOC_DAIFMT_IB_NF:
446 regs->pcr0 |= FSXP | FSRP;
447 break;
448 case SND_SOC_DAIFMT_IB_IF:
449 break;
450 default:
451 return -EINVAL;
452 }
453
454 return 0;
455 }
456
457 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
458 int div_id, int div)
459 {
460 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
461 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
462
463 if (div_id != OMAP_MCBSP_CLKGDV)
464 return -ENODEV;
465
466 regs->srgr1 |= CLKGDV(div - 1);
467
468 return 0;
469 }
470
471 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
472 int clk_id)
473 {
474 int sel_bit;
475 u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
476
477 if (cpu_class_is_omap1()) {
478 /* OMAP1's can use only external source clock */
479 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
480 return -EINVAL;
481 else
482 return 0;
483 }
484
485 if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
486 return -EINVAL;
487
488 if (cpu_is_omap343x())
489 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
490
491 switch (mcbsp_data->bus_id) {
492 case 0:
493 reg = OMAP2_CONTROL_DEVCONF0;
494 sel_bit = 2;
495 break;
496 case 1:
497 reg = OMAP2_CONTROL_DEVCONF0;
498 sel_bit = 6;
499 break;
500 case 2:
501 reg = reg_devconf1;
502 sel_bit = 0;
503 break;
504 case 3:
505 reg = reg_devconf1;
506 sel_bit = 2;
507 break;
508 case 4:
509 reg = reg_devconf1;
510 sel_bit = 4;
511 break;
512 default:
513 return -EINVAL;
514 }
515
516 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
517 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
518 else
519 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
520
521 return 0;
522 }
523
524 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
525 int clk_id, unsigned int freq,
526 int dir)
527 {
528 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
529 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
530 int err = 0;
531
532 switch (clk_id) {
533 case OMAP_MCBSP_SYSCLK_CLK:
534 regs->srgr2 |= CLKSM;
535 break;
536 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
537 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
538 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
539 break;
540
541 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
542 regs->srgr2 |= CLKSM;
543 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
544 regs->pcr0 |= SCLKME;
545 break;
546 default:
547 err = -ENODEV;
548 }
549
550 return err;
551 }
552
553 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
554 .startup = omap_mcbsp_dai_startup,
555 .shutdown = omap_mcbsp_dai_shutdown,
556 .trigger = omap_mcbsp_dai_trigger,
557 .hw_params = omap_mcbsp_dai_hw_params,
558 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
559 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
560 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
561 };
562
563 #define OMAP_MCBSP_DAI_BUILDER(link_id) \
564 { \
565 .name = "omap-mcbsp-dai-"#link_id, \
566 .id = (link_id), \
567 .playback = { \
568 .channels_min = 1, \
569 .channels_max = 4, \
570 .rates = OMAP_MCBSP_RATES, \
571 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
572 }, \
573 .capture = { \
574 .channels_min = 1, \
575 .channels_max = 4, \
576 .rates = OMAP_MCBSP_RATES, \
577 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
578 }, \
579 .ops = &omap_mcbsp_dai_ops, \
580 .private_data = &mcbsp_data[(link_id)].bus_id, \
581 }
582
583 struct snd_soc_dai omap_mcbsp_dai[] = {
584 OMAP_MCBSP_DAI_BUILDER(0),
585 OMAP_MCBSP_DAI_BUILDER(1),
586 #if NUM_LINKS >= 3
587 OMAP_MCBSP_DAI_BUILDER(2),
588 #endif
589 #if NUM_LINKS == 5
590 OMAP_MCBSP_DAI_BUILDER(3),
591 OMAP_MCBSP_DAI_BUILDER(4),
592 #endif
593 };
594
595 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
596
597 static int __init snd_omap_mcbsp_init(void)
598 {
599 return snd_soc_register_dais(omap_mcbsp_dai,
600 ARRAY_SIZE(omap_mcbsp_dai));
601 }
602 module_init(snd_omap_mcbsp_init);
603
604 static void __exit snd_omap_mcbsp_exit(void)
605 {
606 snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
607 }
608 module_exit(snd_omap_mcbsp_exit);
609
610 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
611 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
612 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree