1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/smp_lock.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
20 #include <linux/seq_file.h>
21 #include <linux/cache.h>
22 #include <linux/jiffies.h>
23 #include <linux/profile.h>
24 #include <linux/bootmem.h>
27 #include <asm/ptrace.h>
28 #include <asm/atomic.h>
29 #include <asm/tlbflush.h>
30 #include <asm/mmu_context.h>
31 #include <asm/cpudata.h>
35 #include <asm/pgtable.h>
36 #include <asm/oplib.h>
37 #include <asm/uaccess.h>
38 #include <asm/timer.h>
39 #include <asm/starfire.h>
41 #include <asm/sections.h>
43 extern void calibrate_delay(void);
45 /* Please don't make this stuff initdata!!! --DaveM */
46 static unsigned char boot_cpu_id
;
48 cpumask_t cpu_online_map __read_mostly
= CPU_MASK_NONE
;
49 cpumask_t phys_cpu_present_map __read_mostly
= CPU_MASK_NONE
;
50 static cpumask_t smp_commenced_mask
;
51 static cpumask_t cpu_callout_map
;
53 void smp_info(struct seq_file
*m
)
57 seq_printf(m
, "State:\n");
58 for (i
= 0; i
< NR_CPUS
; i
++) {
61 "CPU%d:\t\tonline\n", i
);
65 void smp_bogo(struct seq_file
*m
)
69 for (i
= 0; i
< NR_CPUS
; i
++)
72 "Cpu%dBogo\t: %lu.%02lu\n"
73 "Cpu%dClkTck\t: %016lx\n",
74 i
, cpu_data(i
).udelay_val
/ (500000/HZ
),
75 (cpu_data(i
).udelay_val
/ (5000/HZ
)) % 100,
76 i
, cpu_data(i
).clock_tick
);
79 void __init
smp_store_cpu_info(int id
)
83 /* multiplier and counter set by
84 smp_setup_percpu_timer() */
85 cpu_data(id
).udelay_val
= loops_per_jiffy
;
87 cpu_find_by_mid(id
, &cpu_node
);
88 cpu_data(id
).clock_tick
= prom_getintdefault(cpu_node
,
89 "clock-frequency", 0);
91 def
= ((tlb_type
== hypervisor
) ? (8 * 1024) : (16 * 1024));
92 cpu_data(id
).dcache_size
= prom_getintdefault(cpu_node
, "dcache-size",
96 cpu_data(id
).dcache_line_size
=
97 prom_getintdefault(cpu_node
, "dcache-line-size", def
);
100 cpu_data(id
).icache_size
= prom_getintdefault(cpu_node
, "icache-size",
104 cpu_data(id
).icache_line_size
=
105 prom_getintdefault(cpu_node
, "icache-line-size", def
);
107 def
= ((tlb_type
== hypervisor
) ?
110 cpu_data(id
).ecache_size
= prom_getintdefault(cpu_node
, "ecache-size",
114 cpu_data(id
).ecache_line_size
=
115 prom_getintdefault(cpu_node
, "ecache-line-size", def
);
117 printk("CPU[%d]: Caches "
118 "D[sz(%d):line_sz(%d)] "
119 "I[sz(%d):line_sz(%d)] "
120 "E[sz(%d):line_sz(%d)]\n",
122 cpu_data(id
).dcache_size
, cpu_data(id
).dcache_line_size
,
123 cpu_data(id
).icache_size
, cpu_data(id
).icache_line_size
,
124 cpu_data(id
).ecache_size
, cpu_data(id
).ecache_line_size
);
127 static void smp_setup_percpu_timer(void);
129 static volatile unsigned long callin_flag
= 0;
131 void __init
smp_callin(void)
133 int cpuid
= hard_smp_processor_id();
135 __local_per_cpu_offset
= __per_cpu_offset(cpuid
);
137 if (tlb_type
== hypervisor
)
138 sun4v_ktsb_register();
142 smp_setup_percpu_timer();
144 if (cheetah_pcache_forced_on
)
145 cheetah_enable_pcache();
150 smp_store_cpu_info(cpuid
);
152 __asm__
__volatile__("membar #Sync\n\t"
153 "flush %%g6" : : : "memory");
155 /* Clear this or we will die instantly when we
156 * schedule back to this idler...
158 current_thread_info()->new_child
= 0;
160 /* Attach to the address space of init_task. */
161 atomic_inc(&init_mm
.mm_count
);
162 current
->active_mm
= &init_mm
;
164 while (!cpu_isset(cpuid
, smp_commenced_mask
))
167 cpu_set(cpuid
, cpu_online_map
);
169 /* idle thread is expected to have preempt disabled */
175 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
176 panic("SMP bolixed\n");
179 static unsigned long current_tick_offset __read_mostly
;
181 /* This tick register synchronization scheme is taken entirely from
182 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
184 * The only change I've made is to rework it so that the master
185 * initiates the synchonization instead of the slave. -DaveM
189 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
191 #define NUM_ROUNDS 64 /* magic value */
192 #define NUM_ITERS 5 /* likewise */
194 static DEFINE_SPINLOCK(itc_sync_lock
);
195 static unsigned long go
[SLAVE
+ 1];
197 #define DEBUG_TICK_SYNC 0
199 static inline long get_delta (long *rt
, long *master
)
201 unsigned long best_t0
= 0, best_t1
= ~0UL, best_tm
= 0;
202 unsigned long tcenter
, t0
, t1
, tm
;
205 for (i
= 0; i
< NUM_ITERS
; i
++) {
206 t0
= tick_ops
->get_tick();
209 while (!(tm
= go
[SLAVE
]))
213 t1
= tick_ops
->get_tick();
215 if (t1
- t0
< best_t1
- best_t0
)
216 best_t0
= t0
, best_t1
= t1
, best_tm
= tm
;
219 *rt
= best_t1
- best_t0
;
220 *master
= best_tm
- best_t0
;
222 /* average best_t0 and best_t1 without overflow: */
223 tcenter
= (best_t0
/2 + best_t1
/2);
224 if (best_t0
% 2 + best_t1
% 2 == 2)
226 return tcenter
- best_tm
;
229 void smp_synchronize_tick_client(void)
231 long i
, delta
, adj
, adjust_latency
= 0, done
= 0;
232 unsigned long flags
, rt
, master_time_stamp
, bound
;
235 long rt
; /* roundtrip time */
236 long master
; /* master's timestamp */
237 long diff
; /* difference between midpoint and master's timestamp */
238 long lat
; /* estimate of itc adjustment latency */
247 local_irq_save(flags
);
249 for (i
= 0; i
< NUM_ROUNDS
; i
++) {
250 delta
= get_delta(&rt
, &master_time_stamp
);
252 done
= 1; /* let's lock on to this... */
258 adjust_latency
+= -delta
;
259 adj
= -delta
+ adjust_latency
/4;
263 tick_ops
->add_tick(adj
, current_tick_offset
);
267 t
[i
].master
= master_time_stamp
;
269 t
[i
].lat
= adjust_latency
/4;
273 local_irq_restore(flags
);
276 for (i
= 0; i
< NUM_ROUNDS
; i
++)
277 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
278 t
[i
].rt
, t
[i
].master
, t
[i
].diff
, t
[i
].lat
);
281 printk(KERN_INFO
"CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
282 "maxerr %lu cycles)\n", smp_processor_id(), delta
, rt
);
285 static void smp_start_sync_tick_client(int cpu
);
287 static void smp_synchronize_one_tick(int cpu
)
289 unsigned long flags
, i
;
293 smp_start_sync_tick_client(cpu
);
295 /* wait for client to be ready */
299 /* now let the client proceed into his loop */
303 spin_lock_irqsave(&itc_sync_lock
, flags
);
305 for (i
= 0; i
< NUM_ROUNDS
*NUM_ITERS
; i
++) {
310 go
[SLAVE
] = tick_ops
->get_tick();
314 spin_unlock_irqrestore(&itc_sync_lock
, flags
);
317 extern void sun4v_init_mondo_queues(int use_bootmem
, int cpu
, int alloc
, int load
);
319 extern unsigned long sparc64_cpu_startup
;
321 /* The OBP cpu startup callback truncates the 3rd arg cookie to
322 * 32-bits (I think) so to be safe we have it read the pointer
323 * contained here so we work on >4GB machines. -DaveM
325 static struct thread_info
*cpu_new_thread
= NULL
;
327 static int __devinit
smp_boot_one_cpu(unsigned int cpu
)
329 unsigned long entry
=
330 (unsigned long)(&sparc64_cpu_startup
);
331 unsigned long cookie
=
332 (unsigned long)(&cpu_new_thread
);
333 struct task_struct
*p
;
338 cpu_new_thread
= task_thread_info(p
);
339 cpu_set(cpu
, cpu_callout_map
);
341 if (tlb_type
== hypervisor
) {
342 /* Alloc the mondo queues, cpu will load them. */
343 sun4v_init_mondo_queues(0, cpu
, 1, 0);
345 prom_startcpu_cpuid(cpu
, entry
, cookie
);
349 cpu_find_by_mid(cpu
, &cpu_node
);
350 prom_startcpu(cpu_node
, entry
, cookie
);
353 for (timeout
= 0; timeout
< 5000000; timeout
++) {
362 printk("Processor %d is stuck.\n", cpu
);
363 cpu_clear(cpu
, cpu_callout_map
);
366 cpu_new_thread
= NULL
;
371 static void spitfire_xcall_helper(u64 data0
, u64 data1
, u64 data2
, u64 pstate
, unsigned long cpu
)
376 if (this_is_starfire
) {
377 /* map to real upaid */
378 cpu
= (((cpu
& 0x3c) << 1) |
379 ((cpu
& 0x40) >> 4) |
383 target
= (cpu
<< 14) | 0x70;
385 /* Ok, this is the real Spitfire Errata #54.
386 * One must read back from a UDB internal register
387 * after writes to the UDB interrupt dispatch, but
388 * before the membar Sync for that write.
389 * So we use the high UDB control register (ASI 0x7f,
390 * ADDR 0x20) for the dummy read. -DaveM
393 __asm__
__volatile__(
394 "wrpr %1, %2, %%pstate\n\t"
395 "stxa %4, [%0] %3\n\t"
396 "stxa %5, [%0+%8] %3\n\t"
398 "stxa %6, [%0+%8] %3\n\t"
400 "stxa %%g0, [%7] %3\n\t"
403 "ldxa [%%g1] 0x7f, %%g0\n\t"
406 : "r" (pstate
), "i" (PSTATE_IE
), "i" (ASI_INTR_W
),
407 "r" (data0
), "r" (data1
), "r" (data2
), "r" (target
),
408 "r" (0x10), "0" (tmp
)
411 /* NOTE: PSTATE_IE is still clear. */
414 __asm__
__volatile__("ldxa [%%g0] %1, %0"
416 : "i" (ASI_INTR_DISPATCH_STAT
));
418 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
425 } while (result
& 0x1);
426 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
429 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
430 smp_processor_id(), result
);
437 static __inline__
void spitfire_xcall_deliver(u64 data0
, u64 data1
, u64 data2
, cpumask_t mask
)
442 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
443 for_each_cpu_mask(i
, mask
)
444 spitfire_xcall_helper(data0
, data1
, data2
, pstate
, i
);
447 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
448 * packet, but we have no use for that. However we do take advantage of
449 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
451 static void cheetah_xcall_deliver(u64 data0
, u64 data1
, u64 data2
, cpumask_t mask
)
454 int nack_busy_id
, is_jbus
;
456 if (cpus_empty(mask
))
459 /* Unfortunately, someone at Sun had the brilliant idea to make the
460 * busy/nack fields hard-coded by ITID number for this Ultra-III
461 * derivative processor.
463 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
464 is_jbus
= ((ver
>> 32) == __JALAPENO_ID
||
465 (ver
>> 32) == __SERRANO_ID
);
467 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
470 __asm__
__volatile__("wrpr %0, %1, %%pstate\n\t"
471 : : "r" (pstate
), "i" (PSTATE_IE
));
473 /* Setup the dispatch data registers. */
474 __asm__
__volatile__("stxa %0, [%3] %6\n\t"
475 "stxa %1, [%4] %6\n\t"
476 "stxa %2, [%5] %6\n\t"
479 : "r" (data0
), "r" (data1
), "r" (data2
),
480 "r" (0x40), "r" (0x50), "r" (0x60),
487 for_each_cpu_mask(i
, mask
) {
488 u64 target
= (i
<< 14) | 0x70;
491 target
|= (nack_busy_id
<< 24);
492 __asm__
__volatile__(
493 "stxa %%g0, [%0] %1\n\t"
496 : "r" (target
), "i" (ASI_INTR_W
));
501 /* Now, poll for completion. */
506 stuck
= 100000 * nack_busy_id
;
508 __asm__
__volatile__("ldxa [%%g0] %1, %0"
509 : "=r" (dispatch_stat
)
510 : "i" (ASI_INTR_DISPATCH_STAT
));
511 if (dispatch_stat
== 0UL) {
512 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
518 } while (dispatch_stat
& 0x5555555555555555UL
);
520 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
523 if ((dispatch_stat
& ~(0x5555555555555555UL
)) == 0) {
524 /* Busy bits will not clear, continue instead
525 * of freezing up on this cpu.
527 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
528 smp_processor_id(), dispatch_stat
);
530 int i
, this_busy_nack
= 0;
532 /* Delay some random time with interrupts enabled
533 * to prevent deadlock.
535 udelay(2 * nack_busy_id
);
537 /* Clear out the mask bits for cpus which did not
540 for_each_cpu_mask(i
, mask
) {
544 check_mask
= (0x2UL
<< (2*i
));
546 check_mask
= (0x2UL
<<
548 if ((dispatch_stat
& check_mask
) == 0)
558 /* Multi-cpu list version. */
559 static int init_cpu_list(u16
*list
, cpumask_t mask
)
564 for_each_cpu_mask(i
, mask
)
570 static int update_cpu_list(u16
*list
, int orig_cnt
, cpumask_t mask
)
574 for (i
= 0; i
< orig_cnt
; i
++) {
575 if (list
[i
] == 0xffff)
579 return init_cpu_list(list
, mask
);
582 static void hypervisor_xcall_deliver(u64 data0
, u64 data1
, u64 data2
, cpumask_t mask
)
584 int this_cpu
= get_cpu();
585 struct trap_per_cpu
*tb
= &trap_block
[this_cpu
];
586 u64
*mondo
= __va(tb
->cpu_mondo_block_pa
);
587 u16
*cpu_list
= __va(tb
->cpu_list_pa
);
596 cnt
= init_cpu_list(cpu_list
, mask
);
598 register unsigned long func
__asm__("%o5");
599 register unsigned long arg0
__asm__("%o0");
600 register unsigned long arg1
__asm__("%o1");
601 register unsigned long arg2
__asm__("%o2");
603 func
= HV_FAST_CPU_MONDO_SEND
;
605 arg1
= tb
->cpu_list_pa
;
606 arg2
= tb
->cpu_mondo_block_pa
;
608 __asm__
__volatile__("ta %8"
609 : "=&r" (func
), "=&r" (arg0
),
610 "=&r" (arg1
), "=&r" (arg2
)
611 : "0" (func
), "1" (arg0
),
612 "2" (arg1
), "3" (arg2
),
615 if (likely(arg0
== HV_EOK
))
618 if (unlikely(++retries
> 100)) {
619 printk("CPU[%d]: sun4v mondo error %lu\n",
624 cnt
= update_cpu_list(cpu_list
, cnt
, mask
);
632 /* Send cross call to all processors mentioned in MASK
635 static void smp_cross_call_masked(unsigned long *func
, u32 ctx
, u64 data1
, u64 data2
, cpumask_t mask
)
637 u64 data0
= (((u64
)ctx
)<<32 | (((u64
)func
) & 0xffffffff));
638 int this_cpu
= get_cpu();
640 cpus_and(mask
, mask
, cpu_online_map
);
641 cpu_clear(this_cpu
, mask
);
643 if (tlb_type
== spitfire
)
644 spitfire_xcall_deliver(data0
, data1
, data2
, mask
);
645 else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
646 cheetah_xcall_deliver(data0
, data1
, data2
, mask
);
648 hypervisor_xcall_deliver(data0
, data1
, data2
, mask
);
649 /* NOTE: Caller runs local copy on master. */
654 extern unsigned long xcall_sync_tick
;
656 static void smp_start_sync_tick_client(int cpu
)
658 cpumask_t mask
= cpumask_of_cpu(cpu
);
660 smp_cross_call_masked(&xcall_sync_tick
,
664 /* Send cross call to all processors except self. */
665 #define smp_cross_call(func, ctx, data1, data2) \
666 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
668 struct call_data_struct
{
669 void (*func
) (void *info
);
675 static DEFINE_SPINLOCK(call_lock
);
676 static struct call_data_struct
*call_data
;
678 extern unsigned long xcall_call_function
;
681 * You must not call this function with disabled interrupts or from a
682 * hardware interrupt handler or from a bottom half handler.
684 static int smp_call_function_mask(void (*func
)(void *info
), void *info
,
685 int nonatomic
, int wait
, cpumask_t mask
)
687 struct call_data_struct data
;
688 int cpus
= cpus_weight(mask
) - 1;
694 /* Can deadlock when called with interrupts disabled */
695 WARN_ON(irqs_disabled());
699 atomic_set(&data
.finished
, 0);
702 spin_lock(&call_lock
);
706 smp_cross_call_masked(&xcall_call_function
, 0, 0, 0, mask
);
709 * Wait for other cpus to complete function or at
710 * least snap the call data.
713 while (atomic_read(&data
.finished
) != cpus
) {
720 spin_unlock(&call_lock
);
725 spin_unlock(&call_lock
);
726 printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
727 (long) num_online_cpus() - 1L,
728 (long) atomic_read(&data
.finished
));
732 int smp_call_function(void (*func
)(void *info
), void *info
,
733 int nonatomic
, int wait
)
735 return smp_call_function_mask(func
, info
, nonatomic
, wait
,
739 void smp_call_function_client(int irq
, struct pt_regs
*regs
)
741 void (*func
) (void *info
) = call_data
->func
;
742 void *info
= call_data
->info
;
744 clear_softint(1 << irq
);
745 if (call_data
->wait
) {
746 /* let initiator proceed only after completion */
748 atomic_inc(&call_data
->finished
);
750 /* let initiator proceed after getting data */
751 atomic_inc(&call_data
->finished
);
756 static void tsb_sync(void *info
)
758 struct mm_struct
*mm
= info
;
760 if (current
->active_mm
== mm
)
761 tsb_context_switch(mm
);
764 void smp_tsb_sync(struct mm_struct
*mm
)
766 smp_call_function_mask(tsb_sync
, mm
, 0, 1, mm
->cpu_vm_mask
);
769 extern unsigned long xcall_flush_tlb_mm
;
770 extern unsigned long xcall_flush_tlb_pending
;
771 extern unsigned long xcall_flush_tlb_kernel_range
;
772 extern unsigned long xcall_report_regs
;
773 extern unsigned long xcall_receive_signal
;
775 #ifdef DCACHE_ALIASING_POSSIBLE
776 extern unsigned long xcall_flush_dcache_page_cheetah
;
778 extern unsigned long xcall_flush_dcache_page_spitfire
;
780 #ifdef CONFIG_DEBUG_DCFLUSH
781 extern atomic_t dcpage_flushes
;
782 extern atomic_t dcpage_flushes_xcall
;
785 static __inline__
void __local_flush_dcache_page(struct page
*page
)
787 #ifdef DCACHE_ALIASING_POSSIBLE
788 __flush_dcache_page(page_address(page
),
789 ((tlb_type
== spitfire
) &&
790 page_mapping(page
) != NULL
));
792 if (page_mapping(page
) != NULL
&&
793 tlb_type
== spitfire
)
794 __flush_icache_page(__pa(page_address(page
)));
798 void smp_flush_dcache_page_impl(struct page
*page
, int cpu
)
800 cpumask_t mask
= cpumask_of_cpu(cpu
);
803 if (tlb_type
== hypervisor
)
806 #ifdef CONFIG_DEBUG_DCFLUSH
807 atomic_inc(&dcpage_flushes
);
810 this_cpu
= get_cpu();
812 if (cpu
== this_cpu
) {
813 __local_flush_dcache_page(page
);
814 } else if (cpu_online(cpu
)) {
815 void *pg_addr
= page_address(page
);
818 if (tlb_type
== spitfire
) {
820 ((u64
)&xcall_flush_dcache_page_spitfire
);
821 if (page_mapping(page
) != NULL
)
822 data0
|= ((u64
)1 << 32);
823 spitfire_xcall_deliver(data0
,
827 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
828 #ifdef DCACHE_ALIASING_POSSIBLE
830 ((u64
)&xcall_flush_dcache_page_cheetah
);
831 cheetah_xcall_deliver(data0
,
836 #ifdef CONFIG_DEBUG_DCFLUSH
837 atomic_inc(&dcpage_flushes_xcall
);
844 void flush_dcache_page_all(struct mm_struct
*mm
, struct page
*page
)
846 void *pg_addr
= page_address(page
);
847 cpumask_t mask
= cpu_online_map
;
851 if (tlb_type
== hypervisor
)
854 this_cpu
= get_cpu();
856 cpu_clear(this_cpu
, mask
);
858 #ifdef CONFIG_DEBUG_DCFLUSH
859 atomic_inc(&dcpage_flushes
);
861 if (cpus_empty(mask
))
863 if (tlb_type
== spitfire
) {
864 data0
= ((u64
)&xcall_flush_dcache_page_spitfire
);
865 if (page_mapping(page
) != NULL
)
866 data0
|= ((u64
)1 << 32);
867 spitfire_xcall_deliver(data0
,
871 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
872 #ifdef DCACHE_ALIASING_POSSIBLE
873 data0
= ((u64
)&xcall_flush_dcache_page_cheetah
);
874 cheetah_xcall_deliver(data0
,
879 #ifdef CONFIG_DEBUG_DCFLUSH
880 atomic_inc(&dcpage_flushes_xcall
);
883 __local_flush_dcache_page(page
);
888 static void __smp_receive_signal_mask(cpumask_t mask
)
890 smp_cross_call_masked(&xcall_receive_signal
, 0, 0, 0, mask
);
893 void smp_receive_signal(int cpu
)
895 cpumask_t mask
= cpumask_of_cpu(cpu
);
898 __smp_receive_signal_mask(mask
);
901 void smp_receive_signal_client(int irq
, struct pt_regs
*regs
)
903 struct mm_struct
*mm
;
905 clear_softint(1 << irq
);
907 /* See if we need to allocate a new TLB context because
908 * the version of the one we are using is now out of date.
910 mm
= current
->active_mm
;
912 if (unlikely(!CTX_VALID(mm
->context
))) {
915 spin_lock_irqsave(&mm
->context
.lock
, flags
);
916 get_new_mmu_context(mm
);
917 load_secondary_context(mm
);
918 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
923 void smp_new_mmu_context_version(void)
925 __smp_receive_signal_mask(cpu_online_map
);
928 void smp_report_regs(void)
930 smp_cross_call(&xcall_report_regs
, 0, 0, 0);
933 /* We know that the window frames of the user have been flushed
934 * to the stack before we get here because all callers of us
935 * are flush_tlb_*() routines, and these run after flush_cache_*()
936 * which performs the flushw.
938 * The SMP TLB coherency scheme we use works as follows:
940 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
941 * space has (potentially) executed on, this is the heuristic
942 * we use to avoid doing cross calls.
944 * Also, for flushing from kswapd and also for clones, we
945 * use cpu_vm_mask as the list of cpus to make run the TLB.
947 * 2) TLB context numbers are shared globally across all processors
948 * in the system, this allows us to play several games to avoid
951 * One invariant is that when a cpu switches to a process, and
952 * that processes tsk->active_mm->cpu_vm_mask does not have the
953 * current cpu's bit set, that tlb context is flushed locally.
955 * If the address space is non-shared (ie. mm->count == 1) we avoid
956 * cross calls when we want to flush the currently running process's
957 * tlb state. This is done by clearing all cpu bits except the current
958 * processor's in current->active_mm->cpu_vm_mask and performing the
959 * flush locally only. This will force any subsequent cpus which run
960 * this task to flush the context from the local tlb if the process
961 * migrates to another cpu (again).
963 * 3) For shared address spaces (threads) and swapping we bite the
964 * bullet for most cases and perform the cross call (but only to
965 * the cpus listed in cpu_vm_mask).
967 * The performance gain from "optimizing" away the cross call for threads is
968 * questionable (in theory the big win for threads is the massive sharing of
969 * address space state across processors).
972 /* This currently is only used by the hugetlb arch pre-fault
973 * hook on UltraSPARC-III+ and later when changing the pagesize
974 * bits of the context register for an address space.
976 void smp_flush_tlb_mm(struct mm_struct
*mm
)
978 u32 ctx
= CTX_HWBITS(mm
->context
);
981 if (atomic_read(&mm
->mm_users
) == 1) {
982 mm
->cpu_vm_mask
= cpumask_of_cpu(cpu
);
983 goto local_flush_and_out
;
986 smp_cross_call_masked(&xcall_flush_tlb_mm
,
991 __flush_tlb_mm(ctx
, SECONDARY_CONTEXT
);
996 void smp_flush_tlb_pending(struct mm_struct
*mm
, unsigned long nr
, unsigned long *vaddrs
)
998 u32 ctx
= CTX_HWBITS(mm
->context
);
1001 if (mm
== current
->active_mm
&& atomic_read(&mm
->mm_users
) == 1)
1002 mm
->cpu_vm_mask
= cpumask_of_cpu(cpu
);
1004 smp_cross_call_masked(&xcall_flush_tlb_pending
,
1005 ctx
, nr
, (unsigned long) vaddrs
,
1008 __flush_tlb_pending(ctx
, nr
, vaddrs
);
1013 void smp_flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
1016 end
= PAGE_ALIGN(end
);
1018 smp_cross_call(&xcall_flush_tlb_kernel_range
,
1021 __flush_tlb_kernel_range(start
, end
);
1026 /* #define CAPTURE_DEBUG */
1027 extern unsigned long xcall_capture
;
1029 static atomic_t smp_capture_depth
= ATOMIC_INIT(0);
1030 static atomic_t smp_capture_registry
= ATOMIC_INIT(0);
1031 static unsigned long penguins_are_doing_time
;
1033 void smp_capture(void)
1035 int result
= atomic_add_ret(1, &smp_capture_depth
);
1038 int ncpus
= num_online_cpus();
1040 #ifdef CAPTURE_DEBUG
1041 printk("CPU[%d]: Sending penguins to jail...",
1042 smp_processor_id());
1044 penguins_are_doing_time
= 1;
1045 membar_storestore_loadstore();
1046 atomic_inc(&smp_capture_registry
);
1047 smp_cross_call(&xcall_capture
, 0, 0, 0);
1048 while (atomic_read(&smp_capture_registry
) != ncpus
)
1050 #ifdef CAPTURE_DEBUG
1056 void smp_release(void)
1058 if (atomic_dec_and_test(&smp_capture_depth
)) {
1059 #ifdef CAPTURE_DEBUG
1060 printk("CPU[%d]: Giving pardon to "
1061 "imprisoned penguins\n",
1062 smp_processor_id());
1064 penguins_are_doing_time
= 0;
1065 membar_storeload_storestore();
1066 atomic_dec(&smp_capture_registry
);
1070 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1071 * can service tlb flush xcalls...
1073 extern void prom_world(int);
1075 void smp_penguin_jailcell(int irq
, struct pt_regs
*regs
)
1077 clear_softint(1 << irq
);
1081 __asm__
__volatile__("flushw");
1083 atomic_inc(&smp_capture_registry
);
1084 membar_storeload_storestore();
1085 while (penguins_are_doing_time
)
1087 atomic_dec(&smp_capture_registry
);
1093 #define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
1094 #define prof_counter(__cpu) cpu_data(__cpu).counter
1096 void smp_percpu_timer_interrupt(struct pt_regs
*regs
)
1098 unsigned long compare
, tick
, pstate
;
1099 int cpu
= smp_processor_id();
1100 int user
= user_mode(regs
);
1103 * Check for level 14 softint.
1106 unsigned long tick_mask
= tick_ops
->softint_mask
;
1108 if (!(get_softint() & tick_mask
)) {
1109 extern void handler_irq(int, struct pt_regs
*);
1111 handler_irq(14, regs
);
1114 clear_softint(tick_mask
);
1118 profile_tick(CPU_PROFILING
, regs
);
1119 if (!--prof_counter(cpu
)) {
1122 if (cpu
== boot_cpu_id
) {
1123 kstat_this_cpu
.irqs
[0]++;
1124 timer_tick_interrupt(regs
);
1127 update_process_times(user
);
1131 prof_counter(cpu
) = prof_multiplier(cpu
);
1134 /* Guarantee that the following sequences execute
1137 __asm__
__volatile__("rdpr %%pstate, %0\n\t"
1138 "wrpr %0, %1, %%pstate"
1142 compare
= tick_ops
->add_compare(current_tick_offset
);
1143 tick
= tick_ops
->get_tick();
1145 /* Restore PSTATE_IE. */
1146 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
1149 } while (time_after_eq(tick
, compare
));
1152 static void __init
smp_setup_percpu_timer(void)
1154 int cpu
= smp_processor_id();
1155 unsigned long pstate
;
1157 prof_counter(cpu
) = prof_multiplier(cpu
) = 1;
1159 /* Guarantee that the following sequences execute
1162 __asm__
__volatile__("rdpr %%pstate, %0\n\t"
1163 "wrpr %0, %1, %%pstate"
1167 tick_ops
->init_tick(current_tick_offset
);
1169 /* Restore PSTATE_IE. */
1170 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
1175 void __init
smp_tick_init(void)
1177 boot_cpu_id
= hard_smp_processor_id();
1178 current_tick_offset
= timer_tick_offset
;
1180 cpu_set(boot_cpu_id
, cpu_online_map
);
1181 prof_counter(boot_cpu_id
) = prof_multiplier(boot_cpu_id
) = 1;
1184 /* /proc/profile writes can call this, don't __init it please. */
1185 static DEFINE_SPINLOCK(prof_setup_lock
);
1187 int setup_profiling_timer(unsigned int multiplier
)
1189 unsigned long flags
;
1192 if ((!multiplier
) || (timer_tick_offset
/ multiplier
) < 1000)
1195 spin_lock_irqsave(&prof_setup_lock
, flags
);
1196 for (i
= 0; i
< NR_CPUS
; i
++)
1197 prof_multiplier(i
) = multiplier
;
1198 current_tick_offset
= (timer_tick_offset
/ multiplier
);
1199 spin_unlock_irqrestore(&prof_setup_lock
, flags
);
1204 /* Constrain the number of cpus to max_cpus. */
1205 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1207 if (num_possible_cpus() > max_cpus
) {
1211 while (!cpu_find_by_instance(instance
, NULL
, &mid
)) {
1212 if (mid
!= boot_cpu_id
) {
1213 cpu_clear(mid
, phys_cpu_present_map
);
1214 if (num_possible_cpus() <= max_cpus
)
1221 smp_store_cpu_info(boot_cpu_id
);
1224 /* Set this up early so that things like the scheduler can init
1225 * properly. We use the same cpu mask for both the present and
1228 void __init
smp_setup_cpu_possible_map(void)
1233 while (!cpu_find_by_instance(instance
, NULL
, &mid
)) {
1235 cpu_set(mid
, phys_cpu_present_map
);
1240 void __devinit
smp_prepare_boot_cpu(void)
1242 int cpu
= hard_smp_processor_id();
1244 if (cpu
>= NR_CPUS
) {
1245 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1249 current_thread_info()->cpu
= cpu
;
1250 __local_per_cpu_offset
= __per_cpu_offset(cpu
);
1252 cpu_set(smp_processor_id(), cpu_online_map
);
1253 cpu_set(smp_processor_id(), phys_cpu_present_map
);
1256 int __devinit
__cpu_up(unsigned int cpu
)
1258 int ret
= smp_boot_one_cpu(cpu
);
1261 cpu_set(cpu
, smp_commenced_mask
);
1262 while (!cpu_isset(cpu
, cpu_online_map
))
1264 if (!cpu_isset(cpu
, cpu_online_map
)) {
1267 /* On SUN4V, writes to %tick and %stick are
1270 if (tlb_type
!= hypervisor
)
1271 smp_synchronize_one_tick(cpu
);
1277 void __init
smp_cpus_done(unsigned int max_cpus
)
1279 unsigned long bogosum
= 0;
1282 for (i
= 0; i
< NR_CPUS
; i
++) {
1284 bogosum
+= cpu_data(i
).udelay_val
;
1286 printk("Total of %ld processors activated "
1287 "(%lu.%02lu BogoMIPS).\n",
1288 (long) num_online_cpus(),
1289 bogosum
/(500000/HZ
),
1290 (bogosum
/(5000/HZ
))%100);
1293 void smp_send_reschedule(int cpu
)
1295 smp_receive_signal(cpu
);
1298 /* This is a nop because we capture all other cpus
1299 * anyways when making the PROM active.
1301 void smp_send_stop(void)
1305 unsigned long __per_cpu_base __read_mostly
;
1306 unsigned long __per_cpu_shift __read_mostly
;
1308 EXPORT_SYMBOL(__per_cpu_base
);
1309 EXPORT_SYMBOL(__per_cpu_shift
);
1311 void __init
setup_per_cpu_areas(void)
1313 unsigned long goal
, size
, i
;
1316 /* Copy section for each CPU (we discard the original) */
1317 goal
= ALIGN(__per_cpu_end
- __per_cpu_start
, SMP_CACHE_BYTES
);
1318 #ifdef CONFIG_MODULES
1319 if (goal
< PERCPU_ENOUGH_ROOM
)
1320 goal
= PERCPU_ENOUGH_ROOM
;
1322 __per_cpu_shift
= 0;
1323 for (size
= 1UL; size
< goal
; size
<<= 1UL)
1326 ptr
= alloc_bootmem(size
* NR_CPUS
);
1328 __per_cpu_base
= ptr
- __per_cpu_start
;
1330 for (i
= 0; i
< NR_CPUS
; i
++, ptr
+= size
)
1331 memcpy(ptr
, __per_cpu_start
, __per_cpu_end
- __per_cpu_start
);