drivers/net/benet/be_hw.h

   1 /*
   2  * Copyright (C) 2005 - 2010 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 /********* Mailbox door bell *************/
  19 /* Used for driver communication with the FW.
  20  * The software must write this register twice to post any command. First,
  21  * it writes the register with hi=1 and the upper bits of the physical address
  22  * for the MAILBOX structure. Software must poll the ready bit until this
  23  * is acknowledged. Then, sotware writes the register with hi=0 with the lower
  24  * bits in the address. It must poll the ready bit until the command is
  25  * complete. Upon completion, the MAILBOX will contain a valid completion
  26  * queue entry.
  27  */
  28 #define MPU_MAILBOX_DB_OFFSET   0x160
  29 #define MPU_MAILBOX_DB_RDY_MASK 0x1     /* bit 0 */
  30 #define MPU_MAILBOX_DB_HI_MASK  0x2     /* bit 1 */
  31
  32 #define MPU_EP_CONTROL          0
  33
  34 /********** MPU semphore ******************/
  35 #define MPU_EP_SEMAPHORE_OFFSET         0xac
  36 #define EP_SEMAPHORE_POST_STAGE_MASK    0x0000FFFF
  37 #define EP_SEMAPHORE_POST_ERR_MASK      0x1
  38 #define EP_SEMAPHORE_POST_ERR_SHIFT     31
  39 /* MPU semphore POST stage values */
  40 #define POST_STAGE_AWAITING_HOST_RDY    0x1 /* FW awaiting goahead from host */
  41 #define POST_STAGE_HOST_RDY             0x2 /* Host has given go-ahed to FW */
  42 #define POST_STAGE_BE_RESET             0x3 /* Host wants to reset chip */
  43 #define POST_STAGE_ARMFW_RDY            0xc000  /* FW is done with POST */
  44
  45 /********* Memory BAR register ************/
  46 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
  47 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
  48  * Disable" may still globally block interrupts in addition to individual
  49  * interrupt masks; a mechanism for the device driver to block all interrupts
  50  * atomically without having to arbitrate for the PCI Interrupt Disable bit
  51  * with the OS.
  52  */
  53 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29) /* bit 29 */
  54
  55 /********* Power managment (WOL) **********/
  56 #define PCICFG_PM_CONTROL_OFFSET                0x44
  57 #define PCICFG_PM_CONTROL_MASK                  0x108   /* bits 3 & 8 */
  58
  59 /********* ISR0 Register offset **********/
  60 #define CEV_ISR0_OFFSET                         0xC18
  61 #define CEV_ISR_SIZE                            4
  62
  63 /********* Event Q door bell *************/
  64 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
  65 #define DB_EQ_RING_ID_MASK              0x1FF   /* bits 0 - 8 */
  66 /* Clear the interrupt for this eq */
  67 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
  68 /* Must be 1 */
  69 #define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
  70 /* Number of event entries processed */
  71 #define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
  72 /* Rearm bit */
  73 #define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
  74
  75 /********* Compl Q door bell *************/
  76 #define DB_CQ_OFFSET                    0x120
  77 #define DB_CQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
  78 /* Number of event entries processed */
  79 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
  80 /* Rearm bit */
  81 #define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
  82
  83 /********** TX ULP door bell *************/
  84 #define DB_TXULP1_OFFSET                0x60
  85 #define DB_TXULP_RING_ID_MASK           0x7FF   /* bits 0 - 10 */
  86 /* Number of tx entries posted */
  87 #define DB_TXULP_NUM_POSTED_SHIFT       (16)    /* bits 16 - 29 */
  88 #define DB_TXULP_NUM_POSTED_MASK        0x3FFF  /* bits 16 - 29 */
  89
  90 /********** RQ(erx) door bell ************/
  91 #define DB_RQ_OFFSET                    0x100
  92 #define DB_RQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
  93 /* Number of rx frags posted */
  94 #define DB_RQ_NUM_POSTED_SHIFT          (24)    /* bits 24 - 31 */
  95
  96 /********** MCC door bell ************/
  97 #define DB_MCCQ_OFFSET                  0x140
  98 #define DB_MCCQ_RING_ID_MASK            0x7FF   /* bits 0 - 10 */
  99 /* Number of entries posted */
 100 #define DB_MCCQ_NUM_POSTED_SHIFT        (16)    /* bits 16 - 29 */
 101
 102 /* Flashrom related descriptors */
 103 #define IMAGE_TYPE_FIRMWARE             160
 104 #define IMAGE_TYPE_BOOTCODE             224
 105 #define IMAGE_TYPE_OPTIONROM            32
 106
 107 #define NUM_FLASHDIR_ENTRIES            32
 108
 109 #define IMG_TYPE_ISCSI_ACTIVE           0
 110 #define IMG_TYPE_REDBOOT                1
 111 #define IMG_TYPE_BIOS                   2
 112 #define IMG_TYPE_PXE_BIOS               3
 113 #define IMG_TYPE_FCOE_BIOS              8
 114 #define IMG_TYPE_ISCSI_BACKUP           9
 115 #define IMG_TYPE_FCOE_FW_ACTIVE         10
 116 #define IMG_TYPE_FCOE_FW_BACKUP         11
 117 #define IMG_TYPE_NCSI_FW                13
 118
 119 #define FLASHROM_OPER_FLASH             1
 120 #define FLASHROM_OPER_SAVE              2
 121 #define FLASHROM_OPER_REPORT            4
 122
 123 #define FLASH_IMAGE_MAX_SIZE_g2            (1310720) /* Max firmware image sz */
 124 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2       (262144)  /* Max OPTION ROM img sz */
 125 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2   (262144)  /* Max Redboot image sz */
 126 #define FLASH_IMAGE_MAX_SIZE_g3            (2097152) /* Max fw image size */
 127 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3       (524288)  /* Max OPTION ROM img sz */
 128 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3   (1048576)  /* Max Redboot image sz */
 129 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3       (262144)  /* Max NSCI image sz */
 130
 131 #define FLASH_NCSI_MAGIC                (0x16032009)
 132 #define FLASH_NCSI_DISABLED             (0)
 133 #define FLASH_NCSI_ENABLED              (1)
 134
 135 #define FLASH_NCSI_BITFILE_HDR_OFFSET   (0x600000)
 136
 137 /* Offsets for components on Flash. */
 138 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
 139 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2  (2359296)
 140 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2  (3670016)
 141 #define FLASH_FCoE_BACKUP_IMAGE_START_g2   (4980736)
 142 #define FLASH_iSCSI_BIOS_START_g2          (7340032)
 143 #define FLASH_PXE_BIOS_START_g2            (7864320)
 144 #define FLASH_FCoE_BIOS_START_g2           (524288)
 145 #define FLASH_REDBOOT_START_g2            (0)
 146
 147 #define FLASH_NCSI_START_g3                (15990784)
 148 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
 149 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3  (4194304)
 150 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3  (6291456)
 151 #define FLASH_FCoE_BACKUP_IMAGE_START_g3   (8388608)
 152 #define FLASH_iSCSI_BIOS_START_g3          (12582912)
 153 #define FLASH_PXE_BIOS_START_g3            (13107200)
 154 #define FLASH_FCoE_BIOS_START_g3           (13631488)
 155 #define FLASH_REDBOOT_START_g3             (262144)
 156
 157
 158
 159
 160 /*
 161  * BE descriptors: host memory data structures whose formats
 162  * are hardwired in BE silicon.
 163  */
 164 /* Event Queue Descriptor */
 165 #define EQ_ENTRY_VALID_MASK             0x1     /* bit 0 */
 166 #define EQ_ENTRY_RES_ID_MASK            0xFFFF  /* bits 16 - 31 */
 167 #define EQ_ENTRY_RES_ID_SHIFT           16
 168
 169 struct be_eq_entry {
 170         u32 evt;
 171 };
 172
 173 /* TX Queue Descriptor */
 174 #define ETH_WRB_FRAG_LEN_MASK           0xFFFF
 175 struct be_eth_wrb {
 176         u32 frag_pa_hi;         /* dword 0 */
 177         u32 frag_pa_lo;         /* dword 1 */
 178         u32 rsvd0;              /* dword 2 */
 179         u32 frag_len;           /* dword 3: bits 0 - 15 */
 180 } __packed;
 181
 182 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
 183  * actual structure is defined as a byte : used to calculate
 184  * offset/shift/mask of each field */
 185 struct amap_eth_hdr_wrb {
 186         u8 rsvd0[32];           /* dword 0 */
 187         u8 rsvd1[32];           /* dword 1 */
 188         u8 complete;            /* dword 2 */
 189         u8 event;
 190         u8 crc;
 191         u8 forward;
 192         u8 ipsec;
 193         u8 mgmt;
 194         u8 ipcs;
 195         u8 udpcs;
 196         u8 tcpcs;
 197         u8 lso;
 198         u8 vlan;
 199         u8 gso[2];
 200         u8 num_wrb[5];
 201         u8 lso_mss[14];
 202         u8 len[16];             /* dword 3 */
 203         u8 vlan_tag[16];
 204 } __packed;
 205
 206 struct be_eth_hdr_wrb {
 207         u32 dw[4];
 208 };
 209
 210 /* TX Compl Queue Descriptor */
 211
 212 /* Pseudo amap definition for eth_tx_compl in which each bit of the
 213  * actual structure is defined as a byte: used to calculate
 214  * offset/shift/mask of each field */
 215 struct amap_eth_tx_compl {
 216         u8 wrb_index[16];       /* dword 0 */
 217         u8 ct[2];               /* dword 0 */
 218         u8 port[2];             /* dword 0 */
 219         u8 rsvd0[8];            /* dword 0 */
 220         u8 status[4];           /* dword 0 */
 221         u8 user_bytes[16];      /* dword 1 */
 222         u8 nwh_bytes[8];        /* dword 1 */
 223         u8 lso;                 /* dword 1 */
 224         u8 cast_enc[2];         /* dword 1 */
 225         u8 rsvd1[5];            /* dword 1 */
 226         u8 rsvd2[32];           /* dword 2 */
 227         u8 pkts[16];            /* dword 3 */
 228         u8 ringid[11];          /* dword 3 */
 229         u8 hash_val[4];         /* dword 3 */
 230         u8 valid;               /* dword 3 */
 231 } __packed;
 232
 233 struct be_eth_tx_compl {
 234         u32 dw[4];
 235 };
 236
 237 /* RX Queue Descriptor */
 238 struct be_eth_rx_d {
 239         u32 fragpa_hi;
 240         u32 fragpa_lo;
 241 };
 242
 243 /* RX Compl Queue Descriptor */
 244
 245 /* Pseudo amap definition for eth_rx_compl in which each bit of the
 246  * actual structure is defined as a byte: used to calculate
 247  * offset/shift/mask of each field */
 248 struct amap_eth_rx_compl {
 249         u8 vlan_tag[16];        /* dword 0 */
 250         u8 pktsize[14];         /* dword 0 */
 251         u8 port;                /* dword 0 */
 252         u8 ip_opt;              /* dword 0 */
 253         u8 err;                 /* dword 1 */
 254         u8 rsshp;               /* dword 1 */
 255         u8 ipf;                 /* dword 1 */
 256         u8 tcpf;                /* dword 1 */
 257         u8 udpf;                /* dword 1 */
 258         u8 ipcksm;              /* dword 1 */
 259         u8 l4_cksm;             /* dword 1 */
 260         u8 ip_version;          /* dword 1 */
 261         u8 macdst[6];           /* dword 1 */
 262         u8 vtp;                 /* dword 1 */
 263         u8 rsvd0;               /* dword 1 */
 264         u8 fragndx[10];         /* dword 1 */
 265         u8 ct[2];               /* dword 1 */
 266         u8 sw;                  /* dword 1 */
 267         u8 numfrags[3];         /* dword 1 */
 268         u8 rss_flush;           /* dword 2 */
 269         u8 cast_enc[2];         /* dword 2 */
 270         u8 vtm;                 /* dword 2 */
 271         u8 rss_bank;            /* dword 2 */
 272         u8 rsvd1[23];           /* dword 2 */
 273         u8 lro_pkt;             /* dword 2 */
 274         u8 rsvd2[2];            /* dword 2 */
 275         u8 valid;               /* dword 2 */
 276         u8 rsshash[32];         /* dword 3 */
 277 } __packed;
 278
 279 struct be_eth_rx_compl {
 280         u32 dw[4];
 281 };
 282
 283 struct controller_id {
 284         u32 vendor;
 285         u32 device;
 286         u32 subvendor;
 287         u32 subdevice;
 288 };
 289
 290 struct flash_comp {
 291         unsigned long offset;
 292         int optype;
 293         int size;
 294 };
 295
 296 struct image_hdr {
 297         u32 imageid;
 298         u32 imageoffset;
 299         u32 imagelength;
 300         u32 image_checksum;
 301         u8 image_version[32];
 302 };
 303 struct flash_file_hdr_g2 {
 304         u8 sign[32];
 305         u32 cksum;
 306         u32 antidote;
 307         struct controller_id cont_id;
 308         u32 file_len;
 309         u32 chunk_num;
 310         u32 total_chunks;
 311         u32 num_imgs;
 312         u8 build[24];
 313 };
 314
 315 struct flash_file_hdr_g3 {
 316         u8 sign[52];
 317         u8 ufi_version[4];
 318         u32 file_len;
 319         u32 cksum;
 320         u32 antidote;
 321         u32 num_imgs;
 322         u8 build[24];
 323         u8 rsvd[32];
 324 };
 325
 326 struct flash_section_hdr {
 327         u32 format_rev;
 328         u32 cksum;
 329         u32 antidote;
 330         u32 build_no;
 331         u8 id_string[64];
 332         u32 active_entry_mask;
 333         u32 valid_entry_mask;
 334         u32 org_content_mask;
 335         u32 rsvd0;
 336         u32 rsvd1;
 337         u32 rsvd2;
 338         u32 rsvd3;
 339         u32 rsvd4;
 340 };
 341
 342 struct flash_section_entry {
 343         u32 type;
 344         u32 offset;
 345         u32 pad_size;
 346         u32 image_size;
 347         u32 cksum;
 348         u32 entry_point;
 349         u32 rsvd0;
 350         u32 rsvd1;
 351         u8 ver_data[32];
 352 };
 353
 354 struct flash_section_info {
 355         u8 cookie[32];
 356         struct flash_section_hdr fsec_hdr;
 357         struct flash_section_entry fsec_entry[32];
 358 };