2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
18 * Intel documents this fairly well, and as far as I know there
19 * are no royalties or anything like that, but even so there are
20 * people who decided that they want to do the same thing in a
21 * completely different way.
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/errno.h>
33 #include <linux/unistd.h>
34 #include <linux/interrupt.h>
35 #include <linux/spinlock.h>
36 #include <linux/debugfs.h>
38 #include <linux/dmapool.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/usb.h>
41 #include <linux/usb/hcd.h>
42 #include <linux/bitops.h>
43 #include <linux/dmi.h>
45 #include <asm/uaccess.h>
48 #include <asm/system.h>
55 #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \
56 Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \
58 #define DRIVER_DESC "USB Universal Host Controller Interface driver"
60 /* for flakey hardware, ignore overcurrent indicators */
62 module_param(ignore_oc
, bool, S_IRUGO
);
63 MODULE_PARM_DESC(ignore_oc
, "ignore hardware overcurrent indications");
66 * debug = 0, no debugging messages
67 * debug = 1, dump failed URBs except for stalls
68 * debug = 2, dump all failed URBs (including stalls)
69 * show all queues in /sys/kernel/debug/uhci/[pci_addr]
70 * debug = 3, show all TDs in URBs when dumping
73 #define DEBUG_CONFIGURED 1
75 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
76 MODULE_PARM_DESC(debug
, "Debug level");
79 #define DEBUG_CONFIGURED 0
84 #define ERRBUF_LEN (32 * 1024)
86 static struct kmem_cache
*uhci_up_cachep
; /* urb_priv */
88 static void suspend_rh(struct uhci_hcd
*uhci
, enum uhci_rh_state new_state
);
89 static void wakeup_rh(struct uhci_hcd
*uhci
);
90 static void uhci_get_current_frame_number(struct uhci_hcd
*uhci
);
93 * Calculate the link pointer DMA value for the first Skeleton QH in a frame.
95 static __le32
uhci_frame_skel_link(struct uhci_hcd
*uhci
, int frame
)
100 * The interrupt queues will be interleaved as evenly as possible.
101 * There's not much to be done about period-1 interrupts; they have
102 * to occur in every frame. But we can schedule period-2 interrupts
103 * in odd-numbered frames, period-4 interrupts in frames congruent
104 * to 2 (mod 4), and so on. This way each frame only has two
105 * interrupt QHs, which will help spread out bandwidth utilization.
107 * ffs (Find First bit Set) does exactly what we need:
108 * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8],
109 * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc.
110 * ffs >= 7 => not on any high-period queue, so use
111 * period-1 QH = skelqh[9].
112 * Add in UHCI_NUMFRAMES to insure at least one bit is set.
114 skelnum
= 8 - (int) __ffs(frame
| UHCI_NUMFRAMES
);
117 return LINK_TO_QH(uhci
->skelqh
[skelnum
]);
120 #include "uhci-debug.c"
122 #include "uhci-hub.c"
125 * Finish up a host controller reset and update the recorded state.
127 static void finish_reset(struct uhci_hcd
*uhci
)
131 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
132 * bits in the port status and control registers.
133 * We have to clear them by hand.
135 for (port
= 0; port
< uhci
->rh_numports
; ++port
)
136 uhci_writew(uhci
, 0, USBPORTSC1
+ (port
* 2));
138 uhci
->port_c_suspend
= uhci
->resuming_ports
= 0;
139 uhci
->rh_state
= UHCI_RH_RESET
;
140 uhci
->is_stopped
= UHCI_IS_STOPPED
;
141 clear_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
145 * Last rites for a defunct/nonfunctional controller
146 * or one we don't want to use any more.
148 static void uhci_hc_died(struct uhci_hcd
*uhci
)
150 uhci_get_current_frame_number(uhci
);
151 uhci
->reset_hc(uhci
);
155 /* The current frame may already be partway finished */
156 ++uhci
->frame_number
;
160 * Initialize a controller that was newly discovered or has lost power
161 * or otherwise been reset while it was suspended. In none of these cases
162 * can we be sure of its previous state.
164 static void check_and_reset_hc(struct uhci_hcd
*uhci
)
166 if (uhci
->check_and_reset_hc(uhci
))
171 * Store the basic register settings needed by the controller.
173 static void configure_hc(struct uhci_hcd
*uhci
)
175 /* Set the frame length to the default: 1 ms exactly */
176 uhci_writeb(uhci
, USBSOF_DEFAULT
, USBSOF
);
178 /* Store the frame list base address */
179 uhci_writel(uhci
, uhci
->frame_dma_handle
, USBFLBASEADD
);
181 /* Set the current frame number */
182 uhci_writew(uhci
, uhci
->frame_number
& UHCI_MAX_SOF_NUMBER
,
185 /* perform any arch/bus specific configuration */
186 if (uhci
->configure_hc
)
187 uhci
->configure_hc(uhci
);
190 static int resume_detect_interrupts_are_broken(struct uhci_hcd
*uhci
)
192 /* If we have to ignore overcurrent events then almost by definition
193 * we can't depend on resume-detect interrupts. */
197 return uhci
->resume_detect_interrupts_are_broken
?
198 uhci
->resume_detect_interrupts_are_broken(uhci
) : 0;
201 static int global_suspend_mode_is_broken(struct uhci_hcd
*uhci
)
203 return uhci
->global_suspend_mode_is_broken
?
204 uhci
->global_suspend_mode_is_broken(uhci
) : 0;
207 static void suspend_rh(struct uhci_hcd
*uhci
, enum uhci_rh_state new_state
)
208 __releases(uhci
->lock
)
209 __acquires(uhci
->lock
)
212 int int_enable
, egsm_enable
, wakeup_enable
;
213 struct usb_device
*rhdev
= uhci_to_hcd(uhci
)->self
.root_hub
;
215 auto_stop
= (new_state
== UHCI_RH_AUTO_STOPPED
);
216 dev_dbg(&rhdev
->dev
, "%s%s\n", __func__
,
217 (auto_stop
? " (auto-stop)" : ""));
219 /* Start off by assuming Resume-Detect interrupts and EGSM work
220 * and that remote wakeups should be enabled.
222 egsm_enable
= USBCMD_EGSM
;
224 int_enable
= USBINTR_RESUME
;
227 /* In auto-stop mode wakeups must always be detected, but
228 * Resume-Detect interrupts may be prohibited. (In the absence
229 * of CONFIG_PM, they are always disallowed.)
232 if (!device_may_wakeup(&rhdev
->dev
))
235 /* In bus-suspend mode wakeups may be disabled, but if they are
236 * allowed then so are Resume-Detect interrupts.
240 if (!rhdev
->do_remote_wakeup
)
245 /* EGSM causes the root hub to echo a 'K' signal (resume) out any
246 * port which requests a remote wakeup. According to the USB spec,
247 * every hub is supposed to do this. But if we are ignoring
248 * remote-wakeup requests anyway then there's no point to it.
249 * We also shouldn't enable EGSM if it's broken.
251 if (!wakeup_enable
|| global_suspend_mode_is_broken(uhci
))
254 /* If we're ignoring wakeup events then there's no reason to
255 * enable Resume-Detect interrupts. We also shouldn't enable
256 * them if they are broken or disallowed.
258 * This logic may lead us to enabling RD but not EGSM. The UHCI
259 * spec foolishly says that RD works only when EGSM is on, but
260 * there's no harm in enabling it anyway -- perhaps some chips
263 if (!wakeup_enable
|| resume_detect_interrupts_are_broken(uhci
) ||
265 uhci
->RD_enable
= int_enable
= 0;
267 uhci_writew(uhci
, int_enable
, USBINTR
);
268 uhci_writew(uhci
, egsm_enable
| USBCMD_CF
, USBCMD
);
272 /* If we're auto-stopping then no devices have been attached
273 * for a while, so there shouldn't be any active URBs and the
274 * controller should stop after a few microseconds. Otherwise
275 * we will give the controller one frame to stop.
277 if (!auto_stop
&& !(uhci_readw(uhci
, USBSTS
) & USBSTS_HCH
)) {
278 uhci
->rh_state
= UHCI_RH_SUSPENDING
;
279 spin_unlock_irq(&uhci
->lock
);
281 spin_lock_irq(&uhci
->lock
);
285 if (!(uhci_readw(uhci
, USBSTS
) & USBSTS_HCH
))
286 dev_warn(uhci_dev(uhci
), "Controller not stopped yet!\n");
288 uhci_get_current_frame_number(uhci
);
290 uhci
->rh_state
= new_state
;
291 uhci
->is_stopped
= UHCI_IS_STOPPED
;
293 /* If interrupts don't work and remote wakeup is enabled then
294 * the suspended root hub needs to be polled.
296 if (!int_enable
&& wakeup_enable
)
297 set_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
299 clear_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
301 uhci_scan_schedule(uhci
);
305 static void start_rh(struct uhci_hcd
*uhci
)
307 uhci
->is_stopped
= 0;
309 /* Mark it configured and running with a 64-byte max packet.
310 * All interrupts are enabled, even though RESUME won't do anything.
312 uhci_writew(uhci
, USBCMD_RS
| USBCMD_CF
| USBCMD_MAXP
, USBCMD
);
313 uhci_writew(uhci
, USBINTR_TIMEOUT
| USBINTR_RESUME
|
314 USBINTR_IOC
| USBINTR_SP
, USBINTR
);
316 uhci
->rh_state
= UHCI_RH_RUNNING
;
317 set_bit(HCD_FLAG_POLL_RH
, &uhci_to_hcd(uhci
)->flags
);
320 static void wakeup_rh(struct uhci_hcd
*uhci
)
321 __releases(uhci
->lock
)
322 __acquires(uhci
->lock
)
324 dev_dbg(&uhci_to_hcd(uhci
)->self
.root_hub
->dev
,
326 uhci
->rh_state
== UHCI_RH_AUTO_STOPPED
?
327 " (auto-start)" : "");
329 /* If we are auto-stopped then no devices are attached so there's
330 * no need for wakeup signals. Otherwise we send Global Resume
333 if (uhci
->rh_state
== UHCI_RH_SUSPENDED
) {
336 /* Keep EGSM on if it was set before */
337 egsm
= uhci_readw(uhci
, USBCMD
) & USBCMD_EGSM
;
338 uhci
->rh_state
= UHCI_RH_RESUMING
;
339 uhci_writew(uhci
, USBCMD_FGR
| USBCMD_CF
| egsm
, USBCMD
);
340 spin_unlock_irq(&uhci
->lock
);
342 spin_lock_irq(&uhci
->lock
);
346 /* End Global Resume and wait for EOP to be sent */
347 uhci_writew(uhci
, USBCMD_CF
, USBCMD
);
350 if (uhci_readw(uhci
, USBCMD
) & USBCMD_FGR
)
351 dev_warn(uhci_dev(uhci
), "FGR not stopped yet!\n");
356 /* Restart root hub polling */
357 mod_timer(&uhci_to_hcd(uhci
)->rh_timer
, jiffies
);
360 static irqreturn_t
uhci_irq(struct usb_hcd
*hcd
)
362 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
363 unsigned short status
;
366 * Read the interrupt status, and write it back to clear the
367 * interrupt cause. Contrary to the UHCI specification, the
368 * "HC Halted" status bit is persistent: it is RO, not R/WC.
370 status
= uhci_readw(uhci
, USBSTS
);
371 if (!(status
& ~USBSTS_HCH
)) /* shared interrupt, not mine */
373 uhci_writew(uhci
, status
, USBSTS
); /* Clear it */
375 if (status
& ~(USBSTS_USBINT
| USBSTS_ERROR
| USBSTS_RD
)) {
376 if (status
& USBSTS_HSE
)
377 dev_err(uhci_dev(uhci
), "host system error, "
379 if (status
& USBSTS_HCPE
)
380 dev_err(uhci_dev(uhci
), "host controller process "
381 "error, something bad happened!\n");
382 if (status
& USBSTS_HCH
) {
383 spin_lock(&uhci
->lock
);
384 if (uhci
->rh_state
>= UHCI_RH_RUNNING
) {
385 dev_err(uhci_dev(uhci
),
386 "host controller halted, "
388 if (debug
> 1 && errbuf
) {
389 /* Print the schedule for debugging */
390 uhci_sprint_schedule(uhci
,
397 /* Force a callback in case there are
399 mod_timer(&hcd
->rh_timer
, jiffies
);
401 spin_unlock(&uhci
->lock
);
405 if (status
& USBSTS_RD
)
406 usb_hcd_poll_rh_status(hcd
);
408 spin_lock(&uhci
->lock
);
409 uhci_scan_schedule(uhci
);
410 spin_unlock(&uhci
->lock
);
417 * Store the current frame number in uhci->frame_number if the controller
418 * is running. Expand from 11 bits (of which we use only 10) to a
419 * full-sized integer.
421 * Like many other parts of the driver, this code relies on being polled
422 * more than once per second as long as the controller is running.
424 static void uhci_get_current_frame_number(struct uhci_hcd
*uhci
)
426 if (!uhci
->is_stopped
) {
429 delta
= (uhci_readw(uhci
, USBFRNUM
) - uhci
->frame_number
) &
430 (UHCI_NUMFRAMES
- 1);
431 uhci
->frame_number
+= delta
;
436 * De-allocate all resources
438 static void release_uhci(struct uhci_hcd
*uhci
)
442 if (DEBUG_CONFIGURED
) {
443 spin_lock_irq(&uhci
->lock
);
444 uhci
->is_initialized
= 0;
445 spin_unlock_irq(&uhci
->lock
);
447 debugfs_remove(uhci
->dentry
);
450 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++)
451 uhci_free_qh(uhci
, uhci
->skelqh
[i
]);
453 uhci_free_td(uhci
, uhci
->term_td
);
455 dma_pool_destroy(uhci
->qh_pool
);
457 dma_pool_destroy(uhci
->td_pool
);
459 kfree(uhci
->frame_cpu
);
461 dma_free_coherent(uhci_dev(uhci
),
462 UHCI_NUMFRAMES
* sizeof(*uhci
->frame
),
463 uhci
->frame
, uhci
->frame_dma_handle
);
467 * Allocate a frame list, and then setup the skeleton
469 * The hardware doesn't really know any difference
470 * in the queues, but the order does matter for the
471 * protocols higher up. The order in which the queues
472 * are encountered by the hardware is:
474 * - All isochronous events are handled before any
475 * of the queues. We don't do that here, because
476 * we'll create the actual TD entries on demand.
477 * - The first queue is the high-period interrupt queue.
478 * - The second queue is the period-1 interrupt and async
479 * (low-speed control, full-speed control, then bulk) queue.
480 * - The third queue is the terminating bandwidth reclamation queue,
481 * which contains no members, loops back to itself, and is present
482 * only when FSBR is on and there are no full-speed control or bulk QHs.
484 static int uhci_start(struct usb_hcd
*hcd
)
486 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
489 struct dentry __maybe_unused
*dentry
;
491 hcd
->uses_new_polling
= 1;
493 spin_lock_init(&uhci
->lock
);
494 setup_timer(&uhci
->fsbr_timer
, uhci_fsbr_timeout
,
495 (unsigned long) uhci
);
496 INIT_LIST_HEAD(&uhci
->idle_qh_list
);
497 init_waitqueue_head(&uhci
->waitqh
);
499 #ifdef UHCI_DEBUG_OPS
500 dentry
= debugfs_create_file(hcd
->self
.bus_name
,
501 S_IFREG
|S_IRUGO
|S_IWUSR
, uhci_debugfs_root
,
502 uhci
, &uhci_debug_operations
);
504 dev_err(uhci_dev(uhci
), "couldn't create uhci debugfs entry\n");
507 uhci
->dentry
= dentry
;
510 uhci
->frame
= dma_alloc_coherent(uhci_dev(uhci
),
511 UHCI_NUMFRAMES
* sizeof(*uhci
->frame
),
512 &uhci
->frame_dma_handle
, 0);
514 dev_err(uhci_dev(uhci
), "unable to allocate "
515 "consistent memory for frame list\n");
516 goto err_alloc_frame
;
518 memset(uhci
->frame
, 0, UHCI_NUMFRAMES
* sizeof(*uhci
->frame
));
520 uhci
->frame_cpu
= kcalloc(UHCI_NUMFRAMES
, sizeof(*uhci
->frame_cpu
),
522 if (!uhci
->frame_cpu
) {
523 dev_err(uhci_dev(uhci
), "unable to allocate "
524 "memory for frame pointers\n");
525 goto err_alloc_frame_cpu
;
528 uhci
->td_pool
= dma_pool_create("uhci_td", uhci_dev(uhci
),
529 sizeof(struct uhci_td
), 16, 0);
530 if (!uhci
->td_pool
) {
531 dev_err(uhci_dev(uhci
), "unable to create td dma_pool\n");
532 goto err_create_td_pool
;
535 uhci
->qh_pool
= dma_pool_create("uhci_qh", uhci_dev(uhci
),
536 sizeof(struct uhci_qh
), 16, 0);
537 if (!uhci
->qh_pool
) {
538 dev_err(uhci_dev(uhci
), "unable to create qh dma_pool\n");
539 goto err_create_qh_pool
;
542 uhci
->term_td
= uhci_alloc_td(uhci
);
543 if (!uhci
->term_td
) {
544 dev_err(uhci_dev(uhci
), "unable to allocate terminating TD\n");
545 goto err_alloc_term_td
;
548 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++) {
549 uhci
->skelqh
[i
] = uhci_alloc_qh(uhci
, NULL
, NULL
);
550 if (!uhci
->skelqh
[i
]) {
551 dev_err(uhci_dev(uhci
), "unable to allocate QH\n");
552 goto err_alloc_skelqh
;
557 * 8 Interrupt queues; link all higher int queues to int1 = async
559 for (i
= SKEL_ISO
+ 1; i
< SKEL_ASYNC
; ++i
)
560 uhci
->skelqh
[i
]->link
= LINK_TO_QH(uhci
->skel_async_qh
);
561 uhci
->skel_async_qh
->link
= UHCI_PTR_TERM
;
562 uhci
->skel_term_qh
->link
= LINK_TO_QH(uhci
->skel_term_qh
);
564 /* This dummy TD is to work around a bug in Intel PIIX controllers */
565 uhci_fill_td(uhci
->term_td
, 0, uhci_explen(0) |
566 (0x7f << TD_TOKEN_DEVADDR_SHIFT
) | USB_PID_IN
, 0);
567 uhci
->term_td
->link
= UHCI_PTR_TERM
;
568 uhci
->skel_async_qh
->element
= uhci
->skel_term_qh
->element
=
569 LINK_TO_TD(uhci
->term_td
);
572 * Fill the frame list: make all entries point to the proper
575 for (i
= 0; i
< UHCI_NUMFRAMES
; i
++) {
577 /* Only place we don't use the frame list routines */
578 uhci
->frame
[i
] = uhci_frame_skel_link(uhci
, i
);
582 * Some architectures require a full mb() to enforce completion of
583 * the memory writes above before the I/O transfers in configure_hc().
588 uhci
->is_initialized
= 1;
589 spin_lock_irq(&uhci
->lock
);
591 spin_unlock_irq(&uhci
->lock
);
598 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++) {
600 uhci_free_qh(uhci
, uhci
->skelqh
[i
]);
603 uhci_free_td(uhci
, uhci
->term_td
);
606 dma_pool_destroy(uhci
->qh_pool
);
609 dma_pool_destroy(uhci
->td_pool
);
612 kfree(uhci
->frame_cpu
);
615 dma_free_coherent(uhci_dev(uhci
),
616 UHCI_NUMFRAMES
* sizeof(*uhci
->frame
),
617 uhci
->frame
, uhci
->frame_dma_handle
);
620 debugfs_remove(uhci
->dentry
);
625 static void uhci_stop(struct usb_hcd
*hcd
)
627 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
629 spin_lock_irq(&uhci
->lock
);
630 if (HCD_HW_ACCESSIBLE(hcd
) && !uhci
->dead
)
632 uhci_scan_schedule(uhci
);
633 spin_unlock_irq(&uhci
->lock
);
634 synchronize_irq(hcd
->irq
);
636 del_timer_sync(&uhci
->fsbr_timer
);
641 static int uhci_rh_suspend(struct usb_hcd
*hcd
)
643 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
646 spin_lock_irq(&uhci
->lock
);
647 if (!HCD_HW_ACCESSIBLE(hcd
))
650 ; /* Dead controllers tell no tales */
652 /* Once the controller is stopped, port resumes that are already
653 * in progress won't complete. Hence if remote wakeup is enabled
654 * for the root hub and any ports are in the middle of a resume or
655 * remote wakeup, we must fail the suspend.
657 else if (hcd
->self
.root_hub
->do_remote_wakeup
&&
658 uhci
->resuming_ports
) {
659 dev_dbg(uhci_dev(uhci
), "suspend failed because a port "
663 suspend_rh(uhci
, UHCI_RH_SUSPENDED
);
664 spin_unlock_irq(&uhci
->lock
);
668 static int uhci_rh_resume(struct usb_hcd
*hcd
)
670 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
673 spin_lock_irq(&uhci
->lock
);
674 if (!HCD_HW_ACCESSIBLE(hcd
))
676 else if (!uhci
->dead
)
678 spin_unlock_irq(&uhci
->lock
);
684 /* Wait until a particular device/endpoint's QH is idle, and free it */
685 static void uhci_hcd_endpoint_disable(struct usb_hcd
*hcd
,
686 struct usb_host_endpoint
*hep
)
688 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
691 spin_lock_irq(&uhci
->lock
);
692 qh
= (struct uhci_qh
*) hep
->hcpriv
;
696 while (qh
->state
!= QH_STATE_IDLE
) {
698 spin_unlock_irq(&uhci
->lock
);
699 wait_event_interruptible(uhci
->waitqh
,
700 qh
->state
== QH_STATE_IDLE
);
701 spin_lock_irq(&uhci
->lock
);
705 uhci_free_qh(uhci
, qh
);
707 spin_unlock_irq(&uhci
->lock
);
710 static int uhci_hcd_get_frame_number(struct usb_hcd
*hcd
)
712 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
713 unsigned frame_number
;
716 /* Minimize latency by avoiding the spinlock */
717 frame_number
= uhci
->frame_number
;
719 delta
= (uhci_readw(uhci
, USBFRNUM
) - frame_number
) &
720 (UHCI_NUMFRAMES
- 1);
721 return frame_number
+ delta
;
724 /* Determines number of ports on controller */
725 static int uhci_count_ports(struct usb_hcd
*hcd
)
727 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
728 unsigned io_size
= (unsigned) hcd
->rsrc_len
;
731 /* The UHCI spec says devices must have 2 ports, and goes on to say
732 * they may have more but gives no way to determine how many there
733 * are. However according to the UHCI spec, Bit 7 of the port
734 * status and control register is always set to 1. So we try to
735 * use this to our advantage. Another common failure mode when
736 * a nonexistent register is addressed is to return all ones, so
737 * we test for that also.
739 for (port
= 0; port
< (io_size
- USBPORTSC1
) / 2; port
++) {
740 unsigned int portstatus
;
742 portstatus
= uhci_readw(uhci
, USBPORTSC1
+ (port
* 2));
743 if (!(portstatus
& 0x0080) || portstatus
== 0xffff)
747 dev_info(uhci_dev(uhci
), "detected %d ports\n", port
);
749 /* Anything greater than 7 is weird so we'll ignore it. */
750 if (port
> UHCI_RH_MAXCHILD
) {
751 dev_info(uhci_dev(uhci
), "port count misdetected? "
752 "forcing to 2 ports\n");
759 static const char hcd_name
[] = "uhci_hcd";
761 #include "uhci-pci.c"
763 static int __init
uhci_hcd_init(void)
765 int retval
= -ENOMEM
;
770 printk(KERN_INFO
"uhci_hcd: " DRIVER_DESC
"%s\n",
771 ignore_oc
? ", overcurrent ignored" : "");
772 set_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
);
774 if (DEBUG_CONFIGURED
) {
775 errbuf
= kmalloc(ERRBUF_LEN
, GFP_KERNEL
);
778 uhci_debugfs_root
= debugfs_create_dir("uhci", usb_debug_root
);
779 if (!uhci_debugfs_root
)
783 uhci_up_cachep
= kmem_cache_create("uhci_urb_priv",
784 sizeof(struct urb_priv
), 0, 0, NULL
);
788 retval
= pci_register_driver(&uhci_pci_driver
);
795 kmem_cache_destroy(uhci_up_cachep
);
798 debugfs_remove(uhci_debugfs_root
);
805 clear_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
);
809 static void __exit
uhci_hcd_cleanup(void)
811 pci_unregister_driver(&uhci_pci_driver
);
812 kmem_cache_destroy(uhci_up_cachep
);
813 debugfs_remove(uhci_debugfs_root
);
815 clear_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
);
818 module_init(uhci_hcd_init
);
819 module_exit(uhci_hcd_cleanup
);
821 MODULE_AUTHOR(DRIVER_AUTHOR
);
822 MODULE_DESCRIPTION(DRIVER_DESC
);
823 MODULE_LICENSE("GPL");