| blob | 945f36341fa6c1891471fb735e4d7b8b5e540d01 |
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #define TTB_S (1 << 1)
23 #define TTB_RGN_NC (0 << 3)
24 #define TTB_RGN_OC_WBWA (1 << 3)
25 #define TTB_RGN_OC_WT (2 << 3)
26 #define TTB_RGN_OC_WB (3 << 3)
27 #define TTB_NOS (1 << 5)
28 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
33 #ifndef CONFIG_SMP
34 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35 #define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
36 #define PMD_FLAGS PMD_SECT_WB
37 #else
38 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
39 #define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40 #define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
41 #endif
43 ENTRY(cpu_v7_proc_init)
44 mov pc, lr
45 ENDPROC(cpu_v7_proc_init)
47 ENTRY(cpu_v7_proc_fin)
48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 bic r0, r0, #0x1000 @ ...i............
50 bic r0, r0, #0x0006 @ .............ca.
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
52 mov pc, lr
53 ENDPROC(cpu_v7_proc_fin)
55 /*
56 * cpu_v7_reset(loc)
57 *
58 * Perform a soft reset of the system. Put the CPU into the
59 * same state as it would be if it had been reset, and branch
60 * to what would be the reset vector.
61 *
62 * - loc - location to jump to for soft reset
63 */
64 .align 5
65 ENTRY(cpu_v7_reset)
66 mov pc, r0
67 ENDPROC(cpu_v7_reset)
69 /*
70 * cpu_v7_do_idle()
71 *
72 * Idle the processor (eg, wait for interrupt).
73 *
74 * IRQs are already disabled.
75 */
76 ENTRY(cpu_v7_do_idle)
77 dsb @ WFI may enter a low-power mode
78 wfi
79 mov pc, lr
80 ENDPROC(cpu_v7_do_idle)
82 ENTRY(cpu_v7_dcache_clean_area)
83 #ifndef TLB_CAN_READ_FROM_L1_CACHE
84 dcache_line_size r2, r3
85 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
86 add r0, r0, r2
87 subs r1, r1, r2
88 bhi 1b
89 dsb
90 #endif
91 mov pc, lr
92 ENDPROC(cpu_v7_dcache_clean_area)
94 /*
95 * cpu_v7_switch_mm(pgd_phys, tsk)
96 *
97 * Set the translation table base pointer to be pgd_phys
98 *
99 * - pgd_phys - physical address of new TTB
100 *
101 * It is assumed that:
102 * - we are not using split page tables
103 */
104 ENTRY(cpu_v7_switch_mm)
105 #ifdef CONFIG_MMU
106 mov r2, #0
107 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
108 orr r0, r0, #TTB_FLAGS
109 #ifdef CONFIG_ARM_ERRATA_430973
110 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
111 #endif
112 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
113 isb
114 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
115 isb
116 mcr p15, 0, r1, c13, c0, 1 @ set context ID
117 isb
118 #endif
119 mov pc, lr
120 ENDPROC(cpu_v7_switch_mm)
122 /*
123 * cpu_v7_set_pte_ext(ptep, pte)
124 *
125 * Set a level 2 translation table entry.
126 *
127 * - ptep - pointer to level 2 translation table entry
128 * (hardware version is stored at -1024 bytes)
129 * - pte - PTE value to store
130 * - ext - value for extended PTE bits
131 */
132 ENTRY(cpu_v7_set_pte_ext)
133 #ifdef CONFIG_MMU
134 ARM( str r1, [r0], #-2048 ) @ linux version
135 THUMB( str r1, [r0] ) @ linux version
136 THUMB( sub r0, r0, #2048 )
138 bic r3, r1, #0x000003f0
139 bic r3, r3, #PTE_TYPE_MASK
140 orr r3, r3, r2
141 orr r3, r3, #PTE_EXT_AP0 | 2
143 tst r1, #1 << 4
144 orrne r3, r3, #PTE_EXT_TEX(1)
146 tst r1, #L_PTE_WRITE
147 tstne r1, #L_PTE_DIRTY
148 orreq r3, r3, #PTE_EXT_APX
150 tst r1, #L_PTE_USER
151 orrne r3, r3, #PTE_EXT_AP1
152 tstne r3, #PTE_EXT_APX
153 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
155 tst r1, #L_PTE_EXEC
156 orreq r3, r3, #PTE_EXT_XN
158 tst r1, #L_PTE_YOUNG
159 tstne r1, #L_PTE_PRESENT
160 moveq r3, #0
162 str r3, [r0]
163 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
164 #endif
165 mov pc, lr
166 ENDPROC(cpu_v7_set_pte_ext)
168 cpu_v7_name:
169 .ascii "ARMv7 Processor"
170 .align
172 __INIT
174 /*
175 * __v7_setup
176 *
177 * Initialise TLB, Caches, and MMU state ready to switch the MMU
178 * on. Return in r0 the new CP15 C1 control register setting.
179 *
180 * We automatically detect if we have a Harvard cache, and use the
181 * Harvard cache control instructions insead of the unified cache
182 * control instructions.
183 *
184 * This should be able to cover all ARMv7 cores.
185 *
186 * It is assumed that:
187 * - cache type register is implemented
188 */
189 __v7_setup:
190 #ifdef CONFIG_SMP
191 mrc p15, 0, r0, c1, c0, 1
192 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
193 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
194 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
195 #endif
196 adr r12, __v7_setup_stack @ the local stack
197 stmia r12, {r0-r5, r7, r9, r11, lr}
198 bl v7_flush_dcache_all
199 ldmia r12, {r0-r5, r7, r9, r11, lr}
201 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
202 and r10, r0, #0xff000000 @ ARM?
203 teq r10, #0x41000000
204 bne 3f
205 and r5, r0, #0x00f00000 @ variant
206 and r6, r0, #0x0000000f @ revision
207 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
208 ubfx r0, r0, #4, #12 @ primary part number
210 /* Cortex-A8 Errata */
211 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
212 teq r0, r10
213 bne 2f
214 #ifdef CONFIG_ARM_ERRATA_430973
215 teq r5, #0x00100000 @ only present in r1p*
216 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
217 orreq r10, r10, #(1 << 6) @ set IBE to 1
218 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
219 #endif
220 #ifdef CONFIG_ARM_ERRATA_458693
221 teq r6, #0x20 @ only present in r2p0
222 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
223 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
224 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
225 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
226 #endif
227 #ifdef CONFIG_ARM_ERRATA_460075
228 teq r6, #0x20 @ only present in r2p0
229 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
230 tsteq r10, #1 << 22
231 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
232 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
233 #endif
234 b 3f
236 /* Cortex-A9 Errata */
237 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
238 teq r0, r10
239 bne 3f
240 #ifdef CONFIG_ARM_ERRATA_742230
241 cmp r6, #0x22 @ only present up to r2p2
242 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
243 orrle r10, r10, #1 << 4 @ set bit #4
244 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
245 #endif
247 3: mov r10, #0
248 #ifdef HARVARD_CACHE
249 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
250 #endif
251 dsb
252 #ifdef CONFIG_MMU
253 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
254 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
255 orr r4, r4, #TTB_FLAGS
256 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
257 mov r10, #0x1f @ domains 0, 1 = manager
258 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
259 /*
260 * Memory region attributes with SCTLR.TRE=1
261 *
262 * n = TEX[0],C,B
263 * TR = PRRR[2n+1:2n] - memory type
264 * IR = NMRR[2n+1:2n] - inner cacheable property
265 * OR = NMRR[2n+17:2n+16] - outer cacheable property
266 *
267 * n TR IR OR
268 * UNCACHED 000 00
269 * BUFFERABLE 001 10 00 00
270 * WRITETHROUGH 010 10 10 10
271 * WRITEBACK 011 10 11 11
272 * reserved 110
273 * WRITEALLOC 111 10 01 01
274 * DEV_SHARED 100 01
275 * DEV_NONSHARED 100 01
276 * DEV_WC 001 10
277 * DEV_CACHED 011 10
278 *
279 * Other attributes:
280 *
281 * DS0 = PRRR[16] = 0 - device shareable property
282 * DS1 = PRRR[17] = 1 - device shareable property
283 * NS0 = PRRR[18] = 0 - normal shareable property
284 * NS1 = PRRR[19] = 1 - normal shareable property
285 * NOS = PRRR[24+n] = 1 - not outer shareable
286 */
287 ldr r5, =0xff0a81a8 @ PRRR
288 ldr r6, =0x40e040e0 @ NMRR
289 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
290 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
291 #endif
292 adr r5, v7_crval
293 ldmia r5, {r5, r6}
294 #ifdef CONFIG_CPU_ENDIAN_BE8
295 orr r6, r6, #1 << 25 @ big-endian page tables
296 #endif
297 mrc p15, 0, r0, c1, c0, 0 @ read control register
298 bic r0, r0, r5 @ clear bits them
299 orr r0, r0, r6 @ set them
300 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
301 mov pc, lr @ return to head.S:__ret
302 ENDPROC(__v7_setup)
304 /* AT
305 * TFR EV X F I D LR S
306 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
307 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
308 * 1 0 110 0011 1100 .111 1101 < we want
309 */
310 .type v7_crval, #object
311 v7_crval:
312 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
314 __v7_setup_stack:
315 .space 4 * 11 @ 11 registers
317 .type v7_processor_functions, #object
318 ENTRY(v7_processor_functions)
319 .word v7_early_abort
320 .word v7_pabort
321 .word cpu_v7_proc_init
322 .word cpu_v7_proc_fin
323 .word cpu_v7_reset
324 .word cpu_v7_do_idle
325 .word cpu_v7_dcache_clean_area
326 .word cpu_v7_switch_mm
327 .word cpu_v7_set_pte_ext
328 .size v7_processor_functions, . - v7_processor_functions
330 .type cpu_arch_name, #object
331 cpu_arch_name:
332 .asciz "armv7"
333 .size cpu_arch_name, . - cpu_arch_name
335 .type cpu_elf_name, #object
336 cpu_elf_name:
337 .asciz "v7"
338 .size cpu_elf_name, . - cpu_elf_name
339 .align
341 .section ".proc.info.init", #alloc, #execinstr
343 /*
344 * Match any ARMv7 processor core.
345 */
346 .type __v7_proc_info, #object
347 __v7_proc_info:
348 .long 0x000f0000 @ Required ID value
349 .long 0x000f0000 @ Mask for ID
350 .long PMD_TYPE_SECT | \
351 PMD_SECT_AP_WRITE | \
352 PMD_SECT_AP_READ | \
353 PMD_FLAGS
354 .long PMD_TYPE_SECT | \
355 PMD_SECT_XN | \
356 PMD_SECT_AP_WRITE | \
357 PMD_SECT_AP_READ
358 b __v7_setup
359 .long cpu_arch_name
360 .long cpu_elf_name
361 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
362 .long cpu_v7_name
363 .long v7_processor_functions
364 .long v7wbi_tlb_fns
365 .long v6_user_fns
366 .long v7_cache_fns
367 .size __v7_proc_info, . - __v7_proc_info