arch/x86/kernel/cpu/common.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3 #include <linux/sched.h>
   4 #include <linux/string.h>
   5 #include <linux/bootmem.h>
   6 #include <linux/bitops.h>
   7 #include <linux/module.h>
   8 #include <linux/kgdb.h>
   9 #include <linux/topology.h>
  10 #include <linux/delay.h>
  11 #include <linux/smp.h>
  12 #include <linux/percpu.h>
  13 #include <asm/i387.h>
  14 #include <asm/msr.h>
  15 #include <asm/io.h>
  16 #include <asm/linkage.h>
  17 #include <asm/mmu_context.h>
  18 #include <asm/mtrr.h>
  19 #include <asm/mce.h>
  20 #include <asm/pat.h>
  21 #include <asm/asm.h>
  22 #include <asm/numa.h>
  23 #include <asm/smp.h>
  24 #include <asm/cpu.h>
  25 #include <asm/cpumask.h>
  26 #ifdef CONFIG_X86_LOCAL_APIC
  27 #include <asm/mpspec.h>
  28 #include <asm/apic.h>
  29 #include <mach_apic.h>
  30 #include <asm/genapic.h>
  31 #endif
  32
  33 #include <asm/pda.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/processor.h>
  36 #include <asm/desc.h>
  37 #include <asm/atomic.h>
  38 #include <asm/proto.h>
  39 #include <asm/sections.h>
  40 #include <asm/setup.h>
  41 #include <asm/hypervisor.h>
  42
  43 #include "cpu.h"
  44
  45 #ifdef CONFIG_X86_64
  46
  47 /* all of these masks are initialized in setup_cpu_local_masks() */
  48 cpumask_var_t cpu_callin_mask;
  49 cpumask_var_t cpu_callout_mask;
  50 cpumask_var_t cpu_initialized_mask;
  51
  52 /* representing cpus for which sibling maps can be computed */
  53 cpumask_var_t cpu_sibling_setup_mask;
  54
  55 #else /* CONFIG_X86_32 */
  56
  57 cpumask_t cpu_callin_map;
  58 cpumask_t cpu_callout_map;
  59 cpumask_t cpu_initialized;
  60 cpumask_t cpu_sibling_setup_map;
  61
  62 #endif /* CONFIG_X86_32 */
  63
  64
  65 static struct cpu_dev *this_cpu __cpuinitdata;
  66
  67 #ifdef CONFIG_X86_64
  68 /* We need valid kernel segments for data and code in long mode too
  69  * IRET will check the segment types  kkeil 2000/10/28
  70  * Also sysret mandates a special GDT layout
  71  */
  72 /* The TLS descriptors are currently at a different place compared to i386.
  73    Hopefully nobody expects them at a fixed place (Wine?) */
  74 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
  75         [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
  76         [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
  77         [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
  78         [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
  79         [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
  80         [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
  81 } };
  82 #else
  83 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
  84         [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
  85         [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
  86         [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
  87         [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
  88         /*
  89          * Segments used for calling PnP BIOS have byte granularity.
  90          * They code segments and data segments have fixed 64k limits,
  91          * the transfer segment sizes are set at run time.
  92          */
  93         /* 32-bit code */
  94         [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
  95         /* 16-bit code */
  96         [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
  97         /* 16-bit data */
  98         [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
  99         /* 16-bit data */
 100         [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
 101         /* 16-bit data */
 102         [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
 103         /*
 104          * The APM segments have byte granularity and their bases
 105          * are set at run time.  All have 64k limits.
 106          */
 107         /* 32-bit code */
 108         [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
 109         /* 16-bit code */
 110         [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
 111         /* data */
 112         [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
 113
 114         [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
 115         [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
 116 } };
 117 #endif
 118 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
 119
 120 #ifdef CONFIG_X86_32
 121 static int cachesize_override __cpuinitdata = -1;
 122 static int disable_x86_serial_nr __cpuinitdata = 1;
 123
 124 static int __init cachesize_setup(char *str)
 125 {
 126         get_option(&str, &cachesize_override);
 127         return 1;
 128 }
 129 __setup("cachesize=", cachesize_setup);
 130
 131 static int __init x86_fxsr_setup(char *s)
 132 {
 133         setup_clear_cpu_cap(X86_FEATURE_FXSR);
 134         setup_clear_cpu_cap(X86_FEATURE_XMM);
 135         return 1;
 136 }
 137 __setup("nofxsr", x86_fxsr_setup);
 138
 139 static int __init x86_sep_setup(char *s)
 140 {
 141         setup_clear_cpu_cap(X86_FEATURE_SEP);
 142         return 1;
 143 }
 144 __setup("nosep", x86_sep_setup);
 145
 146 /* Standard macro to see if a specific flag is changeable */
 147 static inline int flag_is_changeable_p(u32 flag)
 148 {
 149         u32 f1, f2;
 150
 151         /*
 152          * Cyrix and IDT cpus allow disabling of CPUID
 153          * so the code below may return different results
 154          * when it is executed before and after enabling
 155          * the CPUID. Add "volatile" to not allow gcc to
 156          * optimize the subsequent calls to this function.
 157          */
 158         asm volatile ("pushfl\n\t"
 159                       "pushfl\n\t"
 160                       "popl %0\n\t"
 161                       "movl %0,%1\n\t"
 162                       "xorl %2,%0\n\t"
 163                       "pushl %0\n\t"
 164                       "popfl\n\t"
 165                       "pushfl\n\t"
 166                       "popl %0\n\t"
 167                       "popfl\n\t"
 168                       : "=&r" (f1), "=&r" (f2)
 169                       : "ir" (flag));
 170
 171         return ((f1^f2) & flag) != 0;
 172 }
 173
 174 /* Probe for the CPUID instruction */
 175 static int __cpuinit have_cpuid_p(void)
 176 {
 177         return flag_is_changeable_p(X86_EFLAGS_ID);
 178 }
 179
 180 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 181 {
 182         if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
 183                 /* Disable processor serial number */
 184                 unsigned long lo, hi;
 185                 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 186                 lo |= 0x200000;
 187                 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 188                 printk(KERN_NOTICE "CPU serial number disabled.\n");
 189                 clear_cpu_cap(c, X86_FEATURE_PN);
 190
 191                 /* Disabling the serial number may affect the cpuid level */
 192                 c->cpuid_level = cpuid_eax(0);
 193         }
 194 }
 195
 196 static int __init x86_serial_nr_setup(char *s)
 197 {
 198         disable_x86_serial_nr = 0;
 199         return 1;
 200 }
 201 __setup("serialnumber", x86_serial_nr_setup);
 202 #else
 203 static inline int flag_is_changeable_p(u32 flag)
 204 {
 205         return 1;
 206 }
 207 /* Probe for the CPUID instruction */
 208 static inline int have_cpuid_p(void)
 209 {
 210         return 1;
 211 }
 212 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 213 {
 214 }
 215 #endif
 216
 217 /*
 218  * Naming convention should be: <Name> [(<Codename>)]
 219  * This table only is used unless init_<vendor>() below doesn't set it;
 220  * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
 221  *
 222  */
 223
 224 /* Look up CPU names by table lookup. */
 225 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
 226 {
 227         struct cpu_model_info *info;
 228
 229         if (c->x86_model >= 16)
 230                 return NULL;    /* Range check */
 231
 232         if (!this_cpu)
 233                 return NULL;
 234
 235         info = this_cpu->c_models;
 236
 237         while (info && info->family) {
 238                 if (info->family == c->x86)
 239                         return info->model_names[c->x86_model];
 240                 info++;
 241         }
 242         return NULL;            /* Not found */
 243 }
 244
 245 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
 246
 247 /* Current gdt points %fs at the "master" per-cpu area: after this,
 248  * it's on the real one. */
 249 void switch_to_new_gdt(void)
 250 {
 251         struct desc_ptr gdt_descr;
 252
 253         gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
 254         gdt_descr.size = GDT_SIZE - 1;
 255         load_gdt(&gdt_descr);
 256 #ifdef CONFIG_X86_32
 257         asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
 258 #endif
 259 }
 260
 261 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
 262
 263 static void __cpuinit default_init(struct cpuinfo_x86 *c)
 264 {
 265 #ifdef CONFIG_X86_64
 266         display_cacheinfo(c);
 267 #else
 268         /* Not much we can do here... */
 269         /* Check if at least it has cpuid */
 270         if (c->cpuid_level == -1) {
 271                 /* No cpuid. It must be an ancient CPU */
 272                 if (c->x86 == 4)
 273                         strcpy(c->x86_model_id, "486");
 274                 else if (c->x86 == 3)
 275                         strcpy(c->x86_model_id, "386");
 276         }
 277 #endif
 278 }
 279
 280 static struct cpu_dev __cpuinitdata default_cpu = {
 281         .c_init = default_init,
 282         .c_vendor = "Unknown",
 283         .c_x86_vendor = X86_VENDOR_UNKNOWN,
 284 };
 285
 286 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
 287 {
 288         unsigned int *v;
 289         char *p, *q;
 290
 291         if (c->extended_cpuid_level < 0x80000004)
 292                 return;
 293
 294         v = (unsigned int *) c->x86_model_id;
 295         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 296         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 297         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 298         c->x86_model_id[48] = 0;
 299
 300         /* Intel chips right-justify this string for some dumb reason;
 301            undo that brain damage */
 302         p = q = &c->x86_model_id[0];
 303         while (*p == ' ')
 304              p++;
 305         if (p != q) {
 306              while (*p)
 307                   *q++ = *p++;
 308              while (q <= &c->x86_model_id[48])
 309                   *q++ = '\0';  /* Zero-pad the rest */
 310         }
 311 }
 312
 313 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 314 {
 315         unsigned int n, dummy, ebx, ecx, edx, l2size;
 316
 317         n = c->extended_cpuid_level;
 318
 319         if (n >= 0x80000005) {
 320                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 321                 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
 322                                 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
 323                 c->x86_cache_size = (ecx>>24) + (edx>>24);
 324 #ifdef CONFIG_X86_64
 325                 /* On K8 L1 TLB is inclusive, so don't count it */
 326                 c->x86_tlbsize = 0;
 327 #endif
 328         }
 329
 330         if (n < 0x80000006)     /* Some chips just has a large L1. */
 331                 return;
 332
 333         cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 334         l2size = ecx >> 16;
 335
 336 #ifdef CONFIG_X86_64
 337         c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 338 #else
 339         /* do processor-specific cache resizing */
 340         if (this_cpu->c_size_cache)
 341                 l2size = this_cpu->c_size_cache(c, l2size);
 342
 343         /* Allow user to override all this if necessary. */
 344         if (cachesize_override != -1)
 345                 l2size = cachesize_override;
 346
 347         if (l2size == 0)
 348                 return;         /* Again, no L2 cache is possible */
 349 #endif
 350
 351         c->x86_cache_size = l2size;
 352
 353         printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 354                         l2size, ecx & 0xFF);
 355 }
 356
 357 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 358 {
 359 #ifdef CONFIG_X86_HT
 360         u32 eax, ebx, ecx, edx;
 361         int index_msb, core_bits;
 362
 363         if (!cpu_has(c, X86_FEATURE_HT))
 364                 return;
 365
 366         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
 367                 goto out;
 368
 369         if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
 370                 return;
 371
 372         cpuid(1, &eax, &ebx, &ecx, &edx);
 373
 374         smp_num_siblings = (ebx & 0xff0000) >> 16;
 375
 376         if (smp_num_siblings == 1) {
 377                 printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
 378         } else if (smp_num_siblings > 1) {
 379
 380                 if (smp_num_siblings > nr_cpu_ids) {
 381                         printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
 382                                         smp_num_siblings);
 383                         smp_num_siblings = 1;
 384                         return;
 385                 }
 386
 387                 index_msb = get_count_order(smp_num_siblings);
 388 #ifdef CONFIG_X86_64
 389                 c->phys_proc_id = phys_pkg_id(index_msb);
 390 #else
 391                 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
 392 #endif
 393
 394                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 395
 396                 index_msb = get_count_order(smp_num_siblings);
 397
 398                 core_bits = get_count_order(c->x86_max_cores);
 399
 400 #ifdef CONFIG_X86_64
 401                 c->cpu_core_id = phys_pkg_id(index_msb) &
 402                                                ((1 << core_bits) - 1);
 403 #else
 404                 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
 405                                                ((1 << core_bits) - 1);
 406 #endif
 407         }
 408
 409 out:
 410         if ((c->x86_max_cores * smp_num_siblings) > 1) {
 411                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
 412                        c->phys_proc_id);
 413                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
 414                        c->cpu_core_id);
 415         }
 416 #endif
 417 }
 418
 419 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 420 {
 421         char *v = c->x86_vendor_id;
 422         int i;
 423         static int printed;
 424
 425         for (i = 0; i < X86_VENDOR_NUM; i++) {
 426                 if (!cpu_devs[i])
 427                         break;
 428
 429                 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
 430                     (cpu_devs[i]->c_ident[1] &&
 431                      !strcmp(v, cpu_devs[i]->c_ident[1]))) {
 432                         this_cpu = cpu_devs[i];
 433                         c->x86_vendor = this_cpu->c_x86_vendor;
 434                         return;
 435                 }
 436         }
 437
 438         if (!printed) {
 439                 printed++;
 440                 printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v);
 441                 printk(KERN_ERR "CPU: Your system may be unstable.\n");
 442         }
 443
 444         c->x86_vendor = X86_VENDOR_UNKNOWN;
 445         this_cpu = &default_cpu;
 446 }
 447
 448 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
 449 {
 450         /* Get vendor name */
 451         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
 452               (unsigned int *)&c->x86_vendor_id[0],
 453               (unsigned int *)&c->x86_vendor_id[8],
 454               (unsigned int *)&c->x86_vendor_id[4]);
 455
 456         c->x86 = 4;
 457         /* Intel-defined flags: level 0x00000001 */
 458         if (c->cpuid_level >= 0x00000001) {
 459                 u32 junk, tfms, cap0, misc;
 460                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
 461                 c->x86 = (tfms >> 8) & 0xf;
 462                 c->x86_model = (tfms >> 4) & 0xf;
 463                 c->x86_mask = tfms & 0xf;
 464                 if (c->x86 == 0xf)
 465                         c->x86 += (tfms >> 20) & 0xff;
 466                 if (c->x86 >= 0x6)
 467                         c->x86_model += ((tfms >> 16) & 0xf) << 4;
 468                 if (cap0 & (1<<19)) {
 469                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
 470                         c->x86_cache_alignment = c->x86_clflush_size;
 471                 }
 472         }
 473 }
 474
 475 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 476 {
 477         u32 tfms, xlvl;
 478         u32 ebx;
 479
 480         /* Intel-defined flags: level 0x00000001 */
 481         if (c->cpuid_level >= 0x00000001) {
 482                 u32 capability, excap;
 483                 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
 484                 c->x86_capability[0] = capability;
 485                 c->x86_capability[4] = excap;
 486         }
 487
 488         /* AMD-defined flags: level 0x80000001 */
 489         xlvl = cpuid_eax(0x80000000);
 490         c->extended_cpuid_level = xlvl;
 491         if ((xlvl & 0xffff0000) == 0x80000000) {
 492                 if (xlvl >= 0x80000001) {
 493                         c->x86_capability[1] = cpuid_edx(0x80000001);
 494                         c->x86_capability[6] = cpuid_ecx(0x80000001);
 495                 }
 496         }
 497
 498 #ifdef CONFIG_X86_64
 499         if (c->extended_cpuid_level >= 0x80000008) {
 500                 u32 eax = cpuid_eax(0x80000008);
 501
 502                 c->x86_virt_bits = (eax >> 8) & 0xff;
 503                 c->x86_phys_bits = eax & 0xff;
 504         }
 505 #endif
 506
 507         if (c->extended_cpuid_level >= 0x80000007)
 508                 c->x86_power = cpuid_edx(0x80000007);
 509
 510 }
 511
 512 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
 513 {
 514 #ifdef CONFIG_X86_32
 515         int i;
 516
 517         /*
 518          * First of all, decide if this is a 486 or higher
 519          * It's a 486 if we can modify the AC flag
 520          */
 521         if (flag_is_changeable_p(X86_EFLAGS_AC))
 522                 c->x86 = 4;
 523         else
 524                 c->x86 = 3;
 525
 526         for (i = 0; i < X86_VENDOR_NUM; i++)
 527                 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
 528                         c->x86_vendor_id[0] = 0;
 529                         cpu_devs[i]->c_identify(c);
 530                         if (c->x86_vendor_id[0]) {
 531                                 get_cpu_vendor(c);
 532                                 break;
 533                         }
 534                 }
 535 #endif
 536 }
 537
 538 /*
 539  * Do minimum CPU detection early.
 540  * Fields really needed: vendor, cpuid_level, family, model, mask,
 541  * cache alignment.
 542  * The others are not touched to avoid unwanted side effects.
 543  *
 544  * WARNING: this function is only called on the BP.  Don't add code here
 545  * that is supposed to run on all CPUs.
 546  */
 547 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 548 {
 549 #ifdef CONFIG_X86_64
 550         c->x86_clflush_size = 64;
 551 #else
 552         c->x86_clflush_size = 32;
 553 #endif
 554         c->x86_cache_alignment = c->x86_clflush_size;
 555
 556         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 557         c->extended_cpuid_level = 0;
 558
 559         if (!have_cpuid_p())
 560                 identify_cpu_without_cpuid(c);
 561
 562         /* cyrix could have cpuid enabled via c_identify()*/
 563         if (!have_cpuid_p())
 564                 return;
 565
 566         cpu_detect(c);
 567
 568         get_cpu_vendor(c);
 569
 570         get_cpu_cap(c);
 571
 572         if (this_cpu->c_early_init)
 573                 this_cpu->c_early_init(c);
 574
 575         validate_pat_support(c);
 576
 577 #ifdef CONFIG_SMP
 578         c->cpu_index = boot_cpu_id;
 579 #endif
 580 }
 581
 582 void __init early_cpu_init(void)
 583 {
 584         struct cpu_dev **cdev;
 585         int count = 0;
 586
 587         printk("KERNEL supported cpus:\n");
 588         for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
 589                 struct cpu_dev *cpudev = *cdev;
 590                 unsigned int j;
 591
 592                 if (count >= X86_VENDOR_NUM)
 593                         break;
 594                 cpu_devs[count] = cpudev;
 595                 count++;
 596
 597                 for (j = 0; j < 2; j++) {
 598                         if (!cpudev->c_ident[j])
 599                                 continue;
 600                         printk("  %s %s\n", cpudev->c_vendor,
 601                                 cpudev->c_ident[j]);
 602                 }
 603         }
 604
 605         early_identify_cpu(&boot_cpu_data);
 606 }
 607
 608 /*
 609  * The NOPL instruction is supposed to exist on all CPUs with
 610  * family >= 6; unfortunately, that's not true in practice because
 611  * of early VIA chips and (more importantly) broken virtualizers that
 612  * are not easy to detect.  In the latter case it doesn't even *fail*
 613  * reliably, so probing for it doesn't even work.  Disable it completely
 614  * unless we can find a reliable way to detect all the broken cases.
 615  */
 616 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
 617 {
 618         clear_cpu_cap(c, X86_FEATURE_NOPL);
 619 }
 620
 621 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
 622 {
 623         c->extended_cpuid_level = 0;
 624
 625         if (!have_cpuid_p())
 626                 identify_cpu_without_cpuid(c);
 627
 628         /* cyrix could have cpuid enabled via c_identify()*/
 629         if (!have_cpuid_p())
 630                 return;
 631
 632         cpu_detect(c);
 633
 634         get_cpu_vendor(c);
 635
 636         get_cpu_cap(c);
 637
 638         if (c->cpuid_level >= 0x00000001) {
 639                 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
 640 #ifdef CONFIG_X86_32
 641 # ifdef CONFIG_X86_HT
 642                 c->apicid = phys_pkg_id(c->initial_apicid, 0);
 643 # else
 644                 c->apicid = c->initial_apicid;
 645 # endif
 646 #endif
 647
 648 #ifdef CONFIG_X86_HT
 649                 c->phys_proc_id = c->initial_apicid;
 650 #endif
 651         }
 652
 653         get_model_name(c); /* Default name */
 654
 655         init_scattered_cpuid_features(c);
 656         detect_nopl(c);
 657 }
 658
 659 /*
 660  * This does the hard work of actually picking apart the CPU stuff...
 661  */
 662 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
 663 {
 664         int i;
 665
 666         c->loops_per_jiffy = loops_per_jiffy;
 667         c->x86_cache_size = -1;
 668         c->x86_vendor = X86_VENDOR_UNKNOWN;
 669         c->x86_model = c->x86_mask = 0; /* So far unknown... */
 670         c->x86_vendor_id[0] = '\0'; /* Unset */
 671         c->x86_model_id[0] = '\0';  /* Unset */
 672         c->x86_max_cores = 1;
 673         c->x86_coreid_bits = 0;
 674 #ifdef CONFIG_X86_64
 675         c->x86_clflush_size = 64;
 676 #else
 677         c->cpuid_level = -1;    /* CPUID not detected */
 678         c->x86_clflush_size = 32;
 679 #endif
 680         c->x86_cache_alignment = c->x86_clflush_size;
 681         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 682
 683         generic_identify(c);
 684
 685         if (this_cpu->c_identify)
 686                 this_cpu->c_identify(c);
 687
 688 #ifdef CONFIG_X86_64
 689         c->apicid = phys_pkg_id(0);
 690 #endif
 691
 692         /*
 693          * Vendor-specific initialization.  In this section we
 694          * canonicalize the feature flags, meaning if there are
 695          * features a certain CPU supports which CPUID doesn't
 696          * tell us, CPUID claiming incorrect flags, or other bugs,
 697          * we handle them here.
 698          *
 699          * At the end of this section, c->x86_capability better
 700          * indicate the features this CPU genuinely supports!
 701          */
 702         if (this_cpu->c_init)
 703                 this_cpu->c_init(c);
 704
 705         /* Disable the PN if appropriate */
 706         squash_the_stupid_serial_number(c);
 707
 708         /*
 709          * The vendor-specific functions might have changed features.  Now
 710          * we do "generic changes."
 711          */
 712
 713         /* If the model name is still unset, do table lookup. */
 714         if (!c->x86_model_id[0]) {
 715                 char *p;
 716                 p = table_lookup_model(c);
 717                 if (p)
 718                         strcpy(c->x86_model_id, p);
 719                 else
 720                         /* Last resort... */
 721                         sprintf(c->x86_model_id, "%02x/%02x",
 722                                 c->x86, c->x86_model);
 723         }
 724
 725 #ifdef CONFIG_X86_64
 726         detect_ht(c);
 727 #endif
 728
 729         init_hypervisor(c);
 730         /*
 731          * On SMP, boot_cpu_data holds the common feature set between
 732          * all CPUs; so make sure that we indicate which features are
 733          * common between the CPUs.  The first time this routine gets
 734          * executed, c == &boot_cpu_data.
 735          */
 736         if (c != &boot_cpu_data) {
 737                 /* AND the already accumulated flags with these */
 738                 for (i = 0; i < NCAPINTS; i++)
 739                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
 740         }
 741
 742         /* Clear all flags overriden by options */
 743         for (i = 0; i < NCAPINTS; i++)
 744                 c->x86_capability[i] &= ~cleared_cpu_caps[i];
 745
 746 #ifdef CONFIG_X86_MCE
 747         /* Init Machine Check Exception if available. */
 748         mcheck_init(c);
 749 #endif
 750
 751         select_idle_routine(c);
 752
 753 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 754         numa_add_cpu(smp_processor_id());
 755 #endif
 756 }
 757
 758 #ifdef CONFIG_X86_64
 759 static void vgetcpu_set_mode(void)
 760 {
 761         if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
 762                 vgetcpu_mode = VGETCPU_RDTSCP;
 763         else
 764                 vgetcpu_mode = VGETCPU_LSL;
 765 }
 766 #endif
 767
 768 void __init identify_boot_cpu(void)
 769 {
 770         identify_cpu(&boot_cpu_data);
 771 #ifdef CONFIG_X86_32
 772         sysenter_setup();
 773         enable_sep_cpu();
 774 #else
 775         vgetcpu_set_mode();
 776 #endif
 777 }
 778
 779 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
 780 {
 781         BUG_ON(c == &boot_cpu_data);
 782         identify_cpu(c);
 783 #ifdef CONFIG_X86_32
 784         enable_sep_cpu();
 785 #endif
 786         mtrr_ap_init();
 787 }
 788
 789 struct msr_range {
 790         unsigned min;
 791         unsigned max;
 792 };
 793
 794 static struct msr_range msr_range_array[] __cpuinitdata = {
 795         { 0x00000000, 0x00000418},
 796         { 0xc0000000, 0xc000040b},
 797         { 0xc0010000, 0xc0010142},
 798         { 0xc0011000, 0xc001103b},
 799 };
 800
 801 static void __cpuinit print_cpu_msr(void)
 802 {
 803         unsigned index;
 804         u64 val;
 805         int i;
 806         unsigned index_min, index_max;
 807
 808         for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
 809                 index_min = msr_range_array[i].min;
 810                 index_max = msr_range_array[i].max;
 811                 for (index = index_min; index < index_max; index++) {
 812                         if (rdmsrl_amd_safe(index, &val))
 813                                 continue;
 814                         printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
 815                 }
 816         }
 817 }
 818
 819 static int show_msr __cpuinitdata;
 820 static __init int setup_show_msr(char *arg)
 821 {
 822         int num;
 823
 824         get_option(&arg, &num);
 825
 826         if (num > 0)
 827                 show_msr = num;
 828         return 1;
 829 }
 830 __setup("show_msr=", setup_show_msr);
 831
 832 static __init int setup_noclflush(char *arg)
 833 {
 834         setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
 835         return 1;
 836 }
 837 __setup("noclflush", setup_noclflush);
 838
 839 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
 840 {
 841         char *vendor = NULL;
 842
 843         if (c->x86_vendor < X86_VENDOR_NUM)
 844                 vendor = this_cpu->c_vendor;
 845         else if (c->cpuid_level >= 0)
 846                 vendor = c->x86_vendor_id;
 847
 848         if (vendor && !strstr(c->x86_model_id, vendor))
 849                 printk(KERN_CONT "%s ", vendor);
 850
 851         if (c->x86_model_id[0])
 852                 printk(KERN_CONT "%s", c->x86_model_id);
 853         else
 854                 printk(KERN_CONT "%d86", c->x86);
 855
 856         if (c->x86_mask || c->cpuid_level >= 0)
 857                 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
 858         else
 859                 printk(KERN_CONT "\n");
 860
 861 #ifdef CONFIG_SMP
 862         if (c->cpu_index < show_msr)
 863                 print_cpu_msr();
 864 #else
 865         if (show_msr)
 866                 print_cpu_msr();
 867 #endif
 868 }
 869
 870 static __init int setup_disablecpuid(char *arg)
 871 {
 872         int bit;
 873         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
 874                 setup_clear_cpu_cap(bit);
 875         else
 876                 return 0;
 877         return 1;
 878 }
 879 __setup("clearcpuid=", setup_disablecpuid);
 880
 881 #ifdef CONFIG_X86_64
 882 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
 883
 884 static char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
 885
 886 void __cpuinit pda_init(int cpu)
 887 {
 888         struct x8664_pda *pda = cpu_pda(cpu);
 889
 890         /* Setup up data that may be needed in __get_free_pages early */
 891         loadsegment(fs, 0);
 892         loadsegment(gs, 0);
 893
 894         load_pda_offset(cpu);
 895
 896         pda->cpunumber = cpu;
 897         pda->irqcount = -1;
 898         pda->kernelstack = (unsigned long)stack_thread_info() -
 899                                  PDA_STACKOFFSET + THREAD_SIZE;
 900
 901         if (cpu == 0) {
 902                 /* others are initialized in smpboot.c */
 903                 pda->pcurrent = &init_task;
 904                 pda->irqstackptr = boot_cpu_stack;
 905                 pda->irqstackptr += IRQSTACKSIZE - 64;
 906         } else {
 907                 if (!pda->irqstackptr) {
 908                         pda->irqstackptr = (char *)
 909                                 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
 910                         if (!pda->irqstackptr)
 911                                 panic("cannot allocate irqstack for cpu %d",
 912                                       cpu);
 913                         pda->irqstackptr += IRQSTACKSIZE - 64;
 914                 }
 915
 916                 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
 917                         pda->nodenumber = cpu_to_node(cpu);
 918         }
 919 }
 920
 921 static char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
 922                                   DEBUG_STKSZ] __page_aligned_bss;
 923
 924 extern asmlinkage void ignore_sysret(void);
 925
 926 /* May not be marked __init: used by software suspend */
 927 void syscall_init(void)
 928 {
 929         /*
 930          * LSTAR and STAR live in a bit strange symbiosis.
 931          * They both write to the same internal register. STAR allows to
 932          * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
 933          */
 934         wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
 935         wrmsrl(MSR_LSTAR, system_call);
 936         wrmsrl(MSR_CSTAR, ignore_sysret);
 937
 938 #ifdef CONFIG_IA32_EMULATION
 939         syscall32_cpu_init();
 940 #endif
 941
 942         /* Flags to clear on syscall */
 943         wrmsrl(MSR_SYSCALL_MASK,
 944                X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
 945 }
 946
 947 unsigned long kernel_eflags;
 948
 949 /*
 950  * Copies of the original ist values from the tss are only accessed during
 951  * debugging, no special alignment required.
 952  */
 953 DEFINE_PER_CPU(struct orig_ist, orig_ist);
 954
 955 #else
 956
 957 /* Make sure %fs is initialized properly in idle threads */
 958 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
 959 {
 960         memset(regs, 0, sizeof(struct pt_regs));
 961         regs->fs = __KERNEL_PERCPU;
 962         return regs;
 963 }
 964 #endif
 965
 966 /*
 967  * cpu_init() initializes state that is per-CPU. Some data is already
 968  * initialized (naturally) in the bootstrap process, such as the GDT
 969  * and IDT. We reload them nevertheless, this function acts as a
 970  * 'CPU state barrier', nothing should get across.
 971  * A lot of state is already set up in PDA init for 64 bit
 972  */
 973 #ifdef CONFIG_X86_64
 974 void __cpuinit cpu_init(void)
 975 {
 976         int cpu = stack_smp_processor_id();
 977         struct tss_struct *t = &per_cpu(init_tss, cpu);
 978         struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
 979         unsigned long v;
 980         char *estacks = NULL;
 981         struct task_struct *me;
 982         int i;
 983
 984         /* CPU 0 is initialised in head64.c */
 985         if (cpu != 0)
 986                 pda_init(cpu);
 987         else
 988                 estacks = boot_exception_stacks;
 989
 990         me = current;
 991
 992         if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
 993                 panic("CPU#%d already initialized!\n", cpu);
 994
 995         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
 996
 997         clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
 998
 999         /*
1000          * Initialize the per-CPU GDT with the boot GDT,
1001          * and set up the GDT descriptor:
1002          */
1003
1004         switch_to_new_gdt();
1005         load_idt((const struct desc_ptr *)&idt_descr);
1006
1007         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1008         syscall_init();
1009
1010         wrmsrl(MSR_FS_BASE, 0);
1011         wrmsrl(MSR_KERNEL_GS_BASE, 0);
1012         barrier();
1013
1014         check_efer();
1015         if (cpu != 0 && x2apic)
1016                 enable_x2apic();
1017
1018         /*
1019          * set up and load the per-CPU TSS
1020          */
1021         if (!orig_ist->ist[0]) {
1022                 static const unsigned int order[N_EXCEPTION_STACKS] = {
1023                   [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
1024                   [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
1025                 };
1026                 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1027                         if (cpu) {
1028                                 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
1029                                 if (!estacks)
1030                                         panic("Cannot allocate exception "
1031                                               "stack %ld %d\n", v, cpu);
1032                         }
1033                         estacks += PAGE_SIZE << order[v];
1034                         orig_ist->ist[v] = t->x86_tss.ist[v] =
1035                                         (unsigned long)estacks;
1036                 }
1037         }
1038
1039         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1040         /*
1041          * <= is required because the CPU will access up to
1042          * 8 bits beyond the end of the IO permission bitmap.
1043          */
1044         for (i = 0; i <= IO_BITMAP_LONGS; i++)
1045                 t->io_bitmap[i] = ~0UL;
1046
1047         atomic_inc(&init_mm.mm_count);
1048         me->active_mm = &init_mm;
1049         if (me->mm)
1050                 BUG();
1051         enter_lazy_tlb(&init_mm, me);
1052
1053         load_sp0(t, &current->thread);
1054         set_tss_desc(cpu, t);
1055         load_TR_desc();
1056         load_LDT(&init_mm.context);
1057
1058 #ifdef CONFIG_KGDB
1059         /*
1060          * If the kgdb is connected no debug regs should be altered.  This
1061          * is only applicable when KGDB and a KGDB I/O module are built
1062          * into the kernel and you are using early debugging with
1063          * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1064          */
1065         if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1066                 arch_kgdb_ops.correct_hw_break();
1067         else {
1068 #endif
1069         /*
1070          * Clear all 6 debug registers:
1071          */
1072
1073         set_debugreg(0UL, 0);
1074         set_debugreg(0UL, 1);
1075         set_debugreg(0UL, 2);
1076         set_debugreg(0UL, 3);
1077         set_debugreg(0UL, 6);
1078         set_debugreg(0UL, 7);
1079 #ifdef CONFIG_KGDB
1080         /* If the kgdb is connected no debug regs should be altered. */
1081         }
1082 #endif
1083
1084         fpu_init();
1085
1086         raw_local_save_flags(kernel_eflags);
1087
1088         if (is_uv_system())
1089                 uv_cpu_init();
1090 }
1091
1092 #else
1093
1094 void __cpuinit cpu_init(void)
1095 {
1096         int cpu = smp_processor_id();
1097         struct task_struct *curr = current;
1098         struct tss_struct *t = &per_cpu(init_tss, cpu);
1099         struct thread_struct *thread = &curr->thread;
1100
1101         if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1102                 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1103                 for (;;) local_irq_enable();
1104         }
1105
1106         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1107
1108         if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1109                 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1110
1111         load_idt(&idt_descr);
1112         switch_to_new_gdt();
1113
1114         /*
1115          * Set up and load the per-CPU TSS and LDT
1116          */
1117         atomic_inc(&init_mm.mm_count);
1118         curr->active_mm = &init_mm;
1119         if (curr->mm)
1120                 BUG();
1121         enter_lazy_tlb(&init_mm, curr);
1122
1123         load_sp0(t, thread);
1124         set_tss_desc(cpu, t);
1125         load_TR_desc();
1126         load_LDT(&init_mm.context);
1127
1128 #ifdef CONFIG_DOUBLEFAULT
1129         /* Set up doublefault TSS pointer in the GDT */
1130         __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1131 #endif
1132
1133         /* Clear %gs. */
1134         asm volatile ("mov %0, %%gs" : : "r" (0));
1135
1136         /* Clear all 6 debug registers: */
1137         set_debugreg(0, 0);
1138         set_debugreg(0, 1);
1139         set_debugreg(0, 2);
1140         set_debugreg(0, 3);
1141         set_debugreg(0, 6);
1142         set_debugreg(0, 7);
1143
1144         /*
1145          * Force FPU initialization:
1146          */
1147         if (cpu_has_xsave)
1148                 current_thread_info()->status = TS_XSAVE;
1149         else
1150                 current_thread_info()->status = 0;
1151         clear_used_math();
1152         mxcsr_feature_mask_init();
1153
1154         /*
1155          * Boot processor to setup the FP and extended state context info.
1156          */
1157         if (smp_processor_id() == boot_cpu_id)
1158                 init_thread_xstate();
1159
1160         xsave_init();
1161 }
1162
1163
1164 #endif