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agp/intel: Use macro to set the count of the size array
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / agp / intel-gtt.c
blobdedf05dc433dbcdae0e729665c4c89caffd736d8
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <asm/smp.h>
25 #include "agp.h"
26 #include "intel-agp.h"
27 #include <linux/intel-gtt.h>
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_DMAR
37 #define USE_PCI_DMA_API 1
38 #endif
39
40 /* Max amount of stolen space, anything above will be returned to Linux */
41 int intel_max_stolen = 32 * 1024 * 1024;
42 EXPORT_SYMBOL(intel_max_stolen);
43
44 static const struct aper_size_info_fixed intel_i810_sizes[] =
45 {
46 {64, 16384, 4},
47 /* The 32M mode still requires a 64k gatt */
48 {32, 8192, 4}
49 };
50
51 #define AGP_DCACHE_MEMORY 1
52 #define AGP_PHYS_MEMORY 2
53 #define INTEL_AGP_CACHED_MEMORY 3
54
55 static struct gatt_mask intel_i810_masks[] =
56 {
57 {.mask = I810_PTE_VALID, .type = 0},
58 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
59 {.mask = I810_PTE_VALID, .type = 0},
60 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
61 .type = INTEL_AGP_CACHED_MEMORY}
62 };
63
64 #define INTEL_AGP_UNCACHED_MEMORY 0
65 #define INTEL_AGP_CACHED_MEMORY_LLC 1
66 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
67 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
69
70 static struct gatt_mask intel_gen6_masks[] =
71 {
72 {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
73 .type = INTEL_AGP_UNCACHED_MEMORY },
74 {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
75 .type = INTEL_AGP_CACHED_MEMORY_LLC },
76 {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
77 .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
78 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
79 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
80 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
81 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
82 };
83
84 struct intel_gtt_driver {
85 unsigned int gen : 8;
86 unsigned int is_g33 : 1;
87 unsigned int is_pineview : 1;
88 unsigned int is_ironlake : 1;
89 /* Chipset specific GTT setup */
90 int (*setup)(void);
91 };
92
93 static struct _intel_private {
94 struct intel_gtt base;
95 const struct intel_gtt_driver *driver;
96 struct pci_dev *pcidev; /* device one */
97 struct pci_dev *bridge_dev;
98 u8 __iomem *registers;
99 phys_addr_t gtt_bus_addr;
100 phys_addr_t gma_bus_addr;
101 u32 __iomem *gtt; /* I915G */
102 int num_dcache_entries;
103 union {
104 void __iomem *i9xx_flush_page;
105 void *i8xx_flush_page;
106 };
107 struct page *i8xx_page;
108 struct resource ifp_resource;
109 int resource_valid;
110 } intel_private;
111
112 #define INTEL_GTT_GEN intel_private.driver->gen
113 #define IS_G33 intel_private.driver->is_g33
114 #define IS_PINEVIEW intel_private.driver->is_pineview
115 #define IS_IRONLAKE intel_private.driver->is_ironlake
116
117 #ifdef USE_PCI_DMA_API
118 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
119 {
120 *ret = pci_map_page(intel_private.pcidev, page, 0,
121 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
122 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
123 return -EINVAL;
124 return 0;
125 }
126
127 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
128 {
129 pci_unmap_page(intel_private.pcidev, dma,
130 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
131 }
132
133 static void intel_agp_free_sglist(struct agp_memory *mem)
134 {
135 struct sg_table st;
136
137 st.sgl = mem->sg_list;
138 st.orig_nents = st.nents = mem->page_count;
139
140 sg_free_table(&st);
141
142 mem->sg_list = NULL;
143 mem->num_sg = 0;
144 }
145
146 static int intel_agp_map_memory(struct agp_memory *mem)
147 {
148 struct sg_table st;
149 struct scatterlist *sg;
150 int i;
151
152 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
153
154 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
155 goto err;
156
157 mem->sg_list = sg = st.sgl;
158
159 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
160 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
161
162 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
163 mem->page_count, PCI_DMA_BIDIRECTIONAL);
164 if (unlikely(!mem->num_sg))
165 goto err;
166
167 return 0;
168
169 err:
170 sg_free_table(&st);
171 return -ENOMEM;
172 }
173
174 static void intel_agp_unmap_memory(struct agp_memory *mem)
175 {
176 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
177
178 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
179 mem->page_count, PCI_DMA_BIDIRECTIONAL);
180 intel_agp_free_sglist(mem);
181 }
182
183 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
184 off_t pg_start, int mask_type)
185 {
186 struct scatterlist *sg;
187 int i, j;
188
189 j = pg_start;
190
191 WARN_ON(!mem->num_sg);
192
193 if (mem->num_sg == mem->page_count) {
194 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
195 writel(agp_bridge->driver->mask_memory(agp_bridge,
196 sg_dma_address(sg), mask_type),
197 intel_private.gtt+j);
198 j++;
199 }
200 } else {
201 /* sg may merge pages, but we have to separate
202 * per-page addr for GTT */
203 unsigned int len, m;
204
205 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
206 len = sg_dma_len(sg) / PAGE_SIZE;
207 for (m = 0; m < len; m++) {
208 writel(agp_bridge->driver->mask_memory(agp_bridge,
209 sg_dma_address(sg) + m * PAGE_SIZE,
210 mask_type),
211 intel_private.gtt+j);
212 j++;
213 }
214 }
215 }
216 readl(intel_private.gtt+j-1);
217 }
218
219 #else
220
221 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
222 off_t pg_start, int mask_type)
223 {
224 int i, j;
225
226 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
227 writel(agp_bridge->driver->mask_memory(agp_bridge,
228 page_to_phys(mem->pages[i]), mask_type),
229 intel_private.gtt+j);
230 }
231
232 readl(intel_private.gtt+j-1);
233 }
234
235 #endif
236
237 static int intel_i810_fetch_size(void)
238 {
239 u32 smram_miscc;
240 struct aper_size_info_fixed *values;
241
242 pci_read_config_dword(intel_private.bridge_dev,
243 I810_SMRAM_MISCC, &smram_miscc);
244 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
245
246 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
247 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
248 return 0;
249 }
250 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
251 agp_bridge->current_size = (void *) (values + 1);
252 agp_bridge->aperture_size_idx = 1;
253 return values[1].size;
254 } else {
255 agp_bridge->current_size = (void *) (values);
256 agp_bridge->aperture_size_idx = 0;
257 return values[0].size;
258 }
259
260 return 0;
261 }
262
263 static int intel_i810_configure(void)
264 {
265 struct aper_size_info_fixed *current_size;
266 u32 temp;
267 int i;
268
269 current_size = A_SIZE_FIX(agp_bridge->current_size);
270
271 if (!intel_private.registers) {
272 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
273 temp &= 0xfff80000;
274
275 intel_private.registers = ioremap(temp, 128 * 4096);
276 if (!intel_private.registers) {
277 dev_err(&intel_private.pcidev->dev,
278 "can't remap memory\n");
279 return -ENOMEM;
280 }
281 }
282
283 if ((readl(intel_private.registers+I810_DRAM_CTL)
284 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
285 /* This will need to be dynamically assigned */
286 dev_info(&intel_private.pcidev->dev,
287 "detected 4MB dedicated video ram\n");
288 intel_private.num_dcache_entries = 1024;
289 }
290 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
291 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
292 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
293 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
294
295 if (agp_bridge->driver->needs_scratch_page) {
296 for (i = 0; i < current_size->num_entries; i++) {
297 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
298 }
299 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
300 }
301 global_cache_flush();
302 return 0;
303 }
304
305 static void intel_i810_cleanup(void)
306 {
307 writel(0, intel_private.registers+I810_PGETBL_CTL);
308 readl(intel_private.registers); /* PCI Posting. */
309 iounmap(intel_private.registers);
310 }
311
312 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
313 {
314 return;
315 }
316
317 /* Exists to support ARGB cursors */
318 static struct page *i8xx_alloc_pages(void)
319 {
320 struct page *page;
321
322 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
323 if (page == NULL)
324 return NULL;
325
326 if (set_pages_uc(page, 4) < 0) {
327 set_pages_wb(page, 4);
328 __free_pages(page, 2);
329 return NULL;
330 }
331 get_page(page);
332 atomic_inc(&agp_bridge->current_memory_agp);
333 return page;
334 }
335
336 static void i8xx_destroy_pages(struct page *page)
337 {
338 if (page == NULL)
339 return;
340
341 set_pages_wb(page, 4);
342 put_page(page);
343 __free_pages(page, 2);
344 atomic_dec(&agp_bridge->current_memory_agp);
345 }
346
347 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
348 int type)
349 {
350 if (type < AGP_USER_TYPES)
351 return type;
352 else if (type == AGP_USER_CACHED_MEMORY)
353 return INTEL_AGP_CACHED_MEMORY;
354 else
355 return 0;
356 }
357
358 static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
359 int type)
360 {
361 unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT;
362 unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT;
363
364 if (type_mask == AGP_USER_UNCACHED_MEMORY)
365 return INTEL_AGP_UNCACHED_MEMORY;
366 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
367 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
368 INTEL_AGP_CACHED_MEMORY_LLC_MLC;
369 else /* set 'normal'/'cached' to LLC by default */
370 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :
371 INTEL_AGP_CACHED_MEMORY_LLC;
372 }
373
374
375 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
376 int type)
377 {
378 int i, j, num_entries;
379 void *temp;
380 int ret = -EINVAL;
381 int mask_type;
382
383 if (mem->page_count == 0)
384 goto out;
385
386 temp = agp_bridge->current_size;
387 num_entries = A_SIZE_FIX(temp)->num_entries;
388
389 if ((pg_start + mem->page_count) > num_entries)
390 goto out_err;
391
392
393 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
394 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
395 ret = -EBUSY;
396 goto out_err;
397 }
398 }
399
400 if (type != mem->type)
401 goto out_err;
402
403 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
404
405 switch (mask_type) {
406 case AGP_DCACHE_MEMORY:
407 if (!mem->is_flushed)
408 global_cache_flush();
409 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
410 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
411 intel_private.registers+I810_PTE_BASE+(i*4));
412 }
413 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
414 break;
415 case AGP_PHYS_MEMORY:
416 case AGP_NORMAL_MEMORY:
417 if (!mem->is_flushed)
418 global_cache_flush();
419 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
420 writel(agp_bridge->driver->mask_memory(agp_bridge,
421 page_to_phys(mem->pages[i]), mask_type),
422 intel_private.registers+I810_PTE_BASE+(j*4));
423 }
424 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
425 break;
426 default:
427 goto out_err;
428 }
429
430 out:
431 ret = 0;
432 out_err:
433 mem->is_flushed = true;
434 return ret;
435 }
436
437 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
438 int type)
439 {
440 int i;
441
442 if (mem->page_count == 0)
443 return 0;
444
445 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
446 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
447 }
448 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
449
450 return 0;
451 }
452
453 /*
454 * The i810/i830 requires a physical address to program its mouse
455 * pointer into hardware.
456 * However the Xserver still writes to it through the agp aperture.
457 */
458 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
459 {
460 struct agp_memory *new;
461 struct page *page;
462
463 switch (pg_count) {
464 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
465 break;
466 case 4:
467 /* kludge to get 4 physical pages for ARGB cursor */
468 page = i8xx_alloc_pages();
469 break;
470 default:
471 return NULL;
472 }
473
474 if (page == NULL)
475 return NULL;
476
477 new = agp_create_memory(pg_count);
478 if (new == NULL)
479 return NULL;
480
481 new->pages[0] = page;
482 if (pg_count == 4) {
483 /* kludge to get 4 physical pages for ARGB cursor */
484 new->pages[1] = new->pages[0] + 1;
485 new->pages[2] = new->pages[1] + 1;
486 new->pages[3] = new->pages[2] + 1;
487 }
488 new->page_count = pg_count;
489 new->num_scratch_pages = pg_count;
490 new->type = AGP_PHYS_MEMORY;
491 new->physical = page_to_phys(new->pages[0]);
492 return new;
493 }
494
495 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
496 {
497 struct agp_memory *new;
498
499 if (type == AGP_DCACHE_MEMORY) {
500 if (pg_count != intel_private.num_dcache_entries)
501 return NULL;
502
503 new = agp_create_memory(1);
504 if (new == NULL)
505 return NULL;
506
507 new->type = AGP_DCACHE_MEMORY;
508 new->page_count = pg_count;
509 new->num_scratch_pages = 0;
510 agp_free_page_array(new);
511 return new;
512 }
513 if (type == AGP_PHYS_MEMORY)
514 return alloc_agpphysmem_i8xx(pg_count, type);
515 return NULL;
516 }
517
518 static void intel_i810_free_by_type(struct agp_memory *curr)
519 {
520 agp_free_key(curr->key);
521 if (curr->type == AGP_PHYS_MEMORY) {
522 if (curr->page_count == 4)
523 i8xx_destroy_pages(curr->pages[0]);
524 else {
525 agp_bridge->driver->agp_destroy_page(curr->pages[0],
526 AGP_PAGE_DESTROY_UNMAP);
527 agp_bridge->driver->agp_destroy_page(curr->pages[0],
528 AGP_PAGE_DESTROY_FREE);
529 }
530 agp_free_page_array(curr);
531 }
532 kfree(curr);
533 }
534
535 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
536 dma_addr_t addr, int type)
537 {
538 /* Type checking must be done elsewhere */
539 return addr | bridge->driver->masks[type].mask;
540 }
541
542 static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = {
543 {128, 32768, 5},
544 /* The 64M mode still requires a 128k gatt */
545 {64, 16384, 5},
546 {256, 65536, 6},
547 {512, 131072, 7},
548 };
549
550 static unsigned int intel_gtt_stolen_entries(void)
551 {
552 u16 gmch_ctrl;
553 u8 rdct;
554 int local = 0;
555 static const int ddt[4] = { 0, 16, 32, 64 };
556 unsigned int overhead_entries, stolen_entries;
557 unsigned int stolen_size = 0;
558
559 pci_read_config_word(intel_private.bridge_dev,
560 I830_GMCH_CTRL, &gmch_ctrl);
561
562 if (INTEL_GTT_GEN > 4 || IS_PINEVIEW)
563 overhead_entries = 0;
564 else
565 overhead_entries = intel_private.base.gtt_mappable_entries
566 / 1024;
567
568 overhead_entries += 1; /* BIOS popup */
569
570 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
571 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
572 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
573 case I830_GMCH_GMS_STOLEN_512:
574 stolen_size = KB(512);
575 break;
576 case I830_GMCH_GMS_STOLEN_1024:
577 stolen_size = MB(1);
578 break;
579 case I830_GMCH_GMS_STOLEN_8192:
580 stolen_size = MB(8);
581 break;
582 case I830_GMCH_GMS_LOCAL:
583 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
584 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
585 MB(ddt[I830_RDRAM_DDT(rdct)]);
586 local = 1;
587 break;
588 default:
589 stolen_size = 0;
590 break;
591 }
592 } else if (INTEL_GTT_GEN == 6) {
593 /*
594 * SandyBridge has new memory control reg at 0x50.w
595 */
596 u16 snb_gmch_ctl;
597 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
598 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
599 case SNB_GMCH_GMS_STOLEN_32M:
600 stolen_size = MB(32);
601 break;
602 case SNB_GMCH_GMS_STOLEN_64M:
603 stolen_size = MB(64);
604 break;
605 case SNB_GMCH_GMS_STOLEN_96M:
606 stolen_size = MB(96);
607 break;
608 case SNB_GMCH_GMS_STOLEN_128M:
609 stolen_size = MB(128);
610 break;
611 case SNB_GMCH_GMS_STOLEN_160M:
612 stolen_size = MB(160);
613 break;
614 case SNB_GMCH_GMS_STOLEN_192M:
615 stolen_size = MB(192);
616 break;
617 case SNB_GMCH_GMS_STOLEN_224M:
618 stolen_size = MB(224);
619 break;
620 case SNB_GMCH_GMS_STOLEN_256M:
621 stolen_size = MB(256);
622 break;
623 case SNB_GMCH_GMS_STOLEN_288M:
624 stolen_size = MB(288);
625 break;
626 case SNB_GMCH_GMS_STOLEN_320M:
627 stolen_size = MB(320);
628 break;
629 case SNB_GMCH_GMS_STOLEN_352M:
630 stolen_size = MB(352);
631 break;
632 case SNB_GMCH_GMS_STOLEN_384M:
633 stolen_size = MB(384);
634 break;
635 case SNB_GMCH_GMS_STOLEN_416M:
636 stolen_size = MB(416);
637 break;
638 case SNB_GMCH_GMS_STOLEN_448M:
639 stolen_size = MB(448);
640 break;
641 case SNB_GMCH_GMS_STOLEN_480M:
642 stolen_size = MB(480);
643 break;
644 case SNB_GMCH_GMS_STOLEN_512M:
645 stolen_size = MB(512);
646 break;
647 }
648 } else {
649 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
650 case I855_GMCH_GMS_STOLEN_1M:
651 stolen_size = MB(1);
652 break;
653 case I855_GMCH_GMS_STOLEN_4M:
654 stolen_size = MB(4);
655 break;
656 case I855_GMCH_GMS_STOLEN_8M:
657 stolen_size = MB(8);
658 break;
659 case I855_GMCH_GMS_STOLEN_16M:
660 stolen_size = MB(16);
661 break;
662 case I855_GMCH_GMS_STOLEN_32M:
663 stolen_size = MB(32);
664 break;
665 case I915_GMCH_GMS_STOLEN_48M:
666 stolen_size = MB(48);
667 break;
668 case I915_GMCH_GMS_STOLEN_64M:
669 stolen_size = MB(64);
670 break;
671 case G33_GMCH_GMS_STOLEN_128M:
672 stolen_size = MB(128);
673 break;
674 case G33_GMCH_GMS_STOLEN_256M:
675 stolen_size = MB(256);
676 break;
677 case INTEL_GMCH_GMS_STOLEN_96M:
678 stolen_size = MB(96);
679 break;
680 case INTEL_GMCH_GMS_STOLEN_160M:
681 stolen_size = MB(160);
682 break;
683 case INTEL_GMCH_GMS_STOLEN_224M:
684 stolen_size = MB(224);
685 break;
686 case INTEL_GMCH_GMS_STOLEN_352M:
687 stolen_size = MB(352);
688 break;
689 default:
690 stolen_size = 0;
691 break;
692 }
693 }
694
695 if (!local && stolen_size > intel_max_stolen) {
696 dev_info(&intel_private.bridge_dev->dev,
697 "detected %dK stolen memory, trimming to %dK\n",
698 stolen_size / KB(1), intel_max_stolen / KB(1));
699 stolen_size = intel_max_stolen;
700 } else if (stolen_size > 0) {
701 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
702 stolen_size / KB(1), local ? "local" : "stolen");
703 } else {
704 dev_info(&intel_private.bridge_dev->dev,
705 "no pre-allocated video memory detected\n");
706 stolen_size = 0;
707 }
708
709 stolen_entries = stolen_size/KB(4) - overhead_entries;
710
711 return stolen_entries;
712 }
713
714 static unsigned int intel_gtt_total_entries(void)
715 {
716 int size;
717
718 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) {
719 u32 pgetbl_ctl;
720 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
721
722 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
723 case I965_PGETBL_SIZE_128KB:
724 size = KB(128);
725 break;
726 case I965_PGETBL_SIZE_256KB:
727 size = KB(256);
728 break;
729 case I965_PGETBL_SIZE_512KB:
730 size = KB(512);
731 break;
732 case I965_PGETBL_SIZE_1MB:
733 size = KB(1024);
734 break;
735 case I965_PGETBL_SIZE_2MB:
736 size = KB(2048);
737 break;
738 case I965_PGETBL_SIZE_1_5MB:
739 size = KB(1024 + 512);
740 break;
741 default:
742 dev_info(&intel_private.pcidev->dev,
743 "unknown page table size, assuming 512KB\n");
744 size = KB(512);
745 }
746
747 return size/4;
748 } else if (INTEL_GTT_GEN == 6) {
749 u16 snb_gmch_ctl;
750
751 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
752 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
753 default:
754 case SNB_GTT_SIZE_0M:
755 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
756 size = MB(0);
757 break;
758 case SNB_GTT_SIZE_1M:
759 size = MB(1);
760 break;
761 case SNB_GTT_SIZE_2M:
762 size = MB(2);
763 break;
764 }
765 return size/4;
766 } else {
767 /* On previous hardware, the GTT size was just what was
768 * required to map the aperture.
769 */
770 return intel_private.base.gtt_mappable_entries;
771 }
772 }
773
774 static unsigned int intel_gtt_mappable_entries(void)
775 {
776 unsigned int aperture_size;
777 u16 gmch_ctrl;
778
779 aperture_size = 1024 * 1024;
780
781 pci_read_config_word(intel_private.bridge_dev,
782 I830_GMCH_CTRL, &gmch_ctrl);
783
784 if (INTEL_GTT_GEN == 2) {
785 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
786 aperture_size *= 64;
787 else
788 aperture_size *= 128;
789 } else {
790 /* 9xx supports large sizes, just look at the length */
791 aperture_size = pci_resource_len(intel_private.pcidev, 2);
792 }
793
794 return aperture_size >> PAGE_SHIFT;
795 }
796
797 static int intel_gtt_init(void)
798 {
799 u32 gtt_map_size;
800 int ret;
801
802 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
803
804 ret = intel_private.driver->setup();
805 if (ret != 0)
806 return ret;
807
808 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
809 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
810
811 gtt_map_size = intel_private.base.gtt_total_entries * 4;
812
813 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
814 gtt_map_size);
815 if (!intel_private.gtt) {
816 iounmap(intel_private.registers);
817 return -ENOMEM;
818 }
819
820 global_cache_flush(); /* FIXME: ? */
821
822 /* we have to call this as early as possible after the MMIO base address is known */
823 intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
824 if (intel_private.base.gtt_stolen_entries == 0) {
825 iounmap(intel_private.registers);
826 iounmap(intel_private.gtt);
827 return -ENOMEM;
828 }
829
830 return 0;
831 }
832
833 static int intel_fake_agp_fetch_size(void)
834 {
835 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
836 unsigned int aper_size;
837 int i;
838
839 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
840 / MB(1);
841
842 for (i = 0; i < num_sizes; i++) {
843 if (aper_size == intel_fake_agp_sizes[i].size) {
844 agp_bridge->current_size =
845 (void *) (intel_fake_agp_sizes + i);
846 return aper_size;
847 }
848 }
849
850 return 0;
851 }
852
853 static void intel_i830_fini_flush(void)
854 {
855 kunmap(intel_private.i8xx_page);
856 intel_private.i8xx_flush_page = NULL;
857 unmap_page_from_agp(intel_private.i8xx_page);
858
859 __free_page(intel_private.i8xx_page);
860 intel_private.i8xx_page = NULL;
861 }
862
863 static void intel_i830_setup_flush(void)
864 {
865 /* return if we've already set the flush mechanism up */
866 if (intel_private.i8xx_page)
867 return;
868
869 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
870 if (!intel_private.i8xx_page)
871 return;
872
873 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
874 if (!intel_private.i8xx_flush_page)
875 intel_i830_fini_flush();
876 }
877
878 /* The chipset_flush interface needs to get data that has already been
879 * flushed out of the CPU all the way out to main memory, because the GPU
880 * doesn't snoop those buffers.
881 *
882 * The 8xx series doesn't have the same lovely interface for flushing the
883 * chipset write buffers that the later chips do. According to the 865
884 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
885 * that buffer out, we just fill 1KB and clflush it out, on the assumption
886 * that it'll push whatever was in there out. It appears to work.
887 */
888 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
889 {
890 unsigned int *pg = intel_private.i8xx_flush_page;
891
892 memset(pg, 0, 1024);
893
894 if (cpu_has_clflush)
895 clflush_cache_range(pg, 1024);
896 else if (wbinvd_on_all_cpus() != 0)
897 printk(KERN_ERR "Timed out waiting for cache flush.\n");
898 }
899
900 static void intel_enable_gtt(void)
901 {
902 u32 ptetbl_addr, gma_addr;
903 u16 gmch_ctrl;
904
905 ptetbl_addr = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
906
907 if (INTEL_GTT_GEN == 2)
908 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
909 &gma_addr);
910 else
911 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
912 &gma_addr);
913
914 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
915
916 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
917 gmch_ctrl |= I830_GMCH_ENABLED;
918 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
919
920 writel(ptetbl_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
921 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
922 }
923
924 static int i830_setup(void)
925 {
926 u32 reg_addr;
927
928 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
929 reg_addr &= 0xfff80000;
930
931 intel_private.registers = ioremap(reg_addr, KB(64));
932 if (!intel_private.registers)
933 return -ENOMEM;
934
935 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
936
937 intel_i830_setup_flush();
938
939 return 0;
940 }
941
942 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
943 {
944 agp_bridge->gatt_table_real = NULL;
945 agp_bridge->gatt_table = NULL;
946 agp_bridge->gatt_bus_addr = 0;
947
948 return 0;
949 }
950
951 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
952 {
953 return 0;
954 }
955
956 static int intel_i830_configure(void)
957 {
958 int i;
959
960 intel_enable_gtt();
961
962 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
963
964 if (agp_bridge->driver->needs_scratch_page) {
965 for (i = intel_private.base.gtt_stolen_entries;
966 i < intel_private.base.gtt_total_entries; i++) {
967 writel(agp_bridge->scratch_page, intel_private.gtt+i);
968 }
969 readl(intel_private.gtt+i-1); /* PCI Posting. */
970 }
971
972 global_cache_flush();
973
974 return 0;
975 }
976
977 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
978 int type)
979 {
980 int i, j, num_entries;
981 void *temp;
982 int ret = -EINVAL;
983 int mask_type;
984
985 if (mem->page_count == 0)
986 goto out;
987
988 temp = agp_bridge->current_size;
989 num_entries = A_SIZE_FIX(temp)->num_entries;
990
991 if (pg_start < intel_private.base.gtt_stolen_entries) {
992 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
993 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
994 pg_start, intel_private.base.gtt_stolen_entries);
995
996 dev_info(&intel_private.pcidev->dev,
997 "trying to insert into local/stolen memory\n");
998 goto out_err;
999 }
1000
1001 if ((pg_start + mem->page_count) > num_entries)
1002 goto out_err;
1003
1004 /* The i830 can't check the GTT for entries since its read only,
1005 * depend on the caller to make the correct offset decisions.
1006 */
1007
1008 if (type != mem->type)
1009 goto out_err;
1010
1011 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1012
1013 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1014 mask_type != INTEL_AGP_CACHED_MEMORY)
1015 goto out_err;
1016
1017 if (!mem->is_flushed)
1018 global_cache_flush();
1019
1020 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1021 writel(agp_bridge->driver->mask_memory(agp_bridge,
1022 page_to_phys(mem->pages[i]), mask_type),
1023 intel_private.gtt+j);
1024 }
1025 readl(intel_private.gtt+j-1);
1026
1027 out:
1028 ret = 0;
1029 out_err:
1030 mem->is_flushed = true;
1031 return ret;
1032 }
1033
1034 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1035 int type)
1036 {
1037 int i;
1038
1039 if (mem->page_count == 0)
1040 return 0;
1041
1042 if (pg_start < intel_private.base.gtt_stolen_entries) {
1043 dev_info(&intel_private.pcidev->dev,
1044 "trying to disable local/stolen memory\n");
1045 return -EINVAL;
1046 }
1047
1048 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1049 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1050 }
1051 readl(intel_private.gtt+i-1);
1052
1053 return 0;
1054 }
1055
1056 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1057 int type)
1058 {
1059 if (type == AGP_PHYS_MEMORY)
1060 return alloc_agpphysmem_i8xx(pg_count, type);
1061 /* always return NULL for other allocation types for now */
1062 return NULL;
1063 }
1064
1065 static int intel_alloc_chipset_flush_resource(void)
1066 {
1067 int ret;
1068 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1069 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1070 pcibios_align_resource, intel_private.bridge_dev);
1071
1072 return ret;
1073 }
1074
1075 static void intel_i915_setup_chipset_flush(void)
1076 {
1077 int ret;
1078 u32 temp;
1079
1080 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1081 if (!(temp & 0x1)) {
1082 intel_alloc_chipset_flush_resource();
1083 intel_private.resource_valid = 1;
1084 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1085 } else {
1086 temp &= ~1;
1087
1088 intel_private.resource_valid = 1;
1089 intel_private.ifp_resource.start = temp;
1090 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1091 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1092 /* some BIOSes reserve this area in a pnp some don't */
1093 if (ret)
1094 intel_private.resource_valid = 0;
1095 }
1096 }
1097
1098 static void intel_i965_g33_setup_chipset_flush(void)
1099 {
1100 u32 temp_hi, temp_lo;
1101 int ret;
1102
1103 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1104 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1105
1106 if (!(temp_lo & 0x1)) {
1107
1108 intel_alloc_chipset_flush_resource();
1109
1110 intel_private.resource_valid = 1;
1111 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1112 upper_32_bits(intel_private.ifp_resource.start));
1113 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1114 } else {
1115 u64 l64;
1116
1117 temp_lo &= ~0x1;
1118 l64 = ((u64)temp_hi << 32) | temp_lo;
1119
1120 intel_private.resource_valid = 1;
1121 intel_private.ifp_resource.start = l64;
1122 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1123 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1124 /* some BIOSes reserve this area in a pnp some don't */
1125 if (ret)
1126 intel_private.resource_valid = 0;
1127 }
1128 }
1129
1130 static void intel_i9xx_setup_flush(void)
1131 {
1132 /* return if already configured */
1133 if (intel_private.ifp_resource.start)
1134 return;
1135
1136 if (INTEL_GTT_GEN == 6)
1137 return;
1138
1139 /* setup a resource for this object */
1140 intel_private.ifp_resource.name = "Intel Flush Page";
1141 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1142
1143 /* Setup chipset flush for 915 */
1144 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1145 intel_i965_g33_setup_chipset_flush();
1146 } else {
1147 intel_i915_setup_chipset_flush();
1148 }
1149
1150 if (intel_private.ifp_resource.start)
1151 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1152 if (!intel_private.i9xx_flush_page)
1153 dev_err(&intel_private.pcidev->dev,
1154 "can't ioremap flush page - no chipset flushing\n");
1155 }
1156
1157 static int intel_i9xx_configure(void)
1158 {
1159 int i;
1160
1161 intel_enable_gtt();
1162
1163 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
1164
1165 if (agp_bridge->driver->needs_scratch_page) {
1166 for (i = intel_private.base.gtt_stolen_entries; i <
1167 intel_private.base.gtt_total_entries; i++) {
1168 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1169 }
1170 readl(intel_private.gtt+i-1); /* PCI Posting. */
1171 }
1172
1173 global_cache_flush();
1174
1175 return 0;
1176 }
1177
1178 static void intel_gtt_cleanup(void)
1179 {
1180 if (intel_private.i9xx_flush_page)
1181 iounmap(intel_private.i9xx_flush_page);
1182 if (intel_private.resource_valid)
1183 release_resource(&intel_private.ifp_resource);
1184 intel_private.ifp_resource.start = 0;
1185 intel_private.resource_valid = 0;
1186 iounmap(intel_private.gtt);
1187 iounmap(intel_private.registers);
1188 }
1189
1190 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1191 {
1192 if (intel_private.i9xx_flush_page)
1193 writel(1, intel_private.i9xx_flush_page);
1194 }
1195
1196 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1197 int type)
1198 {
1199 int num_entries;
1200 void *temp;
1201 int ret = -EINVAL;
1202 int mask_type;
1203
1204 if (mem->page_count == 0)
1205 goto out;
1206
1207 temp = agp_bridge->current_size;
1208 num_entries = A_SIZE_FIX(temp)->num_entries;
1209
1210 if (pg_start < intel_private.base.gtt_stolen_entries) {
1211 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1212 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1213 pg_start, intel_private.base.gtt_stolen_entries);
1214
1215 dev_info(&intel_private.pcidev->dev,
1216 "trying to insert into local/stolen memory\n");
1217 goto out_err;
1218 }
1219
1220 if ((pg_start + mem->page_count) > num_entries)
1221 goto out_err;
1222
1223 /* The i915 can't check the GTT for entries since it's read only;
1224 * depend on the caller to make the correct offset decisions.
1225 */
1226
1227 if (type != mem->type)
1228 goto out_err;
1229
1230 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1231
1232 if (INTEL_GTT_GEN != 6 && mask_type != 0 &&
1233 mask_type != AGP_PHYS_MEMORY &&
1234 mask_type != INTEL_AGP_CACHED_MEMORY)
1235 goto out_err;
1236
1237 if (!mem->is_flushed)
1238 global_cache_flush();
1239
1240 intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1241
1242 out:
1243 ret = 0;
1244 out_err:
1245 mem->is_flushed = true;
1246 return ret;
1247 }
1248
1249 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1250 int type)
1251 {
1252 int i;
1253
1254 if (mem->page_count == 0)
1255 return 0;
1256
1257 if (pg_start < intel_private.base.gtt_stolen_entries) {
1258 dev_info(&intel_private.pcidev->dev,
1259 "trying to disable local/stolen memory\n");
1260 return -EINVAL;
1261 }
1262
1263 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1264 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1265
1266 readl(intel_private.gtt+i-1);
1267
1268 return 0;
1269 }
1270
1271 static int i9xx_setup(void)
1272 {
1273 u32 reg_addr;
1274
1275 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1276
1277 reg_addr &= 0xfff80000;
1278
1279 intel_private.registers = ioremap(reg_addr, 128 * 4096);
1280 if (!intel_private.registers)
1281 return -ENOMEM;
1282
1283 if (INTEL_GTT_GEN == 3) {
1284 u32 gtt_addr;
1285 pci_read_config_dword(intel_private.pcidev,
1286 I915_PTEADDR, &gtt_addr);
1287 intel_private.gtt_bus_addr = gtt_addr;
1288 } else {
1289 u32 gtt_offset;
1290
1291 switch (INTEL_GTT_GEN) {
1292 case 5:
1293 case 6:
1294 gtt_offset = MB(2);
1295 break;
1296 case 4:
1297 default:
1298 gtt_offset = KB(512);
1299 break;
1300 }
1301 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1302 }
1303
1304 intel_i9xx_setup_flush();
1305
1306 return 0;
1307 }
1308
1309 /*
1310 * The i965 supports 36-bit physical addresses, but to keep
1311 * the format of the GTT the same, the bits that don't fit
1312 * in a 32-bit word are shifted down to bits 4..7.
1313 *
1314 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1315 * is always zero on 32-bit architectures, so no need to make
1316 * this conditional.
1317 */
1318 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1319 dma_addr_t addr, int type)
1320 {
1321 /* Shift high bits down */
1322 addr |= (addr >> 28) & 0xf0;
1323
1324 /* Type checking must be done elsewhere */
1325 return addr | bridge->driver->masks[type].mask;
1326 }
1327
1328 static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
1329 dma_addr_t addr, int type)
1330 {
1331 /* gen6 has bit11-4 for physical addr bit39-32 */
1332 addr |= (addr >> 28) & 0xff0;
1333
1334 /* Type checking must be done elsewhere */
1335 return addr | bridge->driver->masks[type].mask;
1336 }
1337
1338 static const struct agp_bridge_driver intel_810_driver = {
1339 .owner = THIS_MODULE,
1340 .aperture_sizes = intel_i810_sizes,
1341 .size_type = FIXED_APER_SIZE,
1342 .num_aperture_sizes = 2,
1343 .needs_scratch_page = true,
1344 .configure = intel_i810_configure,
1345 .fetch_size = intel_i810_fetch_size,
1346 .cleanup = intel_i810_cleanup,
1347 .mask_memory = intel_i810_mask_memory,
1348 .masks = intel_i810_masks,
1349 .agp_enable = intel_fake_agp_enable,
1350 .cache_flush = global_cache_flush,
1351 .create_gatt_table = agp_generic_create_gatt_table,
1352 .free_gatt_table = agp_generic_free_gatt_table,
1353 .insert_memory = intel_i810_insert_entries,
1354 .remove_memory = intel_i810_remove_entries,
1355 .alloc_by_type = intel_i810_alloc_by_type,
1356 .free_by_type = intel_i810_free_by_type,
1357 .agp_alloc_page = agp_generic_alloc_page,
1358 .agp_alloc_pages = agp_generic_alloc_pages,
1359 .agp_destroy_page = agp_generic_destroy_page,
1360 .agp_destroy_pages = agp_generic_destroy_pages,
1361 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1362 };
1363
1364 static const struct agp_bridge_driver intel_830_driver = {
1365 .owner = THIS_MODULE,
1366 .size_type = FIXED_APER_SIZE,
1367 .aperture_sizes = intel_fake_agp_sizes,
1368 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1369 .needs_scratch_page = true,
1370 .configure = intel_i830_configure,
1371 .fetch_size = intel_fake_agp_fetch_size,
1372 .cleanup = intel_gtt_cleanup,
1373 .mask_memory = intel_i810_mask_memory,
1374 .masks = intel_i810_masks,
1375 .agp_enable = intel_fake_agp_enable,
1376 .cache_flush = global_cache_flush,
1377 .create_gatt_table = intel_fake_agp_create_gatt_table,
1378 .free_gatt_table = intel_fake_agp_free_gatt_table,
1379 .insert_memory = intel_i830_insert_entries,
1380 .remove_memory = intel_i830_remove_entries,
1381 .alloc_by_type = intel_fake_agp_alloc_by_type,
1382 .free_by_type = intel_i810_free_by_type,
1383 .agp_alloc_page = agp_generic_alloc_page,
1384 .agp_alloc_pages = agp_generic_alloc_pages,
1385 .agp_destroy_page = agp_generic_destroy_page,
1386 .agp_destroy_pages = agp_generic_destroy_pages,
1387 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1388 .chipset_flush = intel_i830_chipset_flush,
1389 };
1390
1391 static const struct agp_bridge_driver intel_915_driver = {
1392 .owner = THIS_MODULE,
1393 .size_type = FIXED_APER_SIZE,
1394 .aperture_sizes = intel_fake_agp_sizes,
1395 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1396 .needs_scratch_page = true,
1397 .configure = intel_i9xx_configure,
1398 .fetch_size = intel_fake_agp_fetch_size,
1399 .cleanup = intel_gtt_cleanup,
1400 .mask_memory = intel_i810_mask_memory,
1401 .masks = intel_i810_masks,
1402 .agp_enable = intel_fake_agp_enable,
1403 .cache_flush = global_cache_flush,
1404 .create_gatt_table = intel_fake_agp_create_gatt_table,
1405 .free_gatt_table = intel_fake_agp_free_gatt_table,
1406 .insert_memory = intel_i915_insert_entries,
1407 .remove_memory = intel_i915_remove_entries,
1408 .alloc_by_type = intel_fake_agp_alloc_by_type,
1409 .free_by_type = intel_i810_free_by_type,
1410 .agp_alloc_page = agp_generic_alloc_page,
1411 .agp_alloc_pages = agp_generic_alloc_pages,
1412 .agp_destroy_page = agp_generic_destroy_page,
1413 .agp_destroy_pages = agp_generic_destroy_pages,
1414 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1415 .chipset_flush = intel_i915_chipset_flush,
1416 #ifdef USE_PCI_DMA_API
1417 .agp_map_page = intel_agp_map_page,
1418 .agp_unmap_page = intel_agp_unmap_page,
1419 .agp_map_memory = intel_agp_map_memory,
1420 .agp_unmap_memory = intel_agp_unmap_memory,
1421 #endif
1422 };
1423
1424 static const struct agp_bridge_driver intel_i965_driver = {
1425 .owner = THIS_MODULE,
1426 .size_type = FIXED_APER_SIZE,
1427 .aperture_sizes = intel_fake_agp_sizes,
1428 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1429 .needs_scratch_page = true,
1430 .configure = intel_i9xx_configure,
1431 .fetch_size = intel_fake_agp_fetch_size,
1432 .cleanup = intel_gtt_cleanup,
1433 .mask_memory = intel_i965_mask_memory,
1434 .masks = intel_i810_masks,
1435 .agp_enable = intel_fake_agp_enable,
1436 .cache_flush = global_cache_flush,
1437 .create_gatt_table = intel_fake_agp_create_gatt_table,
1438 .free_gatt_table = intel_fake_agp_free_gatt_table,
1439 .insert_memory = intel_i915_insert_entries,
1440 .remove_memory = intel_i915_remove_entries,
1441 .alloc_by_type = intel_fake_agp_alloc_by_type,
1442 .free_by_type = intel_i810_free_by_type,
1443 .agp_alloc_page = agp_generic_alloc_page,
1444 .agp_alloc_pages = agp_generic_alloc_pages,
1445 .agp_destroy_page = agp_generic_destroy_page,
1446 .agp_destroy_pages = agp_generic_destroy_pages,
1447 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1448 .chipset_flush = intel_i915_chipset_flush,
1449 #ifdef USE_PCI_DMA_API
1450 .agp_map_page = intel_agp_map_page,
1451 .agp_unmap_page = intel_agp_unmap_page,
1452 .agp_map_memory = intel_agp_map_memory,
1453 .agp_unmap_memory = intel_agp_unmap_memory,
1454 #endif
1455 };
1456
1457 static const struct agp_bridge_driver intel_gen6_driver = {
1458 .owner = THIS_MODULE,
1459 .size_type = FIXED_APER_SIZE,
1460 .aperture_sizes = intel_fake_agp_sizes,
1461 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1462 .needs_scratch_page = true,
1463 .configure = intel_i9xx_configure,
1464 .fetch_size = intel_fake_agp_fetch_size,
1465 .cleanup = intel_gtt_cleanup,
1466 .mask_memory = intel_gen6_mask_memory,
1467 .masks = intel_gen6_masks,
1468 .agp_enable = intel_fake_agp_enable,
1469 .cache_flush = global_cache_flush,
1470 .create_gatt_table = intel_fake_agp_create_gatt_table,
1471 .free_gatt_table = intel_fake_agp_free_gatt_table,
1472 .insert_memory = intel_i915_insert_entries,
1473 .remove_memory = intel_i915_remove_entries,
1474 .alloc_by_type = intel_fake_agp_alloc_by_type,
1475 .free_by_type = intel_i810_free_by_type,
1476 .agp_alloc_page = agp_generic_alloc_page,
1477 .agp_alloc_pages = agp_generic_alloc_pages,
1478 .agp_destroy_page = agp_generic_destroy_page,
1479 .agp_destroy_pages = agp_generic_destroy_pages,
1480 .agp_type_to_mask_type = intel_gen6_type_to_mask_type,
1481 .chipset_flush = intel_i915_chipset_flush,
1482 #ifdef USE_PCI_DMA_API
1483 .agp_map_page = intel_agp_map_page,
1484 .agp_unmap_page = intel_agp_unmap_page,
1485 .agp_map_memory = intel_agp_map_memory,
1486 .agp_unmap_memory = intel_agp_unmap_memory,
1487 #endif
1488 };
1489
1490 static const struct agp_bridge_driver intel_g33_driver = {
1491 .owner = THIS_MODULE,
1492 .size_type = FIXED_APER_SIZE,
1493 .aperture_sizes = intel_fake_agp_sizes,
1494 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1495 .needs_scratch_page = true,
1496 .configure = intel_i9xx_configure,
1497 .fetch_size = intel_fake_agp_fetch_size,
1498 .cleanup = intel_gtt_cleanup,
1499 .mask_memory = intel_i965_mask_memory,
1500 .masks = intel_i810_masks,
1501 .agp_enable = intel_fake_agp_enable,
1502 .cache_flush = global_cache_flush,
1503 .create_gatt_table = intel_fake_agp_create_gatt_table,
1504 .free_gatt_table = intel_fake_agp_free_gatt_table,
1505 .insert_memory = intel_i915_insert_entries,
1506 .remove_memory = intel_i915_remove_entries,
1507 .alloc_by_type = intel_fake_agp_alloc_by_type,
1508 .free_by_type = intel_i810_free_by_type,
1509 .agp_alloc_page = agp_generic_alloc_page,
1510 .agp_alloc_pages = agp_generic_alloc_pages,
1511 .agp_destroy_page = agp_generic_destroy_page,
1512 .agp_destroy_pages = agp_generic_destroy_pages,
1513 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1514 .chipset_flush = intel_i915_chipset_flush,
1515 #ifdef USE_PCI_DMA_API
1516 .agp_map_page = intel_agp_map_page,
1517 .agp_unmap_page = intel_agp_unmap_page,
1518 .agp_map_memory = intel_agp_map_memory,
1519 .agp_unmap_memory = intel_agp_unmap_memory,
1520 #endif
1521 };
1522
1523 static const struct intel_gtt_driver i8xx_gtt_driver = {
1524 .gen = 2,
1525 .setup = i830_setup,
1526 };
1527 static const struct intel_gtt_driver i915_gtt_driver = {
1528 .gen = 3,
1529 .setup = i9xx_setup,
1530 };
1531 static const struct intel_gtt_driver g33_gtt_driver = {
1532 .gen = 3,
1533 .is_g33 = 1,
1534 .setup = i9xx_setup,
1535 };
1536 static const struct intel_gtt_driver pineview_gtt_driver = {
1537 .gen = 3,
1538 .is_pineview = 1, .is_g33 = 1,
1539 .setup = i9xx_setup,
1540 };
1541 static const struct intel_gtt_driver i965_gtt_driver = {
1542 .gen = 4,
1543 .setup = i9xx_setup,
1544 };
1545 static const struct intel_gtt_driver g4x_gtt_driver = {
1546 .gen = 5,
1547 .setup = i9xx_setup,
1548 };
1549 static const struct intel_gtt_driver ironlake_gtt_driver = {
1550 .gen = 5,
1551 .is_ironlake = 1,
1552 .setup = i9xx_setup,
1553 };
1554 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1555 .gen = 6,
1556 .setup = i9xx_setup,
1557 };
1558
1559 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1560 * driver and gmch_driver must be non-null, and find_gmch will determine
1561 * which one should be used if a gmch_chip_id is present.
1562 */
1563 static const struct intel_gtt_driver_description {
1564 unsigned int gmch_chip_id;
1565 char *name;
1566 const struct agp_bridge_driver *gmch_driver;
1567 const struct intel_gtt_driver *gtt_driver;
1568 } intel_gtt_chipsets[] = {
1569 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL},
1570 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL},
1571 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL},
1572 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL},
1573 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1574 &intel_830_driver , &i8xx_gtt_driver},
1575 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1576 &intel_830_driver , &i8xx_gtt_driver},
1577 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1578 &intel_830_driver , &i8xx_gtt_driver},
1579 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1580 &intel_830_driver , &i8xx_gtt_driver},
1581 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1582 &intel_830_driver , &i8xx_gtt_driver},
1583 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1584 &intel_915_driver , &i915_gtt_driver },
1585 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1586 &intel_915_driver , &i915_gtt_driver },
1587 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1588 &intel_915_driver , &i915_gtt_driver },
1589 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1590 &intel_915_driver , &i915_gtt_driver },
1591 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1592 &intel_915_driver , &i915_gtt_driver },
1593 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1594 &intel_915_driver , &i915_gtt_driver },
1595 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1596 &intel_i965_driver , &i965_gtt_driver },
1597 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1598 &intel_i965_driver , &i965_gtt_driver },
1599 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1600 &intel_i965_driver , &i965_gtt_driver },
1601 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1602 &intel_i965_driver , &i965_gtt_driver },
1603 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1604 &intel_i965_driver , &i965_gtt_driver },
1605 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1606 &intel_i965_driver , &i965_gtt_driver },
1607 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1608 &intel_g33_driver , &g33_gtt_driver },
1609 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1610 &intel_g33_driver , &g33_gtt_driver },
1611 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1612 &intel_g33_driver , &g33_gtt_driver },
1613 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1614 &intel_g33_driver , &pineview_gtt_driver },
1615 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1616 &intel_g33_driver , &pineview_gtt_driver },
1617 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1618 &intel_i965_driver , &g4x_gtt_driver },
1619 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1620 &intel_i965_driver , &g4x_gtt_driver },
1621 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1622 &intel_i965_driver , &g4x_gtt_driver },
1623 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1624 &intel_i965_driver , &g4x_gtt_driver },
1625 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1626 &intel_i965_driver , &g4x_gtt_driver },
1627 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1628 &intel_i965_driver , &g4x_gtt_driver },
1629 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1630 "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1631 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1632 "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1633 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1634 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1635 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1636 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1637 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1638 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1639 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1640 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1641 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1642 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1643 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1644 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1645 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1646 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1647 { 0, NULL, NULL }
1648 };
1649
1650 static int find_gmch(u16 device)
1651 {
1652 struct pci_dev *gmch_device;
1653
1654 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1655 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1656 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1657 device, gmch_device);
1658 }
1659
1660 if (!gmch_device)
1661 return 0;
1662
1663 intel_private.pcidev = gmch_device;
1664 return 1;
1665 }
1666
1667 int intel_gmch_probe(struct pci_dev *pdev,
1668 struct agp_bridge_data *bridge)
1669 {
1670 int i, mask;
1671 bridge->driver = NULL;
1672
1673 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1674 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1675 bridge->driver =
1676 intel_gtt_chipsets[i].gmch_driver;
1677 intel_private.driver =
1678 intel_gtt_chipsets[i].gtt_driver;
1679 break;
1680 }
1681 }
1682
1683 if (!bridge->driver)
1684 return 0;
1685
1686 bridge->dev_private_data = &intel_private;
1687 bridge->dev = pdev;
1688
1689 intel_private.bridge_dev = pci_dev_get(pdev);
1690
1691 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1692
1693 if (bridge->driver->mask_memory == intel_gen6_mask_memory)
1694 mask = 40;
1695 else if (bridge->driver->mask_memory == intel_i965_mask_memory)
1696 mask = 36;
1697 else
1698 mask = 32;
1699
1700 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1701 dev_err(&intel_private.pcidev->dev,
1702 "set gfx device dma mask %d-bit failed!\n", mask);
1703 else
1704 pci_set_consistent_dma_mask(intel_private.pcidev,
1705 DMA_BIT_MASK(mask));
1706
1707 if (bridge->driver == &intel_810_driver)
1708 return 1;
1709
1710 if (intel_gtt_init() != 0)
1711 return 0;
1712
1713 return 1;
1714 }
1715 EXPORT_SYMBOL(intel_gmch_probe);
1716
1717 struct intel_gtt *intel_gtt_get(void)
1718 {
1719 return &intel_private.base;
1720 }
1721 EXPORT_SYMBOL(intel_gtt_get);
1722
1723 void intel_gmch_remove(struct pci_dev *pdev)
1724 {
1725 if (intel_private.pcidev)
1726 pci_dev_put(intel_private.pcidev);
1727 if (intel_private.bridge_dev)
1728 pci_dev_put(intel_private.bridge_dev);
1729 }
1730 EXPORT_SYMBOL(intel_gmch_remove);
1731
1732 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1733 MODULE_LICENSE("GPL and additional rights");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree