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Merge branch 'topic/hda' into for-linus
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / pci / hda / hda_intel.c
blob0852e204a4c8439e557bd553dcde3aae1f7c173a
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #ifdef CONFIG_X86
50 /* for snoop control */
51 #include <asm/pgtable.h>
52 #include <asm/cacheflush.h>
53 #endif
54 #include <sound/core.h>
55 #include <sound/initval.h>
56 #include "hda_codec.h"
57
58
59 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
61 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
62 static char *model[SNDRV_CARDS];
63 static int position_fix[SNDRV_CARDS];
64 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
65 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
66 static int probe_only[SNDRV_CARDS];
67 static bool single_cmd;
68 static int enable_msi = -1;
69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
70 static char *patch[SNDRV_CARDS];
71 #endif
72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
73 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
74 CONFIG_SND_HDA_INPUT_BEEP_MODE};
75 #endif
76
77 module_param_array(index, int, NULL, 0444);
78 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
79 module_param_array(id, charp, NULL, 0444);
80 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
81 module_param_array(enable, bool, NULL, 0444);
82 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
83 module_param_array(model, charp, NULL, 0444);
84 MODULE_PARM_DESC(model, "Use the given board model.");
85 module_param_array(position_fix, int, NULL, 0444);
86 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
87 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
88 module_param_array(bdl_pos_adj, int, NULL, 0644);
89 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
90 module_param_array(probe_mask, int, NULL, 0444);
91 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
92 module_param_array(probe_only, int, NULL, 0444);
93 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
94 module_param(single_cmd, bool, 0444);
95 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
96 "(for debugging only).");
97 module_param(enable_msi, int, 0444);
98 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
100 module_param_array(patch, charp, NULL, 0444);
101 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
102 #endif
103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
104 module_param_array(beep_mode, int, NULL, 0444);
105 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
106 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
107 #endif
108
109 #ifdef CONFIG_SND_HDA_POWER_SAVE
110 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
111 module_param(power_save, int, 0644);
112 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
113 "(in second, 0 = disable).");
114
115 /* reset the HD-audio controller in power save mode.
116 * this may give more power-saving, but will take longer time to
117 * wake up.
118 */
119 static bool power_save_controller = 1;
120 module_param(power_save_controller, bool, 0644);
121 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
122 #endif
123
124 static bool align_buffer_size = 1;
125 module_param(align_buffer_size, bool, 0644);
126 MODULE_PARM_DESC(align_buffer_size,
127 "Force buffer and period sizes to be multiple of 128 bytes.");
128
129 #ifdef CONFIG_X86
130 static bool hda_snoop = true;
131 module_param_named(snoop, hda_snoop, bool, 0444);
132 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
133 #define azx_snoop(chip) (chip)->snoop
134 #else
135 #define hda_snoop true
136 #define azx_snoop(chip) true
137 #endif
138
139
140 MODULE_LICENSE("GPL");
141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
142 "{Intel, ICH6M},"
143 "{Intel, ICH7},"
144 "{Intel, ESB2},"
145 "{Intel, ICH8},"
146 "{Intel, ICH9},"
147 "{Intel, ICH10},"
148 "{Intel, PCH},"
149 "{Intel, CPT},"
150 "{Intel, PPT},"
151 "{Intel, PBG},"
152 "{Intel, SCH},"
153 "{ATI, SB450},"
154 "{ATI, SB600},"
155 "{ATI, RS600},"
156 "{ATI, RS690},"
157 "{ATI, RS780},"
158 "{ATI, R600},"
159 "{ATI, RV630},"
160 "{ATI, RV610},"
161 "{ATI, RV670},"
162 "{ATI, RV635},"
163 "{ATI, RV620},"
164 "{ATI, RV770},"
165 "{VIA, VT8251},"
166 "{VIA, VT8237A},"
167 "{SiS, SIS966},"
168 "{ULI, M5461}}");
169 MODULE_DESCRIPTION("Intel HDA driver");
170
171 #ifdef CONFIG_SND_VERBOSE_PRINTK
172 #define SFX /* nop */
173 #else
174 #define SFX "hda-intel: "
175 #endif
176
177 /*
178 * registers
179 */
180 #define ICH6_REG_GCAP 0x00
181 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
182 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
183 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
184 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
185 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
186 #define ICH6_REG_VMIN 0x02
187 #define ICH6_REG_VMAJ 0x03
188 #define ICH6_REG_OUTPAY 0x04
189 #define ICH6_REG_INPAY 0x06
190 #define ICH6_REG_GCTL 0x08
191 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
192 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
193 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
194 #define ICH6_REG_WAKEEN 0x0c
195 #define ICH6_REG_STATESTS 0x0e
196 #define ICH6_REG_GSTS 0x10
197 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
198 #define ICH6_REG_INTCTL 0x20
199 #define ICH6_REG_INTSTS 0x24
200 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
201 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
202 #define ICH6_REG_SSYNC 0x38
203 #define ICH6_REG_CORBLBASE 0x40
204 #define ICH6_REG_CORBUBASE 0x44
205 #define ICH6_REG_CORBWP 0x48
206 #define ICH6_REG_CORBRP 0x4a
207 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
208 #define ICH6_REG_CORBCTL 0x4c
209 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
210 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
211 #define ICH6_REG_CORBSTS 0x4d
212 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
213 #define ICH6_REG_CORBSIZE 0x4e
214
215 #define ICH6_REG_RIRBLBASE 0x50
216 #define ICH6_REG_RIRBUBASE 0x54
217 #define ICH6_REG_RIRBWP 0x58
218 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
219 #define ICH6_REG_RINTCNT 0x5a
220 #define ICH6_REG_RIRBCTL 0x5c
221 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
222 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
223 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
224 #define ICH6_REG_RIRBSTS 0x5d
225 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
226 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
227 #define ICH6_REG_RIRBSIZE 0x5e
228
229 #define ICH6_REG_IC 0x60
230 #define ICH6_REG_IR 0x64
231 #define ICH6_REG_IRS 0x68
232 #define ICH6_IRS_VALID (1<<1)
233 #define ICH6_IRS_BUSY (1<<0)
234
235 #define ICH6_REG_DPLBASE 0x70
236 #define ICH6_REG_DPUBASE 0x74
237 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
238
239 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
240 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
241
242 /* stream register offsets from stream base */
243 #define ICH6_REG_SD_CTL 0x00
244 #define ICH6_REG_SD_STS 0x03
245 #define ICH6_REG_SD_LPIB 0x04
246 #define ICH6_REG_SD_CBL 0x08
247 #define ICH6_REG_SD_LVI 0x0c
248 #define ICH6_REG_SD_FIFOW 0x0e
249 #define ICH6_REG_SD_FIFOSIZE 0x10
250 #define ICH6_REG_SD_FORMAT 0x12
251 #define ICH6_REG_SD_BDLPL 0x18
252 #define ICH6_REG_SD_BDLPU 0x1c
253
254 /* PCI space */
255 #define ICH6_PCIREG_TCSEL 0x44
256
257 /*
258 * other constants
259 */
260
261 /* max number of SDs */
262 /* ICH, ATI and VIA have 4 playback and 4 capture */
263 #define ICH6_NUM_CAPTURE 4
264 #define ICH6_NUM_PLAYBACK 4
265
266 /* ULI has 6 playback and 5 capture */
267 #define ULI_NUM_CAPTURE 5
268 #define ULI_NUM_PLAYBACK 6
269
270 /* ATI HDMI has 1 playback and 0 capture */
271 #define ATIHDMI_NUM_CAPTURE 0
272 #define ATIHDMI_NUM_PLAYBACK 1
273
274 /* TERA has 4 playback and 3 capture */
275 #define TERA_NUM_CAPTURE 3
276 #define TERA_NUM_PLAYBACK 4
277
278 /* this number is statically defined for simplicity */
279 #define MAX_AZX_DEV 16
280
281 /* max number of fragments - we may use more if allocating more pages for BDL */
282 #define BDL_SIZE 4096
283 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
284 #define AZX_MAX_FRAG 32
285 /* max buffer size - no h/w limit, you can increase as you like */
286 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
287
288 /* RIRB int mask: overrun[2], response[0] */
289 #define RIRB_INT_RESPONSE 0x01
290 #define RIRB_INT_OVERRUN 0x04
291 #define RIRB_INT_MASK 0x05
292
293 /* STATESTS int mask: S3,SD2,SD1,SD0 */
294 #define AZX_MAX_CODECS 8
295 #define AZX_DEFAULT_CODECS 4
296 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
297
298 /* SD_CTL bits */
299 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
300 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
301 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
302 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
303 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
304 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
305 #define SD_CTL_STREAM_TAG_SHIFT 20
306
307 /* SD_CTL and SD_STS */
308 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
309 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
310 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
311 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
312 SD_INT_COMPLETE)
313
314 /* SD_STS */
315 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
316
317 /* INTCTL and INTSTS */
318 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
319 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
320 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
321
322 /* below are so far hardcoded - should read registers in future */
323 #define ICH6_MAX_CORB_ENTRIES 256
324 #define ICH6_MAX_RIRB_ENTRIES 256
325
326 /* position fix mode */
327 enum {
328 POS_FIX_AUTO,
329 POS_FIX_LPIB,
330 POS_FIX_POSBUF,
331 POS_FIX_VIACOMBO,
332 };
333
334 /* Defines for ATI HD Audio support in SB450 south bridge */
335 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
336 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
337
338 /* Defines for Nvidia HDA support */
339 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
340 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
341 #define NVIDIA_HDA_ISTRM_COH 0x4d
342 #define NVIDIA_HDA_OSTRM_COH 0x4c
343 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
344
345 /* Defines for Intel SCH HDA snoop control */
346 #define INTEL_SCH_HDA_DEVC 0x78
347 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
348
349 /* Define IN stream 0 FIFO size offset in VIA controller */
350 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
351 /* Define VIA HD Audio Device ID*/
352 #define VIA_HDAC_DEVICE_ID 0x3288
353
354 /* HD Audio class code */
355 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
356
357 /*
358 */
359
360 struct azx_dev {
361 struct snd_dma_buffer bdl; /* BDL buffer */
362 u32 *posbuf; /* position buffer pointer */
363
364 unsigned int bufsize; /* size of the play buffer in bytes */
365 unsigned int period_bytes; /* size of the period in bytes */
366 unsigned int frags; /* number for period in the play buffer */
367 unsigned int fifo_size; /* FIFO size */
368 unsigned long start_wallclk; /* start + minimum wallclk */
369 unsigned long period_wallclk; /* wallclk for period */
370
371 void __iomem *sd_addr; /* stream descriptor pointer */
372
373 u32 sd_int_sta_mask; /* stream int status mask */
374
375 /* pcm support */
376 struct snd_pcm_substream *substream; /* assigned substream,
377 * set in PCM open
378 */
379 unsigned int format_val; /* format value to be set in the
380 * controller and the codec
381 */
382 unsigned char stream_tag; /* assigned stream */
383 unsigned char index; /* stream index */
384 int assigned_key; /* last device# key assigned to */
385
386 unsigned int opened :1;
387 unsigned int running :1;
388 unsigned int irq_pending :1;
389 /*
390 * For VIA:
391 * A flag to ensure DMA position is 0
392 * when link position is not greater than FIFO size
393 */
394 unsigned int insufficient :1;
395 unsigned int wc_marked:1;
396 };
397
398 /* CORB/RIRB */
399 struct azx_rb {
400 u32 *buf; /* CORB/RIRB buffer
401 * Each CORB entry is 4byte, RIRB is 8byte
402 */
403 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
404 /* for RIRB */
405 unsigned short rp, wp; /* read/write pointers */
406 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
407 u32 res[AZX_MAX_CODECS]; /* last read value */
408 };
409
410 struct azx_pcm {
411 struct azx *chip;
412 struct snd_pcm *pcm;
413 struct hda_codec *codec;
414 struct hda_pcm_stream *hinfo[2];
415 struct list_head list;
416 };
417
418 struct azx {
419 struct snd_card *card;
420 struct pci_dev *pci;
421 int dev_index;
422
423 /* chip type specific */
424 int driver_type;
425 unsigned int driver_caps;
426 int playback_streams;
427 int playback_index_offset;
428 int capture_streams;
429 int capture_index_offset;
430 int num_streams;
431
432 /* pci resources */
433 unsigned long addr;
434 void __iomem *remap_addr;
435 int irq;
436
437 /* locks */
438 spinlock_t reg_lock;
439 struct mutex open_mutex;
440
441 /* streams (x num_streams) */
442 struct azx_dev *azx_dev;
443
444 /* PCM */
445 struct list_head pcm_list; /* azx_pcm list */
446
447 /* HD codec */
448 unsigned short codec_mask;
449 int codec_probe_mask; /* copied from probe_mask option */
450 struct hda_bus *bus;
451 unsigned int beep_mode;
452
453 /* CORB/RIRB */
454 struct azx_rb corb;
455 struct azx_rb rirb;
456
457 /* CORB/RIRB and position buffers */
458 struct snd_dma_buffer rb;
459 struct snd_dma_buffer posbuf;
460
461 /* flags */
462 int position_fix[2]; /* for both playback/capture streams */
463 int poll_count;
464 unsigned int running :1;
465 unsigned int initialized :1;
466 unsigned int single_cmd :1;
467 unsigned int polling_mode :1;
468 unsigned int msi :1;
469 unsigned int irq_pending_warned :1;
470 unsigned int probing :1; /* codec probing phase */
471 unsigned int snoop:1;
472
473 /* for debugging */
474 unsigned int last_cmd[AZX_MAX_CODECS];
475
476 /* for pending irqs */
477 struct work_struct irq_pending_work;
478
479 /* reboot notifier (for mysterious hangup problem at power-down) */
480 struct notifier_block reboot_notifier;
481 };
482
483 /* driver types */
484 enum {
485 AZX_DRIVER_ICH,
486 AZX_DRIVER_PCH,
487 AZX_DRIVER_SCH,
488 AZX_DRIVER_ATI,
489 AZX_DRIVER_ATIHDMI,
490 AZX_DRIVER_ATIHDMI_NS,
491 AZX_DRIVER_VIA,
492 AZX_DRIVER_SIS,
493 AZX_DRIVER_ULI,
494 AZX_DRIVER_NVIDIA,
495 AZX_DRIVER_TERA,
496 AZX_DRIVER_CTX,
497 AZX_DRIVER_GENERIC,
498 AZX_NUM_DRIVERS, /* keep this as last entry */
499 };
500
501 /* driver quirks (capabilities) */
502 /* bits 0-7 are used for indicating driver type */
503 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
504 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
505 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
506 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
507 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
508 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
509 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
510 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
511 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
512 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
513 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
514 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
515 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
516 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
517
518 /* quirks for ATI SB / AMD Hudson */
519 #define AZX_DCAPS_PRESET_ATI_SB \
520 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
521 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
522
523 /* quirks for ATI/AMD HDMI */
524 #define AZX_DCAPS_PRESET_ATI_HDMI \
525 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
526
527 /* quirks for Nvidia */
528 #define AZX_DCAPS_PRESET_NVIDIA \
529 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
530
531 static char *driver_short_names[] __devinitdata = {
532 [AZX_DRIVER_ICH] = "HDA Intel",
533 [AZX_DRIVER_PCH] = "HDA Intel PCH",
534 [AZX_DRIVER_SCH] = "HDA Intel MID",
535 [AZX_DRIVER_ATI] = "HDA ATI SB",
536 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
537 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
538 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
539 [AZX_DRIVER_SIS] = "HDA SIS966",
540 [AZX_DRIVER_ULI] = "HDA ULI M5461",
541 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
542 [AZX_DRIVER_TERA] = "HDA Teradici",
543 [AZX_DRIVER_CTX] = "HDA Creative",
544 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
545 };
546
547 /*
548 * macros for easy use
549 */
550 #define azx_writel(chip,reg,value) \
551 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
552 #define azx_readl(chip,reg) \
553 readl((chip)->remap_addr + ICH6_REG_##reg)
554 #define azx_writew(chip,reg,value) \
555 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
556 #define azx_readw(chip,reg) \
557 readw((chip)->remap_addr + ICH6_REG_##reg)
558 #define azx_writeb(chip,reg,value) \
559 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
560 #define azx_readb(chip,reg) \
561 readb((chip)->remap_addr + ICH6_REG_##reg)
562
563 #define azx_sd_writel(dev,reg,value) \
564 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
565 #define azx_sd_readl(dev,reg) \
566 readl((dev)->sd_addr + ICH6_REG_##reg)
567 #define azx_sd_writew(dev,reg,value) \
568 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
569 #define azx_sd_readw(dev,reg) \
570 readw((dev)->sd_addr + ICH6_REG_##reg)
571 #define azx_sd_writeb(dev,reg,value) \
572 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
573 #define azx_sd_readb(dev,reg) \
574 readb((dev)->sd_addr + ICH6_REG_##reg)
575
576 /* for pcm support */
577 #define get_azx_dev(substream) (substream->runtime->private_data)
578
579 #ifdef CONFIG_X86
580 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
581 {
582 if (azx_snoop(chip))
583 return;
584 if (addr && size) {
585 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
586 if (on)
587 set_memory_wc((unsigned long)addr, pages);
588 else
589 set_memory_wb((unsigned long)addr, pages);
590 }
591 }
592
593 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
594 bool on)
595 {
596 __mark_pages_wc(chip, buf->area, buf->bytes, on);
597 }
598 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
599 struct snd_pcm_runtime *runtime, bool on)
600 {
601 if (azx_dev->wc_marked != on) {
602 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
603 azx_dev->wc_marked = on;
604 }
605 }
606 #else
607 /* NOP for other archs */
608 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
609 bool on)
610 {
611 }
612 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
613 struct snd_pcm_runtime *runtime, bool on)
614 {
615 }
616 #endif
617
618 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
619 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
620 /*
621 * Interface for HD codec
622 */
623
624 /*
625 * CORB / RIRB interface
626 */
627 static int azx_alloc_cmd_io(struct azx *chip)
628 {
629 int err;
630
631 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
632 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
633 snd_dma_pci_data(chip->pci),
634 PAGE_SIZE, &chip->rb);
635 if (err < 0) {
636 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
637 return err;
638 }
639 mark_pages_wc(chip, &chip->rb, true);
640 return 0;
641 }
642
643 static void azx_init_cmd_io(struct azx *chip)
644 {
645 spin_lock_irq(&chip->reg_lock);
646 /* CORB set up */
647 chip->corb.addr = chip->rb.addr;
648 chip->corb.buf = (u32 *)chip->rb.area;
649 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
650 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
651
652 /* set the corb size to 256 entries (ULI requires explicitly) */
653 azx_writeb(chip, CORBSIZE, 0x02);
654 /* set the corb write pointer to 0 */
655 azx_writew(chip, CORBWP, 0);
656 /* reset the corb hw read pointer */
657 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
658 /* enable corb dma */
659 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
660
661 /* RIRB set up */
662 chip->rirb.addr = chip->rb.addr + 2048;
663 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
664 chip->rirb.wp = chip->rirb.rp = 0;
665 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
666 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
667 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
668
669 /* set the rirb size to 256 entries (ULI requires explicitly) */
670 azx_writeb(chip, RIRBSIZE, 0x02);
671 /* reset the rirb hw write pointer */
672 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
673 /* set N=1, get RIRB response interrupt for new entry */
674 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
675 azx_writew(chip, RINTCNT, 0xc0);
676 else
677 azx_writew(chip, RINTCNT, 1);
678 /* enable rirb dma and response irq */
679 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
680 spin_unlock_irq(&chip->reg_lock);
681 }
682
683 static void azx_free_cmd_io(struct azx *chip)
684 {
685 spin_lock_irq(&chip->reg_lock);
686 /* disable ringbuffer DMAs */
687 azx_writeb(chip, RIRBCTL, 0);
688 azx_writeb(chip, CORBCTL, 0);
689 spin_unlock_irq(&chip->reg_lock);
690 }
691
692 static unsigned int azx_command_addr(u32 cmd)
693 {
694 unsigned int addr = cmd >> 28;
695
696 if (addr >= AZX_MAX_CODECS) {
697 snd_BUG();
698 addr = 0;
699 }
700
701 return addr;
702 }
703
704 static unsigned int azx_response_addr(u32 res)
705 {
706 unsigned int addr = res & 0xf;
707
708 if (addr >= AZX_MAX_CODECS) {
709 snd_BUG();
710 addr = 0;
711 }
712
713 return addr;
714 }
715
716 /* send a command */
717 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
718 {
719 struct azx *chip = bus->private_data;
720 unsigned int addr = azx_command_addr(val);
721 unsigned int wp;
722
723 spin_lock_irq(&chip->reg_lock);
724
725 /* add command to corb */
726 wp = azx_readb(chip, CORBWP);
727 wp++;
728 wp %= ICH6_MAX_CORB_ENTRIES;
729
730 chip->rirb.cmds[addr]++;
731 chip->corb.buf[wp] = cpu_to_le32(val);
732 azx_writel(chip, CORBWP, wp);
733
734 spin_unlock_irq(&chip->reg_lock);
735
736 return 0;
737 }
738
739 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
740
741 /* retrieve RIRB entry - called from interrupt handler */
742 static void azx_update_rirb(struct azx *chip)
743 {
744 unsigned int rp, wp;
745 unsigned int addr;
746 u32 res, res_ex;
747
748 wp = azx_readb(chip, RIRBWP);
749 if (wp == chip->rirb.wp)
750 return;
751 chip->rirb.wp = wp;
752
753 while (chip->rirb.rp != wp) {
754 chip->rirb.rp++;
755 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
756
757 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
758 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
759 res = le32_to_cpu(chip->rirb.buf[rp]);
760 addr = azx_response_addr(res_ex);
761 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
762 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
763 else if (chip->rirb.cmds[addr]) {
764 chip->rirb.res[addr] = res;
765 smp_wmb();
766 chip->rirb.cmds[addr]--;
767 } else
768 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
769 "last cmd=%#08x\n",
770 res, res_ex,
771 chip->last_cmd[addr]);
772 }
773 }
774
775 /* receive a response */
776 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
777 unsigned int addr)
778 {
779 struct azx *chip = bus->private_data;
780 unsigned long timeout;
781 int do_poll = 0;
782
783 again:
784 timeout = jiffies + msecs_to_jiffies(1000);
785 for (;;) {
786 if (chip->polling_mode || do_poll) {
787 spin_lock_irq(&chip->reg_lock);
788 azx_update_rirb(chip);
789 spin_unlock_irq(&chip->reg_lock);
790 }
791 if (!chip->rirb.cmds[addr]) {
792 smp_rmb();
793 bus->rirb_error = 0;
794
795 if (!do_poll)
796 chip->poll_count = 0;
797 return chip->rirb.res[addr]; /* the last value */
798 }
799 if (time_after(jiffies, timeout))
800 break;
801 if (bus->needs_damn_long_delay)
802 msleep(2); /* temporary workaround */
803 else {
804 udelay(10);
805 cond_resched();
806 }
807 }
808
809 if (!chip->polling_mode && chip->poll_count < 2) {
810 snd_printdd(SFX "azx_get_response timeout, "
811 "polling the codec once: last cmd=0x%08x\n",
812 chip->last_cmd[addr]);
813 do_poll = 1;
814 chip->poll_count++;
815 goto again;
816 }
817
818
819 if (!chip->polling_mode) {
820 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
821 "switching to polling mode: last cmd=0x%08x\n",
822 chip->last_cmd[addr]);
823 chip->polling_mode = 1;
824 goto again;
825 }
826
827 if (chip->msi) {
828 snd_printk(KERN_WARNING SFX "No response from codec, "
829 "disabling MSI: last cmd=0x%08x\n",
830 chip->last_cmd[addr]);
831 free_irq(chip->irq, chip);
832 chip->irq = -1;
833 pci_disable_msi(chip->pci);
834 chip->msi = 0;
835 if (azx_acquire_irq(chip, 1) < 0) {
836 bus->rirb_error = 1;
837 return -1;
838 }
839 goto again;
840 }
841
842 if (chip->probing) {
843 /* If this critical timeout happens during the codec probing
844 * phase, this is likely an access to a non-existing codec
845 * slot. Better to return an error and reset the system.
846 */
847 return -1;
848 }
849
850 /* a fatal communication error; need either to reset or to fallback
851 * to the single_cmd mode
852 */
853 bus->rirb_error = 1;
854 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
855 bus->response_reset = 1;
856 return -1; /* give a chance to retry */
857 }
858
859 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
860 "switching to single_cmd mode: last cmd=0x%08x\n",
861 chip->last_cmd[addr]);
862 chip->single_cmd = 1;
863 bus->response_reset = 0;
864 /* release CORB/RIRB */
865 azx_free_cmd_io(chip);
866 /* disable unsolicited responses */
867 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
868 return -1;
869 }
870
871 /*
872 * Use the single immediate command instead of CORB/RIRB for simplicity
873 *
874 * Note: according to Intel, this is not preferred use. The command was
875 * intended for the BIOS only, and may get confused with unsolicited
876 * responses. So, we shouldn't use it for normal operation from the
877 * driver.
878 * I left the codes, however, for debugging/testing purposes.
879 */
880
881 /* receive a response */
882 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
883 {
884 int timeout = 50;
885
886 while (timeout--) {
887 /* check IRV busy bit */
888 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
889 /* reuse rirb.res as the response return value */
890 chip->rirb.res[addr] = azx_readl(chip, IR);
891 return 0;
892 }
893 udelay(1);
894 }
895 if (printk_ratelimit())
896 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
897 azx_readw(chip, IRS));
898 chip->rirb.res[addr] = -1;
899 return -EIO;
900 }
901
902 /* send a command */
903 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
904 {
905 struct azx *chip = bus->private_data;
906 unsigned int addr = azx_command_addr(val);
907 int timeout = 50;
908
909 bus->rirb_error = 0;
910 while (timeout--) {
911 /* check ICB busy bit */
912 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
913 /* Clear IRV valid bit */
914 azx_writew(chip, IRS, azx_readw(chip, IRS) |
915 ICH6_IRS_VALID);
916 azx_writel(chip, IC, val);
917 azx_writew(chip, IRS, azx_readw(chip, IRS) |
918 ICH6_IRS_BUSY);
919 return azx_single_wait_for_response(chip, addr);
920 }
921 udelay(1);
922 }
923 if (printk_ratelimit())
924 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
925 azx_readw(chip, IRS), val);
926 return -EIO;
927 }
928
929 /* receive a response */
930 static unsigned int azx_single_get_response(struct hda_bus *bus,
931 unsigned int addr)
932 {
933 struct azx *chip = bus->private_data;
934 return chip->rirb.res[addr];
935 }
936
937 /*
938 * The below are the main callbacks from hda_codec.
939 *
940 * They are just the skeleton to call sub-callbacks according to the
941 * current setting of chip->single_cmd.
942 */
943
944 /* send a command */
945 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
946 {
947 struct azx *chip = bus->private_data;
948
949 chip->last_cmd[azx_command_addr(val)] = val;
950 if (chip->single_cmd)
951 return azx_single_send_cmd(bus, val);
952 else
953 return azx_corb_send_cmd(bus, val);
954 }
955
956 /* get a response */
957 static unsigned int azx_get_response(struct hda_bus *bus,
958 unsigned int addr)
959 {
960 struct azx *chip = bus->private_data;
961 if (chip->single_cmd)
962 return azx_single_get_response(bus, addr);
963 else
964 return azx_rirb_get_response(bus, addr);
965 }
966
967 #ifdef CONFIG_SND_HDA_POWER_SAVE
968 static void azx_power_notify(struct hda_bus *bus);
969 #endif
970
971 /* reset codec link */
972 static int azx_reset(struct azx *chip, int full_reset)
973 {
974 int count;
975
976 if (!full_reset)
977 goto __skip;
978
979 /* clear STATESTS */
980 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
981
982 /* reset controller */
983 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
984
985 count = 50;
986 while (azx_readb(chip, GCTL) && --count)
987 msleep(1);
988
989 /* delay for >= 100us for codec PLL to settle per spec
990 * Rev 0.9 section 5.5.1
991 */
992 msleep(1);
993
994 /* Bring controller out of reset */
995 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
996
997 count = 50;
998 while (!azx_readb(chip, GCTL) && --count)
999 msleep(1);
1000
1001 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1002 msleep(1);
1003
1004 __skip:
1005 /* check to see if controller is ready */
1006 if (!azx_readb(chip, GCTL)) {
1007 snd_printd(SFX "azx_reset: controller not ready!\n");
1008 return -EBUSY;
1009 }
1010
1011 /* Accept unsolicited responses */
1012 if (!chip->single_cmd)
1013 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1014 ICH6_GCTL_UNSOL);
1015
1016 /* detect codecs */
1017 if (!chip->codec_mask) {
1018 chip->codec_mask = azx_readw(chip, STATESTS);
1019 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1020 }
1021
1022 return 0;
1023 }
1024
1025
1026 /*
1027 * Lowlevel interface
1028 */
1029
1030 /* enable interrupts */
1031 static void azx_int_enable(struct azx *chip)
1032 {
1033 /* enable controller CIE and GIE */
1034 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1035 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1036 }
1037
1038 /* disable interrupts */
1039 static void azx_int_disable(struct azx *chip)
1040 {
1041 int i;
1042
1043 /* disable interrupts in stream descriptor */
1044 for (i = 0; i < chip->num_streams; i++) {
1045 struct azx_dev *azx_dev = &chip->azx_dev[i];
1046 azx_sd_writeb(azx_dev, SD_CTL,
1047 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1048 }
1049
1050 /* disable SIE for all streams */
1051 azx_writeb(chip, INTCTL, 0);
1052
1053 /* disable controller CIE and GIE */
1054 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1055 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1056 }
1057
1058 /* clear interrupts */
1059 static void azx_int_clear(struct azx *chip)
1060 {
1061 int i;
1062
1063 /* clear stream status */
1064 for (i = 0; i < chip->num_streams; i++) {
1065 struct azx_dev *azx_dev = &chip->azx_dev[i];
1066 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1067 }
1068
1069 /* clear STATESTS */
1070 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1071
1072 /* clear rirb status */
1073 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1074
1075 /* clear int status */
1076 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1077 }
1078
1079 /* start a stream */
1080 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1081 {
1082 /*
1083 * Before stream start, initialize parameter
1084 */
1085 azx_dev->insufficient = 1;
1086
1087 /* enable SIE */
1088 azx_writel(chip, INTCTL,
1089 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1090 /* set DMA start and interrupt mask */
1091 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1092 SD_CTL_DMA_START | SD_INT_MASK);
1093 }
1094
1095 /* stop DMA */
1096 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1097 {
1098 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1099 ~(SD_CTL_DMA_START | SD_INT_MASK));
1100 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1101 }
1102
1103 /* stop a stream */
1104 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1105 {
1106 azx_stream_clear(chip, azx_dev);
1107 /* disable SIE */
1108 azx_writel(chip, INTCTL,
1109 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1110 }
1111
1112
1113 /*
1114 * reset and start the controller registers
1115 */
1116 static void azx_init_chip(struct azx *chip, int full_reset)
1117 {
1118 if (chip->initialized)
1119 return;
1120
1121 /* reset controller */
1122 azx_reset(chip, full_reset);
1123
1124 /* initialize interrupts */
1125 azx_int_clear(chip);
1126 azx_int_enable(chip);
1127
1128 /* initialize the codec command I/O */
1129 if (!chip->single_cmd)
1130 azx_init_cmd_io(chip);
1131
1132 /* program the position buffer */
1133 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1134 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1135
1136 chip->initialized = 1;
1137 }
1138
1139 /*
1140 * initialize the PCI registers
1141 */
1142 /* update bits in a PCI register byte */
1143 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1144 unsigned char mask, unsigned char val)
1145 {
1146 unsigned char data;
1147
1148 pci_read_config_byte(pci, reg, &data);
1149 data &= ~mask;
1150 data |= (val & mask);
1151 pci_write_config_byte(pci, reg, data);
1152 }
1153
1154 static void azx_init_pci(struct azx *chip)
1155 {
1156 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1157 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1158 * Ensuring these bits are 0 clears playback static on some HD Audio
1159 * codecs.
1160 * The PCI register TCSEL is defined in the Intel manuals.
1161 */
1162 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1163 snd_printdd(SFX "Clearing TCSEL\n");
1164 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1165 }
1166
1167 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1168 * we need to enable snoop.
1169 */
1170 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1171 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1172 update_pci_byte(chip->pci,
1173 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1174 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1175 }
1176
1177 /* For NVIDIA HDA, enable snoop */
1178 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1179 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1180 update_pci_byte(chip->pci,
1181 NVIDIA_HDA_TRANSREG_ADDR,
1182 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1183 update_pci_byte(chip->pci,
1184 NVIDIA_HDA_ISTRM_COH,
1185 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1186 update_pci_byte(chip->pci,
1187 NVIDIA_HDA_OSTRM_COH,
1188 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1189 }
1190
1191 /* Enable SCH/PCH snoop if needed */
1192 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1193 unsigned short snoop;
1194 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1195 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1196 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1197 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1198 if (!azx_snoop(chip))
1199 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1200 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1201 pci_read_config_word(chip->pci,
1202 INTEL_SCH_HDA_DEVC, &snoop);
1203 }
1204 snd_printdd(SFX "SCH snoop: %s\n",
1205 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1206 ? "Disabled" : "Enabled");
1207 }
1208 }
1209
1210
1211 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1212
1213 /*
1214 * interrupt handler
1215 */
1216 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1217 {
1218 struct azx *chip = dev_id;
1219 struct azx_dev *azx_dev;
1220 u32 status;
1221 u8 sd_status;
1222 int i, ok;
1223
1224 spin_lock(&chip->reg_lock);
1225
1226 status = azx_readl(chip, INTSTS);
1227 if (status == 0) {
1228 spin_unlock(&chip->reg_lock);
1229 return IRQ_NONE;
1230 }
1231
1232 for (i = 0; i < chip->num_streams; i++) {
1233 azx_dev = &chip->azx_dev[i];
1234 if (status & azx_dev->sd_int_sta_mask) {
1235 sd_status = azx_sd_readb(azx_dev, SD_STS);
1236 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1237 if (!azx_dev->substream || !azx_dev->running ||
1238 !(sd_status & SD_INT_COMPLETE))
1239 continue;
1240 /* check whether this IRQ is really acceptable */
1241 ok = azx_position_ok(chip, azx_dev);
1242 if (ok == 1) {
1243 azx_dev->irq_pending = 0;
1244 spin_unlock(&chip->reg_lock);
1245 snd_pcm_period_elapsed(azx_dev->substream);
1246 spin_lock(&chip->reg_lock);
1247 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1248 /* bogus IRQ, process it later */
1249 azx_dev->irq_pending = 1;
1250 queue_work(chip->bus->workq,
1251 &chip->irq_pending_work);
1252 }
1253 }
1254 }
1255
1256 /* clear rirb int */
1257 status = azx_readb(chip, RIRBSTS);
1258 if (status & RIRB_INT_MASK) {
1259 if (status & RIRB_INT_RESPONSE) {
1260 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1261 udelay(80);
1262 azx_update_rirb(chip);
1263 }
1264 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1265 }
1266
1267 #if 0
1268 /* clear state status int */
1269 if (azx_readb(chip, STATESTS) & 0x04)
1270 azx_writeb(chip, STATESTS, 0x04);
1271 #endif
1272 spin_unlock(&chip->reg_lock);
1273
1274 return IRQ_HANDLED;
1275 }
1276
1277
1278 /*
1279 * set up a BDL entry
1280 */
1281 static int setup_bdle(struct snd_pcm_substream *substream,
1282 struct azx_dev *azx_dev, u32 **bdlp,
1283 int ofs, int size, int with_ioc)
1284 {
1285 u32 *bdl = *bdlp;
1286
1287 while (size > 0) {
1288 dma_addr_t addr;
1289 int chunk;
1290
1291 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1292 return -EINVAL;
1293
1294 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1295 /* program the address field of the BDL entry */
1296 bdl[0] = cpu_to_le32((u32)addr);
1297 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1298 /* program the size field of the BDL entry */
1299 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1300 bdl[2] = cpu_to_le32(chunk);
1301 /* program the IOC to enable interrupt
1302 * only when the whole fragment is processed
1303 */
1304 size -= chunk;
1305 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1306 bdl += 4;
1307 azx_dev->frags++;
1308 ofs += chunk;
1309 }
1310 *bdlp = bdl;
1311 return ofs;
1312 }
1313
1314 /*
1315 * set up BDL entries
1316 */
1317 static int azx_setup_periods(struct azx *chip,
1318 struct snd_pcm_substream *substream,
1319 struct azx_dev *azx_dev)
1320 {
1321 u32 *bdl;
1322 int i, ofs, periods, period_bytes;
1323 int pos_adj;
1324
1325 /* reset BDL address */
1326 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1327 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1328
1329 period_bytes = azx_dev->period_bytes;
1330 periods = azx_dev->bufsize / period_bytes;
1331
1332 /* program the initial BDL entries */
1333 bdl = (u32 *)azx_dev->bdl.area;
1334 ofs = 0;
1335 azx_dev->frags = 0;
1336 pos_adj = bdl_pos_adj[chip->dev_index];
1337 if (pos_adj > 0) {
1338 struct snd_pcm_runtime *runtime = substream->runtime;
1339 int pos_align = pos_adj;
1340 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1341 if (!pos_adj)
1342 pos_adj = pos_align;
1343 else
1344 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1345 pos_align;
1346 pos_adj = frames_to_bytes(runtime, pos_adj);
1347 if (pos_adj >= period_bytes) {
1348 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1349 bdl_pos_adj[chip->dev_index]);
1350 pos_adj = 0;
1351 } else {
1352 ofs = setup_bdle(substream, azx_dev,
1353 &bdl, ofs, pos_adj,
1354 !substream->runtime->no_period_wakeup);
1355 if (ofs < 0)
1356 goto error;
1357 }
1358 } else
1359 pos_adj = 0;
1360 for (i = 0; i < periods; i++) {
1361 if (i == periods - 1 && pos_adj)
1362 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1363 period_bytes - pos_adj, 0);
1364 else
1365 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1366 period_bytes,
1367 !substream->runtime->no_period_wakeup);
1368 if (ofs < 0)
1369 goto error;
1370 }
1371 return 0;
1372
1373 error:
1374 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1375 azx_dev->bufsize, period_bytes);
1376 return -EINVAL;
1377 }
1378
1379 /* reset stream */
1380 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1381 {
1382 unsigned char val;
1383 int timeout;
1384
1385 azx_stream_clear(chip, azx_dev);
1386
1387 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1388 SD_CTL_STREAM_RESET);
1389 udelay(3);
1390 timeout = 300;
1391 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1392 --timeout)
1393 ;
1394 val &= ~SD_CTL_STREAM_RESET;
1395 azx_sd_writeb(azx_dev, SD_CTL, val);
1396 udelay(3);
1397
1398 timeout = 300;
1399 /* waiting for hardware to report that the stream is out of reset */
1400 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1401 --timeout)
1402 ;
1403
1404 /* reset first position - may not be synced with hw at this time */
1405 *azx_dev->posbuf = 0;
1406 }
1407
1408 /*
1409 * set up the SD for streaming
1410 */
1411 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1412 {
1413 unsigned int val;
1414 /* make sure the run bit is zero for SD */
1415 azx_stream_clear(chip, azx_dev);
1416 /* program the stream_tag */
1417 val = azx_sd_readl(azx_dev, SD_CTL);
1418 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1419 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1420 if (!azx_snoop(chip))
1421 val |= SD_CTL_TRAFFIC_PRIO;
1422 azx_sd_writel(azx_dev, SD_CTL, val);
1423
1424 /* program the length of samples in cyclic buffer */
1425 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1426
1427 /* program the stream format */
1428 /* this value needs to be the same as the one programmed */
1429 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1430
1431 /* program the stream LVI (last valid index) of the BDL */
1432 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1433
1434 /* program the BDL address */
1435 /* lower BDL address */
1436 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1437 /* upper BDL address */
1438 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1439
1440 /* enable the position buffer */
1441 if (chip->position_fix[0] != POS_FIX_LPIB ||
1442 chip->position_fix[1] != POS_FIX_LPIB) {
1443 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1444 azx_writel(chip, DPLBASE,
1445 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1446 }
1447
1448 /* set the interrupt enable bits in the descriptor control register */
1449 azx_sd_writel(azx_dev, SD_CTL,
1450 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1451
1452 return 0;
1453 }
1454
1455 /*
1456 * Probe the given codec address
1457 */
1458 static int probe_codec(struct azx *chip, int addr)
1459 {
1460 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1461 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1462 unsigned int res;
1463
1464 mutex_lock(&chip->bus->cmd_mutex);
1465 chip->probing = 1;
1466 azx_send_cmd(chip->bus, cmd);
1467 res = azx_get_response(chip->bus, addr);
1468 chip->probing = 0;
1469 mutex_unlock(&chip->bus->cmd_mutex);
1470 if (res == -1)
1471 return -EIO;
1472 snd_printdd(SFX "codec #%d probed OK\n", addr);
1473 return 0;
1474 }
1475
1476 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1477 struct hda_pcm *cpcm);
1478 static void azx_stop_chip(struct azx *chip);
1479
1480 static void azx_bus_reset(struct hda_bus *bus)
1481 {
1482 struct azx *chip = bus->private_data;
1483
1484 bus->in_reset = 1;
1485 azx_stop_chip(chip);
1486 azx_init_chip(chip, 1);
1487 #ifdef CONFIG_PM
1488 if (chip->initialized) {
1489 struct azx_pcm *p;
1490 list_for_each_entry(p, &chip->pcm_list, list)
1491 snd_pcm_suspend_all(p->pcm);
1492 snd_hda_suspend(chip->bus);
1493 snd_hda_resume(chip->bus);
1494 }
1495 #endif
1496 bus->in_reset = 0;
1497 }
1498
1499 /*
1500 * Codec initialization
1501 */
1502
1503 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1504 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1505 [AZX_DRIVER_NVIDIA] = 8,
1506 [AZX_DRIVER_TERA] = 1,
1507 };
1508
1509 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1510 {
1511 struct hda_bus_template bus_temp;
1512 int c, codecs, err;
1513 int max_slots;
1514
1515 memset(&bus_temp, 0, sizeof(bus_temp));
1516 bus_temp.private_data = chip;
1517 bus_temp.modelname = model;
1518 bus_temp.pci = chip->pci;
1519 bus_temp.ops.command = azx_send_cmd;
1520 bus_temp.ops.get_response = azx_get_response;
1521 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1522 bus_temp.ops.bus_reset = azx_bus_reset;
1523 #ifdef CONFIG_SND_HDA_POWER_SAVE
1524 bus_temp.power_save = &power_save;
1525 bus_temp.ops.pm_notify = azx_power_notify;
1526 #endif
1527
1528 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1529 if (err < 0)
1530 return err;
1531
1532 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1533 snd_printd(SFX "Enable delay in RIRB handling\n");
1534 chip->bus->needs_damn_long_delay = 1;
1535 }
1536
1537 codecs = 0;
1538 max_slots = azx_max_codecs[chip->driver_type];
1539 if (!max_slots)
1540 max_slots = AZX_DEFAULT_CODECS;
1541
1542 /* First try to probe all given codec slots */
1543 for (c = 0; c < max_slots; c++) {
1544 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1545 if (probe_codec(chip, c) < 0) {
1546 /* Some BIOSen give you wrong codec addresses
1547 * that don't exist
1548 */
1549 snd_printk(KERN_WARNING SFX
1550 "Codec #%d probe error; "
1551 "disabling it...\n", c);
1552 chip->codec_mask &= ~(1 << c);
1553 /* More badly, accessing to a non-existing
1554 * codec often screws up the controller chip,
1555 * and disturbs the further communications.
1556 * Thus if an error occurs during probing,
1557 * better to reset the controller chip to
1558 * get back to the sanity state.
1559 */
1560 azx_stop_chip(chip);
1561 azx_init_chip(chip, 1);
1562 }
1563 }
1564 }
1565
1566 /* AMD chipsets often cause the communication stalls upon certain
1567 * sequence like the pin-detection. It seems that forcing the synced
1568 * access works around the stall. Grrr...
1569 */
1570 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1571 snd_printd(SFX "Enable sync_write for stable communication\n");
1572 chip->bus->sync_write = 1;
1573 chip->bus->allow_bus_reset = 1;
1574 }
1575
1576 /* Then create codec instances */
1577 for (c = 0; c < max_slots; c++) {
1578 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1579 struct hda_codec *codec;
1580 err = snd_hda_codec_new(chip->bus, c, &codec);
1581 if (err < 0)
1582 continue;
1583 codec->beep_mode = chip->beep_mode;
1584 codecs++;
1585 }
1586 }
1587 if (!codecs) {
1588 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1589 return -ENXIO;
1590 }
1591 return 0;
1592 }
1593
1594 /* configure each codec instance */
1595 static int __devinit azx_codec_configure(struct azx *chip)
1596 {
1597 struct hda_codec *codec;
1598 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1599 snd_hda_codec_configure(codec);
1600 }
1601 return 0;
1602 }
1603
1604
1605 /*
1606 * PCM support
1607 */
1608
1609 /* assign a stream for the PCM */
1610 static inline struct azx_dev *
1611 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1612 {
1613 int dev, i, nums;
1614 struct azx_dev *res = NULL;
1615 /* make a non-zero unique key for the substream */
1616 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1617 (substream->stream + 1);
1618
1619 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1620 dev = chip->playback_index_offset;
1621 nums = chip->playback_streams;
1622 } else {
1623 dev = chip->capture_index_offset;
1624 nums = chip->capture_streams;
1625 }
1626 for (i = 0; i < nums; i++, dev++)
1627 if (!chip->azx_dev[dev].opened) {
1628 res = &chip->azx_dev[dev];
1629 if (res->assigned_key == key)
1630 break;
1631 }
1632 if (res) {
1633 res->opened = 1;
1634 res->assigned_key = key;
1635 }
1636 return res;
1637 }
1638
1639 /* release the assigned stream */
1640 static inline void azx_release_device(struct azx_dev *azx_dev)
1641 {
1642 azx_dev->opened = 0;
1643 }
1644
1645 static struct snd_pcm_hardware azx_pcm_hw = {
1646 .info = (SNDRV_PCM_INFO_MMAP |
1647 SNDRV_PCM_INFO_INTERLEAVED |
1648 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1649 SNDRV_PCM_INFO_MMAP_VALID |
1650 /* No full-resume yet implemented */
1651 /* SNDRV_PCM_INFO_RESUME |*/
1652 SNDRV_PCM_INFO_PAUSE |
1653 SNDRV_PCM_INFO_SYNC_START |
1654 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1655 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1656 .rates = SNDRV_PCM_RATE_48000,
1657 .rate_min = 48000,
1658 .rate_max = 48000,
1659 .channels_min = 2,
1660 .channels_max = 2,
1661 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1662 .period_bytes_min = 128,
1663 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1664 .periods_min = 2,
1665 .periods_max = AZX_MAX_FRAG,
1666 .fifo_size = 0,
1667 };
1668
1669 static int azx_pcm_open(struct snd_pcm_substream *substream)
1670 {
1671 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1672 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1673 struct azx *chip = apcm->chip;
1674 struct azx_dev *azx_dev;
1675 struct snd_pcm_runtime *runtime = substream->runtime;
1676 unsigned long flags;
1677 int err;
1678 int buff_step;
1679
1680 mutex_lock(&chip->open_mutex);
1681 azx_dev = azx_assign_device(chip, substream);
1682 if (azx_dev == NULL) {
1683 mutex_unlock(&chip->open_mutex);
1684 return -EBUSY;
1685 }
1686 runtime->hw = azx_pcm_hw;
1687 runtime->hw.channels_min = hinfo->channels_min;
1688 runtime->hw.channels_max = hinfo->channels_max;
1689 runtime->hw.formats = hinfo->formats;
1690 runtime->hw.rates = hinfo->rates;
1691 snd_pcm_limit_hw_rates(runtime);
1692 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1693 if (align_buffer_size)
1694 /* constrain buffer sizes to be multiple of 128
1695 bytes. This is more efficient in terms of memory
1696 access but isn't required by the HDA spec and
1697 prevents users from specifying exact period/buffer
1698 sizes. For example for 44.1kHz, a period size set
1699 to 20ms will be rounded to 19.59ms. */
1700 buff_step = 128;
1701 else
1702 /* Don't enforce steps on buffer sizes, still need to
1703 be multiple of 4 bytes (HDA spec). Tested on Intel
1704 HDA controllers, may not work on all devices where
1705 option needs to be disabled */
1706 buff_step = 4;
1707
1708 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1709 buff_step);
1710 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1711 buff_step);
1712 snd_hda_power_up(apcm->codec);
1713 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1714 if (err < 0) {
1715 azx_release_device(azx_dev);
1716 snd_hda_power_down(apcm->codec);
1717 mutex_unlock(&chip->open_mutex);
1718 return err;
1719 }
1720 snd_pcm_limit_hw_rates(runtime);
1721 /* sanity check */
1722 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1723 snd_BUG_ON(!runtime->hw.channels_max) ||
1724 snd_BUG_ON(!runtime->hw.formats) ||
1725 snd_BUG_ON(!runtime->hw.rates)) {
1726 azx_release_device(azx_dev);
1727 hinfo->ops.close(hinfo, apcm->codec, substream);
1728 snd_hda_power_down(apcm->codec);
1729 mutex_unlock(&chip->open_mutex);
1730 return -EINVAL;
1731 }
1732 spin_lock_irqsave(&chip->reg_lock, flags);
1733 azx_dev->substream = substream;
1734 azx_dev->running = 0;
1735 spin_unlock_irqrestore(&chip->reg_lock, flags);
1736
1737 runtime->private_data = azx_dev;
1738 snd_pcm_set_sync(substream);
1739 mutex_unlock(&chip->open_mutex);
1740 return 0;
1741 }
1742
1743 static int azx_pcm_close(struct snd_pcm_substream *substream)
1744 {
1745 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1746 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1747 struct azx *chip = apcm->chip;
1748 struct azx_dev *azx_dev = get_azx_dev(substream);
1749 unsigned long flags;
1750
1751 mutex_lock(&chip->open_mutex);
1752 spin_lock_irqsave(&chip->reg_lock, flags);
1753 azx_dev->substream = NULL;
1754 azx_dev->running = 0;
1755 spin_unlock_irqrestore(&chip->reg_lock, flags);
1756 azx_release_device(azx_dev);
1757 hinfo->ops.close(hinfo, apcm->codec, substream);
1758 snd_hda_power_down(apcm->codec);
1759 mutex_unlock(&chip->open_mutex);
1760 return 0;
1761 }
1762
1763 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1764 struct snd_pcm_hw_params *hw_params)
1765 {
1766 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1767 struct azx *chip = apcm->chip;
1768 struct snd_pcm_runtime *runtime = substream->runtime;
1769 struct azx_dev *azx_dev = get_azx_dev(substream);
1770 int ret;
1771
1772 mark_runtime_wc(chip, azx_dev, runtime, false);
1773 azx_dev->bufsize = 0;
1774 azx_dev->period_bytes = 0;
1775 azx_dev->format_val = 0;
1776 ret = snd_pcm_lib_malloc_pages(substream,
1777 params_buffer_bytes(hw_params));
1778 if (ret < 0)
1779 return ret;
1780 mark_runtime_wc(chip, azx_dev, runtime, true);
1781 return ret;
1782 }
1783
1784 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1785 {
1786 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1787 struct azx_dev *azx_dev = get_azx_dev(substream);
1788 struct azx *chip = apcm->chip;
1789 struct snd_pcm_runtime *runtime = substream->runtime;
1790 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1791
1792 /* reset BDL address */
1793 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1794 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1795 azx_sd_writel(azx_dev, SD_CTL, 0);
1796 azx_dev->bufsize = 0;
1797 azx_dev->period_bytes = 0;
1798 azx_dev->format_val = 0;
1799
1800 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1801
1802 mark_runtime_wc(chip, azx_dev, runtime, false);
1803 return snd_pcm_lib_free_pages(substream);
1804 }
1805
1806 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1807 {
1808 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1809 struct azx *chip = apcm->chip;
1810 struct azx_dev *azx_dev = get_azx_dev(substream);
1811 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1812 struct snd_pcm_runtime *runtime = substream->runtime;
1813 unsigned int bufsize, period_bytes, format_val, stream_tag;
1814 int err;
1815 struct hda_spdif_out *spdif =
1816 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1817 unsigned short ctls = spdif ? spdif->ctls : 0;
1818
1819 azx_stream_reset(chip, azx_dev);
1820 format_val = snd_hda_calc_stream_format(runtime->rate,
1821 runtime->channels,
1822 runtime->format,
1823 hinfo->maxbps,
1824 ctls);
1825 if (!format_val) {
1826 snd_printk(KERN_ERR SFX
1827 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1828 runtime->rate, runtime->channels, runtime->format);
1829 return -EINVAL;
1830 }
1831
1832 bufsize = snd_pcm_lib_buffer_bytes(substream);
1833 period_bytes = snd_pcm_lib_period_bytes(substream);
1834
1835 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1836 bufsize, format_val);
1837
1838 if (bufsize != azx_dev->bufsize ||
1839 period_bytes != azx_dev->period_bytes ||
1840 format_val != azx_dev->format_val) {
1841 azx_dev->bufsize = bufsize;
1842 azx_dev->period_bytes = period_bytes;
1843 azx_dev->format_val = format_val;
1844 err = azx_setup_periods(chip, substream, azx_dev);
1845 if (err < 0)
1846 return err;
1847 }
1848
1849 /* wallclk has 24Mhz clock source */
1850 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1851 runtime->rate) * 1000);
1852 azx_setup_controller(chip, azx_dev);
1853 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1854 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1855 else
1856 azx_dev->fifo_size = 0;
1857
1858 stream_tag = azx_dev->stream_tag;
1859 /* CA-IBG chips need the playback stream starting from 1 */
1860 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1861 stream_tag > chip->capture_streams)
1862 stream_tag -= chip->capture_streams;
1863 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1864 azx_dev->format_val, substream);
1865 }
1866
1867 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1868 {
1869 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1870 struct azx *chip = apcm->chip;
1871 struct azx_dev *azx_dev;
1872 struct snd_pcm_substream *s;
1873 int rstart = 0, start, nsync = 0, sbits = 0;
1874 int nwait, timeout;
1875
1876 switch (cmd) {
1877 case SNDRV_PCM_TRIGGER_START:
1878 rstart = 1;
1879 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1880 case SNDRV_PCM_TRIGGER_RESUME:
1881 start = 1;
1882 break;
1883 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1884 case SNDRV_PCM_TRIGGER_SUSPEND:
1885 case SNDRV_PCM_TRIGGER_STOP:
1886 start = 0;
1887 break;
1888 default:
1889 return -EINVAL;
1890 }
1891
1892 snd_pcm_group_for_each_entry(s, substream) {
1893 if (s->pcm->card != substream->pcm->card)
1894 continue;
1895 azx_dev = get_azx_dev(s);
1896 sbits |= 1 << azx_dev->index;
1897 nsync++;
1898 snd_pcm_trigger_done(s, substream);
1899 }
1900
1901 spin_lock(&chip->reg_lock);
1902 if (nsync > 1) {
1903 /* first, set SYNC bits of corresponding streams */
1904 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1905 azx_writel(chip, OLD_SSYNC,
1906 azx_readl(chip, OLD_SSYNC) | sbits);
1907 else
1908 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1909 }
1910 snd_pcm_group_for_each_entry(s, substream) {
1911 if (s->pcm->card != substream->pcm->card)
1912 continue;
1913 azx_dev = get_azx_dev(s);
1914 if (start) {
1915 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1916 if (!rstart)
1917 azx_dev->start_wallclk -=
1918 azx_dev->period_wallclk;
1919 azx_stream_start(chip, azx_dev);
1920 } else {
1921 azx_stream_stop(chip, azx_dev);
1922 }
1923 azx_dev->running = start;
1924 }
1925 spin_unlock(&chip->reg_lock);
1926 if (start) {
1927 if (nsync == 1)
1928 return 0;
1929 /* wait until all FIFOs get ready */
1930 for (timeout = 5000; timeout; timeout--) {
1931 nwait = 0;
1932 snd_pcm_group_for_each_entry(s, substream) {
1933 if (s->pcm->card != substream->pcm->card)
1934 continue;
1935 azx_dev = get_azx_dev(s);
1936 if (!(azx_sd_readb(azx_dev, SD_STS) &
1937 SD_STS_FIFO_READY))
1938 nwait++;
1939 }
1940 if (!nwait)
1941 break;
1942 cpu_relax();
1943 }
1944 } else {
1945 /* wait until all RUN bits are cleared */
1946 for (timeout = 5000; timeout; timeout--) {
1947 nwait = 0;
1948 snd_pcm_group_for_each_entry(s, substream) {
1949 if (s->pcm->card != substream->pcm->card)
1950 continue;
1951 azx_dev = get_azx_dev(s);
1952 if (azx_sd_readb(azx_dev, SD_CTL) &
1953 SD_CTL_DMA_START)
1954 nwait++;
1955 }
1956 if (!nwait)
1957 break;
1958 cpu_relax();
1959 }
1960 }
1961 if (nsync > 1) {
1962 spin_lock(&chip->reg_lock);
1963 /* reset SYNC bits */
1964 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1965 azx_writel(chip, OLD_SSYNC,
1966 azx_readl(chip, OLD_SSYNC) & ~sbits);
1967 else
1968 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1969 spin_unlock(&chip->reg_lock);
1970 }
1971 return 0;
1972 }
1973
1974 /* get the current DMA position with correction on VIA chips */
1975 static unsigned int azx_via_get_position(struct azx *chip,
1976 struct azx_dev *azx_dev)
1977 {
1978 unsigned int link_pos, mini_pos, bound_pos;
1979 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1980 unsigned int fifo_size;
1981
1982 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1983 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1984 /* Playback, no problem using link position */
1985 return link_pos;
1986 }
1987
1988 /* Capture */
1989 /* For new chipset,
1990 * use mod to get the DMA position just like old chipset
1991 */
1992 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1993 mod_dma_pos %= azx_dev->period_bytes;
1994
1995 /* azx_dev->fifo_size can't get FIFO size of in stream.
1996 * Get from base address + offset.
1997 */
1998 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1999
2000 if (azx_dev->insufficient) {
2001 /* Link position never gather than FIFO size */
2002 if (link_pos <= fifo_size)
2003 return 0;
2004
2005 azx_dev->insufficient = 0;
2006 }
2007
2008 if (link_pos <= fifo_size)
2009 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2010 else
2011 mini_pos = link_pos - fifo_size;
2012
2013 /* Find nearest previous boudary */
2014 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2015 mod_link_pos = link_pos % azx_dev->period_bytes;
2016 if (mod_link_pos >= fifo_size)
2017 bound_pos = link_pos - mod_link_pos;
2018 else if (mod_dma_pos >= mod_mini_pos)
2019 bound_pos = mini_pos - mod_mini_pos;
2020 else {
2021 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2022 if (bound_pos >= azx_dev->bufsize)
2023 bound_pos = 0;
2024 }
2025
2026 /* Calculate real DMA position we want */
2027 return bound_pos + mod_dma_pos;
2028 }
2029
2030 static unsigned int azx_get_position(struct azx *chip,
2031 struct azx_dev *azx_dev,
2032 bool with_check)
2033 {
2034 unsigned int pos;
2035 int stream = azx_dev->substream->stream;
2036
2037 switch (chip->position_fix[stream]) {
2038 case POS_FIX_LPIB:
2039 /* read LPIB */
2040 pos = azx_sd_readl(azx_dev, SD_LPIB);
2041 break;
2042 case POS_FIX_VIACOMBO:
2043 pos = azx_via_get_position(chip, azx_dev);
2044 break;
2045 default:
2046 /* use the position buffer */
2047 pos = le32_to_cpu(*azx_dev->posbuf);
2048 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2049 if (!pos || pos == (u32)-1) {
2050 printk(KERN_WARNING
2051 "hda-intel: Invalid position buffer, "
2052 "using LPIB read method instead.\n");
2053 chip->position_fix[stream] = POS_FIX_LPIB;
2054 pos = azx_sd_readl(azx_dev, SD_LPIB);
2055 } else
2056 chip->position_fix[stream] = POS_FIX_POSBUF;
2057 }
2058 break;
2059 }
2060
2061 if (pos >= azx_dev->bufsize)
2062 pos = 0;
2063 return pos;
2064 }
2065
2066 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2067 {
2068 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2069 struct azx *chip = apcm->chip;
2070 struct azx_dev *azx_dev = get_azx_dev(substream);
2071 return bytes_to_frames(substream->runtime,
2072 azx_get_position(chip, azx_dev, false));
2073 }
2074
2075 /*
2076 * Check whether the current DMA position is acceptable for updating
2077 * periods. Returns non-zero if it's OK.
2078 *
2079 * Many HD-audio controllers appear pretty inaccurate about
2080 * the update-IRQ timing. The IRQ is issued before actually the
2081 * data is processed. So, we need to process it afterwords in a
2082 * workqueue.
2083 */
2084 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2085 {
2086 u32 wallclk;
2087 unsigned int pos;
2088 int stream;
2089
2090 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2091 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2092 return -1; /* bogus (too early) interrupt */
2093
2094 stream = azx_dev->substream->stream;
2095 pos = azx_get_position(chip, azx_dev, true);
2096
2097 if (WARN_ONCE(!azx_dev->period_bytes,
2098 "hda-intel: zero azx_dev->period_bytes"))
2099 return -1; /* this shouldn't happen! */
2100 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2101 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2102 /* NG - it's below the first next period boundary */
2103 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2104 azx_dev->start_wallclk += wallclk;
2105 return 1; /* OK, it's fine */
2106 }
2107
2108 /*
2109 * The work for pending PCM period updates.
2110 */
2111 static void azx_irq_pending_work(struct work_struct *work)
2112 {
2113 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2114 int i, pending, ok;
2115
2116 if (!chip->irq_pending_warned) {
2117 printk(KERN_WARNING
2118 "hda-intel: IRQ timing workaround is activated "
2119 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2120 chip->card->number);
2121 chip->irq_pending_warned = 1;
2122 }
2123
2124 for (;;) {
2125 pending = 0;
2126 spin_lock_irq(&chip->reg_lock);
2127 for (i = 0; i < chip->num_streams; i++) {
2128 struct azx_dev *azx_dev = &chip->azx_dev[i];
2129 if (!azx_dev->irq_pending ||
2130 !azx_dev->substream ||
2131 !azx_dev->running)
2132 continue;
2133 ok = azx_position_ok(chip, azx_dev);
2134 if (ok > 0) {
2135 azx_dev->irq_pending = 0;
2136 spin_unlock(&chip->reg_lock);
2137 snd_pcm_period_elapsed(azx_dev->substream);
2138 spin_lock(&chip->reg_lock);
2139 } else if (ok < 0) {
2140 pending = 0; /* too early */
2141 } else
2142 pending++;
2143 }
2144 spin_unlock_irq(&chip->reg_lock);
2145 if (!pending)
2146 return;
2147 msleep(1);
2148 }
2149 }
2150
2151 /* clear irq_pending flags and assure no on-going workq */
2152 static void azx_clear_irq_pending(struct azx *chip)
2153 {
2154 int i;
2155
2156 spin_lock_irq(&chip->reg_lock);
2157 for (i = 0; i < chip->num_streams; i++)
2158 chip->azx_dev[i].irq_pending = 0;
2159 spin_unlock_irq(&chip->reg_lock);
2160 }
2161
2162 #ifdef CONFIG_X86
2163 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2164 struct vm_area_struct *area)
2165 {
2166 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2167 struct azx *chip = apcm->chip;
2168 if (!azx_snoop(chip))
2169 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2170 return snd_pcm_lib_default_mmap(substream, area);
2171 }
2172 #else
2173 #define azx_pcm_mmap NULL
2174 #endif
2175
2176 static struct snd_pcm_ops azx_pcm_ops = {
2177 .open = azx_pcm_open,
2178 .close = azx_pcm_close,
2179 .ioctl = snd_pcm_lib_ioctl,
2180 .hw_params = azx_pcm_hw_params,
2181 .hw_free = azx_pcm_hw_free,
2182 .prepare = azx_pcm_prepare,
2183 .trigger = azx_pcm_trigger,
2184 .pointer = azx_pcm_pointer,
2185 .mmap = azx_pcm_mmap,
2186 .page = snd_pcm_sgbuf_ops_page,
2187 };
2188
2189 static void azx_pcm_free(struct snd_pcm *pcm)
2190 {
2191 struct azx_pcm *apcm = pcm->private_data;
2192 if (apcm) {
2193 list_del(&apcm->list);
2194 kfree(apcm);
2195 }
2196 }
2197
2198 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2199
2200 static int
2201 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2202 struct hda_pcm *cpcm)
2203 {
2204 struct azx *chip = bus->private_data;
2205 struct snd_pcm *pcm;
2206 struct azx_pcm *apcm;
2207 int pcm_dev = cpcm->device;
2208 unsigned int size;
2209 int s, err;
2210
2211 list_for_each_entry(apcm, &chip->pcm_list, list) {
2212 if (apcm->pcm->device == pcm_dev) {
2213 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2214 return -EBUSY;
2215 }
2216 }
2217 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2218 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2219 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2220 &pcm);
2221 if (err < 0)
2222 return err;
2223 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2224 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2225 if (apcm == NULL)
2226 return -ENOMEM;
2227 apcm->chip = chip;
2228 apcm->pcm = pcm;
2229 apcm->codec = codec;
2230 pcm->private_data = apcm;
2231 pcm->private_free = azx_pcm_free;
2232 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2233 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2234 list_add_tail(&apcm->list, &chip->pcm_list);
2235 cpcm->pcm = pcm;
2236 for (s = 0; s < 2; s++) {
2237 apcm->hinfo[s] = &cpcm->stream[s];
2238 if (cpcm->stream[s].substreams)
2239 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2240 }
2241 /* buffer pre-allocation */
2242 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2243 if (size > MAX_PREALLOC_SIZE)
2244 size = MAX_PREALLOC_SIZE;
2245 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2246 snd_dma_pci_data(chip->pci),
2247 size, MAX_PREALLOC_SIZE);
2248 return 0;
2249 }
2250
2251 /*
2252 * mixer creation - all stuff is implemented in hda module
2253 */
2254 static int __devinit azx_mixer_create(struct azx *chip)
2255 {
2256 return snd_hda_build_controls(chip->bus);
2257 }
2258
2259
2260 /*
2261 * initialize SD streams
2262 */
2263 static int __devinit azx_init_stream(struct azx *chip)
2264 {
2265 int i;
2266
2267 /* initialize each stream (aka device)
2268 * assign the starting bdl address to each stream (device)
2269 * and initialize
2270 */
2271 for (i = 0; i < chip->num_streams; i++) {
2272 struct azx_dev *azx_dev = &chip->azx_dev[i];
2273 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2274 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2275 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2276 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2277 azx_dev->sd_int_sta_mask = 1 << i;
2278 /* stream tag: must be non-zero and unique */
2279 azx_dev->index = i;
2280 azx_dev->stream_tag = i + 1;
2281 }
2282
2283 return 0;
2284 }
2285
2286 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2287 {
2288 if (request_irq(chip->pci->irq, azx_interrupt,
2289 chip->msi ? 0 : IRQF_SHARED,
2290 KBUILD_MODNAME, chip)) {
2291 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2292 "disabling device\n", chip->pci->irq);
2293 if (do_disconnect)
2294 snd_card_disconnect(chip->card);
2295 return -1;
2296 }
2297 chip->irq = chip->pci->irq;
2298 pci_intx(chip->pci, !chip->msi);
2299 return 0;
2300 }
2301
2302
2303 static void azx_stop_chip(struct azx *chip)
2304 {
2305 if (!chip->initialized)
2306 return;
2307
2308 /* disable interrupts */
2309 azx_int_disable(chip);
2310 azx_int_clear(chip);
2311
2312 /* disable CORB/RIRB */
2313 azx_free_cmd_io(chip);
2314
2315 /* disable position buffer */
2316 azx_writel(chip, DPLBASE, 0);
2317 azx_writel(chip, DPUBASE, 0);
2318
2319 chip->initialized = 0;
2320 }
2321
2322 #ifdef CONFIG_SND_HDA_POWER_SAVE
2323 /* power-up/down the controller */
2324 static void azx_power_notify(struct hda_bus *bus)
2325 {
2326 struct azx *chip = bus->private_data;
2327 struct hda_codec *c;
2328 int power_on = 0;
2329
2330 list_for_each_entry(c, &bus->codec_list, list) {
2331 if (c->power_on) {
2332 power_on = 1;
2333 break;
2334 }
2335 }
2336 if (power_on)
2337 azx_init_chip(chip, 1);
2338 else if (chip->running && power_save_controller &&
2339 !bus->power_keep_link_on)
2340 azx_stop_chip(chip);
2341 }
2342 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2343
2344 #ifdef CONFIG_PM
2345 /*
2346 * power management
2347 */
2348
2349 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2350 {
2351 struct hda_codec *codec;
2352
2353 list_for_each_entry(codec, &bus->codec_list, list) {
2354 if (snd_hda_codec_needs_resume(codec))
2355 return 1;
2356 }
2357 return 0;
2358 }
2359
2360 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2361 {
2362 struct snd_card *card = pci_get_drvdata(pci);
2363 struct azx *chip = card->private_data;
2364 struct azx_pcm *p;
2365
2366 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2367 azx_clear_irq_pending(chip);
2368 list_for_each_entry(p, &chip->pcm_list, list)
2369 snd_pcm_suspend_all(p->pcm);
2370 if (chip->initialized)
2371 snd_hda_suspend(chip->bus);
2372 azx_stop_chip(chip);
2373 if (chip->irq >= 0) {
2374 free_irq(chip->irq, chip);
2375 chip->irq = -1;
2376 }
2377 if (chip->msi)
2378 pci_disable_msi(chip->pci);
2379 pci_disable_device(pci);
2380 pci_save_state(pci);
2381 pci_set_power_state(pci, pci_choose_state(pci, state));
2382 return 0;
2383 }
2384
2385 static int azx_resume(struct pci_dev *pci)
2386 {
2387 struct snd_card *card = pci_get_drvdata(pci);
2388 struct azx *chip = card->private_data;
2389
2390 pci_set_power_state(pci, PCI_D0);
2391 pci_restore_state(pci);
2392 if (pci_enable_device(pci) < 0) {
2393 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2394 "disabling device\n");
2395 snd_card_disconnect(card);
2396 return -EIO;
2397 }
2398 pci_set_master(pci);
2399 if (chip->msi)
2400 if (pci_enable_msi(pci) < 0)
2401 chip->msi = 0;
2402 if (azx_acquire_irq(chip, 1) < 0)
2403 return -EIO;
2404 azx_init_pci(chip);
2405
2406 if (snd_hda_codecs_inuse(chip->bus))
2407 azx_init_chip(chip, 1);
2408
2409 snd_hda_resume(chip->bus);
2410 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2411 return 0;
2412 }
2413 #endif /* CONFIG_PM */
2414
2415
2416 /*
2417 * reboot notifier for hang-up problem at power-down
2418 */
2419 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2420 {
2421 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2422 snd_hda_bus_reboot_notify(chip->bus);
2423 azx_stop_chip(chip);
2424 return NOTIFY_OK;
2425 }
2426
2427 static void azx_notifier_register(struct azx *chip)
2428 {
2429 chip->reboot_notifier.notifier_call = azx_halt;
2430 register_reboot_notifier(&chip->reboot_notifier);
2431 }
2432
2433 static void azx_notifier_unregister(struct azx *chip)
2434 {
2435 if (chip->reboot_notifier.notifier_call)
2436 unregister_reboot_notifier(&chip->reboot_notifier);
2437 }
2438
2439 /*
2440 * destructor
2441 */
2442 static int azx_free(struct azx *chip)
2443 {
2444 int i;
2445
2446 azx_notifier_unregister(chip);
2447
2448 if (chip->initialized) {
2449 azx_clear_irq_pending(chip);
2450 for (i = 0; i < chip->num_streams; i++)
2451 azx_stream_stop(chip, &chip->azx_dev[i]);
2452 azx_stop_chip(chip);
2453 }
2454
2455 if (chip->irq >= 0)
2456 free_irq(chip->irq, (void*)chip);
2457 if (chip->msi)
2458 pci_disable_msi(chip->pci);
2459 if (chip->remap_addr)
2460 iounmap(chip->remap_addr);
2461
2462 if (chip->azx_dev) {
2463 for (i = 0; i < chip->num_streams; i++)
2464 if (chip->azx_dev[i].bdl.area) {
2465 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2466 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2467 }
2468 }
2469 if (chip->rb.area) {
2470 mark_pages_wc(chip, &chip->rb, false);
2471 snd_dma_free_pages(&chip->rb);
2472 }
2473 if (chip->posbuf.area) {
2474 mark_pages_wc(chip, &chip->posbuf, false);
2475 snd_dma_free_pages(&chip->posbuf);
2476 }
2477 pci_release_regions(chip->pci);
2478 pci_disable_device(chip->pci);
2479 kfree(chip->azx_dev);
2480 kfree(chip);
2481
2482 return 0;
2483 }
2484
2485 static int azx_dev_free(struct snd_device *device)
2486 {
2487 return azx_free(device->device_data);
2488 }
2489
2490 /*
2491 * white/black-listing for position_fix
2492 */
2493 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2494 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2495 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2496 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2497 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2498 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2499 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2500 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2501 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2502 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2503 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2504 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2505 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2506 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2507 {}
2508 };
2509
2510 static int __devinit check_position_fix(struct azx *chip, int fix)
2511 {
2512 const struct snd_pci_quirk *q;
2513
2514 switch (fix) {
2515 case POS_FIX_LPIB:
2516 case POS_FIX_POSBUF:
2517 case POS_FIX_VIACOMBO:
2518 return fix;
2519 }
2520
2521 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2522 if (q) {
2523 printk(KERN_INFO
2524 "hda_intel: position_fix set to %d "
2525 "for device %04x:%04x\n",
2526 q->value, q->subvendor, q->subdevice);
2527 return q->value;
2528 }
2529
2530 /* Check VIA/ATI HD Audio Controller exist */
2531 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2532 snd_printd(SFX "Using VIACOMBO position fix\n");
2533 return POS_FIX_VIACOMBO;
2534 }
2535 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2536 snd_printd(SFX "Using LPIB position fix\n");
2537 return POS_FIX_LPIB;
2538 }
2539 return POS_FIX_AUTO;
2540 }
2541
2542 /*
2543 * black-lists for probe_mask
2544 */
2545 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2546 /* Thinkpad often breaks the controller communication when accessing
2547 * to the non-working (or non-existing) modem codec slot.
2548 */
2549 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2550 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2551 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2552 /* broken BIOS */
2553 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2554 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2555 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2556 /* forced codec slots */
2557 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2558 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2559 {}
2560 };
2561
2562 #define AZX_FORCE_CODEC_MASK 0x100
2563
2564 static void __devinit check_probe_mask(struct azx *chip, int dev)
2565 {
2566 const struct snd_pci_quirk *q;
2567
2568 chip->codec_probe_mask = probe_mask[dev];
2569 if (chip->codec_probe_mask == -1) {
2570 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2571 if (q) {
2572 printk(KERN_INFO
2573 "hda_intel: probe_mask set to 0x%x "
2574 "for device %04x:%04x\n",
2575 q->value, q->subvendor, q->subdevice);
2576 chip->codec_probe_mask = q->value;
2577 }
2578 }
2579
2580 /* check forced option */
2581 if (chip->codec_probe_mask != -1 &&
2582 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2583 chip->codec_mask = chip->codec_probe_mask & 0xff;
2584 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2585 chip->codec_mask);
2586 }
2587 }
2588
2589 /*
2590 * white/black-list for enable_msi
2591 */
2592 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2593 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2594 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2595 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2596 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2597 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2598 {}
2599 };
2600
2601 static void __devinit check_msi(struct azx *chip)
2602 {
2603 const struct snd_pci_quirk *q;
2604
2605 if (enable_msi >= 0) {
2606 chip->msi = !!enable_msi;
2607 return;
2608 }
2609 chip->msi = 1; /* enable MSI as default */
2610 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2611 if (q) {
2612 printk(KERN_INFO
2613 "hda_intel: msi for device %04x:%04x set to %d\n",
2614 q->subvendor, q->subdevice, q->value);
2615 chip->msi = q->value;
2616 return;
2617 }
2618
2619 /* NVidia chipsets seem to cause troubles with MSI */
2620 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2621 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2622 chip->msi = 0;
2623 }
2624 }
2625
2626 /* check the snoop mode availability */
2627 static void __devinit azx_check_snoop_available(struct azx *chip)
2628 {
2629 bool snoop = chip->snoop;
2630
2631 switch (chip->driver_type) {
2632 case AZX_DRIVER_VIA:
2633 /* force to non-snoop mode for a new VIA controller
2634 * when BIOS is set
2635 */
2636 if (snoop) {
2637 u8 val;
2638 pci_read_config_byte(chip->pci, 0x42, &val);
2639 if (!(val & 0x80) && chip->pci->revision == 0x30)
2640 snoop = false;
2641 }
2642 break;
2643 case AZX_DRIVER_ATIHDMI_NS:
2644 /* new ATI HDMI requires non-snoop */
2645 snoop = false;
2646 break;
2647 }
2648
2649 if (snoop != chip->snoop) {
2650 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2651 snoop ? "snoop" : "non-snoop");
2652 chip->snoop = snoop;
2653 }
2654 }
2655
2656 /*
2657 * constructor
2658 */
2659 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2660 int dev, unsigned int driver_caps,
2661 struct azx **rchip)
2662 {
2663 struct azx *chip;
2664 int i, err;
2665 unsigned short gcap;
2666 static struct snd_device_ops ops = {
2667 .dev_free = azx_dev_free,
2668 };
2669
2670 *rchip = NULL;
2671
2672 err = pci_enable_device(pci);
2673 if (err < 0)
2674 return err;
2675
2676 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2677 if (!chip) {
2678 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2679 pci_disable_device(pci);
2680 return -ENOMEM;
2681 }
2682
2683 spin_lock_init(&chip->reg_lock);
2684 mutex_init(&chip->open_mutex);
2685 chip->card = card;
2686 chip->pci = pci;
2687 chip->irq = -1;
2688 chip->driver_caps = driver_caps;
2689 chip->driver_type = driver_caps & 0xff;
2690 check_msi(chip);
2691 chip->dev_index = dev;
2692 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2693 INIT_LIST_HEAD(&chip->pcm_list);
2694
2695 chip->position_fix[0] = chip->position_fix[1] =
2696 check_position_fix(chip, position_fix[dev]);
2697 check_probe_mask(chip, dev);
2698
2699 chip->single_cmd = single_cmd;
2700 chip->snoop = hda_snoop;
2701 azx_check_snoop_available(chip);
2702
2703 if (bdl_pos_adj[dev] < 0) {
2704 switch (chip->driver_type) {
2705 case AZX_DRIVER_ICH:
2706 case AZX_DRIVER_PCH:
2707 bdl_pos_adj[dev] = 1;
2708 break;
2709 default:
2710 bdl_pos_adj[dev] = 32;
2711 break;
2712 }
2713 }
2714
2715 #if BITS_PER_LONG != 64
2716 /* Fix up base address on ULI M5461 */
2717 if (chip->driver_type == AZX_DRIVER_ULI) {
2718 u16 tmp3;
2719 pci_read_config_word(pci, 0x40, &tmp3);
2720 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2721 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2722 }
2723 #endif
2724
2725 err = pci_request_regions(pci, "ICH HD audio");
2726 if (err < 0) {
2727 kfree(chip);
2728 pci_disable_device(pci);
2729 return err;
2730 }
2731
2732 chip->addr = pci_resource_start(pci, 0);
2733 chip->remap_addr = pci_ioremap_bar(pci, 0);
2734 if (chip->remap_addr == NULL) {
2735 snd_printk(KERN_ERR SFX "ioremap error\n");
2736 err = -ENXIO;
2737 goto errout;
2738 }
2739
2740 if (chip->msi)
2741 if (pci_enable_msi(pci) < 0)
2742 chip->msi = 0;
2743
2744 if (azx_acquire_irq(chip, 0) < 0) {
2745 err = -EBUSY;
2746 goto errout;
2747 }
2748
2749 pci_set_master(pci);
2750 synchronize_irq(chip->irq);
2751
2752 gcap = azx_readw(chip, GCAP);
2753 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2754
2755 /* disable SB600 64bit support for safety */
2756 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2757 struct pci_dev *p_smbus;
2758 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2759 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2760 NULL);
2761 if (p_smbus) {
2762 if (p_smbus->revision < 0x30)
2763 gcap &= ~ICH6_GCAP_64OK;
2764 pci_dev_put(p_smbus);
2765 }
2766 }
2767
2768 /* disable 64bit DMA address on some devices */
2769 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2770 snd_printd(SFX "Disabling 64bit DMA\n");
2771 gcap &= ~ICH6_GCAP_64OK;
2772 }
2773
2774 /* disable buffer size rounding to 128-byte multiples if supported */
2775 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2776 align_buffer_size = 0;
2777
2778 /* allow 64bit DMA address if supported by H/W */
2779 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2780 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2781 else {
2782 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2783 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2784 }
2785
2786 /* read number of streams from GCAP register instead of using
2787 * hardcoded value
2788 */
2789 chip->capture_streams = (gcap >> 8) & 0x0f;
2790 chip->playback_streams = (gcap >> 12) & 0x0f;
2791 if (!chip->playback_streams && !chip->capture_streams) {
2792 /* gcap didn't give any info, switching to old method */
2793
2794 switch (chip->driver_type) {
2795 case AZX_DRIVER_ULI:
2796 chip->playback_streams = ULI_NUM_PLAYBACK;
2797 chip->capture_streams = ULI_NUM_CAPTURE;
2798 break;
2799 case AZX_DRIVER_ATIHDMI:
2800 case AZX_DRIVER_ATIHDMI_NS:
2801 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2802 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2803 break;
2804 case AZX_DRIVER_GENERIC:
2805 default:
2806 chip->playback_streams = ICH6_NUM_PLAYBACK;
2807 chip->capture_streams = ICH6_NUM_CAPTURE;
2808 break;
2809 }
2810 }
2811 chip->capture_index_offset = 0;
2812 chip->playback_index_offset = chip->capture_streams;
2813 chip->num_streams = chip->playback_streams + chip->capture_streams;
2814 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2815 GFP_KERNEL);
2816 if (!chip->azx_dev) {
2817 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2818 goto errout;
2819 }
2820
2821 for (i = 0; i < chip->num_streams; i++) {
2822 /* allocate memory for the BDL for each stream */
2823 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2824 snd_dma_pci_data(chip->pci),
2825 BDL_SIZE, &chip->azx_dev[i].bdl);
2826 if (err < 0) {
2827 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2828 goto errout;
2829 }
2830 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2831 }
2832 /* allocate memory for the position buffer */
2833 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2834 snd_dma_pci_data(chip->pci),
2835 chip->num_streams * 8, &chip->posbuf);
2836 if (err < 0) {
2837 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2838 goto errout;
2839 }
2840 mark_pages_wc(chip, &chip->posbuf, true);
2841 /* allocate CORB/RIRB */
2842 err = azx_alloc_cmd_io(chip);
2843 if (err < 0)
2844 goto errout;
2845
2846 /* initialize streams */
2847 azx_init_stream(chip);
2848
2849 /* initialize chip */
2850 azx_init_pci(chip);
2851 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2852
2853 /* codec detection */
2854 if (!chip->codec_mask) {
2855 snd_printk(KERN_ERR SFX "no codecs found!\n");
2856 err = -ENODEV;
2857 goto errout;
2858 }
2859
2860 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2861 if (err <0) {
2862 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2863 goto errout;
2864 }
2865
2866 strcpy(card->driver, "HDA-Intel");
2867 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2868 sizeof(card->shortname));
2869 snprintf(card->longname, sizeof(card->longname),
2870 "%s at 0x%lx irq %i",
2871 card->shortname, chip->addr, chip->irq);
2872
2873 *rchip = chip;
2874 return 0;
2875
2876 errout:
2877 azx_free(chip);
2878 return err;
2879 }
2880
2881 static void power_down_all_codecs(struct azx *chip)
2882 {
2883 #ifdef CONFIG_SND_HDA_POWER_SAVE
2884 /* The codecs were powered up in snd_hda_codec_new().
2885 * Now all initialization done, so turn them down if possible
2886 */
2887 struct hda_codec *codec;
2888 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2889 snd_hda_power_down(codec);
2890 }
2891 #endif
2892 }
2893
2894 static int __devinit azx_probe(struct pci_dev *pci,
2895 const struct pci_device_id *pci_id)
2896 {
2897 static int dev;
2898 struct snd_card *card;
2899 struct azx *chip;
2900 int err;
2901
2902 if (dev >= SNDRV_CARDS)
2903 return -ENODEV;
2904 if (!enable[dev]) {
2905 dev++;
2906 return -ENOENT;
2907 }
2908
2909 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2910 if (err < 0) {
2911 snd_printk(KERN_ERR SFX "Error creating card!\n");
2912 return err;
2913 }
2914
2915 /* set this here since it's referred in snd_hda_load_patch() */
2916 snd_card_set_dev(card, &pci->dev);
2917
2918 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2919 if (err < 0)
2920 goto out_free;
2921 card->private_data = chip;
2922
2923 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2924 chip->beep_mode = beep_mode[dev];
2925 #endif
2926
2927 /* create codec instances */
2928 err = azx_codec_create(chip, model[dev]);
2929 if (err < 0)
2930 goto out_free;
2931 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2932 if (patch[dev] && *patch[dev]) {
2933 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2934 patch[dev]);
2935 err = snd_hda_load_patch(chip->bus, patch[dev]);
2936 if (err < 0)
2937 goto out_free;
2938 }
2939 #endif
2940 if ((probe_only[dev] & 1) == 0) {
2941 err = azx_codec_configure(chip);
2942 if (err < 0)
2943 goto out_free;
2944 }
2945
2946 /* create PCM streams */
2947 err = snd_hda_build_pcms(chip->bus);
2948 if (err < 0)
2949 goto out_free;
2950
2951 /* create mixer controls */
2952 err = azx_mixer_create(chip);
2953 if (err < 0)
2954 goto out_free;
2955
2956 err = snd_card_register(card);
2957 if (err < 0)
2958 goto out_free;
2959
2960 pci_set_drvdata(pci, card);
2961 chip->running = 1;
2962 power_down_all_codecs(chip);
2963 azx_notifier_register(chip);
2964
2965 dev++;
2966 return err;
2967 out_free:
2968 snd_card_free(card);
2969 return err;
2970 }
2971
2972 static void __devexit azx_remove(struct pci_dev *pci)
2973 {
2974 snd_card_free(pci_get_drvdata(pci));
2975 pci_set_drvdata(pci, NULL);
2976 }
2977
2978 /* PCI IDs */
2979 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2980 /* CPT */
2981 { PCI_DEVICE(0x8086, 0x1c20),
2982 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2983 AZX_DCAPS_BUFSIZE },
2984 /* PBG */
2985 { PCI_DEVICE(0x8086, 0x1d20),
2986 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2987 AZX_DCAPS_BUFSIZE},
2988 /* Panther Point */
2989 { PCI_DEVICE(0x8086, 0x1e20),
2990 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2991 AZX_DCAPS_BUFSIZE},
2992 /* SCH */
2993 { PCI_DEVICE(0x8086, 0x811b),
2994 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
2995 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
2996 { PCI_DEVICE(0x8086, 0x080a),
2997 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
2998 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
2999 /* ICH */
3000 { PCI_DEVICE(0x8086, 0x2668),
3001 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3002 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3003 { PCI_DEVICE(0x8086, 0x27d8),
3004 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3005 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3006 { PCI_DEVICE(0x8086, 0x269a),
3007 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3008 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3009 { PCI_DEVICE(0x8086, 0x284b),
3010 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3011 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3012 { PCI_DEVICE(0x8086, 0x293e),
3013 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3014 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3015 { PCI_DEVICE(0x8086, 0x293f),
3016 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3017 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3018 { PCI_DEVICE(0x8086, 0x3a3e),
3019 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3020 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3021 { PCI_DEVICE(0x8086, 0x3a6e),
3022 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3023 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3024 /* Generic Intel */
3025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3026 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3027 .class_mask = 0xffffff,
3028 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3029 /* ATI SB 450/600/700/800/900 */
3030 { PCI_DEVICE(0x1002, 0x437b),
3031 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3032 { PCI_DEVICE(0x1002, 0x4383),
3033 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3034 /* AMD Hudson */
3035 { PCI_DEVICE(0x1022, 0x780d),
3036 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3037 /* ATI HDMI */
3038 { PCI_DEVICE(0x1002, 0x793b),
3039 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3040 { PCI_DEVICE(0x1002, 0x7919),
3041 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3042 { PCI_DEVICE(0x1002, 0x960f),
3043 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3044 { PCI_DEVICE(0x1002, 0x970f),
3045 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3046 { PCI_DEVICE(0x1002, 0xaa00),
3047 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3048 { PCI_DEVICE(0x1002, 0xaa08),
3049 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3050 { PCI_DEVICE(0x1002, 0xaa10),
3051 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3052 { PCI_DEVICE(0x1002, 0xaa18),
3053 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3054 { PCI_DEVICE(0x1002, 0xaa20),
3055 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3056 { PCI_DEVICE(0x1002, 0xaa28),
3057 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3058 { PCI_DEVICE(0x1002, 0xaa30),
3059 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3060 { PCI_DEVICE(0x1002, 0xaa38),
3061 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3062 { PCI_DEVICE(0x1002, 0xaa40),
3063 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3064 { PCI_DEVICE(0x1002, 0xaa48),
3065 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3066 { PCI_DEVICE(0x1002, 0x9902),
3067 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3068 { PCI_DEVICE(0x1002, 0xaaa0),
3069 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3070 { PCI_DEVICE(0x1002, 0xaaa8),
3071 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3072 { PCI_DEVICE(0x1002, 0xaab0),
3073 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3074 /* VIA VT8251/VT8237A */
3075 { PCI_DEVICE(0x1106, 0x3288),
3076 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3077 /* SIS966 */
3078 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3079 /* ULI M5461 */
3080 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3081 /* NVIDIA MCP */
3082 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3083 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3084 .class_mask = 0xffffff,
3085 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3086 /* Teradici */
3087 { PCI_DEVICE(0x6549, 0x1200),
3088 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3089 /* Creative X-Fi (CA0110-IBG) */
3090 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3091 /* the following entry conflicts with snd-ctxfi driver,
3092 * as ctxfi driver mutates from HD-audio to native mode with
3093 * a special command sequence.
3094 */
3095 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3096 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3097 .class_mask = 0xffffff,
3098 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3099 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3100 #else
3101 /* this entry seems still valid -- i.e. without emu20kx chip */
3102 { PCI_DEVICE(0x1102, 0x0009),
3103 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3104 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3105 #endif
3106 /* Vortex86MX */
3107 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3108 /* VMware HDAudio */
3109 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3110 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3111 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3112 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3113 .class_mask = 0xffffff,
3114 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3115 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3116 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3117 .class_mask = 0xffffff,
3118 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3119 { 0, }
3120 };
3121 MODULE_DEVICE_TABLE(pci, azx_ids);
3122
3123 /* pci_driver definition */
3124 static struct pci_driver driver = {
3125 .name = KBUILD_MODNAME,
3126 .id_table = azx_ids,
3127 .probe = azx_probe,
3128 .remove = __devexit_p(azx_remove),
3129 #ifdef CONFIG_PM
3130 .suspend = azx_suspend,
3131 .resume = azx_resume,
3132 #endif
3133 };
3134
3135 static int __init alsa_card_azx_init(void)
3136 {
3137 return pci_register_driver(&driver);
3138 }
3139
3140 static void __exit alsa_card_azx_exit(void)
3141 {
3142 pci_unregister_driver(&driver);
3143 }
3144
3145 module_init(alsa_card_azx_init)
3146 module_exit(alsa_card_azx_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree