2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
33 #include "radeon_drm.h"
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
41 #define PFP_UCODE_SIZE 576
42 #define PM4_UCODE_SIZE 1792
43 #define RLC_UCODE_SIZE 768
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
46 #define R700_RLC_UCODE_SIZE 1024
47 #define EVERGREEN_PFP_UCODE_SIZE 1120
48 #define EVERGREEN_PM4_UCODE_SIZE 1376
49 #define EVERGREEN_RLC_UCODE_SIZE 768
52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
53 MODULE_FIRMWARE("radeon/R600_me.bin");
54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55 MODULE_FIRMWARE("radeon/RV610_me.bin");
56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57 MODULE_FIRMWARE("radeon/RV630_me.bin");
58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59 MODULE_FIRMWARE("radeon/RV620_me.bin");
60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61 MODULE_FIRMWARE("radeon/RV635_me.bin");
62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63 MODULE_FIRMWARE("radeon/RV670_me.bin");
64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65 MODULE_FIRMWARE("radeon/RS780_me.bin");
66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67 MODULE_FIRMWARE("radeon/RV770_me.bin");
68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69 MODULE_FIRMWARE("radeon/RV730_me.bin");
70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71 MODULE_FIRMWARE("radeon/RV710_me.bin");
72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
86 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
87 MODULE_FIRMWARE("radeon/PALM_me.bin");
88 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
90 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
);
92 /* r600,rv610,rv630,rv620,rv635,rv670 */
93 int r600_mc_wait_for_idle(struct radeon_device
*rdev
);
94 void r600_gpu_init(struct radeon_device
*rdev
);
95 void r600_fini(struct radeon_device
*rdev
);
96 void r600_irq_disable(struct radeon_device
*rdev
);
97 static void r600_pcie_gen2_enable(struct radeon_device
*rdev
);
99 /* get temperature in millidegrees */
100 u32
rv6xx_get_temp(struct radeon_device
*rdev
)
102 u32 temp
= (RREG32(CG_THERMAL_STATUS
) & ASIC_T_MASK
) >>
108 void r600_pm_get_dynpm_state(struct radeon_device
*rdev
)
112 rdev
->pm
.dynpm_can_upclock
= true;
113 rdev
->pm
.dynpm_can_downclock
= true;
115 /* power state array is low to high, default is first */
116 if ((rdev
->flags
& RADEON_IS_IGP
) || (rdev
->family
== CHIP_R600
)) {
117 int min_power_state_index
= 0;
119 if (rdev
->pm
.num_power_states
> 2)
120 min_power_state_index
= 1;
122 switch (rdev
->pm
.dynpm_planned_action
) {
123 case DYNPM_ACTION_MINIMUM
:
124 rdev
->pm
.requested_power_state_index
= min_power_state_index
;
125 rdev
->pm
.requested_clock_mode_index
= 0;
126 rdev
->pm
.dynpm_can_downclock
= false;
128 case DYNPM_ACTION_DOWNCLOCK
:
129 if (rdev
->pm
.current_power_state_index
== min_power_state_index
) {
130 rdev
->pm
.requested_power_state_index
= rdev
->pm
.current_power_state_index
;
131 rdev
->pm
.dynpm_can_downclock
= false;
133 if (rdev
->pm
.active_crtc_count
> 1) {
134 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
135 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
137 else if (i
>= rdev
->pm
.current_power_state_index
) {
138 rdev
->pm
.requested_power_state_index
=
139 rdev
->pm
.current_power_state_index
;
142 rdev
->pm
.requested_power_state_index
= i
;
147 if (rdev
->pm
.current_power_state_index
== 0)
148 rdev
->pm
.requested_power_state_index
=
149 rdev
->pm
.num_power_states
- 1;
151 rdev
->pm
.requested_power_state_index
=
152 rdev
->pm
.current_power_state_index
- 1;
155 rdev
->pm
.requested_clock_mode_index
= 0;
156 /* don't use the power state if crtcs are active and no display flag is set */
157 if ((rdev
->pm
.active_crtc_count
> 0) &&
158 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
159 clock_info
[rdev
->pm
.requested_clock_mode_index
].flags
&
160 RADEON_PM_MODE_NO_DISPLAY
)) {
161 rdev
->pm
.requested_power_state_index
++;
164 case DYNPM_ACTION_UPCLOCK
:
165 if (rdev
->pm
.current_power_state_index
== (rdev
->pm
.num_power_states
- 1)) {
166 rdev
->pm
.requested_power_state_index
= rdev
->pm
.current_power_state_index
;
167 rdev
->pm
.dynpm_can_upclock
= false;
169 if (rdev
->pm
.active_crtc_count
> 1) {
170 for (i
= (rdev
->pm
.num_power_states
- 1); i
>= 0; i
--) {
171 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
173 else if (i
<= rdev
->pm
.current_power_state_index
) {
174 rdev
->pm
.requested_power_state_index
=
175 rdev
->pm
.current_power_state_index
;
178 rdev
->pm
.requested_power_state_index
= i
;
183 rdev
->pm
.requested_power_state_index
=
184 rdev
->pm
.current_power_state_index
+ 1;
186 rdev
->pm
.requested_clock_mode_index
= 0;
188 case DYNPM_ACTION_DEFAULT
:
189 rdev
->pm
.requested_power_state_index
= rdev
->pm
.default_power_state_index
;
190 rdev
->pm
.requested_clock_mode_index
= 0;
191 rdev
->pm
.dynpm_can_upclock
= false;
193 case DYNPM_ACTION_NONE
:
195 DRM_ERROR("Requested mode for not defined action\n");
199 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
200 /* for now just select the first power state and switch between clock modes */
201 /* power state array is low to high, default is first (0) */
202 if (rdev
->pm
.active_crtc_count
> 1) {
203 rdev
->pm
.requested_power_state_index
= -1;
204 /* start at 1 as we don't want the default mode */
205 for (i
= 1; i
< rdev
->pm
.num_power_states
; i
++) {
206 if (rdev
->pm
.power_state
[i
].flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
208 else if ((rdev
->pm
.power_state
[i
].type
== POWER_STATE_TYPE_PERFORMANCE
) ||
209 (rdev
->pm
.power_state
[i
].type
== POWER_STATE_TYPE_BATTERY
)) {
210 rdev
->pm
.requested_power_state_index
= i
;
214 /* if nothing selected, grab the default state. */
215 if (rdev
->pm
.requested_power_state_index
== -1)
216 rdev
->pm
.requested_power_state_index
= 0;
218 rdev
->pm
.requested_power_state_index
= 1;
220 switch (rdev
->pm
.dynpm_planned_action
) {
221 case DYNPM_ACTION_MINIMUM
:
222 rdev
->pm
.requested_clock_mode_index
= 0;
223 rdev
->pm
.dynpm_can_downclock
= false;
225 case DYNPM_ACTION_DOWNCLOCK
:
226 if (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
) {
227 if (rdev
->pm
.current_clock_mode_index
== 0) {
228 rdev
->pm
.requested_clock_mode_index
= 0;
229 rdev
->pm
.dynpm_can_downclock
= false;
231 rdev
->pm
.requested_clock_mode_index
=
232 rdev
->pm
.current_clock_mode_index
- 1;
234 rdev
->pm
.requested_clock_mode_index
= 0;
235 rdev
->pm
.dynpm_can_downclock
= false;
237 /* don't use the power state if crtcs are active and no display flag is set */
238 if ((rdev
->pm
.active_crtc_count
> 0) &&
239 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
240 clock_info
[rdev
->pm
.requested_clock_mode_index
].flags
&
241 RADEON_PM_MODE_NO_DISPLAY
)) {
242 rdev
->pm
.requested_clock_mode_index
++;
245 case DYNPM_ACTION_UPCLOCK
:
246 if (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
) {
247 if (rdev
->pm
.current_clock_mode_index
==
248 (rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].num_clock_modes
- 1)) {
249 rdev
->pm
.requested_clock_mode_index
= rdev
->pm
.current_clock_mode_index
;
250 rdev
->pm
.dynpm_can_upclock
= false;
252 rdev
->pm
.requested_clock_mode_index
=
253 rdev
->pm
.current_clock_mode_index
+ 1;
255 rdev
->pm
.requested_clock_mode_index
=
256 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].num_clock_modes
- 1;
257 rdev
->pm
.dynpm_can_upclock
= false;
260 case DYNPM_ACTION_DEFAULT
:
261 rdev
->pm
.requested_power_state_index
= rdev
->pm
.default_power_state_index
;
262 rdev
->pm
.requested_clock_mode_index
= 0;
263 rdev
->pm
.dynpm_can_upclock
= false;
265 case DYNPM_ACTION_NONE
:
267 DRM_ERROR("Requested mode for not defined action\n");
272 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
273 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
274 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
,
275 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
276 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
,
277 rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
281 static int r600_pm_get_type_index(struct radeon_device
*rdev
,
282 enum radeon_pm_state_type ps_type
,
286 int found_instance
= -1;
288 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
289 if (rdev
->pm
.power_state
[i
].type
== ps_type
) {
291 if (found_instance
== instance
)
295 /* return default if no match */
296 return rdev
->pm
.default_power_state_index
;
299 void rs780_pm_init_profile(struct radeon_device
*rdev
)
301 if (rdev
->pm
.num_power_states
== 2) {
303 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
304 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
305 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
306 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
308 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 0;
309 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 0;
310 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
311 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
313 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 0;
314 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 0;
315 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
316 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
318 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 0;
319 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 1;
320 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
321 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
323 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 0;
324 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 0;
325 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
326 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
328 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 0;
329 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 0;
330 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
331 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
333 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 0;
334 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 1;
335 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
336 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
337 } else if (rdev
->pm
.num_power_states
== 3) {
339 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
340 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
341 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
342 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
344 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 1;
345 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 1;
346 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
347 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
349 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 1;
350 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 1;
351 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
352 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
354 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 1;
355 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 2;
356 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
357 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
359 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 1;
360 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 1;
361 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
362 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
364 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 1;
365 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 1;
366 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
367 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
369 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 1;
370 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 2;
371 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
372 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
375 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
376 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
377 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
378 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
380 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 2;
381 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 2;
382 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
383 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
385 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 2;
386 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 2;
387 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
388 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
390 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 2;
391 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 3;
392 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
393 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
395 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 2;
396 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 0;
397 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
398 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
400 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 2;
401 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 0;
402 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
403 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
405 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 2;
406 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 3;
407 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
408 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
412 void r600_pm_init_profile(struct radeon_device
*rdev
)
414 if (rdev
->family
== CHIP_R600
) {
417 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
418 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
419 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
420 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 0;
422 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
423 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
424 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
425 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
427 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
428 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
429 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
430 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 0;
432 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
433 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
434 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
435 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 0;
437 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
438 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
439 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
440 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
442 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
443 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
444 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
445 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 0;
447 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
448 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
449 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
450 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 0;
452 if (rdev
->pm
.num_power_states
< 4) {
454 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
455 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
456 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
457 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 2;
459 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
= 1;
460 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
= 1;
461 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
462 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
464 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
= 1;
465 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
= 1;
466 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
467 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
469 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
= 1;
470 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
= 1;
471 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
472 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 2;
474 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
= 2;
475 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
= 2;
476 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
477 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
479 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
= 2;
480 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
= 2;
481 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
482 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
484 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
= 2;
485 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
= 2;
486 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
487 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 2;
490 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_ps_idx
= rdev
->pm
.default_power_state_index
;
491 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_ps_idx
= rdev
->pm
.default_power_state_index
;
492 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_off_cm_idx
= 0;
493 rdev
->pm
.profiles
[PM_PROFILE_DEFAULT_IDX
].dpms_on_cm_idx
= 2;
495 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
496 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
=
497 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
498 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
=
499 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
500 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
501 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
503 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_ps_idx
=
504 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
505 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_ps_idx
=
506 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
507 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_off_cm_idx
= 0;
508 rdev
->pm
.profiles
[PM_PROFILE_LOW_SH_IDX
].dpms_on_cm_idx
= 0;
511 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
512 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
=
513 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
514 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
=
515 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 0);
516 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
517 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
519 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_ps_idx
=
520 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
521 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_ps_idx
=
522 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
523 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_off_cm_idx
= 0;
524 rdev
->pm
.profiles
[PM_PROFILE_MID_SH_IDX
].dpms_on_cm_idx
= 1;
527 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_ps_idx
=
528 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
529 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_ps_idx
=
530 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 0);
531 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_off_cm_idx
= 0;
532 rdev
->pm
.profiles
[PM_PROFILE_HIGH_SH_IDX
].dpms_on_cm_idx
= 2;
534 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
535 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
=
536 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 1);
537 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
=
538 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 1);
539 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
540 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
542 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_ps_idx
=
543 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
544 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_ps_idx
=
545 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
546 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_off_cm_idx
= 0;
547 rdev
->pm
.profiles
[PM_PROFILE_LOW_MH_IDX
].dpms_on_cm_idx
= 0;
550 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
551 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
=
552 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 1);
553 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
=
554 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_BATTERY
, 1);
555 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
556 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
558 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_ps_idx
=
559 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
560 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_ps_idx
=
561 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
562 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_off_cm_idx
= 0;
563 rdev
->pm
.profiles
[PM_PROFILE_MID_MH_IDX
].dpms_on_cm_idx
= 1;
566 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_ps_idx
=
567 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
568 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_ps_idx
=
569 r600_pm_get_type_index(rdev
, POWER_STATE_TYPE_PERFORMANCE
, 1);
570 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_off_cm_idx
= 0;
571 rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
= 2;
576 void r600_pm_misc(struct radeon_device
*rdev
)
578 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
579 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
580 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
581 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
583 if ((voltage
->type
== VOLTAGE_SW
) && voltage
->voltage
) {
584 if (voltage
->voltage
!= rdev
->pm
.current_vddc
) {
585 radeon_atom_set_voltage(rdev
, voltage
->voltage
);
586 rdev
->pm
.current_vddc
= voltage
->voltage
;
587 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage
->voltage
);
592 bool r600_gui_idle(struct radeon_device
*rdev
)
594 if (RREG32(GRBM_STATUS
) & GUI_ACTIVE
)
600 /* hpd for digital panel detect/disconnect */
601 bool r600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
603 bool connected
= false;
605 if (ASIC_IS_DCE3(rdev
)) {
608 if (RREG32(DC_HPD1_INT_STATUS
) & DC_HPDx_SENSE
)
612 if (RREG32(DC_HPD2_INT_STATUS
) & DC_HPDx_SENSE
)
616 if (RREG32(DC_HPD3_INT_STATUS
) & DC_HPDx_SENSE
)
620 if (RREG32(DC_HPD4_INT_STATUS
) & DC_HPDx_SENSE
)
625 if (RREG32(DC_HPD5_INT_STATUS
) & DC_HPDx_SENSE
)
629 if (RREG32(DC_HPD6_INT_STATUS
) & DC_HPDx_SENSE
)
638 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
642 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
646 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS
) & DC_HOT_PLUG_DETECTx_SENSE
)
656 void r600_hpd_set_polarity(struct radeon_device
*rdev
,
657 enum radeon_hpd_id hpd
)
660 bool connected
= r600_hpd_sense(rdev
, hpd
);
662 if (ASIC_IS_DCE3(rdev
)) {
665 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
667 tmp
&= ~DC_HPDx_INT_POLARITY
;
669 tmp
|= DC_HPDx_INT_POLARITY
;
670 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
673 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
675 tmp
&= ~DC_HPDx_INT_POLARITY
;
677 tmp
|= DC_HPDx_INT_POLARITY
;
678 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
681 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
683 tmp
&= ~DC_HPDx_INT_POLARITY
;
685 tmp
|= DC_HPDx_INT_POLARITY
;
686 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
689 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
691 tmp
&= ~DC_HPDx_INT_POLARITY
;
693 tmp
|= DC_HPDx_INT_POLARITY
;
694 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
697 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
699 tmp
&= ~DC_HPDx_INT_POLARITY
;
701 tmp
|= DC_HPDx_INT_POLARITY
;
702 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
706 tmp
= RREG32(DC_HPD6_INT_CONTROL
);
708 tmp
&= ~DC_HPDx_INT_POLARITY
;
710 tmp
|= DC_HPDx_INT_POLARITY
;
711 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
719 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
721 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
723 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
724 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
727 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
729 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
731 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
732 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
735 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
737 tmp
&= ~DC_HOT_PLUG_DETECTx_INT_POLARITY
;
739 tmp
|= DC_HOT_PLUG_DETECTx_INT_POLARITY
;
740 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
748 void r600_hpd_init(struct radeon_device
*rdev
)
750 struct drm_device
*dev
= rdev
->ddev
;
751 struct drm_connector
*connector
;
753 if (ASIC_IS_DCE3(rdev
)) {
754 u32 tmp
= DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
755 if (ASIC_IS_DCE32(rdev
))
758 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
759 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
760 switch (radeon_connector
->hpd
.hpd
) {
762 WREG32(DC_HPD1_CONTROL
, tmp
);
763 rdev
->irq
.hpd
[0] = true;
766 WREG32(DC_HPD2_CONTROL
, tmp
);
767 rdev
->irq
.hpd
[1] = true;
770 WREG32(DC_HPD3_CONTROL
, tmp
);
771 rdev
->irq
.hpd
[2] = true;
774 WREG32(DC_HPD4_CONTROL
, tmp
);
775 rdev
->irq
.hpd
[3] = true;
779 WREG32(DC_HPD5_CONTROL
, tmp
);
780 rdev
->irq
.hpd
[4] = true;
783 WREG32(DC_HPD6_CONTROL
, tmp
);
784 rdev
->irq
.hpd
[5] = true;
791 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
792 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
793 switch (radeon_connector
->hpd
.hpd
) {
795 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
796 rdev
->irq
.hpd
[0] = true;
799 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
800 rdev
->irq
.hpd
[1] = true;
803 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, DC_HOT_PLUG_DETECTx_EN
);
804 rdev
->irq
.hpd
[2] = true;
811 if (rdev
->irq
.installed
)
815 void r600_hpd_fini(struct radeon_device
*rdev
)
817 struct drm_device
*dev
= rdev
->ddev
;
818 struct drm_connector
*connector
;
820 if (ASIC_IS_DCE3(rdev
)) {
821 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
822 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
823 switch (radeon_connector
->hpd
.hpd
) {
825 WREG32(DC_HPD1_CONTROL
, 0);
826 rdev
->irq
.hpd
[0] = false;
829 WREG32(DC_HPD2_CONTROL
, 0);
830 rdev
->irq
.hpd
[1] = false;
833 WREG32(DC_HPD3_CONTROL
, 0);
834 rdev
->irq
.hpd
[2] = false;
837 WREG32(DC_HPD4_CONTROL
, 0);
838 rdev
->irq
.hpd
[3] = false;
842 WREG32(DC_HPD5_CONTROL
, 0);
843 rdev
->irq
.hpd
[4] = false;
846 WREG32(DC_HPD6_CONTROL
, 0);
847 rdev
->irq
.hpd
[5] = false;
854 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
855 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
856 switch (radeon_connector
->hpd
.hpd
) {
858 WREG32(DC_HOT_PLUG_DETECT1_CONTROL
, 0);
859 rdev
->irq
.hpd
[0] = false;
862 WREG32(DC_HOT_PLUG_DETECT2_CONTROL
, 0);
863 rdev
->irq
.hpd
[1] = false;
866 WREG32(DC_HOT_PLUG_DETECT3_CONTROL
, 0);
867 rdev
->irq
.hpd
[2] = false;
879 void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
884 /* flush hdp cache so updates hit vram */
885 if ((rdev
->family
>= CHIP_RV770
) && (rdev
->family
<= CHIP_RV740
) &&
886 !(rdev
->flags
& RADEON_IS_AGP
)) {
887 void __iomem
*ptr
= (void *)rdev
->gart
.table
.vram
.ptr
;
890 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
891 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
892 * This seems to cause problems on some AGP cards. Just use the old
895 WREG32(HDP_DEBUG1
, 0);
896 tmp
= readl((void __iomem
*)ptr
);
898 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
900 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR
, rdev
->mc
.gtt_start
>> 12);
901 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR
, (rdev
->mc
.gtt_end
- 1) >> 12);
902 WREG32(VM_CONTEXT0_REQUEST_RESPONSE
, REQUEST_TYPE(1));
903 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
905 tmp
= RREG32(VM_CONTEXT0_REQUEST_RESPONSE
);
906 tmp
= (tmp
& RESPONSE_TYPE_MASK
) >> RESPONSE_TYPE_SHIFT
;
908 printk(KERN_WARNING
"[drm] r600 flush TLB failed\n");
918 int r600_pcie_gart_init(struct radeon_device
*rdev
)
922 if (rdev
->gart
.table
.vram
.robj
) {
923 WARN(1, "R600 PCIE GART already initialized\n");
926 /* Initialize common gart structure */
927 r
= radeon_gart_init(rdev
);
930 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 8;
931 return radeon_gart_table_vram_alloc(rdev
);
934 int r600_pcie_gart_enable(struct radeon_device
*rdev
)
939 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
940 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
943 r
= radeon_gart_table_vram_pin(rdev
);
946 radeon_gart_restore(rdev
);
949 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
950 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
951 EFFECTIVE_L2_QUEUE_SIZE(7));
952 WREG32(VM_L2_CNTL2
, 0);
953 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
954 /* Setup TLB control */
955 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
956 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
957 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
958 ENABLE_WAIT_L2_QUERY
;
959 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
960 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
961 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
962 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
963 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
964 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
965 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
966 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
967 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
968 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
969 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
970 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
971 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
972 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
973 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
974 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
975 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
976 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
977 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
978 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
979 (u32
)(rdev
->dummy_page
.addr
>> 12));
980 for (i
= 1; i
< 7; i
++)
981 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
983 r600_pcie_gart_tlb_flush(rdev
);
984 rdev
->gart
.ready
= true;
988 void r600_pcie_gart_disable(struct radeon_device
*rdev
)
993 /* Disable all tables */
994 for (i
= 0; i
< 7; i
++)
995 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
997 /* Disable L2 cache */
998 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
999 EFFECTIVE_L2_QUEUE_SIZE(7));
1000 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1001 /* Setup L1 TLB control */
1002 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1003 ENABLE_WAIT_L2_QUERY
;
1004 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
1005 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
1006 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
1007 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
1008 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
1009 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
1010 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
1011 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
1012 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
);
1013 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
);
1014 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
1015 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
1016 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
);
1017 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
1018 if (rdev
->gart
.table
.vram
.robj
) {
1019 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
1020 if (likely(r
== 0)) {
1021 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
1022 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
1023 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
1028 void r600_pcie_gart_fini(struct radeon_device
*rdev
)
1030 radeon_gart_fini(rdev
);
1031 r600_pcie_gart_disable(rdev
);
1032 radeon_gart_table_vram_free(rdev
);
1035 void r600_agp_enable(struct radeon_device
*rdev
)
1040 /* Setup L2 cache */
1041 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
1042 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
1043 EFFECTIVE_L2_QUEUE_SIZE(7));
1044 WREG32(VM_L2_CNTL2
, 0);
1045 WREG32(VM_L2_CNTL3
, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1046 /* Setup TLB control */
1047 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
1048 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
1049 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1050 ENABLE_WAIT_L2_QUERY
;
1051 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL
, tmp
);
1052 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL
, tmp
);
1053 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL
, tmp
| ENABLE_L1_STRICT_ORDERING
);
1054 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL
, tmp
);
1055 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL
, tmp
);
1056 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL
, tmp
);
1057 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL
, tmp
);
1058 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL
, tmp
);
1059 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL
, tmp
);
1060 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL
, tmp
);
1061 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL
, tmp
);
1062 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL
, tmp
);
1063 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
1064 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL
, tmp
| ENABLE_SEMAPHORE_MODE
);
1065 for (i
= 0; i
< 7; i
++)
1066 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
1069 int r600_mc_wait_for_idle(struct radeon_device
*rdev
)
1074 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1075 /* read MC_STATUS */
1076 tmp
= RREG32(R_000E50_SRBM_STATUS
) & 0x3F00;
1084 static void r600_mc_program(struct radeon_device
*rdev
)
1086 struct rv515_mc_save save
;
1090 /* Initialize HDP */
1091 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1092 WREG32((0x2c14 + j
), 0x00000000);
1093 WREG32((0x2c18 + j
), 0x00000000);
1094 WREG32((0x2c1c + j
), 0x00000000);
1095 WREG32((0x2c20 + j
), 0x00000000);
1096 WREG32((0x2c24 + j
), 0x00000000);
1098 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
1100 rv515_mc_stop(rdev
, &save
);
1101 if (r600_mc_wait_for_idle(rdev
)) {
1102 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1104 /* Lockout access through VGA aperture (doesn't exist before R600) */
1105 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
1106 /* Update configuration */
1107 if (rdev
->flags
& RADEON_IS_AGP
) {
1108 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
1109 /* VRAM before AGP */
1110 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1111 rdev
->mc
.vram_start
>> 12);
1112 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1113 rdev
->mc
.gtt_end
>> 12);
1115 /* VRAM after AGP */
1116 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
1117 rdev
->mc
.gtt_start
>> 12);
1118 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
1119 rdev
->mc
.vram_end
>> 12);
1122 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
, rdev
->mc
.vram_start
>> 12);
1123 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
, rdev
->mc
.vram_end
>> 12);
1125 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
1126 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
1127 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
1128 WREG32(MC_VM_FB_LOCATION
, tmp
);
1129 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
1130 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
1131 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
1132 if (rdev
->flags
& RADEON_IS_AGP
) {
1133 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 22);
1134 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 22);
1135 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
1137 WREG32(MC_VM_AGP_BASE
, 0);
1138 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
1139 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
1141 if (r600_mc_wait_for_idle(rdev
)) {
1142 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1144 rv515_mc_resume(rdev
, &save
);
1145 /* we need to own VRAM, so turn off the VGA renderer here
1146 * to stop it overwriting our objects */
1147 rv515_vga_render_disable(rdev
);
1151 * r600_vram_gtt_location - try to find VRAM & GTT location
1152 * @rdev: radeon device structure holding all necessary informations
1153 * @mc: memory controller structure holding memory informations
1155 * Function will place try to place VRAM at same place as in CPU (PCI)
1156 * address space as some GPU seems to have issue when we reprogram at
1157 * different address space.
1159 * If there is not enough space to fit the unvisible VRAM after the
1160 * aperture then we limit the VRAM size to the aperture.
1162 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1163 * them to be in one from GPU point of view so that we can program GPU to
1164 * catch access outside them (weird GPU policy see ??).
1166 * This function will never fails, worst case are limiting VRAM or GTT.
1168 * Note: GTT start, end, size should be initialized before calling this
1169 * function on AGP platform.
1171 static void r600_vram_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
1173 u64 size_bf
, size_af
;
1175 if (mc
->mc_vram_size
> 0xE0000000) {
1176 /* leave room for at least 512M GTT */
1177 dev_warn(rdev
->dev
, "limiting VRAM\n");
1178 mc
->real_vram_size
= 0xE0000000;
1179 mc
->mc_vram_size
= 0xE0000000;
1181 if (rdev
->flags
& RADEON_IS_AGP
) {
1182 size_bf
= mc
->gtt_start
;
1183 size_af
= 0xFFFFFFFF - mc
->gtt_end
+ 1;
1184 if (size_bf
> size_af
) {
1185 if (mc
->mc_vram_size
> size_bf
) {
1186 dev_warn(rdev
->dev
, "limiting VRAM\n");
1187 mc
->real_vram_size
= size_bf
;
1188 mc
->mc_vram_size
= size_bf
;
1190 mc
->vram_start
= mc
->gtt_start
- mc
->mc_vram_size
;
1192 if (mc
->mc_vram_size
> size_af
) {
1193 dev_warn(rdev
->dev
, "limiting VRAM\n");
1194 mc
->real_vram_size
= size_af
;
1195 mc
->mc_vram_size
= size_af
;
1197 mc
->vram_start
= mc
->gtt_end
;
1199 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
1200 dev_info(rdev
->dev
, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1201 mc
->mc_vram_size
>> 20, mc
->vram_start
,
1202 mc
->vram_end
, mc
->real_vram_size
>> 20);
1205 if (rdev
->flags
& RADEON_IS_IGP
) {
1206 base
= RREG32(MC_VM_FB_LOCATION
) & 0xFFFF;
1209 radeon_vram_location(rdev
, &rdev
->mc
, base
);
1210 rdev
->mc
.gtt_base_align
= 0;
1211 radeon_gtt_location(rdev
, mc
);
1215 int r600_mc_init(struct radeon_device
*rdev
)
1218 int chansize
, numchan
;
1220 /* Get VRAM informations */
1221 rdev
->mc
.vram_is_ddr
= true;
1222 tmp
= RREG32(RAMCFG
);
1223 if (tmp
& CHANSIZE_OVERRIDE
) {
1225 } else if (tmp
& CHANSIZE_MASK
) {
1230 tmp
= RREG32(CHMAP
);
1231 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
1246 rdev
->mc
.vram_width
= numchan
* chansize
;
1247 /* Could aper size report 0 ? */
1248 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
1249 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
1250 /* Setup GPU memory space */
1251 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
1252 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
1253 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
1254 rdev
->mc
.active_vram_size
= rdev
->mc
.visible_vram_size
;
1255 r600_vram_gtt_location(rdev
, &rdev
->mc
);
1257 if (rdev
->flags
& RADEON_IS_IGP
) {
1258 rs690_pm_info(rdev
);
1259 rdev
->mc
.igp_sideport_enabled
= radeon_atombios_sideport_present(rdev
);
1261 radeon_update_bandwidth_info(rdev
);
1265 /* We doesn't check that the GPU really needs a reset we simply do the
1266 * reset, it's up to the caller to determine if the GPU needs one. We
1267 * might add an helper function to check that.
1269 int r600_gpu_soft_reset(struct radeon_device
*rdev
)
1271 struct rv515_mc_save save
;
1272 u32 grbm_busy_mask
= S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1273 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1274 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1275 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1276 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1277 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1278 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1279 S_008010_GUI_ACTIVE(1);
1280 u32 grbm2_busy_mask
= S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1281 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1282 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1283 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1284 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1285 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1286 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1287 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1290 dev_info(rdev
->dev
, "GPU softreset \n");
1291 dev_info(rdev
->dev
, " R_008010_GRBM_STATUS=0x%08X\n",
1292 RREG32(R_008010_GRBM_STATUS
));
1293 dev_info(rdev
->dev
, " R_008014_GRBM_STATUS2=0x%08X\n",
1294 RREG32(R_008014_GRBM_STATUS2
));
1295 dev_info(rdev
->dev
, " R_000E50_SRBM_STATUS=0x%08X\n",
1296 RREG32(R_000E50_SRBM_STATUS
));
1297 rv515_mc_stop(rdev
, &save
);
1298 if (r600_mc_wait_for_idle(rdev
)) {
1299 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
1301 /* Disable CP parsing/prefetching */
1302 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1));
1303 /* Check if any of the rendering block is busy and reset it */
1304 if ((RREG32(R_008010_GRBM_STATUS
) & grbm_busy_mask
) ||
1305 (RREG32(R_008014_GRBM_STATUS2
) & grbm2_busy_mask
)) {
1306 tmp
= S_008020_SOFT_RESET_CR(1) |
1307 S_008020_SOFT_RESET_DB(1) |
1308 S_008020_SOFT_RESET_CB(1) |
1309 S_008020_SOFT_RESET_PA(1) |
1310 S_008020_SOFT_RESET_SC(1) |
1311 S_008020_SOFT_RESET_SMX(1) |
1312 S_008020_SOFT_RESET_SPI(1) |
1313 S_008020_SOFT_RESET_SX(1) |
1314 S_008020_SOFT_RESET_SH(1) |
1315 S_008020_SOFT_RESET_TC(1) |
1316 S_008020_SOFT_RESET_TA(1) |
1317 S_008020_SOFT_RESET_VC(1) |
1318 S_008020_SOFT_RESET_VGT(1);
1319 dev_info(rdev
->dev
, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp
);
1320 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
1321 RREG32(R_008020_GRBM_SOFT_RESET
);
1323 WREG32(R_008020_GRBM_SOFT_RESET
, 0);
1325 /* Reset CP (we always reset CP) */
1326 tmp
= S_008020_SOFT_RESET_CP(1);
1327 dev_info(rdev
->dev
, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp
);
1328 WREG32(R_008020_GRBM_SOFT_RESET
, tmp
);
1329 RREG32(R_008020_GRBM_SOFT_RESET
);
1331 WREG32(R_008020_GRBM_SOFT_RESET
, 0);
1332 /* Wait a little for things to settle down */
1334 dev_info(rdev
->dev
, " R_008010_GRBM_STATUS=0x%08X\n",
1335 RREG32(R_008010_GRBM_STATUS
));
1336 dev_info(rdev
->dev
, " R_008014_GRBM_STATUS2=0x%08X\n",
1337 RREG32(R_008014_GRBM_STATUS2
));
1338 dev_info(rdev
->dev
, " R_000E50_SRBM_STATUS=0x%08X\n",
1339 RREG32(R_000E50_SRBM_STATUS
));
1340 rv515_mc_resume(rdev
, &save
);
1344 bool r600_gpu_is_lockup(struct radeon_device
*rdev
)
1349 struct r100_gpu_lockup
*lockup
;
1352 if (rdev
->family
>= CHIP_RV770
)
1353 lockup
= &rdev
->config
.rv770
.lockup
;
1355 lockup
= &rdev
->config
.r600
.lockup
;
1357 srbm_status
= RREG32(R_000E50_SRBM_STATUS
);
1358 grbm_status
= RREG32(R_008010_GRBM_STATUS
);
1359 grbm_status2
= RREG32(R_008014_GRBM_STATUS2
);
1360 if (!G_008010_GUI_ACTIVE(grbm_status
)) {
1361 r100_gpu_lockup_update(lockup
, &rdev
->cp
);
1364 /* force CP activities */
1365 r
= radeon_ring_lock(rdev
, 2);
1368 radeon_ring_write(rdev
, 0x80000000);
1369 radeon_ring_write(rdev
, 0x80000000);
1370 radeon_ring_unlock_commit(rdev
);
1372 rdev
->cp
.rptr
= RREG32(R600_CP_RB_RPTR
);
1373 return r100_gpu_cp_is_lockup(rdev
, lockup
, &rdev
->cp
);
1376 int r600_asic_reset(struct radeon_device
*rdev
)
1378 return r600_gpu_soft_reset(rdev
);
1381 static u32
r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes
,
1383 u32 backend_disable_mask
)
1385 u32 backend_map
= 0;
1386 u32 enabled_backends_mask
;
1387 u32 enabled_backends_count
;
1389 u32 swizzle_pipe
[R6XX_MAX_PIPES
];
1393 if (num_tile_pipes
> R6XX_MAX_PIPES
)
1394 num_tile_pipes
= R6XX_MAX_PIPES
;
1395 if (num_tile_pipes
< 1)
1397 if (num_backends
> R6XX_MAX_BACKENDS
)
1398 num_backends
= R6XX_MAX_BACKENDS
;
1399 if (num_backends
< 1)
1402 enabled_backends_mask
= 0;
1403 enabled_backends_count
= 0;
1404 for (i
= 0; i
< R6XX_MAX_BACKENDS
; ++i
) {
1405 if (((backend_disable_mask
>> i
) & 1) == 0) {
1406 enabled_backends_mask
|= (1 << i
);
1407 ++enabled_backends_count
;
1409 if (enabled_backends_count
== num_backends
)
1413 if (enabled_backends_count
== 0) {
1414 enabled_backends_mask
= 1;
1415 enabled_backends_count
= 1;
1418 if (enabled_backends_count
!= num_backends
)
1419 num_backends
= enabled_backends_count
;
1421 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R6XX_MAX_PIPES
);
1422 switch (num_tile_pipes
) {
1424 swizzle_pipe
[0] = 0;
1427 swizzle_pipe
[0] = 0;
1428 swizzle_pipe
[1] = 1;
1431 swizzle_pipe
[0] = 0;
1432 swizzle_pipe
[1] = 1;
1433 swizzle_pipe
[2] = 2;
1436 swizzle_pipe
[0] = 0;
1437 swizzle_pipe
[1] = 1;
1438 swizzle_pipe
[2] = 2;
1439 swizzle_pipe
[3] = 3;
1442 swizzle_pipe
[0] = 0;
1443 swizzle_pipe
[1] = 1;
1444 swizzle_pipe
[2] = 2;
1445 swizzle_pipe
[3] = 3;
1446 swizzle_pipe
[4] = 4;
1449 swizzle_pipe
[0] = 0;
1450 swizzle_pipe
[1] = 2;
1451 swizzle_pipe
[2] = 4;
1452 swizzle_pipe
[3] = 5;
1453 swizzle_pipe
[4] = 1;
1454 swizzle_pipe
[5] = 3;
1457 swizzle_pipe
[0] = 0;
1458 swizzle_pipe
[1] = 2;
1459 swizzle_pipe
[2] = 4;
1460 swizzle_pipe
[3] = 6;
1461 swizzle_pipe
[4] = 1;
1462 swizzle_pipe
[5] = 3;
1463 swizzle_pipe
[6] = 5;
1466 swizzle_pipe
[0] = 0;
1467 swizzle_pipe
[1] = 2;
1468 swizzle_pipe
[2] = 4;
1469 swizzle_pipe
[3] = 6;
1470 swizzle_pipe
[4] = 1;
1471 swizzle_pipe
[5] = 3;
1472 swizzle_pipe
[6] = 5;
1473 swizzle_pipe
[7] = 7;
1478 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
1479 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
1480 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
1482 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
1484 cur_backend
= (cur_backend
+ 1) % R6XX_MAX_BACKENDS
;
1490 int r600_count_pipe_bits(uint32_t val
)
1494 for (i
= 0; i
< 32; i
++) {
1501 void r600_gpu_init(struct radeon_device
*rdev
)
1506 u32 cc_rb_backend_disable
;
1507 u32 cc_gc_shader_pipe_config
;
1511 u32 sq_gpr_resource_mgmt_1
= 0;
1512 u32 sq_gpr_resource_mgmt_2
= 0;
1513 u32 sq_thread_resource_mgmt
= 0;
1514 u32 sq_stack_resource_mgmt_1
= 0;
1515 u32 sq_stack_resource_mgmt_2
= 0;
1517 /* FIXME: implement */
1518 switch (rdev
->family
) {
1520 rdev
->config
.r600
.max_pipes
= 4;
1521 rdev
->config
.r600
.max_tile_pipes
= 8;
1522 rdev
->config
.r600
.max_simds
= 4;
1523 rdev
->config
.r600
.max_backends
= 4;
1524 rdev
->config
.r600
.max_gprs
= 256;
1525 rdev
->config
.r600
.max_threads
= 192;
1526 rdev
->config
.r600
.max_stack_entries
= 256;
1527 rdev
->config
.r600
.max_hw_contexts
= 8;
1528 rdev
->config
.r600
.max_gs_threads
= 16;
1529 rdev
->config
.r600
.sx_max_export_size
= 128;
1530 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1531 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1532 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1536 rdev
->config
.r600
.max_pipes
= 2;
1537 rdev
->config
.r600
.max_tile_pipes
= 2;
1538 rdev
->config
.r600
.max_simds
= 3;
1539 rdev
->config
.r600
.max_backends
= 1;
1540 rdev
->config
.r600
.max_gprs
= 128;
1541 rdev
->config
.r600
.max_threads
= 192;
1542 rdev
->config
.r600
.max_stack_entries
= 128;
1543 rdev
->config
.r600
.max_hw_contexts
= 8;
1544 rdev
->config
.r600
.max_gs_threads
= 4;
1545 rdev
->config
.r600
.sx_max_export_size
= 128;
1546 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1547 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1548 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1554 rdev
->config
.r600
.max_pipes
= 1;
1555 rdev
->config
.r600
.max_tile_pipes
= 1;
1556 rdev
->config
.r600
.max_simds
= 2;
1557 rdev
->config
.r600
.max_backends
= 1;
1558 rdev
->config
.r600
.max_gprs
= 128;
1559 rdev
->config
.r600
.max_threads
= 192;
1560 rdev
->config
.r600
.max_stack_entries
= 128;
1561 rdev
->config
.r600
.max_hw_contexts
= 4;
1562 rdev
->config
.r600
.max_gs_threads
= 4;
1563 rdev
->config
.r600
.sx_max_export_size
= 128;
1564 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1565 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1566 rdev
->config
.r600
.sq_num_cf_insts
= 1;
1569 rdev
->config
.r600
.max_pipes
= 4;
1570 rdev
->config
.r600
.max_tile_pipes
= 4;
1571 rdev
->config
.r600
.max_simds
= 4;
1572 rdev
->config
.r600
.max_backends
= 4;
1573 rdev
->config
.r600
.max_gprs
= 192;
1574 rdev
->config
.r600
.max_threads
= 192;
1575 rdev
->config
.r600
.max_stack_entries
= 256;
1576 rdev
->config
.r600
.max_hw_contexts
= 8;
1577 rdev
->config
.r600
.max_gs_threads
= 16;
1578 rdev
->config
.r600
.sx_max_export_size
= 128;
1579 rdev
->config
.r600
.sx_max_export_pos_size
= 16;
1580 rdev
->config
.r600
.sx_max_export_smx_size
= 128;
1581 rdev
->config
.r600
.sq_num_cf_insts
= 2;
1587 /* Initialize HDP */
1588 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
1589 WREG32((0x2c14 + j
), 0x00000000);
1590 WREG32((0x2c18 + j
), 0x00000000);
1591 WREG32((0x2c1c + j
), 0x00000000);
1592 WREG32((0x2c20 + j
), 0x00000000);
1593 WREG32((0x2c24 + j
), 0x00000000);
1596 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
1600 ramcfg
= RREG32(RAMCFG
);
1601 switch (rdev
->config
.r600
.max_tile_pipes
) {
1603 tiling_config
|= PIPE_TILING(0);
1606 tiling_config
|= PIPE_TILING(1);
1609 tiling_config
|= PIPE_TILING(2);
1612 tiling_config
|= PIPE_TILING(3);
1617 rdev
->config
.r600
.tiling_npipes
= rdev
->config
.r600
.max_tile_pipes
;
1618 rdev
->config
.r600
.tiling_nbanks
= 4 << ((ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
1619 tiling_config
|= BANK_TILING((ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
1620 tiling_config
|= GROUP_SIZE((ramcfg
& BURSTLENGTH_MASK
) >> BURSTLENGTH_SHIFT
);
1621 if ((ramcfg
& BURSTLENGTH_MASK
) >> BURSTLENGTH_SHIFT
)
1622 rdev
->config
.r600
.tiling_group_size
= 512;
1624 rdev
->config
.r600
.tiling_group_size
= 256;
1625 tmp
= (ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
;
1627 tiling_config
|= ROW_TILING(3);
1628 tiling_config
|= SAMPLE_SPLIT(3);
1630 tiling_config
|= ROW_TILING(tmp
);
1631 tiling_config
|= SAMPLE_SPLIT(tmp
);
1633 tiling_config
|= BANK_SWAPS(1);
1635 cc_rb_backend_disable
= RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
1636 cc_rb_backend_disable
|=
1637 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK
<< rdev
->config
.r600
.max_backends
) & R6XX_MAX_BACKENDS_MASK
);
1639 cc_gc_shader_pipe_config
= RREG32(CC_GC_SHADER_PIPE_CONFIG
) & 0xffffff00;
1640 cc_gc_shader_pipe_config
|=
1641 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK
<< rdev
->config
.r600
.max_pipes
) & R6XX_MAX_PIPES_MASK
);
1642 cc_gc_shader_pipe_config
|=
1643 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK
<< rdev
->config
.r600
.max_simds
) & R6XX_MAX_SIMDS_MASK
);
1645 backend_map
= r600_get_tile_pipe_to_backend_map(rdev
->config
.r600
.max_tile_pipes
,
1646 (R6XX_MAX_BACKENDS
-
1647 r600_count_pipe_bits((cc_rb_backend_disable
&
1648 R6XX_MAX_BACKENDS_MASK
) >> 16)),
1649 (cc_rb_backend_disable
>> 16));
1650 rdev
->config
.r600
.tile_config
= tiling_config
;
1651 tiling_config
|= BACKEND_MAP(backend_map
);
1652 WREG32(GB_TILING_CONFIG
, tiling_config
);
1653 WREG32(DCP_TILING_CONFIG
, tiling_config
& 0xffff);
1654 WREG32(HDP_TILING_CONFIG
, tiling_config
& 0xffff);
1657 WREG32(CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
1658 WREG32(CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
1659 WREG32(GC_USER_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
1661 tmp
= R6XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& INACTIVE_QD_PIPES_MASK
) >> 8);
1662 WREG32(VGT_OUT_DEALLOC_CNTL
, (tmp
* 4) & DEALLOC_DIST_MASK
);
1663 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, ((tmp
* 4) - 2) & VTX_REUSE_DEPTH_MASK
);
1665 /* Setup some CP states */
1666 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1667 WREG32(CP_MEQ_THRESHOLDS
, (MEQ_END(0x40) | ROQ_END(0x40)));
1669 WREG32(TA_CNTL_AUX
, (DISABLE_CUBE_ANISO
| SYNC_GRADIENT
|
1670 SYNC_WALKER
| SYNC_ALIGNER
));
1671 /* Setup various GPU states */
1672 if (rdev
->family
== CHIP_RV670
)
1673 WREG32(ARB_GDEC_RD_CNTL
, 0x00000021);
1675 tmp
= RREG32(SX_DEBUG_1
);
1676 tmp
|= SMX_EVENT_RELEASE
;
1677 if ((rdev
->family
> CHIP_R600
))
1678 tmp
|= ENABLE_NEW_SMX_ADDRESS
;
1679 WREG32(SX_DEBUG_1
, tmp
);
1681 if (((rdev
->family
) == CHIP_R600
) ||
1682 ((rdev
->family
) == CHIP_RV630
) ||
1683 ((rdev
->family
) == CHIP_RV610
) ||
1684 ((rdev
->family
) == CHIP_RV620
) ||
1685 ((rdev
->family
) == CHIP_RS780
) ||
1686 ((rdev
->family
) == CHIP_RS880
)) {
1687 WREG32(DB_DEBUG
, PREZ_MUST_WAIT_FOR_POSTZ_DONE
);
1689 WREG32(DB_DEBUG
, 0);
1691 WREG32(DB_WATERMARKS
, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1692 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1694 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
1695 WREG32(VGT_NUM_INSTANCES
, 0);
1697 WREG32(SPI_CONFIG_CNTL
, GPR_WRITE_PRIORITY(0));
1698 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(0));
1700 tmp
= RREG32(SQ_MS_FIFO_SIZES
);
1701 if (((rdev
->family
) == CHIP_RV610
) ||
1702 ((rdev
->family
) == CHIP_RV620
) ||
1703 ((rdev
->family
) == CHIP_RS780
) ||
1704 ((rdev
->family
) == CHIP_RS880
)) {
1705 tmp
= (CACHE_FIFO_SIZE(0xa) |
1706 FETCH_FIFO_HIWATER(0xa) |
1707 DONE_FIFO_HIWATER(0xe0) |
1708 ALU_UPDATE_FIFO_HIWATER(0x8));
1709 } else if (((rdev
->family
) == CHIP_R600
) ||
1710 ((rdev
->family
) == CHIP_RV630
)) {
1711 tmp
&= ~DONE_FIFO_HIWATER(0xff);
1712 tmp
|= DONE_FIFO_HIWATER(0x4);
1714 WREG32(SQ_MS_FIFO_SIZES
, tmp
);
1716 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1717 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1719 sq_config
= RREG32(SQ_CONFIG
);
1720 sq_config
&= ~(PS_PRIO(3) |
1724 sq_config
|= (DX9_CONSTS
|
1731 if ((rdev
->family
) == CHIP_R600
) {
1732 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(124) |
1734 NUM_CLAUSE_TEMP_GPRS(4));
1735 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(0) |
1737 sq_thread_resource_mgmt
= (NUM_PS_THREADS(136) |
1738 NUM_VS_THREADS(48) |
1741 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(128) |
1742 NUM_VS_STACK_ENTRIES(128));
1743 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(0) |
1744 NUM_ES_STACK_ENTRIES(0));
1745 } else if (((rdev
->family
) == CHIP_RV610
) ||
1746 ((rdev
->family
) == CHIP_RV620
) ||
1747 ((rdev
->family
) == CHIP_RS780
) ||
1748 ((rdev
->family
) == CHIP_RS880
)) {
1749 /* no vertex cache */
1750 sq_config
&= ~VC_ENABLE
;
1752 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1754 NUM_CLAUSE_TEMP_GPRS(2));
1755 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1757 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1758 NUM_VS_THREADS(78) |
1760 NUM_ES_THREADS(31));
1761 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1762 NUM_VS_STACK_ENTRIES(40));
1763 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1764 NUM_ES_STACK_ENTRIES(16));
1765 } else if (((rdev
->family
) == CHIP_RV630
) ||
1766 ((rdev
->family
) == CHIP_RV635
)) {
1767 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1769 NUM_CLAUSE_TEMP_GPRS(2));
1770 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(18) |
1772 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1773 NUM_VS_THREADS(78) |
1775 NUM_ES_THREADS(31));
1776 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(40) |
1777 NUM_VS_STACK_ENTRIES(40));
1778 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(32) |
1779 NUM_ES_STACK_ENTRIES(16));
1780 } else if ((rdev
->family
) == CHIP_RV670
) {
1781 sq_gpr_resource_mgmt_1
= (NUM_PS_GPRS(44) |
1783 NUM_CLAUSE_TEMP_GPRS(2));
1784 sq_gpr_resource_mgmt_2
= (NUM_GS_GPRS(17) |
1786 sq_thread_resource_mgmt
= (NUM_PS_THREADS(79) |
1787 NUM_VS_THREADS(78) |
1789 NUM_ES_THREADS(31));
1790 sq_stack_resource_mgmt_1
= (NUM_PS_STACK_ENTRIES(64) |
1791 NUM_VS_STACK_ENTRIES(64));
1792 sq_stack_resource_mgmt_2
= (NUM_GS_STACK_ENTRIES(64) |
1793 NUM_ES_STACK_ENTRIES(64));
1796 WREG32(SQ_CONFIG
, sq_config
);
1797 WREG32(SQ_GPR_RESOURCE_MGMT_1
, sq_gpr_resource_mgmt_1
);
1798 WREG32(SQ_GPR_RESOURCE_MGMT_2
, sq_gpr_resource_mgmt_2
);
1799 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
1800 WREG32(SQ_STACK_RESOURCE_MGMT_1
, sq_stack_resource_mgmt_1
);
1801 WREG32(SQ_STACK_RESOURCE_MGMT_2
, sq_stack_resource_mgmt_2
);
1803 if (((rdev
->family
) == CHIP_RV610
) ||
1804 ((rdev
->family
) == CHIP_RV620
) ||
1805 ((rdev
->family
) == CHIP_RS780
) ||
1806 ((rdev
->family
) == CHIP_RS880
)) {
1807 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(TC_ONLY
));
1809 WREG32(VGT_CACHE_INVALIDATION
, CACHE_INVALIDATION(VC_AND_TC
));
1812 /* More default values. 2D/3D driver should adjust as needed */
1813 WREG32(PA_SC_AA_SAMPLE_LOCS_2S
, (S0_X(0xc) | S0_Y(0x4) |
1814 S1_X(0x4) | S1_Y(0xc)));
1815 WREG32(PA_SC_AA_SAMPLE_LOCS_4S
, (S0_X(0xe) | S0_Y(0xe) |
1816 S1_X(0x2) | S1_Y(0x2) |
1817 S2_X(0xa) | S2_Y(0x6) |
1818 S3_X(0x6) | S3_Y(0xa)));
1819 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0
, (S0_X(0xe) | S0_Y(0xb) |
1820 S1_X(0x4) | S1_Y(0xc) |
1821 S2_X(0x1) | S2_Y(0x6) |
1822 S3_X(0xa) | S3_Y(0xe)));
1823 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1
, (S4_X(0x6) | S4_Y(0x1) |
1824 S5_X(0x0) | S5_Y(0x0) |
1825 S6_X(0xb) | S6_Y(0x4) |
1826 S7_X(0x7) | S7_Y(0x8)));
1828 WREG32(VGT_STRMOUT_EN
, 0);
1829 tmp
= rdev
->config
.r600
.max_pipes
* 16;
1830 switch (rdev
->family
) {
1846 WREG32(VGT_ES_PER_GS
, 128);
1847 WREG32(VGT_GS_PER_ES
, tmp
);
1848 WREG32(VGT_GS_PER_VS
, 2);
1849 WREG32(VGT_GS_VERTEX_REUSE
, 16);
1851 /* more default values. 2D/3D driver should adjust as needed */
1852 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
1853 WREG32(VGT_STRMOUT_EN
, 0);
1855 WREG32(PA_SC_MODE_CNTL
, 0);
1856 WREG32(PA_SC_AA_CONFIG
, 0);
1857 WREG32(PA_SC_LINE_STIPPLE
, 0);
1858 WREG32(SPI_INPUT_Z
, 0);
1859 WREG32(SPI_PS_IN_CONTROL_0
, NUM_INTERP(2));
1860 WREG32(CB_COLOR7_FRAG
, 0);
1862 /* Clear render buffer base addresses */
1863 WREG32(CB_COLOR0_BASE
, 0);
1864 WREG32(CB_COLOR1_BASE
, 0);
1865 WREG32(CB_COLOR2_BASE
, 0);
1866 WREG32(CB_COLOR3_BASE
, 0);
1867 WREG32(CB_COLOR4_BASE
, 0);
1868 WREG32(CB_COLOR5_BASE
, 0);
1869 WREG32(CB_COLOR6_BASE
, 0);
1870 WREG32(CB_COLOR7_BASE
, 0);
1871 WREG32(CB_COLOR7_FRAG
, 0);
1873 switch (rdev
->family
) {
1878 tmp
= TC_L2_SIZE(8);
1882 tmp
= TC_L2_SIZE(4);
1885 tmp
= TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT
;
1888 tmp
= TC_L2_SIZE(0);
1891 WREG32(TC_CNTL
, tmp
);
1893 tmp
= RREG32(HDP_HOST_PATH_CNTL
);
1894 WREG32(HDP_HOST_PATH_CNTL
, tmp
);
1896 tmp
= RREG32(ARB_POP
);
1897 tmp
|= ENABLE_TC128
;
1898 WREG32(ARB_POP
, tmp
);
1900 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
1901 WREG32(PA_CL_ENHANCE
, (CLIP_VTX_REORDER_ENA
|
1903 WREG32(PA_SC_ENHANCE
, FORCE_EOV_MAX_CLK_CNT(4095));
1908 * Indirect registers accessor
1910 u32
r600_pciep_rreg(struct radeon_device
*rdev
, u32 reg
)
1914 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
1915 (void)RREG32(PCIE_PORT_INDEX
);
1916 r
= RREG32(PCIE_PORT_DATA
);
1920 void r600_pciep_wreg(struct radeon_device
*rdev
, u32 reg
, u32 v
)
1922 WREG32(PCIE_PORT_INDEX
, ((reg
) & 0xff));
1923 (void)RREG32(PCIE_PORT_INDEX
);
1924 WREG32(PCIE_PORT_DATA
, (v
));
1925 (void)RREG32(PCIE_PORT_DATA
);
1931 void r600_cp_stop(struct radeon_device
*rdev
)
1933 rdev
->mc
.active_vram_size
= rdev
->mc
.visible_vram_size
;
1934 WREG32(R_0086D8_CP_ME_CNTL
, S_0086D8_CP_ME_HALT(1));
1935 WREG32(SCRATCH_UMSK
, 0);
1938 int r600_init_microcode(struct radeon_device
*rdev
)
1940 struct platform_device
*pdev
;
1941 const char *chip_name
;
1942 const char *rlc_chip_name
;
1943 size_t pfp_req_size
, me_req_size
, rlc_req_size
;
1949 pdev
= platform_device_register_simple("radeon_cp", 0, NULL
, 0);
1952 printk(KERN_ERR
"radeon_cp: Failed to register firmware\n");
1956 switch (rdev
->family
) {
1959 rlc_chip_name
= "R600";
1962 chip_name
= "RV610";
1963 rlc_chip_name
= "R600";
1966 chip_name
= "RV630";
1967 rlc_chip_name
= "R600";
1970 chip_name
= "RV620";
1971 rlc_chip_name
= "R600";
1974 chip_name
= "RV635";
1975 rlc_chip_name
= "R600";
1978 chip_name
= "RV670";
1979 rlc_chip_name
= "R600";
1983 chip_name
= "RS780";
1984 rlc_chip_name
= "R600";
1987 chip_name
= "RV770";
1988 rlc_chip_name
= "R700";
1992 chip_name
= "RV730";
1993 rlc_chip_name
= "R700";
1996 chip_name
= "RV710";
1997 rlc_chip_name
= "R700";
2000 chip_name
= "CEDAR";
2001 rlc_chip_name
= "CEDAR";
2004 chip_name
= "REDWOOD";
2005 rlc_chip_name
= "REDWOOD";
2008 chip_name
= "JUNIPER";
2009 rlc_chip_name
= "JUNIPER";
2013 chip_name
= "CYPRESS";
2014 rlc_chip_name
= "CYPRESS";
2018 rlc_chip_name
= "SUMO";
2023 if (rdev
->family
>= CHIP_CEDAR
) {
2024 pfp_req_size
= EVERGREEN_PFP_UCODE_SIZE
* 4;
2025 me_req_size
= EVERGREEN_PM4_UCODE_SIZE
* 4;
2026 rlc_req_size
= EVERGREEN_RLC_UCODE_SIZE
* 4;
2027 } else if (rdev
->family
>= CHIP_RV770
) {
2028 pfp_req_size
= R700_PFP_UCODE_SIZE
* 4;
2029 me_req_size
= R700_PM4_UCODE_SIZE
* 4;
2030 rlc_req_size
= R700_RLC_UCODE_SIZE
* 4;
2032 pfp_req_size
= PFP_UCODE_SIZE
* 4;
2033 me_req_size
= PM4_UCODE_SIZE
* 12;
2034 rlc_req_size
= RLC_UCODE_SIZE
* 4;
2037 DRM_INFO("Loading %s Microcode\n", chip_name
);
2039 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_pfp.bin", chip_name
);
2040 err
= request_firmware(&rdev
->pfp_fw
, fw_name
, &pdev
->dev
);
2043 if (rdev
->pfp_fw
->size
!= pfp_req_size
) {
2045 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2046 rdev
->pfp_fw
->size
, fw_name
);
2051 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_me.bin", chip_name
);
2052 err
= request_firmware(&rdev
->me_fw
, fw_name
, &pdev
->dev
);
2055 if (rdev
->me_fw
->size
!= me_req_size
) {
2057 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2058 rdev
->me_fw
->size
, fw_name
);
2062 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_rlc.bin", rlc_chip_name
);
2063 err
= request_firmware(&rdev
->rlc_fw
, fw_name
, &pdev
->dev
);
2066 if (rdev
->rlc_fw
->size
!= rlc_req_size
) {
2068 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2069 rdev
->rlc_fw
->size
, fw_name
);
2074 platform_device_unregister(pdev
);
2079 "r600_cp: Failed to load firmware \"%s\"\n",
2081 release_firmware(rdev
->pfp_fw
);
2082 rdev
->pfp_fw
= NULL
;
2083 release_firmware(rdev
->me_fw
);
2085 release_firmware(rdev
->rlc_fw
);
2086 rdev
->rlc_fw
= NULL
;
2091 static int r600_cp_load_microcode(struct radeon_device
*rdev
)
2093 const __be32
*fw_data
;
2096 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
2101 WREG32(CP_RB_CNTL
, RB_NO_UPDATE
| RB_BLKSZ(15) | RB_BUFSZ(3));
2104 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
2105 RREG32(GRBM_SOFT_RESET
);
2107 WREG32(GRBM_SOFT_RESET
, 0);
2109 WREG32(CP_ME_RAM_WADDR
, 0);
2111 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
2112 WREG32(CP_ME_RAM_WADDR
, 0);
2113 for (i
= 0; i
< PM4_UCODE_SIZE
* 3; i
++)
2114 WREG32(CP_ME_RAM_DATA
,
2115 be32_to_cpup(fw_data
++));
2117 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
2118 WREG32(CP_PFP_UCODE_ADDR
, 0);
2119 for (i
= 0; i
< PFP_UCODE_SIZE
; i
++)
2120 WREG32(CP_PFP_UCODE_DATA
,
2121 be32_to_cpup(fw_data
++));
2123 WREG32(CP_PFP_UCODE_ADDR
, 0);
2124 WREG32(CP_ME_RAM_WADDR
, 0);
2125 WREG32(CP_ME_RAM_RADDR
, 0);
2129 int r600_cp_start(struct radeon_device
*rdev
)
2134 r
= radeon_ring_lock(rdev
, 7);
2136 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
2139 radeon_ring_write(rdev
, PACKET3(PACKET3_ME_INITIALIZE
, 5));
2140 radeon_ring_write(rdev
, 0x1);
2141 if (rdev
->family
>= CHIP_RV770
) {
2142 radeon_ring_write(rdev
, 0x0);
2143 radeon_ring_write(rdev
, rdev
->config
.rv770
.max_hw_contexts
- 1);
2145 radeon_ring_write(rdev
, 0x3);
2146 radeon_ring_write(rdev
, rdev
->config
.r600
.max_hw_contexts
- 1);
2148 radeon_ring_write(rdev
, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2149 radeon_ring_write(rdev
, 0);
2150 radeon_ring_write(rdev
, 0);
2151 radeon_ring_unlock_commit(rdev
);
2154 WREG32(R_0086D8_CP_ME_CNTL
, cp_me
);
2158 int r600_cp_resume(struct radeon_device
*rdev
)
2165 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
2166 RREG32(GRBM_SOFT_RESET
);
2168 WREG32(GRBM_SOFT_RESET
, 0);
2170 /* Set ring buffer size */
2171 rb_bufsz
= drm_order(rdev
->cp
.ring_size
/ 8);
2172 tmp
= (drm_order(RADEON_GPU_PAGE_SIZE
/8) << 8) | rb_bufsz
;
2174 tmp
|= BUF_SWAP_32BIT
;
2176 WREG32(CP_RB_CNTL
, tmp
);
2177 WREG32(CP_SEM_WAIT_TIMER
, 0x4);
2179 /* Set the write pointer delay */
2180 WREG32(CP_RB_WPTR_DELAY
, 0);
2182 /* Initialize the ring buffer's read and write pointers */
2183 WREG32(CP_RB_CNTL
, tmp
| RB_RPTR_WR_ENA
);
2184 WREG32(CP_RB_RPTR_WR
, 0);
2185 WREG32(CP_RB_WPTR
, 0);
2187 /* set the wb address whether it's enabled or not */
2188 WREG32(CP_RB_RPTR_ADDR
, (rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFFFFFFFC);
2189 WREG32(CP_RB_RPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ RADEON_WB_CP_RPTR_OFFSET
) & 0xFF);
2190 WREG32(SCRATCH_ADDR
, ((rdev
->wb
.gpu_addr
+ RADEON_WB_SCRATCH_OFFSET
) >> 8) & 0xFFFFFFFF);
2192 if (rdev
->wb
.enabled
)
2193 WREG32(SCRATCH_UMSK
, 0xff);
2195 tmp
|= RB_NO_UPDATE
;
2196 WREG32(SCRATCH_UMSK
, 0);
2200 WREG32(CP_RB_CNTL
, tmp
);
2202 WREG32(CP_RB_BASE
, rdev
->cp
.gpu_addr
>> 8);
2203 WREG32(CP_DEBUG
, (1 << 27) | (1 << 28));
2205 rdev
->cp
.rptr
= RREG32(CP_RB_RPTR
);
2206 rdev
->cp
.wptr
= RREG32(CP_RB_WPTR
);
2208 r600_cp_start(rdev
);
2209 rdev
->cp
.ready
= true;
2210 r
= radeon_ring_test(rdev
);
2212 rdev
->cp
.ready
= false;
2218 void r600_cp_commit(struct radeon_device
*rdev
)
2220 WREG32(CP_RB_WPTR
, rdev
->cp
.wptr
);
2221 (void)RREG32(CP_RB_WPTR
);
2224 void r600_ring_init(struct radeon_device
*rdev
, unsigned ring_size
)
2228 /* Align ring size */
2229 rb_bufsz
= drm_order(ring_size
/ 8);
2230 ring_size
= (1 << (rb_bufsz
+ 1)) * 4;
2231 rdev
->cp
.ring_size
= ring_size
;
2232 rdev
->cp
.align_mask
= 16 - 1;
2235 void r600_cp_fini(struct radeon_device
*rdev
)
2238 radeon_ring_fini(rdev
);
2243 * GPU scratch registers helpers function.
2245 void r600_scratch_init(struct radeon_device
*rdev
)
2249 rdev
->scratch
.num_reg
= 7;
2250 rdev
->scratch
.reg_base
= SCRATCH_REG0
;
2251 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
2252 rdev
->scratch
.free
[i
] = true;
2253 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
2257 int r600_ring_test(struct radeon_device
*rdev
)
2264 r
= radeon_scratch_get(rdev
, &scratch
);
2266 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r
);
2269 WREG32(scratch
, 0xCAFEDEAD);
2270 r
= radeon_ring_lock(rdev
, 3);
2272 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
2273 radeon_scratch_free(rdev
, scratch
);
2276 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2277 radeon_ring_write(rdev
, ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
2278 radeon_ring_write(rdev
, 0xDEADBEEF);
2279 radeon_ring_unlock_commit(rdev
);
2280 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2281 tmp
= RREG32(scratch
);
2282 if (tmp
== 0xDEADBEEF)
2286 if (i
< rdev
->usec_timeout
) {
2287 DRM_INFO("ring test succeeded in %d usecs\n", i
);
2289 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2293 radeon_scratch_free(rdev
, scratch
);
2297 void r600_fence_ring_emit(struct radeon_device
*rdev
,
2298 struct radeon_fence
*fence
)
2300 if (rdev
->wb
.use_event
) {
2301 u64 addr
= rdev
->wb
.gpu_addr
+ R600_WB_EVENT_OFFSET
+
2302 (u64
)(rdev
->fence_drv
.scratch_reg
- rdev
->scratch
.reg_base
);
2303 /* EVENT_WRITE_EOP - flush caches, send int */
2304 radeon_ring_write(rdev
, PACKET3(PACKET3_EVENT_WRITE_EOP
, 4));
2305 radeon_ring_write(rdev
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS
) | EVENT_INDEX(5));
2306 radeon_ring_write(rdev
, addr
& 0xffffffff);
2307 radeon_ring_write(rdev
, (upper_32_bits(addr
) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2308 radeon_ring_write(rdev
, fence
->seq
);
2309 radeon_ring_write(rdev
, 0);
2311 radeon_ring_write(rdev
, PACKET3(PACKET3_EVENT_WRITE
, 0));
2312 radeon_ring_write(rdev
, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT
) | EVENT_INDEX(0));
2313 /* wait for 3D idle clean */
2314 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2315 radeon_ring_write(rdev
, (WAIT_UNTIL
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
2316 radeon_ring_write(rdev
, WAIT_3D_IDLE_bit
| WAIT_3D_IDLECLEAN_bit
);
2317 /* Emit fence sequence & fire IRQ */
2318 radeon_ring_write(rdev
, PACKET3(PACKET3_SET_CONFIG_REG
, 1));
2319 radeon_ring_write(rdev
, ((rdev
->fence_drv
.scratch_reg
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2));
2320 radeon_ring_write(rdev
, fence
->seq
);
2321 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2322 radeon_ring_write(rdev
, PACKET0(CP_INT_STATUS
, 0));
2323 radeon_ring_write(rdev
, RB_INT_STAT
);
2327 int r600_copy_blit(struct radeon_device
*rdev
,
2328 uint64_t src_offset
, uint64_t dst_offset
,
2329 unsigned num_pages
, struct radeon_fence
*fence
)
2333 mutex_lock(&rdev
->r600_blit
.mutex
);
2334 rdev
->r600_blit
.vb_ib
= NULL
;
2335 r
= r600_blit_prepare_copy(rdev
, num_pages
* RADEON_GPU_PAGE_SIZE
);
2337 if (rdev
->r600_blit
.vb_ib
)
2338 radeon_ib_free(rdev
, &rdev
->r600_blit
.vb_ib
);
2339 mutex_unlock(&rdev
->r600_blit
.mutex
);
2342 r600_kms_blit_copy(rdev
, src_offset
, dst_offset
, num_pages
* RADEON_GPU_PAGE_SIZE
);
2343 r600_blit_done_copy(rdev
, fence
);
2344 mutex_unlock(&rdev
->r600_blit
.mutex
);
2348 int r600_set_surface_reg(struct radeon_device
*rdev
, int reg
,
2349 uint32_t tiling_flags
, uint32_t pitch
,
2350 uint32_t offset
, uint32_t obj_size
)
2352 /* FIXME: implement */
2356 void r600_clear_surface_reg(struct radeon_device
*rdev
, int reg
)
2358 /* FIXME: implement */
2362 bool r600_card_posted(struct radeon_device
*rdev
)
2366 /* first check CRTCs */
2367 reg
= RREG32(D1CRTC_CONTROL
) |
2368 RREG32(D2CRTC_CONTROL
);
2372 /* then check MEM_SIZE, in case the crtcs are off */
2373 if (RREG32(CONFIG_MEMSIZE
))
2379 int r600_startup(struct radeon_device
*rdev
)
2383 /* enable pcie gen2 link */
2384 r600_pcie_gen2_enable(rdev
);
2386 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
2387 r
= r600_init_microcode(rdev
);
2389 DRM_ERROR("Failed to load firmware!\n");
2394 r600_mc_program(rdev
);
2395 if (rdev
->flags
& RADEON_IS_AGP
) {
2396 r600_agp_enable(rdev
);
2398 r
= r600_pcie_gart_enable(rdev
);
2402 r600_gpu_init(rdev
);
2403 r
= r600_blit_init(rdev
);
2405 r600_blit_fini(rdev
);
2406 rdev
->asic
->copy
= NULL
;
2407 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
2410 /* allocate wb buffer */
2411 r
= radeon_wb_init(rdev
);
2416 r
= r600_irq_init(rdev
);
2418 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
2419 radeon_irq_kms_fini(rdev
);
2424 r
= radeon_ring_init(rdev
, rdev
->cp
.ring_size
);
2427 r
= r600_cp_load_microcode(rdev
);
2430 r
= r600_cp_resume(rdev
);
2437 void r600_vga_set_state(struct radeon_device
*rdev
, bool state
)
2441 temp
= RREG32(CONFIG_CNTL
);
2442 if (state
== false) {
2448 WREG32(CONFIG_CNTL
, temp
);
2451 int r600_resume(struct radeon_device
*rdev
)
2455 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2456 * posting will perform necessary task to bring back GPU into good
2460 atom_asic_init(rdev
->mode_info
.atom_context
);
2462 r
= r600_startup(rdev
);
2464 DRM_ERROR("r600 startup failed on resume\n");
2468 r
= r600_ib_test(rdev
);
2470 DRM_ERROR("radeon: failled testing IB (%d).\n", r
);
2474 r
= r600_audio_init(rdev
);
2476 DRM_ERROR("radeon: audio resume failed\n");
2483 int r600_suspend(struct radeon_device
*rdev
)
2487 r600_audio_fini(rdev
);
2488 /* FIXME: we should wait for ring to be empty */
2490 rdev
->cp
.ready
= false;
2491 r600_irq_suspend(rdev
);
2492 radeon_wb_disable(rdev
);
2493 r600_pcie_gart_disable(rdev
);
2494 /* unpin shaders bo */
2495 if (rdev
->r600_blit
.shader_obj
) {
2496 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
2498 radeon_bo_unpin(rdev
->r600_blit
.shader_obj
);
2499 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
2505 /* Plan is to move initialization in that function and use
2506 * helper function so that radeon_device_init pretty much
2507 * do nothing more than calling asic specific function. This
2508 * should also allow to remove a bunch of callback function
2511 int r600_init(struct radeon_device
*rdev
)
2515 r
= radeon_dummy_page_init(rdev
);
2518 if (r600_debugfs_mc_info_init(rdev
)) {
2519 DRM_ERROR("Failed to register debugfs file for mc !\n");
2521 /* This don't do much */
2522 r
= radeon_gem_init(rdev
);
2526 if (!radeon_get_bios(rdev
)) {
2527 if (ASIC_IS_AVIVO(rdev
))
2530 /* Must be an ATOMBIOS */
2531 if (!rdev
->is_atom_bios
) {
2532 dev_err(rdev
->dev
, "Expecting atombios for R600 GPU\n");
2535 r
= radeon_atombios_init(rdev
);
2538 /* Post card if necessary */
2539 if (!r600_card_posted(rdev
)) {
2541 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
2544 DRM_INFO("GPU not posted. posting now...\n");
2545 atom_asic_init(rdev
->mode_info
.atom_context
);
2547 /* Initialize scratch registers */
2548 r600_scratch_init(rdev
);
2549 /* Initialize surface registers */
2550 radeon_surface_init(rdev
);
2551 /* Initialize clocks */
2552 radeon_get_clock_info(rdev
->ddev
);
2554 r
= radeon_fence_driver_init(rdev
);
2557 if (rdev
->flags
& RADEON_IS_AGP
) {
2558 r
= radeon_agp_init(rdev
);
2560 radeon_agp_disable(rdev
);
2562 r
= r600_mc_init(rdev
);
2565 /* Memory manager */
2566 r
= radeon_bo_init(rdev
);
2570 r
= radeon_irq_kms_init(rdev
);
2574 rdev
->cp
.ring_obj
= NULL
;
2575 r600_ring_init(rdev
, 1024 * 1024);
2577 rdev
->ih
.ring_obj
= NULL
;
2578 r600_ih_ring_init(rdev
, 64 * 1024);
2580 r
= r600_pcie_gart_init(rdev
);
2584 rdev
->accel_working
= true;
2585 r
= r600_startup(rdev
);
2587 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
2589 r600_irq_fini(rdev
);
2590 radeon_wb_fini(rdev
);
2591 radeon_irq_kms_fini(rdev
);
2592 r600_pcie_gart_fini(rdev
);
2593 rdev
->accel_working
= false;
2595 if (rdev
->accel_working
) {
2596 r
= radeon_ib_pool_init(rdev
);
2598 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
2599 rdev
->accel_working
= false;
2601 r
= r600_ib_test(rdev
);
2603 dev_err(rdev
->dev
, "IB test failed (%d).\n", r
);
2604 rdev
->accel_working
= false;
2609 r
= r600_audio_init(rdev
);
2611 return r
; /* TODO error handling */
2615 void r600_fini(struct radeon_device
*rdev
)
2617 r600_audio_fini(rdev
);
2618 r600_blit_fini(rdev
);
2620 r600_irq_fini(rdev
);
2621 radeon_wb_fini(rdev
);
2622 radeon_irq_kms_fini(rdev
);
2623 r600_pcie_gart_fini(rdev
);
2624 radeon_agp_fini(rdev
);
2625 radeon_gem_fini(rdev
);
2626 radeon_fence_driver_fini(rdev
);
2627 radeon_bo_fini(rdev
);
2628 radeon_atombios_fini(rdev
);
2631 radeon_dummy_page_fini(rdev
);
2638 void r600_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
2640 /* FIXME: implement */
2641 radeon_ring_write(rdev
, PACKET3(PACKET3_INDIRECT_BUFFER
, 2));
2642 radeon_ring_write(rdev
, ib
->gpu_addr
& 0xFFFFFFFC);
2643 radeon_ring_write(rdev
, upper_32_bits(ib
->gpu_addr
) & 0xFF);
2644 radeon_ring_write(rdev
, ib
->length_dw
);
2647 int r600_ib_test(struct radeon_device
*rdev
)
2649 struct radeon_ib
*ib
;
2655 r
= radeon_scratch_get(rdev
, &scratch
);
2657 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r
);
2660 WREG32(scratch
, 0xCAFEDEAD);
2661 r
= radeon_ib_get(rdev
, &ib
);
2663 DRM_ERROR("radeon: failed to get ib (%d).\n", r
);
2666 ib
->ptr
[0] = PACKET3(PACKET3_SET_CONFIG_REG
, 1);
2667 ib
->ptr
[1] = ((scratch
- PACKET3_SET_CONFIG_REG_OFFSET
) >> 2);
2668 ib
->ptr
[2] = 0xDEADBEEF;
2669 ib
->ptr
[3] = PACKET2(0);
2670 ib
->ptr
[4] = PACKET2(0);
2671 ib
->ptr
[5] = PACKET2(0);
2672 ib
->ptr
[6] = PACKET2(0);
2673 ib
->ptr
[7] = PACKET2(0);
2674 ib
->ptr
[8] = PACKET2(0);
2675 ib
->ptr
[9] = PACKET2(0);
2676 ib
->ptr
[10] = PACKET2(0);
2677 ib
->ptr
[11] = PACKET2(0);
2678 ib
->ptr
[12] = PACKET2(0);
2679 ib
->ptr
[13] = PACKET2(0);
2680 ib
->ptr
[14] = PACKET2(0);
2681 ib
->ptr
[15] = PACKET2(0);
2683 r
= radeon_ib_schedule(rdev
, ib
);
2685 radeon_scratch_free(rdev
, scratch
);
2686 radeon_ib_free(rdev
, &ib
);
2687 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r
);
2690 r
= radeon_fence_wait(ib
->fence
, false);
2692 DRM_ERROR("radeon: fence wait failed (%d).\n", r
);
2695 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
2696 tmp
= RREG32(scratch
);
2697 if (tmp
== 0xDEADBEEF)
2701 if (i
< rdev
->usec_timeout
) {
2702 DRM_INFO("ib test succeeded in %u usecs\n", i
);
2704 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2708 radeon_scratch_free(rdev
, scratch
);
2709 radeon_ib_free(rdev
, &ib
);
2716 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2717 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2718 * writing to the ring and the GPU consuming, the GPU writes to the ring
2719 * and host consumes. As the host irq handler processes interrupts, it
2720 * increments the rptr. When the rptr catches up with the wptr, all the
2721 * current interrupts have been processed.
2724 void r600_ih_ring_init(struct radeon_device
*rdev
, unsigned ring_size
)
2728 /* Align ring size */
2729 rb_bufsz
= drm_order(ring_size
/ 4);
2730 ring_size
= (1 << rb_bufsz
) * 4;
2731 rdev
->ih
.ring_size
= ring_size
;
2732 rdev
->ih
.ptr_mask
= rdev
->ih
.ring_size
- 1;
2736 static int r600_ih_ring_alloc(struct radeon_device
*rdev
)
2740 /* Allocate ring buffer */
2741 if (rdev
->ih
.ring_obj
== NULL
) {
2742 r
= radeon_bo_create(rdev
, NULL
, rdev
->ih
.ring_size
,
2744 RADEON_GEM_DOMAIN_GTT
,
2745 &rdev
->ih
.ring_obj
);
2747 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r
);
2750 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
2751 if (unlikely(r
!= 0))
2753 r
= radeon_bo_pin(rdev
->ih
.ring_obj
,
2754 RADEON_GEM_DOMAIN_GTT
,
2755 &rdev
->ih
.gpu_addr
);
2757 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2758 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r
);
2761 r
= radeon_bo_kmap(rdev
->ih
.ring_obj
,
2762 (void **)&rdev
->ih
.ring
);
2763 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2765 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r
);
2772 static void r600_ih_ring_fini(struct radeon_device
*rdev
)
2775 if (rdev
->ih
.ring_obj
) {
2776 r
= radeon_bo_reserve(rdev
->ih
.ring_obj
, false);
2777 if (likely(r
== 0)) {
2778 radeon_bo_kunmap(rdev
->ih
.ring_obj
);
2779 radeon_bo_unpin(rdev
->ih
.ring_obj
);
2780 radeon_bo_unreserve(rdev
->ih
.ring_obj
);
2782 radeon_bo_unref(&rdev
->ih
.ring_obj
);
2783 rdev
->ih
.ring
= NULL
;
2784 rdev
->ih
.ring_obj
= NULL
;
2788 void r600_rlc_stop(struct radeon_device
*rdev
)
2791 if ((rdev
->family
>= CHIP_RV770
) &&
2792 (rdev
->family
<= CHIP_RV740
)) {
2793 /* r7xx asics need to soft reset RLC before halting */
2794 WREG32(SRBM_SOFT_RESET
, SOFT_RESET_RLC
);
2795 RREG32(SRBM_SOFT_RESET
);
2797 WREG32(SRBM_SOFT_RESET
, 0);
2798 RREG32(SRBM_SOFT_RESET
);
2801 WREG32(RLC_CNTL
, 0);
2804 static void r600_rlc_start(struct radeon_device
*rdev
)
2806 WREG32(RLC_CNTL
, RLC_ENABLE
);
2809 static int r600_rlc_init(struct radeon_device
*rdev
)
2812 const __be32
*fw_data
;
2817 r600_rlc_stop(rdev
);
2819 WREG32(RLC_HB_BASE
, 0);
2820 WREG32(RLC_HB_CNTL
, 0);
2821 WREG32(RLC_HB_RPTR
, 0);
2822 WREG32(RLC_HB_WPTR
, 0);
2823 WREG32(RLC_HB_WPTR_LSB_ADDR
, 0);
2824 WREG32(RLC_HB_WPTR_MSB_ADDR
, 0);
2825 WREG32(RLC_MC_CNTL
, 0);
2826 WREG32(RLC_UCODE_CNTL
, 0);
2828 fw_data
= (const __be32
*)rdev
->rlc_fw
->data
;
2829 if (rdev
->family
>= CHIP_CEDAR
) {
2830 for (i
= 0; i
< EVERGREEN_RLC_UCODE_SIZE
; i
++) {
2831 WREG32(RLC_UCODE_ADDR
, i
);
2832 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2834 } else if (rdev
->family
>= CHIP_RV770
) {
2835 for (i
= 0; i
< R700_RLC_UCODE_SIZE
; i
++) {
2836 WREG32(RLC_UCODE_ADDR
, i
);
2837 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2840 for (i
= 0; i
< RLC_UCODE_SIZE
; i
++) {
2841 WREG32(RLC_UCODE_ADDR
, i
);
2842 WREG32(RLC_UCODE_DATA
, be32_to_cpup(fw_data
++));
2845 WREG32(RLC_UCODE_ADDR
, 0);
2847 r600_rlc_start(rdev
);
2852 static void r600_enable_interrupts(struct radeon_device
*rdev
)
2854 u32 ih_cntl
= RREG32(IH_CNTL
);
2855 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
2857 ih_cntl
|= ENABLE_INTR
;
2858 ih_rb_cntl
|= IH_RB_ENABLE
;
2859 WREG32(IH_CNTL
, ih_cntl
);
2860 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2861 rdev
->ih
.enabled
= true;
2864 void r600_disable_interrupts(struct radeon_device
*rdev
)
2866 u32 ih_rb_cntl
= RREG32(IH_RB_CNTL
);
2867 u32 ih_cntl
= RREG32(IH_CNTL
);
2869 ih_rb_cntl
&= ~IH_RB_ENABLE
;
2870 ih_cntl
&= ~ENABLE_INTR
;
2871 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2872 WREG32(IH_CNTL
, ih_cntl
);
2873 /* set rptr, wptr to 0 */
2874 WREG32(IH_RB_RPTR
, 0);
2875 WREG32(IH_RB_WPTR
, 0);
2876 rdev
->ih
.enabled
= false;
2881 static void r600_disable_interrupt_state(struct radeon_device
*rdev
)
2885 WREG32(CP_INT_CNTL
, CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
);
2886 WREG32(GRBM_INT_CNTL
, 0);
2887 WREG32(DxMODE_INT_MASK
, 0);
2888 WREG32(D1GRPH_INTERRUPT_CONTROL
, 0);
2889 WREG32(D2GRPH_INTERRUPT_CONTROL
, 0);
2890 if (ASIC_IS_DCE3(rdev
)) {
2891 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL
, 0);
2892 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL
, 0);
2893 tmp
= RREG32(DC_HPD1_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2894 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
2895 tmp
= RREG32(DC_HPD2_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2896 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
2897 tmp
= RREG32(DC_HPD3_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2898 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
2899 tmp
= RREG32(DC_HPD4_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2900 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
2901 if (ASIC_IS_DCE32(rdev
)) {
2902 tmp
= RREG32(DC_HPD5_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2903 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
2904 tmp
= RREG32(DC_HPD6_INT_CONTROL
) & DC_HPDx_INT_POLARITY
;
2905 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
2908 WREG32(DACA_AUTODETECT_INT_CONTROL
, 0);
2909 WREG32(DACB_AUTODETECT_INT_CONTROL
, 0);
2910 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2911 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
2912 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2913 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
2914 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & DC_HOT_PLUG_DETECTx_INT_POLARITY
;
2915 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
2919 int r600_irq_init(struct radeon_device
*rdev
)
2923 u32 interrupt_cntl
, ih_cntl
, ih_rb_cntl
;
2926 ret
= r600_ih_ring_alloc(rdev
);
2931 r600_disable_interrupts(rdev
);
2934 ret
= r600_rlc_init(rdev
);
2936 r600_ih_ring_fini(rdev
);
2940 /* setup interrupt control */
2941 /* set dummy read address to ring address */
2942 WREG32(INTERRUPT_CNTL2
, rdev
->ih
.gpu_addr
>> 8);
2943 interrupt_cntl
= RREG32(INTERRUPT_CNTL
);
2944 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2945 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2947 interrupt_cntl
&= ~IH_DUMMY_RD_OVERRIDE
;
2948 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2949 interrupt_cntl
&= ~IH_REQ_NONSNOOP_EN
;
2950 WREG32(INTERRUPT_CNTL
, interrupt_cntl
);
2952 WREG32(IH_RB_BASE
, rdev
->ih
.gpu_addr
>> 8);
2953 rb_bufsz
= drm_order(rdev
->ih
.ring_size
/ 4);
2955 ih_rb_cntl
= (IH_WPTR_OVERFLOW_ENABLE
|
2956 IH_WPTR_OVERFLOW_CLEAR
|
2959 if (rdev
->wb
.enabled
)
2960 ih_rb_cntl
|= IH_WPTR_WRITEBACK_ENABLE
;
2962 /* set the writeback address whether it's enabled or not */
2963 WREG32(IH_RB_WPTR_ADDR_LO
, (rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFFFFFFFC);
2964 WREG32(IH_RB_WPTR_ADDR_HI
, upper_32_bits(rdev
->wb
.gpu_addr
+ R600_WB_IH_WPTR_OFFSET
) & 0xFF);
2966 WREG32(IH_RB_CNTL
, ih_rb_cntl
);
2968 /* set rptr, wptr to 0 */
2969 WREG32(IH_RB_RPTR
, 0);
2970 WREG32(IH_RB_WPTR
, 0);
2972 /* Default settings for IH_CNTL (disabled at first) */
2973 ih_cntl
= MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2974 /* RPTR_REARM only works if msi's are enabled */
2975 if (rdev
->msi_enabled
)
2976 ih_cntl
|= RPTR_REARM
;
2979 ih_cntl
|= IH_MC_SWAP(IH_MC_SWAP_32BIT
);
2981 WREG32(IH_CNTL
, ih_cntl
);
2983 /* force the active interrupt state to all disabled */
2984 if (rdev
->family
>= CHIP_CEDAR
)
2985 evergreen_disable_interrupt_state(rdev
);
2987 r600_disable_interrupt_state(rdev
);
2990 r600_enable_interrupts(rdev
);
2995 void r600_irq_suspend(struct radeon_device
*rdev
)
2997 r600_irq_disable(rdev
);
2998 r600_rlc_stop(rdev
);
3001 void r600_irq_fini(struct radeon_device
*rdev
)
3003 r600_irq_suspend(rdev
);
3004 r600_ih_ring_fini(rdev
);
3007 int r600_irq_set(struct radeon_device
*rdev
)
3009 u32 cp_int_cntl
= CNTX_BUSY_INT_ENABLE
| CNTX_EMPTY_INT_ENABLE
;
3011 u32 hpd1
, hpd2
, hpd3
, hpd4
= 0, hpd5
= 0, hpd6
= 0;
3012 u32 grbm_int_cntl
= 0;
3014 u32 d1grph
= 0, d2grph
= 0;
3016 if (!rdev
->irq
.installed
) {
3017 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3020 /* don't enable anything if the ih is disabled */
3021 if (!rdev
->ih
.enabled
) {
3022 r600_disable_interrupts(rdev
);
3023 /* force the active interrupt state to all disabled */
3024 r600_disable_interrupt_state(rdev
);
3028 hdmi1
= RREG32(R600_HDMI_BLOCK1
+ R600_HDMI_CNTL
) & ~R600_HDMI_INT_EN
;
3029 if (ASIC_IS_DCE3(rdev
)) {
3030 hdmi2
= RREG32(R600_HDMI_BLOCK3
+ R600_HDMI_CNTL
) & ~R600_HDMI_INT_EN
;
3031 hpd1
= RREG32(DC_HPD1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3032 hpd2
= RREG32(DC_HPD2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3033 hpd3
= RREG32(DC_HPD3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3034 hpd4
= RREG32(DC_HPD4_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3035 if (ASIC_IS_DCE32(rdev
)) {
3036 hpd5
= RREG32(DC_HPD5_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3037 hpd6
= RREG32(DC_HPD6_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3040 hdmi2
= RREG32(R600_HDMI_BLOCK2
+ R600_HDMI_CNTL
) & ~R600_HDMI_INT_EN
;
3041 hpd1
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3042 hpd2
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3043 hpd3
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
) & ~DC_HPDx_INT_EN
;
3046 if (rdev
->irq
.sw_int
) {
3047 DRM_DEBUG("r600_irq_set: sw int\n");
3048 cp_int_cntl
|= RB_INT_ENABLE
;
3049 cp_int_cntl
|= TIME_STAMP_INT_ENABLE
;
3051 if (rdev
->irq
.crtc_vblank_int
[0] ||
3052 rdev
->irq
.pflip
[0]) {
3053 DRM_DEBUG("r600_irq_set: vblank 0\n");
3054 mode_int
|= D1MODE_VBLANK_INT_MASK
;
3056 if (rdev
->irq
.crtc_vblank_int
[1] ||
3057 rdev
->irq
.pflip
[1]) {
3058 DRM_DEBUG("r600_irq_set: vblank 1\n");
3059 mode_int
|= D2MODE_VBLANK_INT_MASK
;
3061 if (rdev
->irq
.hpd
[0]) {
3062 DRM_DEBUG("r600_irq_set: hpd 1\n");
3063 hpd1
|= DC_HPDx_INT_EN
;
3065 if (rdev
->irq
.hpd
[1]) {
3066 DRM_DEBUG("r600_irq_set: hpd 2\n");
3067 hpd2
|= DC_HPDx_INT_EN
;
3069 if (rdev
->irq
.hpd
[2]) {
3070 DRM_DEBUG("r600_irq_set: hpd 3\n");
3071 hpd3
|= DC_HPDx_INT_EN
;
3073 if (rdev
->irq
.hpd
[3]) {
3074 DRM_DEBUG("r600_irq_set: hpd 4\n");
3075 hpd4
|= DC_HPDx_INT_EN
;
3077 if (rdev
->irq
.hpd
[4]) {
3078 DRM_DEBUG("r600_irq_set: hpd 5\n");
3079 hpd5
|= DC_HPDx_INT_EN
;
3081 if (rdev
->irq
.hpd
[5]) {
3082 DRM_DEBUG("r600_irq_set: hpd 6\n");
3083 hpd6
|= DC_HPDx_INT_EN
;
3085 if (rdev
->irq
.hdmi
[0]) {
3086 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3087 hdmi1
|= R600_HDMI_INT_EN
;
3089 if (rdev
->irq
.hdmi
[1]) {
3090 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3091 hdmi2
|= R600_HDMI_INT_EN
;
3093 if (rdev
->irq
.gui_idle
) {
3094 DRM_DEBUG("gui idle\n");
3095 grbm_int_cntl
|= GUI_IDLE_INT_ENABLE
;
3098 WREG32(CP_INT_CNTL
, cp_int_cntl
);
3099 WREG32(DxMODE_INT_MASK
, mode_int
);
3100 WREG32(D1GRPH_INTERRUPT_CONTROL
, d1grph
);
3101 WREG32(D2GRPH_INTERRUPT_CONTROL
, d2grph
);
3102 WREG32(GRBM_INT_CNTL
, grbm_int_cntl
);
3103 WREG32(R600_HDMI_BLOCK1
+ R600_HDMI_CNTL
, hdmi1
);
3104 if (ASIC_IS_DCE3(rdev
)) {
3105 WREG32(R600_HDMI_BLOCK3
+ R600_HDMI_CNTL
, hdmi2
);
3106 WREG32(DC_HPD1_INT_CONTROL
, hpd1
);
3107 WREG32(DC_HPD2_INT_CONTROL
, hpd2
);
3108 WREG32(DC_HPD3_INT_CONTROL
, hpd3
);
3109 WREG32(DC_HPD4_INT_CONTROL
, hpd4
);
3110 if (ASIC_IS_DCE32(rdev
)) {
3111 WREG32(DC_HPD5_INT_CONTROL
, hpd5
);
3112 WREG32(DC_HPD6_INT_CONTROL
, hpd6
);
3115 WREG32(R600_HDMI_BLOCK2
+ R600_HDMI_CNTL
, hdmi2
);
3116 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, hpd1
);
3117 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, hpd2
);
3118 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, hpd3
);
3124 static inline void r600_irq_ack(struct radeon_device
*rdev
)
3128 if (ASIC_IS_DCE3(rdev
)) {
3129 rdev
->irq
.stat_regs
.r600
.disp_int
= RREG32(DCE3_DISP_INTERRUPT_STATUS
);
3130 rdev
->irq
.stat_regs
.r600
.disp_int_cont
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE
);
3131 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
= RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2
);
3133 rdev
->irq
.stat_regs
.r600
.disp_int
= RREG32(DISP_INTERRUPT_STATUS
);
3134 rdev
->irq
.stat_regs
.r600
.disp_int_cont
= RREG32(DISP_INTERRUPT_STATUS_CONTINUE
);
3135 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
= 0;
3137 rdev
->irq
.stat_regs
.r600
.d1grph_int
= RREG32(D1GRPH_INTERRUPT_STATUS
);
3138 rdev
->irq
.stat_regs
.r600
.d2grph_int
= RREG32(D2GRPH_INTERRUPT_STATUS
);
3140 if (rdev
->irq
.stat_regs
.r600
.d1grph_int
& DxGRPH_PFLIP_INT_OCCURRED
)
3141 WREG32(D1GRPH_INTERRUPT_STATUS
, DxGRPH_PFLIP_INT_CLEAR
);
3142 if (rdev
->irq
.stat_regs
.r600
.d2grph_int
& DxGRPH_PFLIP_INT_OCCURRED
)
3143 WREG32(D2GRPH_INTERRUPT_STATUS
, DxGRPH_PFLIP_INT_CLEAR
);
3144 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VBLANK_INTERRUPT
)
3145 WREG32(D1MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
3146 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VLINE_INTERRUPT
)
3147 WREG32(D1MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
3148 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VBLANK_INTERRUPT
)
3149 WREG32(D2MODE_VBLANK_STATUS
, DxMODE_VBLANK_ACK
);
3150 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VLINE_INTERRUPT
)
3151 WREG32(D2MODE_VLINE_STATUS
, DxMODE_VLINE_ACK
);
3152 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD1_INTERRUPT
) {
3153 if (ASIC_IS_DCE3(rdev
)) {
3154 tmp
= RREG32(DC_HPD1_INT_CONTROL
);
3155 tmp
|= DC_HPDx_INT_ACK
;
3156 WREG32(DC_HPD1_INT_CONTROL
, tmp
);
3158 tmp
= RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
);
3159 tmp
|= DC_HPDx_INT_ACK
;
3160 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL
, tmp
);
3163 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD2_INTERRUPT
) {
3164 if (ASIC_IS_DCE3(rdev
)) {
3165 tmp
= RREG32(DC_HPD2_INT_CONTROL
);
3166 tmp
|= DC_HPDx_INT_ACK
;
3167 WREG32(DC_HPD2_INT_CONTROL
, tmp
);
3169 tmp
= RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
);
3170 tmp
|= DC_HPDx_INT_ACK
;
3171 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL
, tmp
);
3174 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD3_INTERRUPT
) {
3175 if (ASIC_IS_DCE3(rdev
)) {
3176 tmp
= RREG32(DC_HPD3_INT_CONTROL
);
3177 tmp
|= DC_HPDx_INT_ACK
;
3178 WREG32(DC_HPD3_INT_CONTROL
, tmp
);
3180 tmp
= RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
);
3181 tmp
|= DC_HPDx_INT_ACK
;
3182 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL
, tmp
);
3185 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD4_INTERRUPT
) {
3186 tmp
= RREG32(DC_HPD4_INT_CONTROL
);
3187 tmp
|= DC_HPDx_INT_ACK
;
3188 WREG32(DC_HPD4_INT_CONTROL
, tmp
);
3190 if (ASIC_IS_DCE32(rdev
)) {
3191 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD5_INTERRUPT
) {
3192 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
3193 tmp
|= DC_HPDx_INT_ACK
;
3194 WREG32(DC_HPD5_INT_CONTROL
, tmp
);
3196 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD6_INTERRUPT
) {
3197 tmp
= RREG32(DC_HPD5_INT_CONTROL
);
3198 tmp
|= DC_HPDx_INT_ACK
;
3199 WREG32(DC_HPD6_INT_CONTROL
, tmp
);
3202 if (RREG32(R600_HDMI_BLOCK1
+ R600_HDMI_STATUS
) & R600_HDMI_INT_PENDING
) {
3203 WREG32_P(R600_HDMI_BLOCK1
+ R600_HDMI_CNTL
, R600_HDMI_INT_ACK
, ~R600_HDMI_INT_ACK
);
3205 if (ASIC_IS_DCE3(rdev
)) {
3206 if (RREG32(R600_HDMI_BLOCK3
+ R600_HDMI_STATUS
) & R600_HDMI_INT_PENDING
) {
3207 WREG32_P(R600_HDMI_BLOCK3
+ R600_HDMI_CNTL
, R600_HDMI_INT_ACK
, ~R600_HDMI_INT_ACK
);
3210 if (RREG32(R600_HDMI_BLOCK2
+ R600_HDMI_STATUS
) & R600_HDMI_INT_PENDING
) {
3211 WREG32_P(R600_HDMI_BLOCK2
+ R600_HDMI_CNTL
, R600_HDMI_INT_ACK
, ~R600_HDMI_INT_ACK
);
3216 void r600_irq_disable(struct radeon_device
*rdev
)
3218 r600_disable_interrupts(rdev
);
3219 /* Wait and acknowledge irq */
3222 r600_disable_interrupt_state(rdev
);
3225 static inline u32
r600_get_ih_wptr(struct radeon_device
*rdev
)
3229 if (rdev
->wb
.enabled
)
3230 wptr
= rdev
->wb
.wb
[R600_WB_IH_WPTR_OFFSET
/4];
3232 wptr
= RREG32(IH_RB_WPTR
);
3234 if (wptr
& RB_OVERFLOW
) {
3235 /* When a ring buffer overflow happen start parsing interrupt
3236 * from the last not overwritten vector (wptr + 16). Hopefully
3237 * this should allow us to catchup.
3239 dev_warn(rdev
->dev
, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3240 wptr
, rdev
->ih
.rptr
, (wptr
+ 16) + rdev
->ih
.ptr_mask
);
3241 rdev
->ih
.rptr
= (wptr
+ 16) & rdev
->ih
.ptr_mask
;
3242 tmp
= RREG32(IH_RB_CNTL
);
3243 tmp
|= IH_WPTR_OVERFLOW_CLEAR
;
3244 WREG32(IH_RB_CNTL
, tmp
);
3246 return (wptr
& rdev
->ih
.ptr_mask
);
3250 * Each IV ring entry is 128 bits:
3251 * [7:0] - interrupt source id
3253 * [59:32] - interrupt source data
3254 * [127:60] - reserved
3256 * The basic interrupt vector entries
3257 * are decoded as follows:
3258 * src_id src_data description
3263 * 19 0 FP Hot plug detection A
3264 * 19 1 FP Hot plug detection B
3265 * 19 2 DAC A auto-detection
3266 * 19 3 DAC B auto-detection
3272 * 181 - EOP Interrupt
3275 * Note, these are based on r600 and may need to be
3276 * adjusted or added to on newer asics
3279 int r600_irq_process(struct radeon_device
*rdev
)
3281 u32 wptr
= r600_get_ih_wptr(rdev
);
3282 u32 rptr
= rdev
->ih
.rptr
;
3283 u32 src_id
, src_data
;
3285 unsigned long flags
;
3286 bool queue_hotplug
= false;
3288 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr
, wptr
);
3289 if (!rdev
->ih
.enabled
)
3292 spin_lock_irqsave(&rdev
->ih
.lock
, flags
);
3295 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
3298 if (rdev
->shutdown
) {
3299 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
3304 /* display interrupts */
3307 rdev
->ih
.wptr
= wptr
;
3308 while (rptr
!= wptr
) {
3309 /* wptr/rptr are in bytes! */
3310 ring_index
= rptr
/ 4;
3311 src_id
= rdev
->ih
.ring
[ring_index
] & 0xff;
3312 src_data
= rdev
->ih
.ring
[ring_index
+ 1] & 0xfffffff;
3315 case 1: /* D1 vblank/vline */
3317 case 0: /* D1 vblank */
3318 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VBLANK_INTERRUPT
) {
3319 if (rdev
->irq
.crtc_vblank_int
[0]) {
3320 drm_handle_vblank(rdev
->ddev
, 0);
3321 rdev
->pm
.vblank_sync
= true;
3322 wake_up(&rdev
->irq
.vblank_queue
);
3324 if (rdev
->irq
.pflip
[0])
3325 radeon_crtc_handle_flip(rdev
, 0);
3326 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D1_VBLANK_INTERRUPT
;
3327 DRM_DEBUG("IH: D1 vblank\n");
3330 case 1: /* D1 vline */
3331 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D1_VLINE_INTERRUPT
) {
3332 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D1_VLINE_INTERRUPT
;
3333 DRM_DEBUG("IH: D1 vline\n");
3337 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3341 case 5: /* D2 vblank/vline */
3343 case 0: /* D2 vblank */
3344 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VBLANK_INTERRUPT
) {
3345 if (rdev
->irq
.crtc_vblank_int
[1]) {
3346 drm_handle_vblank(rdev
->ddev
, 1);
3347 rdev
->pm
.vblank_sync
= true;
3348 wake_up(&rdev
->irq
.vblank_queue
);
3350 if (rdev
->irq
.pflip
[1])
3351 radeon_crtc_handle_flip(rdev
, 1);
3352 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D2_VBLANK_INTERRUPT
;
3353 DRM_DEBUG("IH: D2 vblank\n");
3356 case 1: /* D1 vline */
3357 if (rdev
->irq
.stat_regs
.r600
.disp_int
& LB_D2_VLINE_INTERRUPT
) {
3358 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~LB_D2_VLINE_INTERRUPT
;
3359 DRM_DEBUG("IH: D2 vline\n");
3363 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3367 case 19: /* HPD/DAC hotplug */
3370 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD1_INTERRUPT
) {
3371 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~DC_HPD1_INTERRUPT
;
3372 queue_hotplug
= true;
3373 DRM_DEBUG("IH: HPD1\n");
3377 if (rdev
->irq
.stat_regs
.r600
.disp_int
& DC_HPD2_INTERRUPT
) {
3378 rdev
->irq
.stat_regs
.r600
.disp_int
&= ~DC_HPD2_INTERRUPT
;
3379 queue_hotplug
= true;
3380 DRM_DEBUG("IH: HPD2\n");
3384 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD3_INTERRUPT
) {
3385 rdev
->irq
.stat_regs
.r600
.disp_int_cont
&= ~DC_HPD3_INTERRUPT
;
3386 queue_hotplug
= true;
3387 DRM_DEBUG("IH: HPD3\n");
3391 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont
& DC_HPD4_INTERRUPT
) {
3392 rdev
->irq
.stat_regs
.r600
.disp_int_cont
&= ~DC_HPD4_INTERRUPT
;
3393 queue_hotplug
= true;
3394 DRM_DEBUG("IH: HPD4\n");
3398 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD5_INTERRUPT
) {
3399 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
&= ~DC_HPD5_INTERRUPT
;
3400 queue_hotplug
= true;
3401 DRM_DEBUG("IH: HPD5\n");
3405 if (rdev
->irq
.stat_regs
.r600
.disp_int_cont2
& DC_HPD6_INTERRUPT
) {
3406 rdev
->irq
.stat_regs
.r600
.disp_int_cont2
&= ~DC_HPD6_INTERRUPT
;
3407 queue_hotplug
= true;
3408 DRM_DEBUG("IH: HPD6\n");
3412 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3417 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data
);
3418 r600_audio_schedule_polling(rdev
);
3420 case 176: /* CP_INT in ring buffer */
3421 case 177: /* CP_INT in IB1 */
3422 case 178: /* CP_INT in IB2 */
3423 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data
);
3424 radeon_fence_process(rdev
);
3426 case 181: /* CP EOP event */
3427 DRM_DEBUG("IH: CP EOP\n");
3428 radeon_fence_process(rdev
);
3430 case 233: /* GUI IDLE */
3431 DRM_DEBUG("IH: CP EOP\n");
3432 rdev
->pm
.gui_idle
= true;
3433 wake_up(&rdev
->irq
.idle_queue
);
3436 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id
, src_data
);
3440 /* wptr/rptr are in bytes! */
3442 rptr
&= rdev
->ih
.ptr_mask
;
3444 /* make sure wptr hasn't changed while processing */
3445 wptr
= r600_get_ih_wptr(rdev
);
3446 if (wptr
!= rdev
->ih
.wptr
)
3449 schedule_work(&rdev
->hotplug_work
);
3450 rdev
->ih
.rptr
= rptr
;
3451 WREG32(IH_RB_RPTR
, rdev
->ih
.rptr
);
3452 spin_unlock_irqrestore(&rdev
->ih
.lock
, flags
);
3459 #if defined(CONFIG_DEBUG_FS)
3461 static int r600_debugfs_cp_ring_info(struct seq_file
*m
, void *data
)
3463 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3464 struct drm_device
*dev
= node
->minor
->dev
;
3465 struct radeon_device
*rdev
= dev
->dev_private
;
3466 unsigned count
, i
, j
;
3468 radeon_ring_free_size(rdev
);
3469 count
= (rdev
->cp
.ring_size
/ 4) - rdev
->cp
.ring_free_dw
;
3470 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(CP_STAT
));
3471 seq_printf(m
, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR
));
3472 seq_printf(m
, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR
));
3473 seq_printf(m
, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev
->cp
.wptr
);
3474 seq_printf(m
, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev
->cp
.rptr
);
3475 seq_printf(m
, "%u free dwords in ring\n", rdev
->cp
.ring_free_dw
);
3476 seq_printf(m
, "%u dwords in ring\n", count
);
3478 for (j
= 0; j
<= count
; j
++) {
3479 seq_printf(m
, "r[%04d]=0x%08x\n", i
, rdev
->cp
.ring
[i
]);
3480 i
= (i
+ 1) & rdev
->cp
.ptr_mask
;
3485 static int r600_debugfs_mc_info(struct seq_file
*m
, void *data
)
3487 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3488 struct drm_device
*dev
= node
->minor
->dev
;
3489 struct radeon_device
*rdev
= dev
->dev_private
;
3491 DREG32_SYS(m
, rdev
, R_000E50_SRBM_STATUS
);
3492 DREG32_SYS(m
, rdev
, VM_L2_STATUS
);
3496 static struct drm_info_list r600_mc_info_list
[] = {
3497 {"r600_mc_info", r600_debugfs_mc_info
, 0, NULL
},
3498 {"r600_ring_info", r600_debugfs_cp_ring_info
, 0, NULL
},
3502 int r600_debugfs_mc_info_init(struct radeon_device
*rdev
)
3504 #if defined(CONFIG_DEBUG_FS)
3505 return radeon_debugfs_add_files(rdev
, r600_mc_info_list
, ARRAY_SIZE(r600_mc_info_list
));
3512 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3513 * rdev: radeon device structure
3514 * bo: buffer object struct which userspace is waiting for idle
3516 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3517 * through ring buffer, this leads to corruption in rendering, see
3518 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3519 * directly perform HDP flush by writing register through MMIO.
3521 void r600_ioctl_wait_idle(struct radeon_device
*rdev
, struct radeon_bo
*bo
)
3523 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3524 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3525 * This seems to cause problems on some AGP cards. Just use the old
3528 if ((rdev
->family
>= CHIP_RV770
) && (rdev
->family
<= CHIP_RV740
) &&
3529 rdev
->vram_scratch
.ptr
&& !(rdev
->flags
& RADEON_IS_AGP
)) {
3530 void __iomem
*ptr
= (void *)rdev
->vram_scratch
.ptr
;
3533 WREG32(HDP_DEBUG1
, 0);
3534 tmp
= readl((void __iomem
*)ptr
);
3536 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
, 0x1);
3539 void r600_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
)
3541 u32 link_width_cntl
, mask
, target_reg
;
3543 if (rdev
->flags
& RADEON_IS_IGP
)
3546 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3549 /* x2 cards have a special sequence */
3550 if (ASIC_IS_X2(rdev
))
3553 /* FIXME wait for idle */
3557 mask
= RADEON_PCIE_LC_LINK_WIDTH_X0
;
3560 mask
= RADEON_PCIE_LC_LINK_WIDTH_X1
;
3563 mask
= RADEON_PCIE_LC_LINK_WIDTH_X2
;
3566 mask
= RADEON_PCIE_LC_LINK_WIDTH_X4
;
3569 mask
= RADEON_PCIE_LC_LINK_WIDTH_X8
;
3572 mask
= RADEON_PCIE_LC_LINK_WIDTH_X12
;
3576 mask
= RADEON_PCIE_LC_LINK_WIDTH_X16
;
3580 link_width_cntl
= RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
3582 if ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) ==
3583 (mask
<< RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
))
3586 if (link_width_cntl
& R600_PCIE_LC_UPCONFIGURE_DIS
)
3589 link_width_cntl
&= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK
|
3590 RADEON_PCIE_LC_RECONFIG_NOW
|
3591 R600_PCIE_LC_RENEGOTIATE_EN
|
3592 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE
);
3593 link_width_cntl
|= mask
;
3595 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3597 /* some northbridges can renegotiate the link rather than requiring
3598 * a complete re-config.
3599 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3601 if (link_width_cntl
& R600_PCIE_LC_RENEGOTIATION_SUPPORT
)
3602 link_width_cntl
|= R600_PCIE_LC_RENEGOTIATE_EN
| R600_PCIE_LC_UPCONFIGURE_SUPPORT
;
3604 link_width_cntl
|= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE
;
3606 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, (link_width_cntl
|
3607 RADEON_PCIE_LC_RECONFIG_NOW
));
3609 if (rdev
->family
>= CHIP_RV770
)
3610 target_reg
= R700_TARGET_AND_CURRENT_PROFILE_INDEX
;
3612 target_reg
= R600_TARGET_AND_CURRENT_PROFILE_INDEX
;
3614 /* wait for lane set to complete */
3615 link_width_cntl
= RREG32(target_reg
);
3616 while (link_width_cntl
== 0xffffffff)
3617 link_width_cntl
= RREG32(target_reg
);
3621 int r600_get_pcie_lanes(struct radeon_device
*rdev
)
3623 u32 link_width_cntl
;
3625 if (rdev
->flags
& RADEON_IS_IGP
)
3628 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3631 /* x2 cards have a special sequence */
3632 if (ASIC_IS_X2(rdev
))
3635 /* FIXME wait for idle */
3637 link_width_cntl
= RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
3639 switch ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
) {
3640 case RADEON_PCIE_LC_LINK_WIDTH_X0
:
3642 case RADEON_PCIE_LC_LINK_WIDTH_X1
:
3644 case RADEON_PCIE_LC_LINK_WIDTH_X2
:
3646 case RADEON_PCIE_LC_LINK_WIDTH_X4
:
3648 case RADEON_PCIE_LC_LINK_WIDTH_X8
:
3650 case RADEON_PCIE_LC_LINK_WIDTH_X16
:
3656 static void r600_pcie_gen2_enable(struct radeon_device
*rdev
)
3658 u32 link_width_cntl
, lanes
, speed_cntl
, training_cntl
, tmp
;
3661 if (rdev
->flags
& RADEON_IS_IGP
)
3664 if (!(rdev
->flags
& RADEON_IS_PCIE
))
3667 /* x2 cards have a special sequence */
3668 if (ASIC_IS_X2(rdev
))
3671 /* only RV6xx+ chips are supported */
3672 if (rdev
->family
<= CHIP_R600
)
3675 /* 55 nm r6xx asics */
3676 if ((rdev
->family
== CHIP_RV670
) ||
3677 (rdev
->family
== CHIP_RV620
) ||
3678 (rdev
->family
== CHIP_RV635
)) {
3679 /* advertise upconfig capability */
3680 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3681 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3682 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3683 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3684 if (link_width_cntl
& LC_RENEGOTIATION_SUPPORT
) {
3685 lanes
= (link_width_cntl
& LC_LINK_WIDTH_RD_MASK
) >> LC_LINK_WIDTH_RD_SHIFT
;
3686 link_width_cntl
&= ~(LC_LINK_WIDTH_MASK
|
3687 LC_RECONFIG_ARC_MISSING_ESCAPE
);
3688 link_width_cntl
|= lanes
| LC_RECONFIG_NOW
| LC_RENEGOTIATE_EN
;
3689 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3691 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
3692 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
3696 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3697 if ((speed_cntl
& LC_OTHER_SIDE_EVER_SENT_GEN2
) &&
3698 (speed_cntl
& LC_OTHER_SIDE_SUPPORTS_GEN2
)) {
3700 /* 55 nm r6xx asics */
3701 if ((rdev
->family
== CHIP_RV670
) ||
3702 (rdev
->family
== CHIP_RV620
) ||
3703 (rdev
->family
== CHIP_RV635
)) {
3704 WREG32(MM_CFGREGS_CNTL
, 0x8);
3705 link_cntl2
= RREG32(0x4088);
3706 WREG32(MM_CFGREGS_CNTL
, 0);
3707 /* not supported yet */
3708 if (link_cntl2
& SELECTABLE_DEEMPHASIS
)
3712 speed_cntl
&= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
;
3713 speed_cntl
|= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT
);
3714 speed_cntl
&= ~LC_VOLTAGE_TIMER_SEL_MASK
;
3715 speed_cntl
&= ~LC_FORCE_DIS_HW_SPEED_CHANGE
;
3716 speed_cntl
|= LC_FORCE_EN_HW_SPEED_CHANGE
;
3717 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3719 tmp
= RREG32(0x541c);
3720 WREG32(0x541c, tmp
| 0x8);
3721 WREG32(MM_CFGREGS_CNTL
, MM_WR_TO_CFG_EN
);
3722 link_cntl2
= RREG16(0x4088);
3723 link_cntl2
&= ~TARGET_LINK_SPEED_MASK
;
3725 WREG16(0x4088, link_cntl2
);
3726 WREG32(MM_CFGREGS_CNTL
, 0);
3728 if ((rdev
->family
== CHIP_RV670
) ||
3729 (rdev
->family
== CHIP_RV620
) ||
3730 (rdev
->family
== CHIP_RV635
)) {
3731 training_cntl
= RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL
);
3732 training_cntl
&= ~LC_POINT_7_PLUS_EN
;
3733 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL
, training_cntl
);
3735 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3736 speed_cntl
&= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN
;
3737 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3740 speed_cntl
= RREG32_PCIE_P(PCIE_LC_SPEED_CNTL
);
3741 speed_cntl
|= LC_GEN2_EN_STRAP
;
3742 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL
, speed_cntl
);
3745 link_width_cntl
= RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
);
3746 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3748 link_width_cntl
|= LC_UPCONFIGURE_DIS
;
3750 link_width_cntl
&= ~LC_UPCONFIGURE_DIS
;
3751 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);