drivers/net/amd8111e.h

   1 /*
   2  * Advanced  Micro Devices Inc. AMD8111E Linux Network Driver
   3  * Copyright (C) 2003 Advanced Micro Devices
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
  18  * USA
  19
  20 Module Name:
  21
  22     amd8111e.h
  23
  24 Abstract:
  25
  26          AMD8111 based 10/100 Ethernet Controller driver definitions.
  27
  28 Environment:
  29
  30         Kernel Mode
  31
  32 Revision History:
  33         3.0.0
  34            Initial Revision.
  35         3.0.1
  36 */
  37
  38 #ifndef _AMD811E_H
  39 #define _AMD811E_H
  40
  41 /* Command style register access
  42
  43 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the  value bit that specifies the value that will be written into the selected bits of register.
  44
  45 eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
  46
  47 */
  48
  49 /*  Offset for Memory Mapped Registers. */
  50 /* 32 bit registers */
  51
  52 #define  ASF_STAT               0x00    /* ASF status register */
  53 #define CHIPID                  0x04    /* Chip ID regsiter */
  54 #define MIB_DATA                0x10    /* MIB data register */
  55 #define MIB_ADDR                0x14    /* MIB address register */
  56 #define STAT0                   0x30    /* Status0 register */
  57 #define INT0                    0x38    /* Interrupt0 register */
  58 #define INTEN0                  0x40    /* Interrupt0  enable register*/
  59 #define CMD0                    0x48    /* Command0 register */
  60 #define CMD2                    0x50    /* Command2 register */
  61 #define CMD3                    0x54    /* Command3 resiter */
  62 #define CMD7                    0x64    /* Command7 register */
  63
  64 #define CTRL1                   0x6C    /* Control1 register */
  65 #define CTRL2                   0x70    /* Control2 register */
  66
  67 #define XMT_RING_LIMIT          0x7C    /* Transmit ring limit register */
  68
  69 #define AUTOPOLL0               0x88    /* Auto-poll0 register */
  70 #define AUTOPOLL1               0x8A    /* Auto-poll1 register */
  71 #define AUTOPOLL2               0x8C    /* Auto-poll2 register */
  72 #define AUTOPOLL3               0x8E    /* Auto-poll3 register */
  73 #define AUTOPOLL4               0x90    /* Auto-poll4 register */
  74 #define AUTOPOLL5               0x92    /* Auto-poll5 register */
  75
  76 #define AP_VALUE                0x98    /* Auto-poll value register */
  77 #define DLY_INT_A               0xA8    /* Group A delayed interrupt register */
  78 #define DLY_INT_B               0xAC    /* Group B delayed interrupt register */
  79
  80 #define FLOW_CONTROL            0xC8    /* Flow control register */
  81 #define PHY_ACCESS              0xD0    /* PHY access register */
  82
  83 #define STVAL                   0xD8    /* Software timer value register */
  84
  85 #define XMT_RING_BASE_ADDR0     0x100   /* Transmit ring0 base addr register */
  86 #define XMT_RING_BASE_ADDR1     0x108   /* Transmit ring1 base addr register */
  87 #define XMT_RING_BASE_ADDR2     0x110   /* Transmit ring2 base addr register */
  88 #define XMT_RING_BASE_ADDR3     0x118   /* Transmit ring2 base addr register */
  89
  90 #define RCV_RING_BASE_ADDR0     0x120   /* Transmit ring0 base addr register */
  91
  92 #define PMAT0                   0x190   /* OnNow pattern register0 */
  93 #define PMAT1                   0x194   /* OnNow pattern register1 */
  94
  95 /* 16bit registers */
  96
  97 #define XMT_RING_LEN0           0x140   /* Transmit Ring0 length register */
  98 #define XMT_RING_LEN1           0x144   /* Transmit Ring1 length register */
  99 #define XMT_RING_LEN2           0x148   /* Transmit Ring2 length register */
 100 #define XMT_RING_LEN3           0x14C   /* Transmit Ring3 length register */
 101
 102 #define RCV_RING_LEN0           0x150   /* Receive Ring0 length register */
 103
 104 #define SRAM_SIZE               0x178   /* SRAM size register */
 105 #define SRAM_BOUNDARY           0x17A   /* SRAM boundary register */
 106
 107 /* 48bit register */
 108
 109 #define PADR                    0x160   /* Physical address register */
 110
 111 #define IFS1                    0x18C   /* Inter-frame spacing Part1 register */
 112 #define IFS                     0x18D   /* Inter-frame spacing register */
 113 #define IPG                     0x18E   /* Inter-frame gap register */
 114 /* 64bit register */
 115
 116 #define LADRF                   0x168   /* Logical address filter register */
 117
 118
 119 /* Register Bit Definitions */
 120 typedef enum {
 121
 122         ASF_INIT_DONE           = (1 << 1),
 123         ASF_INIT_PRESENT        = (1 << 0),
 124
 125 }STAT_ASF_BITS;
 126
 127 typedef enum {
 128
 129         MIB_CMD_ACTIVE          = (1 << 15 ),
 130         MIB_RD_CMD              = (1 << 13 ),
 131         MIB_CLEAR               = (1 << 12 ),
 132         MIB_ADDRESS             = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
 133                                         (1 << 4) | (1 << 5),
 134 }MIB_ADDR_BITS;
 135
 136
 137 typedef enum {
 138
 139         PMAT_DET                = (1 << 12),
 140         MP_DET                  = (1 << 11),
 141         LC_DET                  = (1 << 10),
 142         SPEED_MASK              = (1 << 9)|(1 << 8)|(1 << 7),
 143         FULL_DPLX               = (1 << 6),
 144         LINK_STATS              = (1 << 5),
 145         AUTONEG_COMPLETE        = (1 << 4),
 146         MIIPD                   = (1 << 3),
 147         RX_SUSPENDED            = (1 << 2),
 148         TX_SUSPENDED            = (1 << 1),
 149         RUNNING                 = (1 << 0),
 150
 151 }STAT0_BITS;
 152
 153 #define PHY_SPEED_10            0x2
 154 #define PHY_SPEED_100           0x3
 155
 156 /* INT0                         0x38, 32bit register */
 157 typedef enum {
 158
 159         INTR                    = (1 << 31),
 160         PCSINT                  = (1 << 28),
 161         LCINT                   = (1 << 27),
 162         APINT5                  = (1 << 26),
 163         APINT4                  = (1 << 25),
 164         APINT3                  = (1 << 24),
 165         TINT_SUM                = (1 << 23),
 166         APINT2                  = (1 << 22),
 167         APINT1                  = (1 << 21),
 168         APINT0                  = (1 << 20),
 169         MIIPDTINT               = (1 << 19),
 170         MCCINT                  = (1 << 17),
 171         MREINT                  = (1 << 16),
 172         RINT_SUM                = (1 << 15),
 173         SPNDINT                 = (1 << 14),
 174         MPINT                   = (1 << 13),
 175         SINT                    = (1 << 12),
 176         TINT3                   = (1 << 11),
 177         TINT2                   = (1 << 10),
 178         TINT1                   = (1 << 9),
 179         TINT0                   = (1 << 8),
 180         UINT                    = (1 << 7),
 181         STINT                   = (1 << 4),
 182         RINT0                   = (1 << 0),
 183
 184 }INT0_BITS;
 185
 186 typedef enum {
 187
 188         VAL3                    = (1 << 31),   /* VAL bit for byte 3 */
 189         VAL2                    = (1 << 23),   /* VAL bit for byte 2 */
 190         VAL1                    = (1 << 15),   /* VAL bit for byte 1 */
 191         VAL0                    = (1 << 7),    /* VAL bit for byte 0 */
 192
 193 }VAL_BITS;
 194
 195 typedef enum {
 196
 197         /* VAL3 */
 198         LCINTEN                 = (1 << 27),
 199         APINT5EN                = (1 << 26),
 200         APINT4EN                = (1 << 25),
 201         APINT3EN                = (1 << 24),
 202         /* VAL2 */
 203         APINT2EN                = (1 << 22),
 204         APINT1EN                = (1 << 21),
 205         APINT0EN                = (1 << 20),
 206         MIIPDTINTEN             = (1 << 19),
 207         MCCIINTEN               = (1 << 18),
 208         MCCINTEN                = (1 << 17),
 209         MREINTEN                = (1 << 16),
 210         /* VAL1 */
 211         SPNDINTEN               = (1 << 14),
 212         MPINTEN                 = (1 << 13),
 213         TINTEN3                 = (1 << 11),
 214         SINTEN                  = (1 << 12),
 215         TINTEN2                 = (1 << 10),
 216         TINTEN1                 = (1 << 9),
 217         TINTEN0                 = (1 << 8),
 218         /* VAL0 */
 219         STINTEN                 = (1 << 4),
 220         RINTEN0                 = (1 << 0),
 221
 222         INTEN0_CLEAR            = 0x1F7F7F1F, /* Command style register */
 223
 224 }INTEN0_BITS;
 225
 226 typedef enum {
 227         /* VAL2 */
 228         RDMD0                   = (1 << 16),
 229         /* VAL1 */
 230         TDMD3                   = (1 << 11),
 231         TDMD2                   = (1 << 10),
 232         TDMD1                   = (1 << 9),
 233         TDMD0                   = (1 << 8),
 234         /* VAL0 */
 235         UINTCMD                 = (1 << 6),
 236         RX_FAST_SPND            = (1 << 5),
 237         TX_FAST_SPND            = (1 << 4),
 238         RX_SPND                 = (1 << 3),
 239         TX_SPND                 = (1 << 2),
 240         INTREN                  = (1 << 1),
 241         RUN                     = (1 << 0),
 242
 243         CMD0_CLEAR              = 0x000F0F7F,   /* Command style register */
 244
 245 }CMD0_BITS;
 246
 247 typedef enum {
 248
 249         /* VAL3 */
 250         CONDUIT_MODE            = (1 << 29),
 251         /* VAL2 */
 252         RPA                     = (1 << 19),
 253         DRCVPA                  = (1 << 18),
 254         DRCVBC                  = (1 << 17),
 255         PROM                    = (1 << 16),
 256         /* VAL1 */
 257         ASTRP_RCV               = (1 << 13),
 258         RCV_DROP0               = (1 << 12),
 259         EMBA                    = (1 << 11),
 260         DXMT2PD                 = (1 << 10),
 261         LTINTEN                 = (1 << 9),
 262         DXMTFCS                 = (1 << 8),
 263         /* VAL0 */
 264         APAD_XMT                = (1 << 6),
 265         DRTY                    = (1 << 5),
 266         INLOOP                  = (1 << 4),
 267         EXLOOP                  = (1 << 3),
 268         REX_RTRY                = (1 << 2),
 269         REX_UFLO                = (1 << 1),
 270         REX_LCOL                = (1 << 0),
 271
 272         CMD2_CLEAR              = 0x3F7F3F7F,   /* Command style register */
 273
 274 }CMD2_BITS;
 275
 276 typedef enum {
 277
 278         /* VAL3 */
 279         ASF_INIT_DONE_ALIAS     = (1 << 29),
 280         /* VAL2 */
 281         JUMBO                   = (1 << 21),
 282         VSIZE                   = (1 << 20),
 283         VLONLY                  = (1 << 19),
 284         VL_TAG_DEL              = (1 << 18),
 285         /* VAL1 */
 286         EN_PMGR                 = (1 << 14),
 287         INTLEVEL                = (1 << 13),
 288         FORCE_FULL_DUPLEX       = (1 << 12),
 289         FORCE_LINK_STATUS       = (1 << 11),
 290         APEP                    = (1 << 10),
 291         MPPLBA                  = (1 << 9),
 292         /* VAL0 */
 293         RESET_PHY_PULSE         = (1 << 2),
 294         RESET_PHY               = (1 << 1),
 295         PHY_RST_POL             = (1 << 0),
 296
 297 }CMD3_BITS;
 298
 299
 300 typedef enum {
 301
 302         /* VAL0 */
 303         PMAT_SAVE_MATCH         = (1 << 4),
 304         PMAT_MODE               = (1 << 3),
 305         MPEN_SW                 = (1 << 1),
 306         LCMODE_SW               = (1 << 0),
 307
 308         CMD7_CLEAR              = 0x0000001B    /* Command style register */
 309
 310 }CMD7_BITS;
 311
 312
 313 typedef enum {
 314
 315         RESET_PHY_WIDTH         = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
 316         XMTSP_MASK              = (1 << 9) | (1 << 8),  /* 9:8 */
 317         XMTSP_128               = (1 << 9),     /* 9 */
 318         XMTSP_64                = (1 << 8),
 319         CACHE_ALIGN             = (1 << 4),
 320         BURST_LIMIT_MASK        = (0xF << 0 ),
 321         CTRL1_DEFAULT           = 0x00010111,
 322
 323 }CTRL1_BITS;
 324
 325 typedef enum {
 326
 327         FMDC_MASK               = (1 << 9)|(1 << 8),    /* 9:8 */
 328         XPHYRST                 = (1 << 7),
 329         XPHYANE                 = (1 << 6),
 330         XPHYFD                  = (1 << 5),
 331         XPHYSP                  = (1 << 4) | (1 << 3),  /* 4:3 */
 332         APDW_MASK               = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */
 333
 334 }CTRL2_BITS;
 335
 336 /* XMT_RING_LIMIT               0x7C, 32bit register */
 337 typedef enum {
 338
 339         XMT_RING2_LIMIT         = (0xFF << 16), /* 23:16 */
 340         XMT_RING1_LIMIT         = (0xFF << 8),  /* 15:8 */
 341         XMT_RING0_LIMIT         = (0xFF << 0),  /* 7:0 */
 342
 343 }XMT_RING_LIMIT_BITS;
 344
 345 typedef enum {
 346
 347         AP_REG0_EN              = (1 << 15),
 348         AP_REG0_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
 349         AP_PHY0_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
 350
 351 }AUTOPOLL0_BITS;
 352
 353 /* AUTOPOLL1                    0x8A, 16bit register */
 354 typedef enum {
 355
 356         AP_REG1_EN              = (1 << 15),
 357         AP_REG1_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
 358         AP_PRE_SUP1             = (1 << 6),
 359         AP_PHY1_DFLT            = (1 << 5),
 360         AP_PHY1_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
 361
 362 }AUTOPOLL1_BITS;
 363
 364
 365 typedef enum {
 366
 367         AP_REG2_EN              = (1 << 15),
 368         AP_REG2_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
 369         AP_PRE_SUP2             = (1 << 6),
 370         AP_PHY2_DFLT            = (1 << 5),
 371         AP_PHY2_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
 372
 373 }AUTOPOLL2_BITS;
 374
 375 typedef enum {
 376
 377         AP_REG3_EN              = (1 << 15),
 378         AP_REG3_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
 379         AP_PRE_SUP3             = (1 << 6),
 380         AP_PHY3_DFLT            = (1 << 5),
 381         AP_PHY3_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
 382
 383 }AUTOPOLL3_BITS;
 384
 385
 386 typedef enum {
 387
 388         AP_REG4_EN              = (1 << 15),
 389         AP_REG4_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
 390         AP_PRE_SUP4             = (1 << 6),
 391         AP_PHY4_DFLT            = (1 << 5),
 392         AP_PHY4_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
 393
 394 }AUTOPOLL4_BITS;
 395
 396
 397 typedef enum {
 398
 399         AP_REG5_EN              = (1 << 15),
 400         AP_REG5_ADDR_MASK       = (0xF << 8) |(1 << 12),/* 12:8 */
 401         AP_PRE_SUP5             = (1 << 6),
 402         AP_PHY5_DFLT            = (1 << 5),
 403         AP_PHY5_ADDR_MASK       = (0xF << 0) |(1 << 4),/* 4:0 */
 404
 405 }AUTOPOLL5_BITS;
 406
 407
 408
 409
 410 /* AP_VALUE                     0x98, 32bit ragister */
 411 typedef enum {
 412
 413         AP_VAL_ACTIVE           = (1 << 31),
 414         AP_VAL_RD_CMD           = ( 1 << 29),
 415         AP_ADDR                 = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */
 416         AP_VAL                  = (0xF << 0) | (0xF << 4) |( 0xF << 8) |
 417                                   (0xF << 12),  /* 15:0 */
 418
 419 }AP_VALUE_BITS;
 420
 421 typedef enum {
 422
 423         DLY_INT_A_R3            = (1 << 31),
 424         DLY_INT_A_R2            = (1 << 30),
 425         DLY_INT_A_R1            = (1 << 29),
 426         DLY_INT_A_R0            = (1 << 28),
 427         DLY_INT_A_T3            = (1 << 27),
 428         DLY_INT_A_T2            = (1 << 26),
 429         DLY_INT_A_T1            = (1 << 25),
 430         DLY_INT_A_T0            = ( 1 << 24),
 431         EVENT_COUNT_A           = (0xF << 16) | (0x1 << 20),/* 20:16 */
 432         MAX_DELAY_TIME_A        = (0xF << 0) | (0xF << 4) | (1 << 8)|
 433                                   (1 << 9) | (1 << 10), /* 10:0 */
 434
 435 }DLY_INT_A_BITS;
 436
 437 typedef enum {
 438
 439         DLY_INT_B_R3            = (1 << 31),
 440         DLY_INT_B_R2            = (1 << 30),
 441         DLY_INT_B_R1            = (1 << 29),
 442         DLY_INT_B_R0            = (1 << 28),
 443         DLY_INT_B_T3            = (1 << 27),
 444         DLY_INT_B_T2            = (1 << 26),
 445         DLY_INT_B_T1            = (1 << 25),
 446         DLY_INT_B_T0            = ( 1 << 24),
 447         EVENT_COUNT_B           = (0xF << 16) | (0x1 << 20),/* 20:16 */
 448         MAX_DELAY_TIME_B        = (0xF << 0) | (0xF << 4) | (1 << 8)|
 449                                   (1 << 9) | (1 << 10), /* 10:0 */
 450 }DLY_INT_B_BITS;
 451
 452
 453 /* FLOW_CONTROL                 0xC8, 32bit register */
 454 typedef enum {
 455
 456         PAUSE_LEN_CHG           = (1 << 30),
 457         FTPE                    = (1 << 22),
 458         FRPE                    = (1 << 21),
 459         NAPA                    = (1 << 20),
 460         NPA                     = (1 << 19),
 461         FIXP                    = ( 1 << 18),
 462         FCCMD                   = ( 1 << 16),
 463         PAUSE_LEN               = (0xF << 0) | (0xF << 4) |( 0xF << 8) |                                          (0xF << 12),  /* 15:0 */
 464
 465 }FLOW_CONTROL_BITS;
 466
 467 /* PHY_ ACCESS                  0xD0, 32bit register */
 468 typedef enum {
 469
 470         PHY_CMD_ACTIVE          = (1 << 31),
 471         PHY_WR_CMD              = (1 << 30),
 472         PHY_RD_CMD              = (1 << 29),
 473         PHY_RD_ERR              = (1 << 28),
 474         PHY_PRE_SUP             = (1 << 27),
 475         PHY_ADDR                = (1 << 21) | (1 << 22) | (1 << 23)|
 476                                         (1 << 24) |(1 << 25),/* 25:21 */
 477         PHY_REG_ADDR            = (1 << 16) | (1 << 17) | (1 << 18)|                                                    (1 << 19) | (1 << 20),/* 20:16 */
 478         PHY_DATA                = (0xF << 0)|(0xF << 4) |(0xF << 8)|
 479                                         (0xF << 12),/* 15:0 */
 480
 481 }PHY_ACCESS_BITS;
 482
 483
 484 /* PMAT0                        0x190,   32bit register */
 485 typedef enum {
 486         PMR_ACTIVE              = (1 << 31),
 487         PMR_WR_CMD              = (1 << 30),
 488         PMR_RD_CMD              = (1 << 29),
 489         PMR_BANK                = (1 <<28),
 490         PMR_ADDR                = (0xF << 16)|(1 << 20)|(1 << 21)|
 491                                         (1 << 22),/* 22:16 */
 492         PMR_B4                  = (0xF << 0) | (0xF << 4),/* 15:0 */
 493 }PMAT0_BITS;
 494
 495
 496 /* PMAT1                        0x194,   32bit register */
 497 typedef enum {
 498         PMR_B3                  = (0xF << 24) | (0xF <<28),/* 31:24 */
 499         PMR_B2                  = (0xF << 16) |(0xF << 20),/* 23:16 */
 500         PMR_B1                  = (0xF << 8) | (0xF <<12), /* 15:8 */
 501         PMR_B0                  = (0xF << 0)|(0xF << 4),/* 7:0 */
 502 }PMAT1_BITS;
 503
 504 /************************************************************************/
 505 /*                                                                      */
 506 /*                      MIB counter definitions                         */
 507 /*                                                                      */
 508 /************************************************************************/
 509
 510 #define rcv_miss_pkts                           0x00
 511 #define rcv_octets                              0x01
 512 #define rcv_broadcast_pkts                      0x02
 513 #define rcv_multicast_pkts                      0x03
 514 #define rcv_undersize_pkts                      0x04
 515 #define rcv_oversize_pkts                       0x05
 516 #define rcv_fragments                           0x06
 517 #define rcv_jabbers                             0x07
 518 #define rcv_unicast_pkts                        0x08
 519 #define rcv_alignment_errors                    0x09
 520 #define rcv_fcs_errors                          0x0A
 521 #define rcv_good_octets                         0x0B
 522 #define rcv_mac_ctrl                            0x0C
 523 #define rcv_flow_ctrl                           0x0D
 524 #define rcv_pkts_64_octets                      0x0E
 525 #define rcv_pkts_65to127_octets                 0x0F
 526 #define rcv_pkts_128to255_octets                0x10
 527 #define rcv_pkts_256to511_octets                0x11
 528 #define rcv_pkts_512to1023_octets               0x12
 529 #define rcv_pkts_1024to1518_octets              0x13
 530 #define rcv_unsupported_opcode                  0x14
 531 #define rcv_symbol_errors                       0x15
 532 #define rcv_drop_pkts_ring1                     0x16
 533 #define rcv_drop_pkts_ring2                     0x17
 534 #define rcv_drop_pkts_ring3                     0x18
 535 #define rcv_drop_pkts_ring4                     0x19
 536 #define rcv_jumbo_pkts                          0x1A
 537
 538 #define xmt_underrun_pkts                       0x20
 539 #define xmt_octets                              0x21
 540 #define xmt_packets                             0x22
 541 #define xmt_broadcast_pkts                      0x23
 542 #define xmt_multicast_pkts                      0x24
 543 #define xmt_collisions                          0x25
 544 #define xmt_unicast_pkts                        0x26
 545 #define xmt_one_collision                       0x27
 546 #define xmt_multiple_collision                  0x28
 547 #define xmt_deferred_transmit                   0x29
 548 #define xmt_late_collision                      0x2A
 549 #define xmt_excessive_defer                     0x2B
 550 #define xmt_loss_carrier                        0x2C
 551 #define xmt_excessive_collision                 0x2D
 552 #define xmt_back_pressure                       0x2E
 553 #define xmt_flow_ctrl                           0x2F
 554 #define xmt_pkts_64_octets                      0x30
 555 #define xmt_pkts_65to127_octets                 0x31
 556 #define xmt_pkts_128to255_octets                0x32
 557 #define xmt_pkts_256to511_octets                0x33
 558 #define xmt_pkts_512to1023_octets               0x34
 559 #define xmt_pkts_1024to1518_octet               0x35
 560 #define xmt_oversize_pkts                       0x36
 561 #define xmt_jumbo_pkts                          0x37
 562
 563
 564 /* Driver definitions */
 565
 566 #define  PCI_VENDOR_ID_AMD              0x1022
 567 #define  PCI_DEVICE_ID_AMD8111E_7462    0x7462
 568
 569 #define MAX_UNITS                       8 /* Maximum number of devices possible */
 570
 571 #define NUM_TX_BUFFERS                  32 /* Number of transmit buffers */
 572 #define NUM_RX_BUFFERS                  32 /* Number of receive buffers */
 573
 574 #define TX_BUFF_MOD_MASK                31 /* (NUM_TX_BUFFERS -1) */
 575 #define RX_BUFF_MOD_MASK                31 /* (NUM_RX_BUFFERS -1) */
 576
 577 #define NUM_TX_RING_DR                  32
 578 #define NUM_RX_RING_DR                  32
 579
 580 #define TX_RING_DR_MOD_MASK             31 /* (NUM_TX_RING_DR -1) */
 581 #define RX_RING_DR_MOD_MASK             31 /* (NUM_RX_RING_DR -1) */
 582
 583 #define MAX_FILTER_SIZE                 64 /* Maximum multicast address */
 584 #define AMD8111E_MIN_MTU                60
 585 #define AMD8111E_MAX_MTU                9000
 586
 587 #define PKT_BUFF_SZ                     1536
 588 #define MIN_PKT_LEN                     60
 589 #define ETH_ADDR_LEN                    6
 590
 591 #define  AMD8111E_TX_TIMEOUT            (3 * HZ)/* 3 sec */
 592 #define SOFT_TIMER_FREQ                 0xBEBC  /* 0.5 sec */
 593 #define DELAY_TIMER_CONV                50    /* msec to 10 usec conversion.
 594                                                  Only 500 usec resolution */
 595 #define OPTION_VLAN_ENABLE              0x0001
 596 #define OPTION_JUMBO_ENABLE             0x0002
 597 #define OPTION_MULTICAST_ENABLE         0x0004
 598 #define OPTION_WOL_ENABLE               0x0008
 599 #define OPTION_WAKE_MAGIC_ENABLE        0x0010
 600 #define OPTION_WAKE_PHY_ENABLE          0x0020
 601 #define OPTION_INTR_COAL_ENABLE         0x0040
 602 #define OPTION_DYN_IPG_ENABLE           0x0080
 603
 604 #define PHY_REG_ADDR_MASK               0x1f
 605
 606 /* ipg parameters */
 607 #define DEFAULT_IPG                     0x60
 608 #define IFS1_DELTA                      36
 609 #define IPG_CONVERGE_JIFFIES (HZ/2)
 610 #define IPG_STABLE_TIME 5
 611 #define MIN_IPG 96
 612 #define MAX_IPG 255
 613 #define IPG_STEP        16
 614 #define CSTATE  1
 615 #define SSTATE  2
 616
 617 /* Assume contoller gets data 10 times the maximum processing time */
 618 #define  REPEAT_CNT                     10
 619
 620 /* amd8111e decriptor flag definitions */
 621 typedef enum {
 622
 623         OWN_BIT         =       (1 << 15),
 624         ADD_FCS_BIT     =       (1 << 13),
 625         LTINT_BIT       =       (1 << 12),
 626         STP_BIT         =       (1 << 9),
 627         ENP_BIT         =       (1 << 8),
 628         KILL_BIT        =       (1 << 6),
 629         TCC_VLAN_INSERT =       (1 << 1),
 630         TCC_VLAN_REPLACE =      (1 << 1) |( 1<< 0),
 631
 632 }TX_FLAG_BITS;
 633
 634 typedef enum {
 635         ERR_BIT         =       (1 << 14),
 636         FRAM_BIT        =       (1 << 13),
 637         OFLO_BIT        =       (1 << 12),
 638         CRC_BIT         =       (1 << 11),
 639         PAM_BIT         =       (1 << 6),
 640         LAFM_BIT        =       (1 << 5),
 641         BAM_BIT         =       (1 << 4),
 642         TT_VLAN_TAGGED  =       (1 << 3) |(1 << 2),/* 0x000 */
 643         TT_PRTY_TAGGED  =       (1 << 3),/* 0x0008 */
 644
 645 }RX_FLAG_BITS;
 646
 647 #define RESET_RX_FLAGS          0x0000
 648 #define TT_MASK                 0x000c
 649 #define TCC_MASK                0x0003
 650
 651 /* driver ioctl parameters */
 652 #define AMD8111E_REG_DUMP_LEN    13*sizeof(u32)
 653
 654 /* amd8111e desriptor format */
 655
 656 struct amd8111e_tx_dr{
 657
 658         __le16 buff_count; /* Size of the buffer pointed by this descriptor */
 659
 660         __le16 tx_flags;
 661
 662         __le16 tag_ctrl_info;
 663
 664         __le16 tag_ctrl_cmd;
 665
 666         __le32 buff_phy_addr;
 667
 668         __le32 reserved;
 669 };
 670
 671 struct amd8111e_rx_dr{
 672
 673         __le32 reserved;
 674
 675         __le16 msg_count; /* Received message len */
 676
 677         __le16 tag_ctrl_info;
 678
 679         __le16 buff_count;  /* Len of the buffer pointed by descriptor. */
 680
 681         __le16 rx_flags;
 682
 683         __le32 buff_phy_addr;
 684
 685 };
 686 struct amd8111e_link_config{
 687
 688 #define SPEED_INVALID           0xffff
 689 #define DUPLEX_INVALID          0xff
 690 #define AUTONEG_INVALID         0xff
 691
 692         unsigned long                   orig_phy_option;
 693         u16                             speed;
 694         u8                              duplex;
 695         u8                              autoneg;
 696         u8                              reserved;  /* 32bit alignment */
 697 };
 698
 699 enum coal_type{
 700
 701         NO_COALESCE,
 702         LOW_COALESCE,
 703         MEDIUM_COALESCE,
 704         HIGH_COALESCE,
 705
 706 };
 707
 708 enum coal_mode{
 709         RX_INTR_COAL,
 710         TX_INTR_COAL,
 711         DISABLE_COAL,
 712         ENABLE_COAL,
 713
 714 };
 715 #define MAX_TIMEOUT     40
 716 #define MAX_EVENT_COUNT 31
 717 struct amd8111e_coalesce_conf{
 718
 719         unsigned int rx_timeout;
 720         unsigned int rx_event_count;
 721         unsigned long rx_packets;
 722         unsigned long rx_prev_packets;
 723         unsigned long rx_bytes;
 724         unsigned long rx_prev_bytes;
 725         unsigned int rx_coal_type;
 726
 727         unsigned int tx_timeout;
 728         unsigned int tx_event_count;
 729         unsigned long tx_packets;
 730         unsigned long tx_prev_packets;
 731         unsigned long tx_bytes;
 732         unsigned long tx_prev_bytes;
 733         unsigned int tx_coal_type;
 734
 735 };
 736 struct ipg_info{
 737
 738         unsigned int ipg_state;
 739         unsigned int ipg;
 740         unsigned int current_ipg;
 741         unsigned int col_cnt;
 742         unsigned int diff_col_cnt;
 743         unsigned int timer_tick;
 744         unsigned int prev_ipg;
 745         struct timer_list ipg_timer;
 746 };
 747
 748 struct amd8111e_priv{
 749
 750         struct amd8111e_tx_dr*  tx_ring;
 751         struct amd8111e_rx_dr* rx_ring;
 752         dma_addr_t tx_ring_dma_addr;    /* tx descriptor ring base address */
 753         dma_addr_t rx_ring_dma_addr;    /* rx descriptor ring base address */
 754         const char *name;
 755         struct pci_dev *pci_dev;        /* Ptr to the associated pci_dev */
 756         struct net_device* amd8111e_net_dev;    /* ptr to associated net_device */
 757         /* Transmit and recive skbs */
 758         struct sk_buff *tx_skbuff[NUM_TX_BUFFERS];
 759         struct sk_buff *rx_skbuff[NUM_RX_BUFFERS];
 760         /* Transmit and receive dma mapped addr */
 761         dma_addr_t tx_dma_addr[NUM_TX_BUFFERS];
 762         dma_addr_t rx_dma_addr[NUM_RX_BUFFERS];
 763         /* Reg memory mapped address */
 764         void __iomem *mmio;
 765
 766         struct napi_struct napi;
 767
 768         spinlock_t lock;        /* Guard lock */
 769         unsigned long rx_idx, tx_idx;   /* The next free ring entry */
 770         unsigned long tx_complete_idx;
 771         unsigned long tx_ring_complete_idx;
 772         unsigned long tx_ring_idx;
 773         unsigned int rx_buff_len;       /* Buffer length of rx buffers */
 774         int options;            /* Options enabled/disabled for the device */
 775
 776         unsigned long ext_phy_option;
 777         int ext_phy_addr;
 778         u32 ext_phy_id;
 779
 780         struct amd8111e_link_config link_config;
 781         int pm_cap;
 782
 783         struct net_device *next;
 784         int mii;
 785         struct mii_if_info mii_if;
 786 #if AMD8111E_VLAN_TAG_USED
 787         struct vlan_group               *vlgrp;
 788 #endif
 789         char opened;
 790         struct net_device_stats stats;
 791         unsigned int drv_rx_errors;
 792         struct dev_mc_list* mc_list;
 793         struct amd8111e_coalesce_conf coal_conf;
 794
 795         struct ipg_info  ipg_data;
 796
 797 };
 798
 799 /* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
 800 BUG? */
 801 #define  amd8111e_writeq(_UlData,_memMap)   \
 802                 writel(*(u32*)(&_UlData), _memMap);     \
 803                 writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
 804
 805 /* maps the external speed options to internal value */
 806 typedef enum {
 807         SPEED_AUTONEG,
 808         SPEED10_HALF,
 809         SPEED10_FULL,
 810         SPEED100_HALF,
 811         SPEED100_FULL,
 812 }EXT_PHY_OPTION;
 813
 814 static int card_idx;
 815 static int speed_duplex[MAX_UNITS] = { 0, };
 816 static int coalesce[MAX_UNITS] = {1,1,1,1,1,1,1,1};
 817 static int dynamic_ipg[MAX_UNITS] = {0,0,0,0,0,0,0,0};
 818 static unsigned int chip_version;
 819
 820 #endif /* _AMD8111E_H */
 821