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ext3: Always set dx_node's fake_dirent explicitly.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / serial / imx.c
blobfd6b1352b2d7b44b7a1461f4c709d6df4e6b07d2
1 /*
2 * linux/drivers/serial/imx.c
3 *
4 * Driver for Motorola IMX serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Author: Sascha Hauer <sascha@saschahauer.de>
9 * Copyright (C) 2004 Pengutronix
10 *
11 * Copyright (C) 2009 emlix GmbH
12 * Author: Fabian Godehardt (added IrDA support for iMX)
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 * [29-Mar-2005] Mike Lee
29 * Added hardware handshake
30 */
31
32 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33 #define SUPPORT_SYSRQ
34 #endif
35
36 #include <linux/module.h>
37 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/console.h>
40 #include <linux/sysrq.h>
41 #include <linux/platform_device.h>
42 #include <linux/tty.h>
43 #include <linux/tty_flip.h>
44 #include <linux/serial_core.h>
45 #include <linux/serial.h>
46 #include <linux/clk.h>
47 #include <linux/delay.h>
48 #include <linux/rational.h>
49
50 #include <asm/io.h>
51 #include <asm/irq.h>
52 #include <mach/hardware.h>
53 #include <mach/imx-uart.h>
54
55 /* Register definitions */
56 #define URXD0 0x0 /* Receiver Register */
57 #define URTX0 0x40 /* Transmitter Register */
58 #define UCR1 0x80 /* Control Register 1 */
59 #define UCR2 0x84 /* Control Register 2 */
60 #define UCR3 0x88 /* Control Register 3 */
61 #define UCR4 0x8c /* Control Register 4 */
62 #define UFCR 0x90 /* FIFO Control Register */
63 #define USR1 0x94 /* Status Register 1 */
64 #define USR2 0x98 /* Status Register 2 */
65 #define UESC 0x9c /* Escape Character Register */
66 #define UTIM 0xa0 /* Escape Timer Register */
67 #define UBIR 0xa4 /* BRM Incremental Register */
68 #define UBMR 0xa8 /* BRM Modulator Register */
69 #define UBRC 0xac /* Baud Rate Count Register */
70 #define MX2_ONEMS 0xb0 /* One Millisecond register */
71 #define UTS (cpu_is_mx1() ? 0xd0 : 0xb4) /* UART Test Register */
72
73 /* UART Control Register Bit Fields.*/
74 #define URXD_CHARRDY (1<<15)
75 #define URXD_ERR (1<<14)
76 #define URXD_OVRRUN (1<<13)
77 #define URXD_FRMERR (1<<12)
78 #define URXD_BRK (1<<11)
79 #define URXD_PRERR (1<<10)
80 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
81 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
82 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
83 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
84 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
85 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
86 #define UCR1_IREN (1<<7) /* Infrared interface enable */
87 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
88 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
89 #define UCR1_SNDBRK (1<<4) /* Send break */
90 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
91 #define MX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, mx1 only */
92 #define UCR1_DOZE (1<<1) /* Doze */
93 #define UCR1_UARTEN (1<<0) /* UART enabled */
94 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
95 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
96 #define UCR2_CTSC (1<<13) /* CTS pin control */
97 #define UCR2_CTS (1<<12) /* Clear to send */
98 #define UCR2_ESCEN (1<<11) /* Escape enable */
99 #define UCR2_PREN (1<<8) /* Parity enable */
100 #define UCR2_PROE (1<<7) /* Parity odd/even */
101 #define UCR2_STPB (1<<6) /* Stop */
102 #define UCR2_WS (1<<5) /* Word size */
103 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
104 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
105 #define UCR2_RXEN (1<<1) /* Receiver enabled */
106 #define UCR2_SRST (1<<0) /* SW reset */
107 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
108 #define UCR3_PARERREN (1<<12) /* Parity enable */
109 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
110 #define UCR3_DSR (1<<10) /* Data set ready */
111 #define UCR3_DCD (1<<9) /* Data carrier detect */
112 #define UCR3_RI (1<<8) /* Ring indicator */
113 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
114 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
115 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
116 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
117 #define MX1_UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */
118 #define MX1_UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */
119 #define MX2_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
120 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121 #define UCR3_BPEN (1<<0) /* Preset registers enable */
122 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
123 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
124 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
125 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
126 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
127 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
128 #define UCR4_IRSC (1<<5) /* IR special case */
129 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
130 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
131 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
132 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
133 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
134 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
135 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
136 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
137 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
138 #define USR1_RTSS (1<<14) /* RTS pin status */
139 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
140 #define USR1_RTSD (1<<12) /* RTS delta */
141 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
142 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
143 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
144 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
145 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
146 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
147 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
148 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
149 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
150 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
151 #define USR2_IDLE (1<<12) /* Idle condition */
152 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
153 #define USR2_WAKE (1<<7) /* Wake */
154 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
155 #define USR2_TXDC (1<<3) /* Transmitter complete */
156 #define USR2_BRCD (1<<2) /* Break condition */
157 #define USR2_ORE (1<<1) /* Overrun error */
158 #define USR2_RDR (1<<0) /* Recv data ready */
159 #define UTS_FRCPERR (1<<13) /* Force parity error */
160 #define UTS_LOOP (1<<12) /* Loop tx and rx */
161 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
162 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
163 #define UTS_TXFULL (1<<4) /* TxFIFO full */
164 #define UTS_RXFULL (1<<3) /* RxFIFO full */
165 #define UTS_SOFTRST (1<<0) /* Software reset */
166
167 /* We've been assigned a range on the "Low-density serial ports" major */
168 #define SERIAL_IMX_MAJOR 207
169 #define MINOR_START 16
170 #define DEV_NAME "ttymxc"
171 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
172
173 /*
174 * This determines how often we check the modem status signals
175 * for any change. They generally aren't connected to an IRQ
176 * so we have to poll them. We also check immediately before
177 * filling the TX fifo incase CTS has been dropped.
178 */
179 #define MCTRL_TIMEOUT (250*HZ/1000)
180
181 #define DRIVER_NAME "IMX-uart"
182
183 #define UART_NR 8
184
185 struct imx_port {
186 struct uart_port port;
187 struct timer_list timer;
188 unsigned int old_status;
189 int txirq,rxirq,rtsirq;
190 unsigned int have_rtscts:1;
191 unsigned int use_irda:1;
192 unsigned int irda_inv_rx:1;
193 unsigned int irda_inv_tx:1;
194 unsigned short trcv_delay; /* transceiver delay */
195 struct clk *clk;
196 };
197
198 #ifdef CONFIG_IRDA
199 #define USE_IRDA(sport) ((sport)->use_irda)
200 #else
201 #define USE_IRDA(sport) (0)
202 #endif
203
204 /*
205 * Handle any change of modem status signal since we were last called.
206 */
207 static void imx_mctrl_check(struct imx_port *sport)
208 {
209 unsigned int status, changed;
210
211 status = sport->port.ops->get_mctrl(&sport->port);
212 changed = status ^ sport->old_status;
213
214 if (changed == 0)
215 return;
216
217 sport->old_status = status;
218
219 if (changed & TIOCM_RI)
220 sport->port.icount.rng++;
221 if (changed & TIOCM_DSR)
222 sport->port.icount.dsr++;
223 if (changed & TIOCM_CAR)
224 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
225 if (changed & TIOCM_CTS)
226 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
227
228 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
229 }
230
231 /*
232 * This is our per-port timeout handler, for checking the
233 * modem status signals.
234 */
235 static void imx_timeout(unsigned long data)
236 {
237 struct imx_port *sport = (struct imx_port *)data;
238 unsigned long flags;
239
240 if (sport->port.state) {
241 spin_lock_irqsave(&sport->port.lock, flags);
242 imx_mctrl_check(sport);
243 spin_unlock_irqrestore(&sport->port.lock, flags);
244
245 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
246 }
247 }
248
249 /*
250 * interrupts disabled on entry
251 */
252 static void imx_stop_tx(struct uart_port *port)
253 {
254 struct imx_port *sport = (struct imx_port *)port;
255 unsigned long temp;
256
257 if (USE_IRDA(sport)) {
258 /* half duplex - wait for end of transmission */
259 int n = 256;
260 while ((--n > 0) &&
261 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
262 udelay(5);
263 barrier();
264 }
265 /*
266 * irda transceiver - wait a bit more to avoid
267 * cutoff, hardware dependent
268 */
269 udelay(sport->trcv_delay);
270
271 /*
272 * half duplex - reactivate receive mode,
273 * flush receive pipe echo crap
274 */
275 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
276 temp = readl(sport->port.membase + UCR1);
277 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
278 writel(temp, sport->port.membase + UCR1);
279
280 temp = readl(sport->port.membase + UCR4);
281 temp &= ~(UCR4_TCEN);
282 writel(temp, sport->port.membase + UCR4);
283
284 while (readl(sport->port.membase + URXD0) &
285 URXD_CHARRDY)
286 barrier();
287
288 temp = readl(sport->port.membase + UCR1);
289 temp |= UCR1_RRDYEN;
290 writel(temp, sport->port.membase + UCR1);
291
292 temp = readl(sport->port.membase + UCR4);
293 temp |= UCR4_DREN;
294 writel(temp, sport->port.membase + UCR4);
295 }
296 return;
297 }
298
299 temp = readl(sport->port.membase + UCR1);
300 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
301 }
302
303 /*
304 * interrupts disabled on entry
305 */
306 static void imx_stop_rx(struct uart_port *port)
307 {
308 struct imx_port *sport = (struct imx_port *)port;
309 unsigned long temp;
310
311 temp = readl(sport->port.membase + UCR2);
312 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
313 }
314
315 /*
316 * Set the modem control timer to fire immediately.
317 */
318 static void imx_enable_ms(struct uart_port *port)
319 {
320 struct imx_port *sport = (struct imx_port *)port;
321
322 mod_timer(&sport->timer, jiffies);
323 }
324
325 static inline void imx_transmit_buffer(struct imx_port *sport)
326 {
327 struct circ_buf *xmit = &sport->port.state->xmit;
328
329 while (!(readl(sport->port.membase + UTS) & UTS_TXFULL)) {
330 /* send xmit->buf[xmit->tail]
331 * out the port here */
332 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
333 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
334 sport->port.icount.tx++;
335 if (uart_circ_empty(xmit))
336 break;
337 }
338
339 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
340 uart_write_wakeup(&sport->port);
341
342 if (uart_circ_empty(xmit))
343 imx_stop_tx(&sport->port);
344 }
345
346 /*
347 * interrupts disabled on entry
348 */
349 static void imx_start_tx(struct uart_port *port)
350 {
351 struct imx_port *sport = (struct imx_port *)port;
352 unsigned long temp;
353
354 if (USE_IRDA(sport)) {
355 /* half duplex in IrDA mode; have to disable receive mode */
356 temp = readl(sport->port.membase + UCR4);
357 temp &= ~(UCR4_DREN);
358 writel(temp, sport->port.membase + UCR4);
359
360 temp = readl(sport->port.membase + UCR1);
361 temp &= ~(UCR1_RRDYEN);
362 writel(temp, sport->port.membase + UCR1);
363 }
364
365 temp = readl(sport->port.membase + UCR1);
366 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
367
368 if (USE_IRDA(sport)) {
369 temp = readl(sport->port.membase + UCR1);
370 temp |= UCR1_TRDYEN;
371 writel(temp, sport->port.membase + UCR1);
372
373 temp = readl(sport->port.membase + UCR4);
374 temp |= UCR4_TCEN;
375 writel(temp, sport->port.membase + UCR4);
376 }
377
378 if (readl(sport->port.membase + UTS) & UTS_TXEMPTY)
379 imx_transmit_buffer(sport);
380 }
381
382 static irqreturn_t imx_rtsint(int irq, void *dev_id)
383 {
384 struct imx_port *sport = dev_id;
385 unsigned int val = readl(sport->port.membase + USR1) & USR1_RTSS;
386 unsigned long flags;
387
388 spin_lock_irqsave(&sport->port.lock, flags);
389
390 writel(USR1_RTSD, sport->port.membase + USR1);
391 uart_handle_cts_change(&sport->port, !!val);
392 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
393
394 spin_unlock_irqrestore(&sport->port.lock, flags);
395 return IRQ_HANDLED;
396 }
397
398 static irqreturn_t imx_txint(int irq, void *dev_id)
399 {
400 struct imx_port *sport = dev_id;
401 struct circ_buf *xmit = &sport->port.state->xmit;
402 unsigned long flags;
403
404 spin_lock_irqsave(&sport->port.lock,flags);
405 if (sport->port.x_char)
406 {
407 /* Send next char */
408 writel(sport->port.x_char, sport->port.membase + URTX0);
409 goto out;
410 }
411
412 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
413 imx_stop_tx(&sport->port);
414 goto out;
415 }
416
417 imx_transmit_buffer(sport);
418
419 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
420 uart_write_wakeup(&sport->port);
421
422 out:
423 spin_unlock_irqrestore(&sport->port.lock,flags);
424 return IRQ_HANDLED;
425 }
426
427 static irqreturn_t imx_rxint(int irq, void *dev_id)
428 {
429 struct imx_port *sport = dev_id;
430 unsigned int rx,flg,ignored = 0;
431 struct tty_struct *tty = sport->port.state->port.tty;
432 unsigned long flags, temp;
433
434 spin_lock_irqsave(&sport->port.lock,flags);
435
436 while (readl(sport->port.membase + USR2) & USR2_RDR) {
437 flg = TTY_NORMAL;
438 sport->port.icount.rx++;
439
440 rx = readl(sport->port.membase + URXD0);
441
442 temp = readl(sport->port.membase + USR2);
443 if (temp & USR2_BRCD) {
444 writel(temp | USR2_BRCD, sport->port.membase + USR2);
445 if (uart_handle_break(&sport->port))
446 continue;
447 }
448
449 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
450 continue;
451
452 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
453 if (rx & URXD_PRERR)
454 sport->port.icount.parity++;
455 else if (rx & URXD_FRMERR)
456 sport->port.icount.frame++;
457 if (rx & URXD_OVRRUN)
458 sport->port.icount.overrun++;
459
460 if (rx & sport->port.ignore_status_mask) {
461 if (++ignored > 100)
462 goto out;
463 continue;
464 }
465
466 rx &= sport->port.read_status_mask;
467
468 if (rx & URXD_PRERR)
469 flg = TTY_PARITY;
470 else if (rx & URXD_FRMERR)
471 flg = TTY_FRAME;
472 if (rx & URXD_OVRRUN)
473 flg = TTY_OVERRUN;
474
475 #ifdef SUPPORT_SYSRQ
476 sport->port.sysrq = 0;
477 #endif
478 }
479
480 tty_insert_flip_char(tty, rx, flg);
481 }
482
483 out:
484 spin_unlock_irqrestore(&sport->port.lock,flags);
485 tty_flip_buffer_push(tty);
486 return IRQ_HANDLED;
487 }
488
489 static irqreturn_t imx_int(int irq, void *dev_id)
490 {
491 struct imx_port *sport = dev_id;
492 unsigned int sts;
493
494 sts = readl(sport->port.membase + USR1);
495
496 if (sts & USR1_RRDY)
497 imx_rxint(irq, dev_id);
498
499 if (sts & USR1_TRDY &&
500 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
501 imx_txint(irq, dev_id);
502
503 if (sts & USR1_RTSD)
504 imx_rtsint(irq, dev_id);
505
506 return IRQ_HANDLED;
507 }
508
509 /*
510 * Return TIOCSER_TEMT when transmitter is not busy.
511 */
512 static unsigned int imx_tx_empty(struct uart_port *port)
513 {
514 struct imx_port *sport = (struct imx_port *)port;
515
516 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
517 }
518
519 /*
520 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
521 */
522 static unsigned int imx_get_mctrl(struct uart_port *port)
523 {
524 struct imx_port *sport = (struct imx_port *)port;
525 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
526
527 if (readl(sport->port.membase + USR1) & USR1_RTSS)
528 tmp |= TIOCM_CTS;
529
530 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
531 tmp |= TIOCM_RTS;
532
533 return tmp;
534 }
535
536 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
537 {
538 struct imx_port *sport = (struct imx_port *)port;
539 unsigned long temp;
540
541 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
542
543 if (mctrl & TIOCM_RTS)
544 temp |= UCR2_CTS;
545
546 writel(temp, sport->port.membase + UCR2);
547 }
548
549 /*
550 * Interrupts always disabled.
551 */
552 static void imx_break_ctl(struct uart_port *port, int break_state)
553 {
554 struct imx_port *sport = (struct imx_port *)port;
555 unsigned long flags, temp;
556
557 spin_lock_irqsave(&sport->port.lock, flags);
558
559 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
560
561 if ( break_state != 0 )
562 temp |= UCR1_SNDBRK;
563
564 writel(temp, sport->port.membase + UCR1);
565
566 spin_unlock_irqrestore(&sport->port.lock, flags);
567 }
568
569 #define TXTL 2 /* reset default */
570 #define RXTL 1 /* reset default */
571
572 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
573 {
574 unsigned int val;
575 unsigned int ufcr_rfdiv;
576
577 /* set receiver / transmitter trigger level.
578 * RFDIV is set such way to satisfy requested uartclk value
579 */
580 val = TXTL << 10 | RXTL;
581 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
582 / sport->port.uartclk;
583
584 if(!ufcr_rfdiv)
585 ufcr_rfdiv = 1;
586
587 val |= UFCR_RFDIV_REG(ufcr_rfdiv);
588
589 writel(val, sport->port.membase + UFCR);
590
591 return 0;
592 }
593
594 /* half the RX buffer size */
595 #define CTSTL 16
596
597 static int imx_startup(struct uart_port *port)
598 {
599 struct imx_port *sport = (struct imx_port *)port;
600 int retval;
601 unsigned long flags, temp;
602
603 imx_setup_ufcr(sport, 0);
604
605 /* disable the DREN bit (Data Ready interrupt enable) before
606 * requesting IRQs
607 */
608 temp = readl(sport->port.membase + UCR4);
609
610 if (USE_IRDA(sport))
611 temp |= UCR4_IRSC;
612
613 /* set the trigger level for CTS */
614 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
615 temp |= CTSTL<< UCR4_CTSTL_SHF;
616
617 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
618
619 if (USE_IRDA(sport)) {
620 /* reset fifo's and state machines */
621 int i = 100;
622 temp = readl(sport->port.membase + UCR2);
623 temp &= ~UCR2_SRST;
624 writel(temp, sport->port.membase + UCR2);
625 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
626 (--i > 0)) {
627 udelay(1);
628 }
629 }
630
631 /*
632 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
633 * chips only have one interrupt.
634 */
635 if (sport->txirq > 0) {
636 retval = request_irq(sport->rxirq, imx_rxint, 0,
637 DRIVER_NAME, sport);
638 if (retval)
639 goto error_out1;
640
641 retval = request_irq(sport->txirq, imx_txint, 0,
642 DRIVER_NAME, sport);
643 if (retval)
644 goto error_out2;
645
646 /* do not use RTS IRQ on IrDA */
647 if (!USE_IRDA(sport)) {
648 retval = request_irq(sport->rtsirq, imx_rtsint,
649 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
650 IRQF_TRIGGER_FALLING |
651 IRQF_TRIGGER_RISING,
652 DRIVER_NAME, sport);
653 if (retval)
654 goto error_out3;
655 }
656 } else {
657 retval = request_irq(sport->port.irq, imx_int, 0,
658 DRIVER_NAME, sport);
659 if (retval) {
660 free_irq(sport->port.irq, sport);
661 goto error_out1;
662 }
663 }
664
665 /*
666 * Finally, clear and enable interrupts
667 */
668 writel(USR1_RTSD, sport->port.membase + USR1);
669
670 temp = readl(sport->port.membase + UCR1);
671 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
672
673 if (USE_IRDA(sport)) {
674 temp |= UCR1_IREN;
675 temp &= ~(UCR1_RTSDEN);
676 }
677
678 writel(temp, sport->port.membase + UCR1);
679
680 temp = readl(sport->port.membase + UCR2);
681 temp |= (UCR2_RXEN | UCR2_TXEN);
682 writel(temp, sport->port.membase + UCR2);
683
684 if (USE_IRDA(sport)) {
685 /* clear RX-FIFO */
686 int i = 64;
687 while ((--i > 0) &&
688 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
689 barrier();
690 }
691 }
692
693 if (!cpu_is_mx1()) {
694 temp = readl(sport->port.membase + UCR3);
695 temp |= MX2_UCR3_RXDMUXSEL;
696 writel(temp, sport->port.membase + UCR3);
697 }
698
699 if (USE_IRDA(sport)) {
700 temp = readl(sport->port.membase + UCR4);
701 if (sport->irda_inv_rx)
702 temp |= UCR4_INVR;
703 else
704 temp &= ~(UCR4_INVR);
705 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
706
707 temp = readl(sport->port.membase + UCR3);
708 if (sport->irda_inv_tx)
709 temp |= UCR3_INVT;
710 else
711 temp &= ~(UCR3_INVT);
712 writel(temp, sport->port.membase + UCR3);
713 }
714
715 /*
716 * Enable modem status interrupts
717 */
718 spin_lock_irqsave(&sport->port.lock,flags);
719 imx_enable_ms(&sport->port);
720 spin_unlock_irqrestore(&sport->port.lock,flags);
721
722 if (USE_IRDA(sport)) {
723 struct imxuart_platform_data *pdata;
724 pdata = sport->port.dev->platform_data;
725 sport->irda_inv_rx = pdata->irda_inv_rx;
726 sport->irda_inv_tx = pdata->irda_inv_tx;
727 sport->trcv_delay = pdata->transceiver_delay;
728 if (pdata->irda_enable)
729 pdata->irda_enable(1);
730 }
731
732 return 0;
733
734 error_out3:
735 if (sport->txirq)
736 free_irq(sport->txirq, sport);
737 error_out2:
738 if (sport->rxirq)
739 free_irq(sport->rxirq, sport);
740 error_out1:
741 return retval;
742 }
743
744 static void imx_shutdown(struct uart_port *port)
745 {
746 struct imx_port *sport = (struct imx_port *)port;
747 unsigned long temp;
748
749 temp = readl(sport->port.membase + UCR2);
750 temp &= ~(UCR2_TXEN);
751 writel(temp, sport->port.membase + UCR2);
752
753 if (USE_IRDA(sport)) {
754 struct imxuart_platform_data *pdata;
755 pdata = sport->port.dev->platform_data;
756 if (pdata->irda_enable)
757 pdata->irda_enable(0);
758 }
759
760 /*
761 * Stop our timer.
762 */
763 del_timer_sync(&sport->timer);
764
765 /*
766 * Free the interrupts
767 */
768 if (sport->txirq > 0) {
769 if (!USE_IRDA(sport))
770 free_irq(sport->rtsirq, sport);
771 free_irq(sport->txirq, sport);
772 free_irq(sport->rxirq, sport);
773 } else
774 free_irq(sport->port.irq, sport);
775
776 /*
777 * Disable all interrupts, port and break condition.
778 */
779
780 temp = readl(sport->port.membase + UCR1);
781 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
782 if (USE_IRDA(sport))
783 temp &= ~(UCR1_IREN);
784
785 writel(temp, sport->port.membase + UCR1);
786 }
787
788 static void
789 imx_set_termios(struct uart_port *port, struct ktermios *termios,
790 struct ktermios *old)
791 {
792 struct imx_port *sport = (struct imx_port *)port;
793 unsigned long flags;
794 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
795 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
796 unsigned int div, ufcr;
797 unsigned long num, denom;
798 uint64_t tdiv64;
799
800 /*
801 * If we don't support modem control lines, don't allow
802 * these to be set.
803 */
804 if (0) {
805 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
806 termios->c_cflag |= CLOCAL;
807 }
808
809 /*
810 * We only support CS7 and CS8.
811 */
812 while ((termios->c_cflag & CSIZE) != CS7 &&
813 (termios->c_cflag & CSIZE) != CS8) {
814 termios->c_cflag &= ~CSIZE;
815 termios->c_cflag |= old_csize;
816 old_csize = CS8;
817 }
818
819 if ((termios->c_cflag & CSIZE) == CS8)
820 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
821 else
822 ucr2 = UCR2_SRST | UCR2_IRTS;
823
824 if (termios->c_cflag & CRTSCTS) {
825 if( sport->have_rtscts ) {
826 ucr2 &= ~UCR2_IRTS;
827 ucr2 |= UCR2_CTSC;
828 } else {
829 termios->c_cflag &= ~CRTSCTS;
830 }
831 }
832
833 if (termios->c_cflag & CSTOPB)
834 ucr2 |= UCR2_STPB;
835 if (termios->c_cflag & PARENB) {
836 ucr2 |= UCR2_PREN;
837 if (termios->c_cflag & PARODD)
838 ucr2 |= UCR2_PROE;
839 }
840
841 /*
842 * Ask the core to calculate the divisor for us.
843 */
844 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
845 quot = uart_get_divisor(port, baud);
846
847 spin_lock_irqsave(&sport->port.lock, flags);
848
849 sport->port.read_status_mask = 0;
850 if (termios->c_iflag & INPCK)
851 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
852 if (termios->c_iflag & (BRKINT | PARMRK))
853 sport->port.read_status_mask |= URXD_BRK;
854
855 /*
856 * Characters to ignore
857 */
858 sport->port.ignore_status_mask = 0;
859 if (termios->c_iflag & IGNPAR)
860 sport->port.ignore_status_mask |= URXD_PRERR;
861 if (termios->c_iflag & IGNBRK) {
862 sport->port.ignore_status_mask |= URXD_BRK;
863 /*
864 * If we're ignoring parity and break indicators,
865 * ignore overruns too (for real raw support).
866 */
867 if (termios->c_iflag & IGNPAR)
868 sport->port.ignore_status_mask |= URXD_OVRRUN;
869 }
870
871 del_timer_sync(&sport->timer);
872
873 /*
874 * Update the per-port timeout.
875 */
876 uart_update_timeout(port, termios->c_cflag, baud);
877
878 /*
879 * disable interrupts and drain transmitter
880 */
881 old_ucr1 = readl(sport->port.membase + UCR1);
882 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
883 sport->port.membase + UCR1);
884
885 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
886 barrier();
887
888 /* then, disable everything */
889 old_txrxen = readl(sport->port.membase + UCR2);
890 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
891 sport->port.membase + UCR2);
892 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
893
894 if (USE_IRDA(sport)) {
895 /*
896 * use maximum available submodule frequency to
897 * avoid missing short pulses due to low sampling rate
898 */
899 div = 1;
900 } else {
901 div = sport->port.uartclk / (baud * 16);
902 if (div > 7)
903 div = 7;
904 if (!div)
905 div = 1;
906 }
907
908 rational_best_approximation(16 * div * baud, sport->port.uartclk,
909 1 << 16, 1 << 16, &num, &denom);
910
911 if (port->state && port->state->port.tty) {
912 tdiv64 = sport->port.uartclk;
913 tdiv64 *= num;
914 do_div(tdiv64, denom * 16 * div);
915 tty_encode_baud_rate(sport->port.state->port.tty,
916 (speed_t)tdiv64, (speed_t)tdiv64);
917 }
918
919 num -= 1;
920 denom -= 1;
921
922 ufcr = readl(sport->port.membase + UFCR);
923 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
924 writel(ufcr, sport->port.membase + UFCR);
925
926 writel(num, sport->port.membase + UBIR);
927 writel(denom, sport->port.membase + UBMR);
928
929 if (!cpu_is_mx1())
930 writel(sport->port.uartclk / div / 1000,
931 sport->port.membase + MX2_ONEMS);
932
933 writel(old_ucr1, sport->port.membase + UCR1);
934
935 /* set the parity, stop bits and data size */
936 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
937
938 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
939 imx_enable_ms(&sport->port);
940
941 spin_unlock_irqrestore(&sport->port.lock, flags);
942 }
943
944 static const char *imx_type(struct uart_port *port)
945 {
946 struct imx_port *sport = (struct imx_port *)port;
947
948 return sport->port.type == PORT_IMX ? "IMX" : NULL;
949 }
950
951 /*
952 * Release the memory region(s) being used by 'port'.
953 */
954 static void imx_release_port(struct uart_port *port)
955 {
956 struct platform_device *pdev = to_platform_device(port->dev);
957 struct resource *mmres;
958
959 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
960 release_mem_region(mmres->start, mmres->end - mmres->start + 1);
961 }
962
963 /*
964 * Request the memory region(s) being used by 'port'.
965 */
966 static int imx_request_port(struct uart_port *port)
967 {
968 struct platform_device *pdev = to_platform_device(port->dev);
969 struct resource *mmres;
970 void *ret;
971
972 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
973 if (!mmres)
974 return -ENODEV;
975
976 ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
977 "imx-uart");
978
979 return ret ? 0 : -EBUSY;
980 }
981
982 /*
983 * Configure/autoconfigure the port.
984 */
985 static void imx_config_port(struct uart_port *port, int flags)
986 {
987 struct imx_port *sport = (struct imx_port *)port;
988
989 if (flags & UART_CONFIG_TYPE &&
990 imx_request_port(&sport->port) == 0)
991 sport->port.type = PORT_IMX;
992 }
993
994 /*
995 * Verify the new serial_struct (for TIOCSSERIAL).
996 * The only change we allow are to the flags and type, and
997 * even then only between PORT_IMX and PORT_UNKNOWN
998 */
999 static int
1000 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1001 {
1002 struct imx_port *sport = (struct imx_port *)port;
1003 int ret = 0;
1004
1005 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1006 ret = -EINVAL;
1007 if (sport->port.irq != ser->irq)
1008 ret = -EINVAL;
1009 if (ser->io_type != UPIO_MEM)
1010 ret = -EINVAL;
1011 if (sport->port.uartclk / 16 != ser->baud_base)
1012 ret = -EINVAL;
1013 if ((void *)sport->port.mapbase != ser->iomem_base)
1014 ret = -EINVAL;
1015 if (sport->port.iobase != ser->port)
1016 ret = -EINVAL;
1017 if (ser->hub6 != 0)
1018 ret = -EINVAL;
1019 return ret;
1020 }
1021
1022 static struct uart_ops imx_pops = {
1023 .tx_empty = imx_tx_empty,
1024 .set_mctrl = imx_set_mctrl,
1025 .get_mctrl = imx_get_mctrl,
1026 .stop_tx = imx_stop_tx,
1027 .start_tx = imx_start_tx,
1028 .stop_rx = imx_stop_rx,
1029 .enable_ms = imx_enable_ms,
1030 .break_ctl = imx_break_ctl,
1031 .startup = imx_startup,
1032 .shutdown = imx_shutdown,
1033 .set_termios = imx_set_termios,
1034 .type = imx_type,
1035 .release_port = imx_release_port,
1036 .request_port = imx_request_port,
1037 .config_port = imx_config_port,
1038 .verify_port = imx_verify_port,
1039 };
1040
1041 static struct imx_port *imx_ports[UART_NR];
1042
1043 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1044 static void imx_console_putchar(struct uart_port *port, int ch)
1045 {
1046 struct imx_port *sport = (struct imx_port *)port;
1047
1048 while (readl(sport->port.membase + UTS) & UTS_TXFULL)
1049 barrier();
1050
1051 writel(ch, sport->port.membase + URTX0);
1052 }
1053
1054 /*
1055 * Interrupts are disabled on entering
1056 */
1057 static void
1058 imx_console_write(struct console *co, const char *s, unsigned int count)
1059 {
1060 struct imx_port *sport = imx_ports[co->index];
1061 unsigned int old_ucr1, old_ucr2, ucr1;
1062
1063 /*
1064 * First, save UCR1/2 and then disable interrupts
1065 */
1066 ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);
1067 old_ucr2 = readl(sport->port.membase + UCR2);
1068
1069 if (cpu_is_mx1())
1070 ucr1 |= MX1_UCR1_UARTCLKEN;
1071 ucr1 |= UCR1_UARTEN;
1072 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1073
1074 writel(ucr1, sport->port.membase + UCR1);
1075
1076 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1077
1078 uart_console_write(&sport->port, s, count, imx_console_putchar);
1079
1080 /*
1081 * Finally, wait for transmitter to become empty
1082 * and restore UCR1/2
1083 */
1084 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1085
1086 writel(old_ucr1, sport->port.membase + UCR1);
1087 writel(old_ucr2, sport->port.membase + UCR2);
1088 }
1089
1090 /*
1091 * If the port was already initialised (eg, by a boot loader),
1092 * try to determine the current setup.
1093 */
1094 static void __init
1095 imx_console_get_options(struct imx_port *sport, int *baud,
1096 int *parity, int *bits)
1097 {
1098
1099 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1100 /* ok, the port was enabled */
1101 unsigned int ucr2, ubir,ubmr, uartclk;
1102 unsigned int baud_raw;
1103 unsigned int ucfr_rfdiv;
1104
1105 ucr2 = readl(sport->port.membase + UCR2);
1106
1107 *parity = 'n';
1108 if (ucr2 & UCR2_PREN) {
1109 if (ucr2 & UCR2_PROE)
1110 *parity = 'o';
1111 else
1112 *parity = 'e';
1113 }
1114
1115 if (ucr2 & UCR2_WS)
1116 *bits = 8;
1117 else
1118 *bits = 7;
1119
1120 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1121 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1122
1123 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1124 if (ucfr_rfdiv == 6)
1125 ucfr_rfdiv = 7;
1126 else
1127 ucfr_rfdiv = 6 - ucfr_rfdiv;
1128
1129 uartclk = clk_get_rate(sport->clk);
1130 uartclk /= ucfr_rfdiv;
1131
1132 { /*
1133 * The next code provides exact computation of
1134 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1135 * without need of float support or long long division,
1136 * which would be required to prevent 32bit arithmetic overflow
1137 */
1138 unsigned int mul = ubir + 1;
1139 unsigned int div = 16 * (ubmr + 1);
1140 unsigned int rem = uartclk % div;
1141
1142 baud_raw = (uartclk / div) * mul;
1143 baud_raw += (rem * mul + div / 2) / div;
1144 *baud = (baud_raw + 50) / 100 * 100;
1145 }
1146
1147 if(*baud != baud_raw)
1148 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1149 baud_raw, *baud);
1150 }
1151 }
1152
1153 static int __init
1154 imx_console_setup(struct console *co, char *options)
1155 {
1156 struct imx_port *sport;
1157 int baud = 9600;
1158 int bits = 8;
1159 int parity = 'n';
1160 int flow = 'n';
1161
1162 /*
1163 * Check whether an invalid uart number has been specified, and
1164 * if so, search for the first available port that does have
1165 * console support.
1166 */
1167 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1168 co->index = 0;
1169 sport = imx_ports[co->index];
1170 if(sport == NULL)
1171 return -ENODEV;
1172
1173 if (options)
1174 uart_parse_options(options, &baud, &parity, &bits, &flow);
1175 else
1176 imx_console_get_options(sport, &baud, &parity, &bits);
1177
1178 imx_setup_ufcr(sport, 0);
1179
1180 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1181 }
1182
1183 static struct uart_driver imx_reg;
1184 static struct console imx_console = {
1185 .name = DEV_NAME,
1186 .write = imx_console_write,
1187 .device = uart_console_device,
1188 .setup = imx_console_setup,
1189 .flags = CON_PRINTBUFFER,
1190 .index = -1,
1191 .data = &imx_reg,
1192 };
1193
1194 #define IMX_CONSOLE &imx_console
1195 #else
1196 #define IMX_CONSOLE NULL
1197 #endif
1198
1199 static struct uart_driver imx_reg = {
1200 .owner = THIS_MODULE,
1201 .driver_name = DRIVER_NAME,
1202 .dev_name = DEV_NAME,
1203 .major = SERIAL_IMX_MAJOR,
1204 .minor = MINOR_START,
1205 .nr = ARRAY_SIZE(imx_ports),
1206 .cons = IMX_CONSOLE,
1207 };
1208
1209 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1210 {
1211 struct imx_port *sport = platform_get_drvdata(dev);
1212
1213 if (sport)
1214 uart_suspend_port(&imx_reg, &sport->port);
1215
1216 return 0;
1217 }
1218
1219 static int serial_imx_resume(struct platform_device *dev)
1220 {
1221 struct imx_port *sport = platform_get_drvdata(dev);
1222
1223 if (sport)
1224 uart_resume_port(&imx_reg, &sport->port);
1225
1226 return 0;
1227 }
1228
1229 static int serial_imx_probe(struct platform_device *pdev)
1230 {
1231 struct imx_port *sport;
1232 struct imxuart_platform_data *pdata;
1233 void __iomem *base;
1234 int ret = 0;
1235 struct resource *res;
1236
1237 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1238 if (!sport)
1239 return -ENOMEM;
1240
1241 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1242 if (!res) {
1243 ret = -ENODEV;
1244 goto free;
1245 }
1246
1247 base = ioremap(res->start, PAGE_SIZE);
1248 if (!base) {
1249 ret = -ENOMEM;
1250 goto free;
1251 }
1252
1253 sport->port.dev = &pdev->dev;
1254 sport->port.mapbase = res->start;
1255 sport->port.membase = base;
1256 sport->port.type = PORT_IMX,
1257 sport->port.iotype = UPIO_MEM;
1258 sport->port.irq = platform_get_irq(pdev, 0);
1259 sport->rxirq = platform_get_irq(pdev, 0);
1260 sport->txirq = platform_get_irq(pdev, 1);
1261 sport->rtsirq = platform_get_irq(pdev, 2);
1262 sport->port.fifosize = 32;
1263 sport->port.ops = &imx_pops;
1264 sport->port.flags = UPF_BOOT_AUTOCONF;
1265 sport->port.line = pdev->id;
1266 init_timer(&sport->timer);
1267 sport->timer.function = imx_timeout;
1268 sport->timer.data = (unsigned long)sport;
1269
1270 sport->clk = clk_get(&pdev->dev, "uart");
1271 if (IS_ERR(sport->clk)) {
1272 ret = PTR_ERR(sport->clk);
1273 goto unmap;
1274 }
1275 clk_enable(sport->clk);
1276
1277 sport->port.uartclk = clk_get_rate(sport->clk);
1278
1279 imx_ports[pdev->id] = sport;
1280
1281 pdata = pdev->dev.platform_data;
1282 if (pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
1283 sport->have_rtscts = 1;
1284
1285 #ifdef CONFIG_IRDA
1286 if (pdata && (pdata->flags & IMXUART_IRDA))
1287 sport->use_irda = 1;
1288 #endif
1289
1290 if (pdata && pdata->init) {
1291 ret = pdata->init(pdev);
1292 if (ret)
1293 goto clkput;
1294 }
1295
1296 ret = uart_add_one_port(&imx_reg, &sport->port);
1297 if (ret)
1298 goto deinit;
1299 platform_set_drvdata(pdev, &sport->port);
1300
1301 return 0;
1302 deinit:
1303 if (pdata && pdata->exit)
1304 pdata->exit(pdev);
1305 clkput:
1306 clk_put(sport->clk);
1307 clk_disable(sport->clk);
1308 unmap:
1309 iounmap(sport->port.membase);
1310 free:
1311 kfree(sport);
1312
1313 return ret;
1314 }
1315
1316 static int serial_imx_remove(struct platform_device *pdev)
1317 {
1318 struct imxuart_platform_data *pdata;
1319 struct imx_port *sport = platform_get_drvdata(pdev);
1320
1321 pdata = pdev->dev.platform_data;
1322
1323 platform_set_drvdata(pdev, NULL);
1324
1325 if (sport) {
1326 uart_remove_one_port(&imx_reg, &sport->port);
1327 clk_put(sport->clk);
1328 }
1329
1330 clk_disable(sport->clk);
1331
1332 if (pdata && pdata->exit)
1333 pdata->exit(pdev);
1334
1335 iounmap(sport->port.membase);
1336 kfree(sport);
1337
1338 return 0;
1339 }
1340
1341 static struct platform_driver serial_imx_driver = {
1342 .probe = serial_imx_probe,
1343 .remove = serial_imx_remove,
1344
1345 .suspend = serial_imx_suspend,
1346 .resume = serial_imx_resume,
1347 .driver = {
1348 .name = "imx-uart",
1349 .owner = THIS_MODULE,
1350 },
1351 };
1352
1353 static int __init imx_serial_init(void)
1354 {
1355 int ret;
1356
1357 printk(KERN_INFO "Serial: IMX driver\n");
1358
1359 ret = uart_register_driver(&imx_reg);
1360 if (ret)
1361 return ret;
1362
1363 ret = platform_driver_register(&serial_imx_driver);
1364 if (ret != 0)
1365 uart_unregister_driver(&imx_reg);
1366
1367 return 0;
1368 }
1369
1370 static void __exit imx_serial_exit(void)
1371 {
1372 platform_driver_unregister(&serial_imx_driver);
1373 uart_unregister_driver(&imx_reg);
1374 }
1375
1376 module_init(imx_serial_init);
1377 module_exit(imx_serial_exit);
1378
1379 MODULE_AUTHOR("Sascha Hauer");
1380 MODULE_DESCRIPTION("IMX generic serial port driver");
1381 MODULE_LICENSE("GPL");
1382 MODULE_ALIAS("platform:imx-uart");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree