| blob | a1f3bf0cd630d2de15be155830ca7f038de904f7 |
1 /* bnx2x_reg.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
11 * R - Read only
12 * RC - Clear on read
13 * RW - Read/Write
14 * ST - Statistics register (clear on read)
15 * W - Write only
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
19 *
20 */
23 /* [R 19] Interrupt register #0 read */
24 #define BRB1_REG_BRB1_INT_STS 0x6011c
25 /* [RW 4] Parity mask register #0 read/write */
26 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
27 /* [R 4] Parity register #0 read */
28 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
29 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
30 address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
31 BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
32 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
33 /* [RW 10] The number of free blocks above which the High_llfc signal to
34 interface #n is de-asserted. */
35 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
36 /* [RW 10] The number of free blocks below which the High_llfc signal to
37 interface #n is asserted. */
38 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
39 /* [RW 23] LL RAM data. */
40 #define BRB1_REG_LL_RAM 0x61000
41 /* [RW 10] The number of free blocks above which the Low_llfc signal to
42 interface #n is de-asserted. */
43 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
44 /* [RW 10] The number of free blocks below which the Low_llfc signal to
45 interface #n is asserted. */
46 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
47 /* [R 24] The number of full blocks. */
48 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
49 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
50 was asserted. */
51 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
52 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
53 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
54 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
55 asserted. */
56 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
57 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
58 /* [RW 10] Write client 0: De-assert pause threshold. */
59 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
60 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
61 /* [RW 10] Write client 0: Assert pause threshold. */
62 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
63 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
64 /* [R 24] The number of full blocks occupied by port. */
65 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
66 /* [RW 1] Reset the design by software. */
67 #define BRB1_REG_SOFT_RESET 0x600dc
68 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
69 #define CCM_REG_CAM_OCCUP 0xd0188
70 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
71 acknowledge output is deasserted; all other signals are treated as usual;
72 if 1 - normal activity. */
73 #define CCM_REG_CCM_CFC_IFEN 0xd003c
74 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
75 disregarded; valid is deasserted; all other signals are treated as usual;
76 if 1 - normal activity. */
77 #define CCM_REG_CCM_CQM_IFEN 0xd000c
78 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
79 Otherwise 0 is inserted. */
80 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
81 /* [RW 11] Interrupt mask register #0 read/write */
82 #define CCM_REG_CCM_INT_MASK 0xd01e4
83 /* [R 11] Interrupt register #0 read */
84 #define CCM_REG_CCM_INT_STS 0xd01d8
85 /* [R 27] Parity register #0 read */
86 #define CCM_REG_CCM_PRTY_STS 0xd01e8
87 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
88 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
89 Is used to determine the number of the AG context REG-pairs written back;
90 when the input message Reg1WbFlg isn't set. */
91 #define CCM_REG_CCM_REG0_SZ 0xd00c4
92 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
93 disregarded; valid is deasserted; all other signals are treated as usual;
94 if 1 - normal activity. */
95 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
96 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
97 disregarded; valid is deasserted; all other signals are treated as usual;
98 if 1 - normal activity. */
99 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
100 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
101 disregarded; valid output is deasserted; all other signals are treated as
102 usual; if 1 - normal activity. */
103 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
104 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
105 are disregarded; all other signals are treated as usual; if 1 - normal
106 activity. */
107 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
108 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
109 disregarded; valid output is deasserted; all other signals are treated as
110 usual; if 1 - normal activity. */
111 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
112 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
113 input is disregarded; all other signals are treated as usual; if 1 -
114 normal activity. */
115 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
116 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
117 the initial credit value; read returns the current value of the credit
118 counter. Must be initialized to 1 at start-up. */
119 #define CCM_REG_CFC_INIT_CRD 0xd0204
120 /* [RW 2] Auxillary counter flag Q number 1. */
121 #define CCM_REG_CNT_AUX1_Q 0xd00c8
122 /* [RW 2] Auxillary counter flag Q number 2. */
123 #define CCM_REG_CNT_AUX2_Q 0xd00cc
124 /* [RW 28] The CM header value for QM request (primary). */
125 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
126 /* [RW 28] The CM header value for QM request (secondary). */
127 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
128 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
129 acknowledge output is deasserted; all other signals are treated as usual;
130 if 1 - normal activity. */
131 #define CCM_REG_CQM_CCM_IFEN 0xd0014
132 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
133 the initial credit value; read returns the current value of the credit
134 counter. Must be initialized to 32 at start-up. */
135 #define CCM_REG_CQM_INIT_CRD 0xd020c
136 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
137 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
138 prioritised); 2 stands for weight 2; tc. */
139 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
140 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
141 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
142 prioritised); 2 stands for weight 2; tc. */
143 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
144 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
145 acknowledge output is deasserted; all other signals are treated as usual;
146 if 1 - normal activity. */
147 #define CCM_REG_CSDM_IFEN 0xd0018
148 /* [RC 1] Set when the message length mismatch (relative to last indication)
149 at the SDM interface is detected. */
150 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
151 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
152 weight 8 (the most prioritised); 1 stands for weight 1(least
153 prioritised); 2 stands for weight 2; tc. */
154 #define CCM_REG_CSDM_WEIGHT 0xd00b4
155 /* [RW 28] The CM header for QM formatting in case of an error in the QM
156 inputs. */
157 #define CCM_REG_ERR_CCM_HDR 0xd0094
158 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
159 #define CCM_REG_ERR_EVNT_ID 0xd0098
160 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
161 writes the initial credit value; read returns the current value of the
162 credit counter. Must be initialized to 64 at start-up. */
163 #define CCM_REG_FIC0_INIT_CRD 0xd0210
164 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
165 writes the initial credit value; read returns the current value of the
166 credit counter. Must be initialized to 64 at start-up. */
167 #define CCM_REG_FIC1_INIT_CRD 0xd0214
168 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
169 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
170 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
171 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
172 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
173 #define CCM_REG_GR_ARB_TYPE 0xd015c
174 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
175 highest priority is 3. It is supposed; that the Store channel priority is
176 the compliment to 4 of the rest priorities - Aggregation channel; Load
177 (FIC0) channel and Load (FIC1). */
178 #define CCM_REG_GR_LD0_PR 0xd0164
179 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
180 highest priority is 3. It is supposed; that the Store channel priority is
181 the compliment to 4 of the rest priorities - Aggregation channel; Load
182 (FIC0) channel and Load (FIC1). */
183 #define CCM_REG_GR_LD1_PR 0xd0168
184 /* [RW 2] General flags index. */
185 #define CCM_REG_INV_DONE_Q 0xd0108
186 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
187 context and sent to STORM; for a specific connection type. The double
188 REG-pairs are used in order to align to STORM context row size of 128
189 bits. The offset of these data in the STORM context is always 0. Index
190 _(0..15) stands for the connection type (one of 16). */
191 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
192 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
193 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
194 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
195 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
196 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
197 acknowledge output is deasserted; all other signals are treated as usual;
198 if 1 - normal activity. */
199 #define CCM_REG_PBF_IFEN 0xd0028
200 /* [RC 1] Set when the message length mismatch (relative to last indication)
201 at the pbf interface is detected. */
202 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
203 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
204 weight 8 (the most prioritised); 1 stands for weight 1(least
205 prioritised); 2 stands for weight 2; tc. */
206 #define CCM_REG_PBF_WEIGHT 0xd00ac
207 #define CCM_REG_PHYS_QNUM1_0 0xd0134
208 #define CCM_REG_PHYS_QNUM1_1 0xd0138
209 #define CCM_REG_PHYS_QNUM2_0 0xd013c
210 #define CCM_REG_PHYS_QNUM2_1 0xd0140
211 #define CCM_REG_PHYS_QNUM3_0 0xd0144
212 #define CCM_REG_PHYS_QNUM3_1 0xd0148
213 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
214 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
215 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
216 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
217 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
218 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
219 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
220 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
221 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
222 disregarded; acknowledge output is deasserted; all other signals are
223 treated as usual; if 1 - normal activity. */
224 #define CCM_REG_STORM_CCM_IFEN 0xd0010
225 /* [RC 1] Set when the message length mismatch (relative to last indication)
226 at the STORM interface is detected. */
227 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
228 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
229 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
230 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
231 tc. */
232 #define CCM_REG_STORM_WEIGHT 0xd009c
233 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
234 disregarded; acknowledge output is deasserted; all other signals are
235 treated as usual; if 1 - normal activity. */
236 #define CCM_REG_TSEM_IFEN 0xd001c
237 /* [RC 1] Set when the message length mismatch (relative to last indication)
238 at the tsem interface is detected. */
239 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
240 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
241 weight 8 (the most prioritised); 1 stands for weight 1(least
242 prioritised); 2 stands for weight 2; tc. */
243 #define CCM_REG_TSEM_WEIGHT 0xd00a0
244 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
245 disregarded; acknowledge output is deasserted; all other signals are
246 treated as usual; if 1 - normal activity. */
247 #define CCM_REG_USEM_IFEN 0xd0024
248 /* [RC 1] Set when message length mismatch (relative to last indication) at
249 the usem interface is detected. */
250 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
251 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
252 weight 8 (the most prioritised); 1 stands for weight 1(least
253 prioritised); 2 stands for weight 2; tc. */
254 #define CCM_REG_USEM_WEIGHT 0xd00a8
255 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
256 disregarded; acknowledge output is deasserted; all other signals are
257 treated as usual; if 1 - normal activity. */
258 #define CCM_REG_XSEM_IFEN 0xd0020
259 /* [RC 1] Set when the message length mismatch (relative to last indication)
260 at the xsem interface is detected. */
261 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
262 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
263 weight 8 (the most prioritised); 1 stands for weight 1(least
264 prioritised); 2 stands for weight 2; tc. */
265 #define CCM_REG_XSEM_WEIGHT 0xd00a4
266 /* [RW 19] Indirect access to the descriptor table of the XX protection
267 mechanism. The fields are: [5:0] - message length; [12:6] - message
268 pointer; 18:13] - next pointer. */
269 #define CCM_REG_XX_DESCR_TABLE 0xd0300
270 #define CCM_REG_XX_DESCR_TABLE_SIZE 36
271 /* [R 7] Used to read the value of XX protection Free counter. */
272 #define CCM_REG_XX_FREE 0xd0184
273 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
274 of the Input Stage XX protection buffer by the XX protection pending
275 messages. Max credit available - 127. Write writes the initial credit
276 value; read returns the current value of the credit counter. Must be
277 initialized to maximum XX protected message size - 2 at start-up. */
278 #define CCM_REG_XX_INIT_CRD 0xd0220
279 /* [RW 7] The maximum number of pending messages; which may be stored in XX
280 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
281 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
282 counter. */
283 #define CCM_REG_XX_MSG_NUM 0xd0224
284 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
285 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
286 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
287 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
288 header pointer. */
289 #define CCM_REG_XX_TABLE 0xd0280
290 #define CDU_REG_CDU_CHK_MASK0 0x101000
291 #define CDU_REG_CDU_CHK_MASK1 0x101004
292 #define CDU_REG_CDU_CONTROL0 0x101008
293 #define CDU_REG_CDU_DEBUG 0x101010
294 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
295 /* [RW 7] Interrupt mask register #0 read/write */
296 #define CDU_REG_CDU_INT_MASK 0x10103c
297 /* [R 7] Interrupt register #0 read */
298 #define CDU_REG_CDU_INT_STS 0x101030
299 /* [RW 5] Parity mask register #0 read/write */
300 #define CDU_REG_CDU_PRTY_MASK 0x10104c
301 /* [R 5] Parity register #0 read */
302 #define CDU_REG_CDU_PRTY_STS 0x101040
303 /* [RC 32] logging of error data in case of a CDU load error:
304 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
305 ype_error; ctual_active; ctual_compressed_context}; */
306 #define CDU_REG_ERROR_DATA 0x101014
307 /* [WB 216] L1TT ram access. each entry has the following format :
308 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
309 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
310 #define CDU_REG_L1TT 0x101800
311 /* [WB 24] MATT ram access. each entry has the following
312 format:{RegionLength[11:0]; egionOffset[11:0]} */
313 #define CDU_REG_MATT 0x101100
314 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
315 #define CDU_REG_MF_MODE 0x101050
316 /* [R 1] indication the initializing the activity counter by the hardware
317 was done. */
318 #define CFC_REG_AC_INIT_DONE 0x104078
319 /* [RW 13] activity counter ram access */
320 #define CFC_REG_ACTIVITY_COUNTER 0x104400
321 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
322 /* [R 1] indication the initializing the cams by the hardware was done. */
323 #define CFC_REG_CAM_INIT_DONE 0x10407c
324 /* [RW 2] Interrupt mask register #0 read/write */
325 #define CFC_REG_CFC_INT_MASK 0x104108
326 /* [R 2] Interrupt register #0 read */
327 #define CFC_REG_CFC_INT_STS 0x1040fc
328 /* [RC 2] Interrupt register #0 read clear */
329 #define CFC_REG_CFC_INT_STS_CLR 0x104100
330 /* [RW 4] Parity mask register #0 read/write */
331 #define CFC_REG_CFC_PRTY_MASK 0x104118
332 /* [R 4] Parity register #0 read */
333 #define CFC_REG_CFC_PRTY_STS 0x10410c
334 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
335 #define CFC_REG_CID_CAM 0x104800
336 #define CFC_REG_CONTROL0 0x104028
337 #define CFC_REG_DEBUG0 0x104050
338 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
339 vector) whether the cfc should be disabled upon it */
340 #define CFC_REG_DISABLE_ON_ERROR 0x104044
341 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
342 set one of these bits. the bit description can be found in CFC
343 specifications */
344 #define CFC_REG_ERROR_VECTOR 0x10403c
345 /* [WB 93] LCID info ram access */
346 #define CFC_REG_INFO_RAM 0x105000
347 #define CFC_REG_INFO_RAM_SIZE 1024
348 #define CFC_REG_INIT_REG 0x10404c
349 #define CFC_REG_INTERFACES 0x104058
350 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
351 field allows changing the priorities of the weighted-round-robin arbiter
352 which selects which CFC load client should be served next */
353 #define CFC_REG_LCREQ_WEIGHTS 0x104084
354 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
355 #define CFC_REG_LINK_LIST 0x104c00
356 #define CFC_REG_LINK_LIST_SIZE 256
357 /* [R 1] indication the initializing the link list by the hardware was done. */
358 #define CFC_REG_LL_INIT_DONE 0x104074
359 /* [R 9] Number of allocated LCIDs which are at empty state */
360 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
361 /* [R 9] Number of Arriving LCIDs in Link List Block */
362 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
363 /* [R 9] Number of Leaving LCIDs in Link List Block */
364 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
365 /* [RW 8] The event id for aggregated interrupt 0 */
366 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
367 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
368 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
369 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
370 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
371 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
372 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
373 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
374 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
375 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
376 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
377 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c
378 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050
379 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054
380 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058
381 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c
382 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
383 or auto-mask-mode (1) */
384 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0
385 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4
386 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8
387 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec
388 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0
389 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4
390 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8
391 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0
392 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4
393 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8
394 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc
395 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
396 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
397 /* [RW 16] The maximum value of the competion counter #0 */
398 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
399 /* [RW 16] The maximum value of the competion counter #1 */
400 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
401 /* [RW 16] The maximum value of the competion counter #2 */
402 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
403 /* [RW 16] The maximum value of the competion counter #3 */
404 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
405 /* [RW 13] The start address in the internal RAM for the completion
406 counters. */
407 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
408 /* [RW 32] Interrupt mask register #0 read/write */
409 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
410 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
411 /* [R 32] Interrupt register #0 read */
412 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
413 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
414 /* [RW 11] Parity mask register #0 read/write */
415 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
416 /* [R 11] Parity register #0 read */
417 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
418 #define CSDM_REG_ENABLE_IN1 0xc2238
419 #define CSDM_REG_ENABLE_IN2 0xc223c
420 #define CSDM_REG_ENABLE_OUT1 0xc2240
421 #define CSDM_REG_ENABLE_OUT2 0xc2244
422 /* [RW 4] The initial number of messages that can be sent to the pxp control
423 interface without receiving any ACK. */
424 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
425 /* [ST 32] The number of ACK after placement messages received */
426 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
427 /* [ST 32] The number of packet end messages received from the parser */
428 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
429 /* [ST 32] The number of requests received from the pxp async if */
430 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
431 /* [ST 32] The number of commands received in queue 0 */
432 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
433 /* [ST 32] The number of commands received in queue 10 */
434 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
435 /* [ST 32] The number of commands received in queue 11 */
436 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
437 /* [ST 32] The number of commands received in queue 1 */
438 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
439 /* [ST 32] The number of commands received in queue 3 */
440 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
441 /* [ST 32] The number of commands received in queue 4 */
442 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
443 /* [ST 32] The number of commands received in queue 5 */
444 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
445 /* [ST 32] The number of commands received in queue 6 */
446 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
447 /* [ST 32] The number of commands received in queue 7 */
448 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
449 /* [ST 32] The number of commands received in queue 8 */
450 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
451 /* [ST 32] The number of commands received in queue 9 */
452 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
453 /* [RW 13] The start address in the internal RAM for queue counters */
454 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
455 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
456 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
457 /* [R 1] parser fifo empty in sdm_sync block */
458 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
459 /* [R 1] parser serial fifo empty in sdm_sync block */
460 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
461 /* [RW 32] Tick for timer counter. Applicable only when
462 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
463 #define CSDM_REG_TIMER_TICK 0xc2000
464 /* [RW 5] The number of time_slots in the arbitration cycle */
465 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
466 /* [RW 3] The source that is associated with arbitration element 0. Source
467 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
468 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
469 #define CSEM_REG_ARB_ELEMENT0 0x200020
470 /* [RW 3] The source that is associated with arbitration element 1. Source
471 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
472 sleeping thread with priority 1; 4- sleeping thread with priority 2.
473 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
474 #define CSEM_REG_ARB_ELEMENT1 0x200024
475 /* [RW 3] The source that is associated with arbitration element 2. Source
476 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
477 sleeping thread with priority 1; 4- sleeping thread with priority 2.
478 Could not be equal to register ~csem_registers_arb_element0.arb_element0
479 and ~csem_registers_arb_element1.arb_element1 */
480 #define CSEM_REG_ARB_ELEMENT2 0x200028
481 /* [RW 3] The source that is associated with arbitration element 3. Source
482 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
483 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
484 not be equal to register ~csem_registers_arb_element0.arb_element0 and
485 ~csem_registers_arb_element1.arb_element1 and
486 ~csem_registers_arb_element2.arb_element2 */
487 #define CSEM_REG_ARB_ELEMENT3 0x20002c
488 /* [RW 3] The source that is associated with arbitration element 4. Source
489 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
490 sleeping thread with priority 1; 4- sleeping thread with priority 2.
491 Could not be equal to register ~csem_registers_arb_element0.arb_element0
492 and ~csem_registers_arb_element1.arb_element1 and
493 ~csem_registers_arb_element2.arb_element2 and
494 ~csem_registers_arb_element3.arb_element3 */
495 #define CSEM_REG_ARB_ELEMENT4 0x200030
496 /* [RW 32] Interrupt mask register #0 read/write */
497 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
498 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
499 /* [R 32] Interrupt register #0 read */
500 #define CSEM_REG_CSEM_INT_STS_0 0x200104
501 #define CSEM_REG_CSEM_INT_STS_1 0x200114
502 /* [RW 32] Parity mask register #0 read/write */
503 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
504 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
505 /* [R 32] Parity register #0 read */
506 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
507 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
508 #define CSEM_REG_ENABLE_IN 0x2000a4
509 #define CSEM_REG_ENABLE_OUT 0x2000a8
510 /* [RW 32] This address space contains all registers and memories that are
511 placed in SEM_FAST block. The SEM_FAST registers are described in
512 appendix B. In order to access the sem_fast registers the base address
513 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
514 #define CSEM_REG_FAST_MEMORY 0x220000
515 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
516 by the microcode */
517 #define CSEM_REG_FIC0_DISABLE 0x200224
518 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
519 by the microcode */
520 #define CSEM_REG_FIC1_DISABLE 0x200234
521 /* [RW 15] Interrupt table Read and write access to it is not possible in
522 the middle of the work */
523 #define CSEM_REG_INT_TABLE 0x200400
524 /* [ST 24] Statistics register. The number of messages that entered through
525 FIC0 */
526 #define CSEM_REG_MSG_NUM_FIC0 0x200000
527 /* [ST 24] Statistics register. The number of messages that entered through
528 FIC1 */
529 #define CSEM_REG_MSG_NUM_FIC1 0x200004
530 /* [ST 24] Statistics register. The number of messages that were sent to
531 FOC0 */
532 #define CSEM_REG_MSG_NUM_FOC0 0x200008
533 /* [ST 24] Statistics register. The number of messages that were sent to
534 FOC1 */
535 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
536 /* [ST 24] Statistics register. The number of messages that were sent to
537 FOC2 */
538 #define CSEM_REG_MSG_NUM_FOC2 0x200010
539 /* [ST 24] Statistics register. The number of messages that were sent to
540 FOC3 */
541 #define CSEM_REG_MSG_NUM_FOC3 0x200014
542 /* [RW 1] Disables input messages from the passive buffer May be updated
543 during run_time by the microcode */
544 #define CSEM_REG_PAS_DISABLE 0x20024c
545 /* [WB 128] Debug only. Passive buffer memory */
546 #define CSEM_REG_PASSIVE_BUFFER 0x202000
547 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
548 #define CSEM_REG_PRAM 0x240000
549 /* [R 16] Valid sleeping threads indication have bit per thread */
550 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
551 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
552 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
553 /* [RW 16] List of free threads . There is a bit per thread. */
554 #define CSEM_REG_THREADS_LIST 0x2002e4
555 /* [RW 3] The arbitration scheme of time_slot 0 */
556 #define CSEM_REG_TS_0_AS 0x200038
557 /* [RW 3] The arbitration scheme of time_slot 10 */
558 #define CSEM_REG_TS_10_AS 0x200060
559 /* [RW 3] The arbitration scheme of time_slot 11 */
560 #define CSEM_REG_TS_11_AS 0x200064
561 /* [RW 3] The arbitration scheme of time_slot 12 */
562 #define CSEM_REG_TS_12_AS 0x200068
563 /* [RW 3] The arbitration scheme of time_slot 13 */
564 #define CSEM_REG_TS_13_AS 0x20006c
565 /* [RW 3] The arbitration scheme of time_slot 14 */
566 #define CSEM_REG_TS_14_AS 0x200070
567 /* [RW 3] The arbitration scheme of time_slot 15 */
568 #define CSEM_REG_TS_15_AS 0x200074
569 /* [RW 3] The arbitration scheme of time_slot 16 */
570 #define CSEM_REG_TS_16_AS 0x200078
571 /* [RW 3] The arbitration scheme of time_slot 17 */
572 #define CSEM_REG_TS_17_AS 0x20007c
573 /* [RW 3] The arbitration scheme of time_slot 18 */
574 #define CSEM_REG_TS_18_AS 0x200080
575 /* [RW 3] The arbitration scheme of time_slot 1 */
576 #define CSEM_REG_TS_1_AS 0x20003c
577 /* [RW 3] The arbitration scheme of time_slot 2 */
578 #define CSEM_REG_TS_2_AS 0x200040
579 /* [RW 3] The arbitration scheme of time_slot 3 */
580 #define CSEM_REG_TS_3_AS 0x200044
581 /* [RW 3] The arbitration scheme of time_slot 4 */
582 #define CSEM_REG_TS_4_AS 0x200048
583 /* [RW 3] The arbitration scheme of time_slot 5 */
584 #define CSEM_REG_TS_5_AS 0x20004c
585 /* [RW 3] The arbitration scheme of time_slot 6 */
586 #define CSEM_REG_TS_6_AS 0x200050
587 /* [RW 3] The arbitration scheme of time_slot 7 */
588 #define CSEM_REG_TS_7_AS 0x200054
589 /* [RW 3] The arbitration scheme of time_slot 8 */
590 #define CSEM_REG_TS_8_AS 0x200058
591 /* [RW 3] The arbitration scheme of time_slot 9 */
592 #define CSEM_REG_TS_9_AS 0x20005c
593 /* [RW 1] Parity mask register #0 read/write */
594 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
595 /* [R 1] Parity register #0 read */
596 #define DBG_REG_DBG_PRTY_STS 0xc09c
597 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
598 as 14*X+Y. */
599 #define DMAE_REG_CMD_MEM 0x102400
600 #define DMAE_REG_CMD_MEM_SIZE 224
601 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
602 initial value is all ones. */
603 #define DMAE_REG_CRC16C_INIT 0x10201c
604 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
605 CRC-16 T10 initial value is all ones. */
606 #define DMAE_REG_CRC16T10_INIT 0x102020
607 /* [RW 2] Interrupt mask register #0 read/write */
608 #define DMAE_REG_DMAE_INT_MASK 0x102054
609 /* [RW 4] Parity mask register #0 read/write */
610 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
611 /* [R 4] Parity register #0 read */
612 #define DMAE_REG_DMAE_PRTY_STS 0x102058
613 /* [RW 1] Command 0 go. */
614 #define DMAE_REG_GO_C0 0x102080
615 /* [RW 1] Command 1 go. */
616 #define DMAE_REG_GO_C1 0x102084
617 /* [RW 1] Command 10 go. */
618 #define DMAE_REG_GO_C10 0x102088
619 /* [RW 1] Command 11 go. */
620 #define DMAE_REG_GO_C11 0x10208c
621 /* [RW 1] Command 12 go. */
622 #define DMAE_REG_GO_C12 0x102090
623 /* [RW 1] Command 13 go. */
624 #define DMAE_REG_GO_C13 0x102094
625 /* [RW 1] Command 14 go. */
626 #define DMAE_REG_GO_C14 0x102098
627 /* [RW 1] Command 15 go. */
628 #define DMAE_REG_GO_C15 0x10209c
629 /* [RW 1] Command 2 go. */
630 #define DMAE_REG_GO_C2 0x1020a0
631 /* [RW 1] Command 3 go. */
632 #define DMAE_REG_GO_C3 0x1020a4
633 /* [RW 1] Command 4 go. */
634 #define DMAE_REG_GO_C4 0x1020a8
635 /* [RW 1] Command 5 go. */
636 #define DMAE_REG_GO_C5 0x1020ac
637 /* [RW 1] Command 6 go. */
638 #define DMAE_REG_GO_C6 0x1020b0
639 /* [RW 1] Command 7 go. */
640 #define DMAE_REG_GO_C7 0x1020b4
641 /* [RW 1] Command 8 go. */
642 #define DMAE_REG_GO_C8 0x1020b8
643 /* [RW 1] Command 9 go. */
644 #define DMAE_REG_GO_C9 0x1020bc
645 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
646 input is disregarded; valid is deasserted; all other signals are treated
647 as usual; if 1 - normal activity. */
648 #define DMAE_REG_GRC_IFEN 0x102008
649 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
650 acknowledge input is disregarded; valid is deasserted; full is asserted;
651 all other signals are treated as usual; if 1 - normal activity. */
652 #define DMAE_REG_PCI_IFEN 0x102004
653 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
654 initial value to the credit counter; related to the address. Read returns
655 the current value of the counter. */
656 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
657 /* [RW 8] Aggregation command. */
658 #define DORQ_REG_AGG_CMD0 0x170060
659 /* [RW 8] Aggregation command. */
660 #define DORQ_REG_AGG_CMD1 0x170064
661 /* [RW 8] Aggregation command. */
662 #define DORQ_REG_AGG_CMD2 0x170068
663 /* [RW 8] Aggregation command. */
664 #define DORQ_REG_AGG_CMD3 0x17006c
665 /* [RW 28] UCM Header. */
666 #define DORQ_REG_CMHEAD_RX 0x170050
667 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
668 #define DORQ_REG_DB_ADDR0 0x17008c
669 /* [RW 5] Interrupt mask register #0 read/write */
670 #define DORQ_REG_DORQ_INT_MASK 0x170180
671 /* [R 5] Interrupt register #0 read */
672 #define DORQ_REG_DORQ_INT_STS 0x170174
673 /* [RC 5] Interrupt register #0 read clear */
674 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
675 /* [RW 2] Parity mask register #0 read/write */
676 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
677 /* [R 2] Parity register #0 read */
678 #define DORQ_REG_DORQ_PRTY_STS 0x170184
679 /* [RW 8] The address to write the DPM CID to STORM. */
680 #define DORQ_REG_DPM_CID_ADDR 0x170044
681 /* [RW 5] The DPM mode CID extraction offset. */
682 #define DORQ_REG_DPM_CID_OFST 0x170030
683 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
684 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
685 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
686 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
687 /* [R 13] Current value of the DQ FIFO fill level according to following
688 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
689 doorbell. */
690 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
691 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
692 equal to full threshold; reset on full clear. */
693 #define DORQ_REG_DQ_FULL_ST 0x1700c0
694 /* [RW 28] The value sent to CM header in the case of CFC load error. */
695 #define DORQ_REG_ERR_CMHEAD 0x170058
696 #define DORQ_REG_IF_EN 0x170004
697 #define DORQ_REG_MODE_ACT 0x170008
698 /* [RW 5] The normal mode CID extraction offset. */
699 #define DORQ_REG_NORM_CID_OFST 0x17002c
700 /* [RW 28] TCM Header when only TCP context is loaded. */
701 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
702 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
703 Interface. */
704 #define DORQ_REG_OUTST_REQ 0x17003c
705 #define DORQ_REG_REGN 0x170038
706 /* [R 4] Current value of response A counter credit. Initial credit is
707 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
708 register. */
709 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
710 /* [R 4] Current value of response B counter credit. Initial credit is
711 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
712 register. */
713 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
714 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
715 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
716 read reads this written value. */
717 #define DORQ_REG_RSP_INIT_CRD 0x170048
718 /* [RW 4] Initial activity counter value on the load request; when the
719 shortcut is done. */
720 #define DORQ_REG_SHRT_ACT_CNT 0x170070
721 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
722 #define DORQ_REG_SHRT_CMHEAD 0x170054
723 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
724 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
725 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
726 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
727 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
728 #define HC_REG_AGG_INT_0 0x108050
729 #define HC_REG_AGG_INT_1 0x108054
730 #define HC_REG_ATTN_BIT 0x108120
731 #define HC_REG_ATTN_IDX 0x108100
732 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
733 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
734 #define HC_REG_ATTN_NUM_P0 0x108038
735 #define HC_REG_ATTN_NUM_P1 0x10803c
736 #define HC_REG_COMMAND_REG 0x108180
737 #define HC_REG_CONFIG_0 0x108000
738 #define HC_REG_CONFIG_1 0x108004
739 #define HC_REG_FUNC_NUM_P0 0x1080ac
740 #define HC_REG_FUNC_NUM_P1 0x1080b0
741 /* [RW 3] Parity mask register #0 read/write */
742 #define HC_REG_HC_PRTY_MASK 0x1080a0
743 /* [R 3] Parity register #0 read */
744 #define HC_REG_HC_PRTY_STS 0x108094
745 #define HC_REG_INT_MASK 0x108108
746 #define HC_REG_LEADING_EDGE_0 0x108040
747 #define HC_REG_LEADING_EDGE_1 0x108048
748 #define HC_REG_P0_PROD_CONS 0x108200
749 #define HC_REG_P1_PROD_CONS 0x108400
750 #define HC_REG_PBA_COMMAND 0x108140
751 #define HC_REG_PCI_CONFIG_0 0x108010
752 #define HC_REG_PCI_CONFIG_1 0x108014
753 #define HC_REG_STATISTIC_COUNTERS 0x109000
754 #define HC_REG_TRAILING_EDGE_0 0x108044
755 #define HC_REG_TRAILING_EDGE_1 0x10804c
756 #define HC_REG_UC_RAM_ADDR_0 0x108028
757 #define HC_REG_UC_RAM_ADDR_1 0x108030
758 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
759 #define HC_REG_VQID_0 0x108008
760 #define HC_REG_VQID_1 0x10800c
761 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
762 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
763 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
764 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
765 #define MCP_REG_MCPR_NVM_READ 0x86410
766 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
767 #define MCP_REG_MCPR_NVM_WRITE 0x86408
768 #define MCP_REG_MCPR_SCRATCH 0xa0000
769 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
770 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
771 /* [R 32] read first 32 bit after inversion of function 0. mapped as
772 follows: [0] NIG attention for function0; [1] NIG attention for
773 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
774 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
775 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
776 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
777 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
778 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
779 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
780 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
781 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
782 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
783 Parity error; [31] PBF Hw interrupt; */
784 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
785 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
786 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
787 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
788 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
789 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
790 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
791 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
792 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
793 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
794 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
795 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
796 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
797 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
798 interrupt; */
799 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
800 /* [R 32] read second 32 bit after inversion of function 0. mapped as
801 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
802 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
803 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
804 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
805 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
806 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
807 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
808 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
809 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
810 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
811 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
812 interrupt; */
813 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
814 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
815 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
816 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
817 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
818 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
819 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
820 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
821 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
822 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
823 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
824 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
825 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
826 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
827 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
828 /* [R 32] read third 32 bit after inversion of function 0. mapped as
829 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
830 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
831 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
832 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
833 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
834 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
835 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
836 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
837 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
838 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
839 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
840 attn1; */
841 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
842 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
843 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
844 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
845 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
846 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
847 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
848 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
849 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
850 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
851 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
852 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
853 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
854 timers attn_4 func1; [30] General attn0; [31] General attn1; */
855 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
856 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
857 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
858 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
859 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
860 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
861 [14] General attn16; [15] General attn17; [16] General attn18; [17]
862 General attn19; [18] General attn20; [19] General attn21; [20] Main power
863 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
864 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
865 Latched timeout attention; [27] GRC Latched reserved access attention;
866 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
867 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
868 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
869 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
870 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
871 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
872 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
873 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
874 General attn13; [12] General attn14; [13] General attn15; [14] General
875 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
876 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
877 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
878 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
879 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
880 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
881 ump_tx_parity; [31] MCP Latched scpad_parity; */
882 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
883 /* [W 14] write to this register results with the clear of the latched
884 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
885 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
886 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
887 GRC Latched reserved access attention; one in d7 clears Latched
888 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
889 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
890 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
891 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
892 from this register return zero */
893 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
894 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
895 as follows: [0] NIG attention for function0; [1] NIG attention for
896 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
897 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
898 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
899 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
900 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
901 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
902 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
903 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
904 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
905 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
906 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
907 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
908 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
909 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
910 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
911 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
912 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
913 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
914 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
915 as follows: [0] NIG attention for function0; [1] NIG attention for
916 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
917 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
918 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
919 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
920 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
921 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
922 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
923 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
924 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
925 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
926 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
927 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
928 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
929 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
930 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
931 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
932 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
933 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
934 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
935 as follows: [0] NIG attention for function0; [1] NIG attention for
936 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
937 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
938 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
939 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
940 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
941 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
942 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
943 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
944 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
945 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
946 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
947 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
948 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
949 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
950 as follows: [0] NIG attention for function0; [1] NIG attention for
951 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
952 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
953 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
954 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
955 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
956 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
957 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
958 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
959 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
960 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
961 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
962 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
963 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
964 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
965 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
966 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
967 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
968 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
969 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
970 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
971 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
972 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
973 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
974 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
975 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
976 interrupt; */
977 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
978 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
979 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
980 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
981 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
982 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
983 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
984 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
985 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
986 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
987 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
988 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
989 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
990 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
991 interrupt; */
992 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
993 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
994 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
995 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
996 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
997 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
998 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
999 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1000 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1001 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1002 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1003 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1004 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1005 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1006 interrupt; */
1007 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1008 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1009 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1010 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1011 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1012 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1013 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1014 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1015 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1016 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1017 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1018 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1019 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1020 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1021 interrupt; */
1022 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1023 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1024 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1025 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1026 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1027 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1028 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1029 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1030 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1031 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1032 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1033 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1034 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1035 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1036 attn1; */
1037 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1038 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1039 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1040 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1041 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1042 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1043 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1044 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1045 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1046 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1047 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1048 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1049 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1050 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1051 attn1; */
1052 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1053 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1054 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1055 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1056 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1057 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1058 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1059 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1060 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1061 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1062 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1063 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1064 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1065 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1066 attn1; */
1067 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1068 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1069 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1070 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1071 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1072 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1073 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1074 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1075 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1076 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1077 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1078 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1079 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1080 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1081 attn1; */
1082 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1083 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1084 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1085 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1086 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1087 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1088 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1089 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1090 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1091 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1092 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1093 Latched timeout attention; [27] GRC Latched reserved access attention;
1094 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1095 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1096 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1097 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1098 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1099 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1100 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1101 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1102 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1103 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1104 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1105 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1106 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1107 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1108 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1109 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1110 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1111 Latched timeout attention; [27] GRC Latched reserved access attention;
1112 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1113 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1114 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1115 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1116 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1117 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1118 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1119 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1120 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1121 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1122 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1123 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1124 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1125 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1126 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1127 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1128 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1129 Latched timeout attention; [27] GRC Latched reserved access attention;
1130 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1131 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1132 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1133 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1134 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1135 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1136 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1137 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1138 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1139 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1140 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1141 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1142 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1143 Latched timeout attention; [27] GRC Latched reserved access attention;
1144 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1145 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1146 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1147 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1148 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1149 128 bit vector */
1150 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1151 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1152 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1153 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1154 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1155 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1156 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1157 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1158 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1159 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1160 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1161 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1162 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1163 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1164 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1165 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1166 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1167 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1168 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1169 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1170 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1171 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1172 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1173 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1174 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1175 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1176 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1177 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1178 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1179 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1180 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1181 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1182 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1183 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1184 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1185 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1186 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1187 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1188 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1189 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1190 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1191 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1192 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1193 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1194 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1195 [9:8] = raserved. Zero = mask; one = unmask */
1196 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1197 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1198 /* [RW 1] If set a system kill occurred */
1199 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1200 /* [RW 32] Represent the status of the input vector to the AEU when a system
1201 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1202 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1203 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1204 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1205 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1206 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1207 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1208 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1209 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1210 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1211 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1212 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1213 interrupt; */
1214 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1215 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1216 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1217 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1218 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1219 Port. */
1220 #define MISC_REG_BOND_ID 0xa400
1221 /* [R 8] These bits indicate the metal revision of the chip. This value
1222 starts at 0x00 for each all-layer tape-out and increments by one for each
1223 tape-out. */
1224 #define MISC_REG_CHIP_METAL 0xa404
1225 /* [R 16] These bits indicate the part number for the chip. */
1226 #define MISC_REG_CHIP_NUM 0xa408
1227 /* [R 4] These bits indicate the base revision of the chip. This value
1228 starts at 0x0 for the A0 tape-out and increments by one for each
1229 all-layer tape-out. */
1230 #define MISC_REG_CHIP_REV 0xa40c
1231 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1232 32 clients. Each client can be controlled by one driver only. One in each
1233 bit represent that this driver control the appropriate client (Ex: bit 5
1234 is set means this driver control client number 5). addr1 = set; addr0 =
1235 clear; read from both addresses will give the same result = status. write
1236 to address 1 will set a request to control all the clients that their
1237 appropriate bit (in the write command) is set. if the client is free (the
1238 appropriate bit in all the other drivers is clear) one will be written to
1239 that driver register; if the client isn't free the bit will remain zero.
1240 if the appropriate bit is set (the driver request to gain control on a
1241 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1242 interrupt will be asserted). write to address 0 will set a request to
1243 free all the clients that their appropriate bit (in the write command) is
1244 set. if the appropriate bit is clear (the driver request to free a client
1245 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1246 be asserted). */
1247 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1248 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1249 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1250 only. */
1251 #define MISC_REG_E1HMF_MODE 0xa5f8
1252 /* [RW 32] Debug only: spare RW register reset by core reset */
1253 #define MISC_REG_GENERIC_CR_0 0xa460
1254 /* [RW 32] Debug only: spare RW register reset by por reset */
1255 #define MISC_REG_GENERIC_POR_1 0xa474
1256 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1257 these bits is written as a '1'; the corresponding SPIO bit will turn off
1258 it's drivers and become an input. This is the reset state of all GPIO
1259 pins. The read value of these bits will be a '1' if that last command
1260 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1261 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1262 as a '1'; the corresponding GPIO bit will drive low. The read value of
1263 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1264 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1265 SET When any of these bits is written as a '1'; the corresponding GPIO
1266 bit will drive high (if it has that capability). The read value of these
1267 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1268 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1269 RO; These bits indicate the read value of each of the eight GPIO pins.
1270 This is the result value of the pin; not the drive value. Writing these
1271 bits will have not effect. */
1272 #define MISC_REG_GPIO 0xa490
1273 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1274 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1275 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1276 [7] p1_gpio_3; */
1277 #define MISC_REG_GPIO_EVENT_EN 0xa2bc
1278 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1279 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1280 This will acknowledge an interrupt on the falling edge of corresponding
1281 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1282 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1283 register. This will acknowledge an interrupt on the rising edge of
1284 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1285 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1286 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1287 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1288 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1289 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1290 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1291 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1292 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1293 set when the GPIO input does not match the current value in #OLD_VALUE
1294 (reset value 0). */
1295 #define MISC_REG_GPIO_INT 0xa494
1296 /* [R 28] this field hold the last information that caused reserved
1297 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1298 [27:24] the master that caused the attention - according to the following
1299 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1300 dbu; 8 = dmae */
1301 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1302 /* [R 28] this field hold the last information that caused timeout
1303 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1304 [27:24] the master that caused the attention - according to the following
1305 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1306 dbu; 8 = dmae */
1307 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1308 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1309 access that does not finish within
1310 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1311 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1312 assert it attention output. */
1313 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1314 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1315 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1316 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1317 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1318 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1319 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1320 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1321 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1322 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1323 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1324 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1325 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1326 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1327 connected to RESET input directly. [15] capRetry_en (reset value 0)
1328 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1329 value 0) bit to continuously monitor vco freq (inverted). [17]
1330 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1331 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1332 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1333 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1334 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1335 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1336 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1337 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1338 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1339 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1340 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1341 register bits. */
1342 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1343 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1344 /* [RW 4] Interrupt mask register #0 read/write */
1345 #define MISC_REG_MISC_INT_MASK 0xa388
1346 /* [RW 1] Parity mask register #0 read/write */
1347 #define MISC_REG_MISC_PRTY_MASK 0xa398
1348 /* [R 1] Parity register #0 read */
1349 #define MISC_REG_MISC_PRTY_STS 0xa38c
1350 #define MISC_REG_NIG_WOL_P0 0xa270
1351 #define MISC_REG_NIG_WOL_P1 0xa274
1352 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1353 assertion */
1354 #define MISC_REG_PCIE_HOT_RESET 0xa618
1355 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1356 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1357 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1358 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1359 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1360 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1361 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1362 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1363 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1364 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1365 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1366 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1367 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1368 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1369 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1370 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1371 testa_en (reset value 0); */
1372 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1373 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1374 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1375 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1376 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1377 write/read zero = the specific block is in reset; addr 0-wr- the write
1378 value will be written to the register; addr 1-set - one will be written
1379 to all the bits that have the value of one in the data written (bits that
1380 have the value of zero will not be change) ; addr 2-clear - zero will be
1381 written to all the bits that have the value of one in the data written
1382 (bits that have the value of zero will not be change); addr 3-ignore;
1383 read ignore from all addr except addr 00; inside order of the bits is:
1384 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1385 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1386 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1387 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1388 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1389 rst_pxp_rq_rd_wr; 31:17] reserved */
1390 #define MISC_REG_RESET_REG_2 0xa590
1391 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1392 shared with the driver resides */
1393 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1394 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1395 the corresponding SPIO bit will turn off it's drivers and become an
1396 input. This is the reset state of all SPIO pins. The read value of these
1397 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1398 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1399 is written as a '1'; the corresponding SPIO bit will drive low. The read
1400 value of these bits will be a '1' if that last command (#SET; #CLR; or
1401 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1402 these bits is written as a '1'; the corresponding SPIO bit will drive
1403 high (if it has that capability). The read value of these bits will be a
1404 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1405 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1406 each of the eight SPIO pins. This is the result value of the pin; not the
1407 drive value. Writing these bits will have not effect. Each 8 bits field
1408 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1409 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1410 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1411 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1412 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1413 select VAUX supply. (This is an output pin only; it is not controlled by
1414 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1415 field is not applicable for this pin; only the VALUE fields is relevant -
1416 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1417 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1418 device ID select; read by UMP firmware. */
1419 #define MISC_REG_SPIO 0xa4fc
1420 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1421 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1422 [7:0] reserved */
1423 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1424 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1425 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1426 interrupt on the falling edge of corresponding SPIO input (reset value
1427 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1428 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1429 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1430 RO; These bits indicate the old value of the SPIO input value. When the
1431 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1432 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1433 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1434 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1435 RO; These bits indicate the current SPIO interrupt state for each SPIO
1436 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1437 command bit is written. This bit is set when the SPIO input does not
1438 match the current value in #OLD_VALUE (reset value 0). */
1439 #define MISC_REG_SPIO_INT 0xa500
1440 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1441 the counter reached zero and the reload bit
1442 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1443 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1444 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1445 in this register. addres 0 - timer 1; address 1 - timer 2, ... address 7 -
1446 timer 8 */
1447 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1448 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1449 loaded; 0-prepare; -unprepare */
1450 #define MISC_REG_UNPREPARED 0xa424
1451 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1452 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1453 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1454 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1455 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1456 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1457 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1458 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1459 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1460 /* [RW 1] Input enable for RX_BMAC0 IF */
1461 #define NIG_REG_BMAC0_IN_EN 0x100ac
1462 /* [RW 1] output enable for TX_BMAC0 IF */
1463 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1464 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1465 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1466 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1467 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1468 /* [RW 1] output enable for RX BRB1 port0 IF */
1469 #define NIG_REG_BRB0_OUT_EN 0x100f8
1470 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1471 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1472 /* [RW 1] output enable for RX BRB1 port1 IF */
1473 #define NIG_REG_BRB1_OUT_EN 0x100fc
1474 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1475 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1476 /* [RW 1] output enable for RX BRB1 LP IF */
1477 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1478 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1479 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1480 72:73]-vnic_num; 81:74]-sideband_info */
1481 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1482 /* [RW 1] Input enable for TX Debug packet */
1483 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1484 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1485 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1486 First packet may be deleted from the middle. And last packet will be
1487 always deleted till the end. */
1488 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1489 /* [RW 1] Output enable to EMAC0 */
1490 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1491 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1492 to emac for port0; other way to bmac for port0 */
1493 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1494 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1495 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1496 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1497 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1498 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1499 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1500 /* [RW 1] Input enable for RX_EMAC0 IF */
1501 #define NIG_REG_EMAC0_IN_EN 0x100a4
1502 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1503 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1504 /* [R 1] status from emac0. This bit is set when MDINT from either the
1505 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1506 be cleared in the attached PHY device that is driving the MINT pin. */
1507 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1508 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1509 are described in appendix A. In order to access the BMAC0 registers; the
1510 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1511 added to each BMAC register offset */
1512 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1513 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1514 are described in appendix A. In order to access the BMAC0 registers; the
1515 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1516 added to each BMAC register offset */
1517 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1518 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1519 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1520 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1521 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1522 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1523 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
1524 logic for interrupts must be used. Enable per bit of interrupt of
1525 ~latch_status.latch_status */
1526 #define NIG_REG_LATCH_BC_0 0x16210
1527 /* [RW 27] Latch for each interrupt from Unicore.b[0]
1528 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
1529 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
1530 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
1531 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
1532 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
1533 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
1534 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
1535 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
1536 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
1537 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
1538 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
1539 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
1540 #define NIG_REG_LATCH_STATUS_0 0x18000
1541 /* [RW 1] led 10g for port 0 */
1542 #define NIG_REG_LED_10G_P0 0x10320
1543 /* [RW 1] led 10g for port 1 */
1544 #define NIG_REG_LED_10G_P1 0x10324
1545 /* [RW 1] Port0: This bit is set to enable the use of the
1546 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1547 defined below. If this bit is cleared; then the blink rate will be about
1548 8Hz. */
1549 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1550 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1551 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1552 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1553 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1554 /* [RW 1] Port0: If set along with the
1555 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1556 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1557 bit; the Traffic LED will blink with the blink rate specified in
1558 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1559 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1560 fields. */
1561 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1562 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1563 Traffic LED will then be controlled via bit ~nig_registers_
1564 led_control_traffic_p0.led_control_traffic_p0 and bit
1565 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1566 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1567 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1568 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1569 set; the LED will blink with blink rate specified in
1570 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1571 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1572 fields. */
1573 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1574 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1575 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1576 #define NIG_REG_LED_MODE_P0 0x102f0
1577 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1578 tsdm enable; b2- usdm enable */
1579 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
1580 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
1581 /* [RW 1] SAFC enable for port0. This register may get 1 only when
1582 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1583 port */
1584 #define NIG_REG_LLFC_ENABLE_0 0x16208
1585 /* [RW 16] classes are high-priority for port0 */
1586 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
1587 /* [RW 16] classes are low-priority for port0 */
1588 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
1589 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1590 #define NIG_REG_LLFC_OUT_EN_0 0x160c8
1591 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1592 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
1593 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1594 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
1595 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1596 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1597 /* [RW 2] Determine the classification participants. 0: no classification.1:
1598 classification upon VLAN id. 2: classification upon MAC address. 3:
1599 classification upon both VLAN id & MAC addr. */
1600 #define NIG_REG_LLH0_CLS_TYPE 0x16080
1601 /* [RW 32] cm header for llh0 */
1602 #define NIG_REG_LLH0_CM_HEADER 0x1007c
1603 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1604 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1605 /* [RW 16] destination TCP address 1. The LLH will look for this address in
1606 all incoming packets. */
1607 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
1608 /* [RW 16] destination UDP address 1 The LLH will look for this address in
1609 all incoming packets. */
1610 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
1611 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
1612 /* [RW 8] event id for llh0 */
1613 #define NIG_REG_LLH0_EVENT_ID 0x10084
1614 #define NIG_REG_LLH0_FUNC_EN 0x160fc
1615 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1616 /* [RW 1] Determine the IP version to look for in
1617 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1618 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1619 /* [RW 1] t bit for llh0 */
1620 #define NIG_REG_LLH0_T_BIT 0x10074
1621 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1622 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
1623 /* [RW 8] init credit counter for port0 in LLH */
1624 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1625 #define NIG_REG_LLH0_XCM_MASK 0x10130
1626 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
1627 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1628 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1629 /* [RW 2] Determine the classification participants. 0: no classification.1:
1630 classification upon VLAN id. 2: classification upon MAC address. 3:
1631 classification upon both VLAN id & MAC addr. */
1632 #define NIG_REG_LLH1_CLS_TYPE 0x16084
1633 /* [RW 32] cm header for llh1 */
1634 #define NIG_REG_LLH1_CM_HEADER 0x10080
1635 #define NIG_REG_LLH1_ERROR_MASK 0x10090
1636 /* [RW 8] event id for llh1 */
1637 #define NIG_REG_LLH1_EVENT_ID 0x10088
1638 /* [RW 8] init credit counter for port1 in LLH */
1639 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1640 #define NIG_REG_LLH1_XCM_MASK 0x10134
1641 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
1642 e1hov */
1643 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
1644 /* [RW 1] When this bit is set; the LLH will classify the packet before
1645 sending it to the BRB or calculating WoL on it. */
1646 #define NIG_REG_LLH_MF_MODE 0x16024
1647 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1648 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1649 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1650 #define NIG_REG_NIG_EMAC0_EN 0x1003c
1651 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1652 #define NIG_REG_NIG_EMAC1_EN 0x10040
1653 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1654 EMAC0 to strip the CRC from the ingress packets. */
1655 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1656 /* [R 32] Interrupt register #0 read */
1657 #define NIG_REG_NIG_INT_STS_0 0x103b0
1658 #define NIG_REG_NIG_INT_STS_1 0x103c0
1659 /* [R 32] Parity register #0 read */
1660 #define NIG_REG_NIG_PRTY_STS 0x103d0
1661 /* [RW 1] Pause enable for port0. This register may get 1 only when
1662 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
1663 port */
1664 #define NIG_REG_PAUSE_ENABLE_0 0x160c0
1665 /* [RW 1] Input enable for RX PBF LP IF */
1666 #define NIG_REG_PBF_LB_IN_EN 0x100b4
1667 /* [RW 1] Value of this register will be transmitted to port swap when
1668 ~nig_registers_strap_override.strap_override =1 */
1669 #define NIG_REG_PORT_SWAP 0x10394
1670 /* [RW 1] output enable for RX parser descriptor IF */
1671 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
1672 /* [RW 1] Input enable for RX parser request IF */
1673 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
1674 /* [RW 5] control to serdes - CL45 DEVAD */
1675 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
1676 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
1677 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
1678 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1679 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1680 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1681 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1682 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1683 for port0 */
1684 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1685 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
1686 for port0 */
1687 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
1688 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1689 between 1024 and 1522 bytes for port0 */
1690 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
1691 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1692 between 1523 bytes and above for port0 */
1693 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
1694 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1695 for port1 */
1696 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
1697 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1698 between 1024 and 1522 bytes for port1 */
1699 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
1700 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1701 between 1523 bytes and above for port1 */
1702 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
1703 /* [WB_R 64] Rx statistics : User octets received for LP */
1704 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
1705 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1706 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
1707 /* [RW 1] port swap mux selection. If this register equal to 0 then port
1708 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
1709 ort swap is equal to ~nig_registers_port_swap.port_swap */
1710 #define NIG_REG_STRAP_OVERRIDE 0x10398
1711 /* [RW 1] output enable for RX_XCM0 IF */
1712 #define NIG_REG_XCM0_OUT_EN 0x100f0
1713 /* [RW 1] output enable for RX_XCM1 IF */
1714 #define NIG_REG_XCM1_OUT_EN 0x100f4
1715 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
1716 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
1717 /* [RW 5] control to xgxs - CL45 DEVAD */
1718 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
1719 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
1720 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
1721 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1722 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1723 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
1724 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
1725 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
1726 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
1727 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
1728 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
1729 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
1730 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
1731 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
1732 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
1733 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
1734 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
1735 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
1736 /* [RW 1] Disable processing further tasks from port 0 (after ending the
1737 current task in process). */
1738 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
1739 /* [RW 1] Disable processing further tasks from port 1 (after ending the
1740 current task in process). */
1741 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
1742 /* [RW 1] Disable processing further tasks from port 4 (after ending the
1743 current task in process). */
1744 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
1745 #define PBF_REG_IF_ENABLE_REG 0x140044
1746 /* [RW 1] Init bit. When set the initial credits are copied to the credit
1747 registers (except the port credits). Should be set and then reset after
1748 the configuration of the block has ended. */
1749 #define PBF_REG_INIT 0x140000
1750 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
1751 copied to the credit register. Should be set and then reset after the
1752 configuration of the port has ended. */
1753 #define PBF_REG_INIT_P0 0x140004
1754 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
1755 copied to the credit register. Should be set and then reset after the
1756 configuration of the port has ended. */
1757 #define PBF_REG_INIT_P1 0x140008
1758 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
1759 copied to the credit register. Should be set and then reset after the
1760 configuration of the port has ended. */
1761 #define PBF_REG_INIT_P4 0x14000c
1762 /* [RW 1] Enable for mac interface 0. */
1763 #define PBF_REG_MAC_IF0_ENABLE 0x140030
1764 /* [RW 1] Enable for mac interface 1. */
1765 #define PBF_REG_MAC_IF1_ENABLE 0x140034
1766 /* [RW 1] Enable for the loopback interface. */
1767 #define PBF_REG_MAC_LB_ENABLE 0x140040
1768 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
1769 not suppoterd. */
1770 #define PBF_REG_P0_ARB_THRSH 0x1400e4
1771 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
1772 #define PBF_REG_P0_CREDIT 0x140200
1773 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
1774 lines. */
1775 #define PBF_REG_P0_INIT_CRD 0x1400d0
1776 /* [RW 1] Indication that pause is enabled for port 0. */
1777 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
1778 /* [R 8] Number of tasks in port 0 task queue. */
1779 #define PBF_REG_P0_TASK_CNT 0x140204
1780 /* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
1781 #define PBF_REG_P1_CREDIT 0x140208
1782 /* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
1783 lines. */
1784 #define PBF_REG_P1_INIT_CRD 0x1400d4
1785 /* [R 8] Number of tasks in port 1 task queue. */
1786 #define PBF_REG_P1_TASK_CNT 0x14020c
1787 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
1788 #define PBF_REG_P4_CREDIT 0x140210
1789 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
1790 lines. */
1791 #define PBF_REG_P4_INIT_CRD 0x1400e0
1792 /* [R 8] Number of tasks in port 4 task queue. */
1793 #define PBF_REG_P4_TASK_CNT 0x140214
1794 /* [RW 5] Interrupt mask register #0 read/write */
1795 #define PBF_REG_PBF_INT_MASK 0x1401d4
1796 /* [R 5] Interrupt register #0 read */
1797 #define PBF_REG_PBF_INT_STS 0x1401c8
1798 #define PB_REG_CONTROL 0
1799 /* [RW 2] Interrupt mask register #0 read/write */
1800 #define PB_REG_PB_INT_MASK 0x28
1801 /* [R 2] Interrupt register #0 read */
1802 #define PB_REG_PB_INT_STS 0x1c
1803 /* [RW 4] Parity mask register #0 read/write */
1804 #define PB_REG_PB_PRTY_MASK 0x38
1805 /* [R 4] Parity register #0 read */
1806 #define PB_REG_PB_PRTY_STS 0x2c
1807 #define PRS_REG_A_PRSU_20 0x40134
1808 /* [R 8] debug only: CFC load request current credit. Transaction based. */
1809 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
1810 /* [R 8] debug only: CFC search request current credit. Transaction based. */
1811 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
1812 /* [RW 6] The initial credit for the search message to the CFC interface.
1813 Credit is transaction based. */
1814 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1815 /* [RW 24] CID for port 0 if no match */
1816 #define PRS_REG_CID_PORT_0 0x400fc
1817 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1818 load response is reset and packet type is 0. Used in packet start message
1819 to TCM. */
1820 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
1821 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
1822 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
1823 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
1824 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
1825 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
1826 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1827 load response is set and packet type is 0. Used in packet start message
1828 to TCM. */
1829 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
1830 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
1831 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
1832 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
1833 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
1834 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
1835 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
1836 Used in packet start message to TCM. */
1837 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
1838 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
1839 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
1840 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
1841 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
1842 message to TCM. */
1843 #define PRS_REG_CM_HDR_TYPE_0 0x40078
1844 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
1845 #define PRS_REG_CM_HDR_TYPE_2 0x40080
1846 #define PRS_REG_CM_HDR_TYPE_3 0x40084
1847 #define PRS_REG_CM_HDR_TYPE_4 0x40088
1848 /* [RW 32] The CM header in case there was not a match on the connection */
1849 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
1850 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
1851 #define PRS_REG_E1HOV_MODE 0x401c8
1852 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
1853 start message to TCM. */
1854 #define PRS_REG_EVENT_ID_1 0x40054
1855 #define PRS_REG_EVENT_ID_2 0x40058
1856 #define PRS_REG_EVENT_ID_3 0x4005c
1857 /* [RW 16] The Ethernet type value for FCoE */
1858 #define PRS_REG_FCOE_TYPE 0x401d0
1859 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
1860 load request message. */
1861 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
1862 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
1863 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
1864 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
1865 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
1866 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
1867 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
1868 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
1869 /* [RW 4] The increment value to send in the CFC load request message */
1870 #define PRS_REG_INC_VALUE 0x40048
1871 /* [RW 1] If set indicates not to send messages to CFC on received packets */
1872 #define PRS_REG_NIC_MODE 0x40138
1873 /* [RW 8] The 8-bit event ID for cases where there is no match on the
1874 connection. Used in packet start message to TCM. */
1875 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
1876 /* [ST 24] The number of input CFC flush packets */
1877 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
1878 /* [ST 32] The number of cycles the Parser halted its operation since it
1879 could not allocate the next serial number */
1880 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
1881 /* [ST 24] The number of input packets */
1882 #define PRS_REG_NUM_OF_PACKETS 0x40124
1883 /* [ST 24] The number of input transparent flush packets */
1884 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
1885 /* [RW 8] Context region for received Ethernet packet with a match and
1886 packet type 0. Used in CFC load request message */
1887 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
1888 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
1889 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
1890 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
1891 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
1892 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
1893 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
1894 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
1895 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
1896 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
1897 /* [R 2] debug only: Number of pending requests for header parsing. */
1898 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
1899 /* [R 1] Interrupt register #0 read */
1900 #define PRS_REG_PRS_INT_STS 0x40188
1901 /* [RW 8] Parity mask register #0 read/write */
1902 #define PRS_REG_PRS_PRTY_MASK 0x401a4
1903 /* [R 8] Parity register #0 read */
1904 #define PRS_REG_PRS_PRTY_STS 0x40198
1905 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
1906 request message */
1907 #define PRS_REG_PURE_REGIONS 0x40024
1908 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
1909 serail number was released by SDM but cannot be used because a previous
1910 serial number was not released. */
1911 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
1912 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
1913 serail number was released by SDM but cannot be used because a previous
1914 serial number was not released. */
1915 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
1916 /* [R 4] debug only: SRC current credit. Transaction based. */
1917 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
1918 /* [R 8] debug only: TCM current credit. Cycle based. */
1919 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
1920 /* [R 8] debug only: TSDM current credit. Transaction based. */
1921 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
1922 /* [R 6] Debug only: Number of used entries in the data FIFO */
1923 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
1924 /* [R 7] Debug only: Number of used entries in the header FIFO */
1925 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
1926 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
1927 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
1928 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
1929 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
1930 #define PXP2_REG_PGL_CONTROL0 0x120490
1931 #define PXP2_REG_PGL_CONTROL1 0x120514
1932 #define PXP2_REG_PGL_DEBUG 0x120520
1933 /* [RW 32] third dword data of expansion rom request. this register is
1934 special. reading from it provides a vector outstanding read requests. if
1935 a bit is zero it means that a read request on the corresponding tag did
1936 not finish yet (not all completions have arrived for it) */
1937 #define PXP2_REG_PGL_EXP_ROM2 0x120808
1938 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
1939 its[15:0]-address */
1940 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
1941 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
1942 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
1943 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
1944 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
1945 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
1946 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
1947 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
1948 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
1949 its[15:0]-address */
1950 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
1951 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
1952 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
1953 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
1954 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
1955 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
1956 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
1957 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
1958 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
1959 its[15:0]-address */
1960 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
1961 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
1962 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
1963 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
1964 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
1965 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
1966 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
1967 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
1968 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
1969 its[15:0]-address */
1970 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
1971 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
1972 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
1973 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
1974 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
1975 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
1976 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
1977 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
1978 /* [RW 3] this field allows one function to pretend being another function
1979 when accessing any BAR mapped resource within the device. the value of
1980 the field is the number of the function that will be accessed
1981 effectively. after software write to this bit it must read it in order to
1982 know that the new value is updated */
1983 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
1984 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
1985 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
1986 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
1987 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
1988 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
1989 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
1990 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
1991 /* [R 1] this bit indicates that a read request was blocked because of
1992 bus_master_en was deasserted */
1993 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
1994 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
1995 /* [R 18] debug only */
1996 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
1997 /* [R 1] this bit indicates that a write request was blocked because of
1998 bus_master_en was deasserted */
1999 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
2000 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
2001 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2002 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2003 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
2004 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2005 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
2006 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
2007 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
2008 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
2009 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
2010 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
2011 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
2012 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2013 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2014 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
2015 #define PXP2_REG_PSWRQ_BW_L28 0x120318
2016 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
2017 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
2018 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
2019 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
2020 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
2021 #define PXP2_REG_PSWRQ_BW_RD 0x120324
2022 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
2023 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2024 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
2025 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
2026 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2027 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
2028 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
2029 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
2030 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
2031 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
2032 #define PXP2_REG_PSWRQ_BW_WR 0x120328
2033 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
2034 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
2035 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
2036 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
2037 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
2038 /* [RW 32] Interrupt mask register #0 read/write */
2039 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
2040 /* [R 32] Interrupt register #0 read */
2041 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
2042 #define PXP2_REG_PXP2_INT_STS_1 0x120608
2043 /* [RC 32] Interrupt register #0 read clear */
2044 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
2045 /* [RW 32] Parity mask register #0 read/write */
2046 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
2047 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
2048 /* [R 32] Parity register #0 read */
2049 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
2050 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
2051 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
2052 indication about backpressure) */
2053 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
2054 /* [R 8] Debug only: The blocks counter - number of unused block ids */
2055 #define PXP2_REG_RD_BLK_CNT 0x120418
2056 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
2057 Must be bigger than 6. Normally should not be changed. */
2058 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
2059 /* [RW 2] CDU byte swapping mode configuration for master read requests */
2060 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
2061 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
2062 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
2063 /* [R 1] PSWRD internal memories initialization is done */
2064 #define PXP2_REG_RD_INIT_DONE 0x120370
2065 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2066 allocated for vq10 */
2067 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
2068 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2069 allocated for vq11 */
2070 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
2071 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2072 allocated for vq17 */
2073 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
2074 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2075 allocated for vq18 */
2076 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
2077 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2078 allocated for vq19 */
2079 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
2080 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2081 allocated for vq22 */
2082 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
2083 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2084 allocated for vq25 */
2085 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
2086 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2087 allocated for vq6 */
2088 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
2089 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2090 allocated for vq9 */
2091 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
2092 /* [RW 2] PBF byte swapping mode configuration for master read requests */
2093 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
2094 /* [R 1] Debug only: Indication if delivery ports are idle */
2095 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
2096 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
2097 /* [RW 2] QM byte swapping mode configuration for master read requests */
2098 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
2099 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
2100 #define PXP2_REG_RD_SR_CNT 0x120414
2101 /* [RW 2] SRC byte swapping mode configuration for master read requests */
2102 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
2103 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
2104 be bigger than 1. Normally should not be changed. */
2105 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
2106 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
2107 #define PXP2_REG_RD_START_INIT 0x12036c
2108 /* [RW 2] TM byte swapping mode configuration for master read requests */
2109 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
2110 /* [RW 10] Bandwidth addition to VQ0 write requests */
2111 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
2112 /* [RW 10] Bandwidth addition to VQ12 read requests */
2113 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
2114 /* [RW 10] Bandwidth addition to VQ13 read requests */
2115 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
2116 /* [RW 10] Bandwidth addition to VQ14 read requests */
2117 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
2118 /* [RW 10] Bandwidth addition to VQ15 read requests */
2119 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
2120 /* [RW 10] Bandwidth addition to VQ16 read requests */
2121 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
2122 /* [RW 10] Bandwidth addition to VQ17 read requests */
2123 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
2124 /* [RW 10] Bandwidth addition to VQ18 read requests */
2125 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
2126 /* [RW 10] Bandwidth addition to VQ19 read requests */
2127 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
2128 /* [RW 10] Bandwidth addition to VQ20 read requests */
2129 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
2130 /* [RW 10] Bandwidth addition to VQ22 read requests */
2131 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
2132 /* [RW 10] Bandwidth addition to VQ23 read requests */
2133 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
2134 /* [RW 10] Bandwidth addition to VQ24 read requests */
2135 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
2136 /* [RW 10] Bandwidth addition to VQ25 read requests */
2137 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
2138 /* [RW 10] Bandwidth addition to VQ26 read requests */
2139 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
2140 /* [RW 10] Bandwidth addition to VQ27 read requests */
2141 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
2142 /* [RW 10] Bandwidth addition to VQ4 read requests */
2143 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
2144 /* [RW 10] Bandwidth addition to VQ5 read requests */
2145 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
2146 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
2147 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
2148 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
2149 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
2150 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
2151 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
2152 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
2153 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
2154 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
2155 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
2156 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
2157 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
2158 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
2159 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
2160 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
2161 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
2162 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
2163 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
2164 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
2165 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
2166 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
2167 #define PXP2_REG_RQ_BW_RD_L22 0x120300
2168 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
2169 #define PXP2_REG_RQ_BW_RD_L23 0x120304
2170 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
2171 #define PXP2_REG_RQ_BW_RD_L24 0x120308
2172 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
2173 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
2174 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
2175 #define PXP2_REG_RQ_BW_RD_L26 0x120310
2176 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
2177 #define PXP2_REG_RQ_BW_RD_L27 0x120314
2178 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
2179 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
2180 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
2181 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
2182 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
2183 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
2184 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
2185 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
2186 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
2187 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
2188 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
2189 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
2190 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
2191 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
2192 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
2193 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
2194 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
2195 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
2196 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
2197 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
2198 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
2199 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
2200 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
2201 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
2202 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
2203 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
2204 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
2205 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
2206 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
2207 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
2208 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
2209 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
2210 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
2211 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
2212 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
2213 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
2214 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
2215 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
2216 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
2217 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
2218 /* [RW 10] Bandwidth addition to VQ29 write requests */
2219 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
2220 /* [RW 10] Bandwidth addition to VQ30 write requests */
2221 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
2222 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
2223 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
2224 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
2225 #define PXP2_REG_RQ_BW_WR_L30 0x120320
2226 /* [RW 7] Bandwidth upper bound for VQ29 */
2227 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2228 /* [RW 7] Bandwidth upper bound for VQ30 */
2229 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
2230 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
2231 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
2232 /* [RW 2] Endian mode for cdu */
2233 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
2234 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
2235 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
2236 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2237 -128k */
2238 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
2239 /* [R 1] 1' indicates that the requester has finished its internal
2240 configuration */
2241 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
2242 /* [RW 2] Endian mode for debug */
2243 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
2244 /* [RW 1] When '1'; requests will enter input buffers but wont get out
2245 towards the glue */
2246 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
2247 /* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */
2248 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
2249 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
2250 be asserted */
2251 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
2252 /* [RW 2] Endian mode for hc */
2253 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
2254 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
2255 compatibility needs; Note that different registers are used per mode */
2256 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
2257 /* [WB 53] Onchip address table */
2258 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
2259 /* [WB 53] Onchip address table - B0 */
2260 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
2261 /* [RW 13] Pending read limiter threshold; in Dwords */
2262 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
2263 /* [RW 2] Endian mode for qm */
2264 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
2265 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
2266 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
2267 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2268 -128k */
2269 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
2270 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
2271 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
2272 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2273 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2274 #define PXP2_REG_RQ_RD_MBS0 0x120160
2275 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
2276 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2277 #define PXP2_REG_RQ_RD_MBS1 0x120168
2278 /* [RW 2] Endian mode for src */
2279 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
2280 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
2281 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
2282 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2283 -128k */
2284 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2285 /* [RW 2] Endian mode for tm */
2286 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
2287 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
2288 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
2289 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2290 -128k */
2291 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
2292 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2293 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
2294 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
2295 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
2296 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2297 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2298 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
2299 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
2300 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
2301 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
2302 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
2303 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
2304 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
2305 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
2306 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
2307 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
2308 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
2309 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
2310 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
2311 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
2312 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
2313 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
2314 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
2315 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
2316 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
2317 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
2318 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
2319 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
2320 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
2321 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
2322 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
2323 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
2324 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
2325 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
2326 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
2327 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
2328 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
2329 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
2330 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
2331 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
2332 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
2333 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
2334 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
2335 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
2336 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
2337 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
2338 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
2339 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
2340 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
2341 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
2342 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
2343 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
2344 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
2345 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
2346 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
2347 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
2348 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
2349 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
2350 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
2351 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
2352 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
2353 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
2354 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
2355 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
2356 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
2357 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
2358 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
2359 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2360 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2361 001:256B; 010: 512B; */
2362 #define PXP2_REG_RQ_WR_MBS0 0x12015c
2363 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2364 001:256B; 010: 512B; */
2365 #define PXP2_REG_RQ_WR_MBS1 0x120164
2366 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2367 buffer reaches this number has_payload will be asserted */
2368 #define PXP2_REG_WR_CDU_MPS 0x1205f0
2369 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2370 buffer reaches this number has_payload will be asserted */
2371 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
2372 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2373 buffer reaches this number has_payload will be asserted */
2374 #define PXP2_REG_WR_DBG_MPS 0x1205e8
2375 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2376 buffer reaches this number has_payload will be asserted */
2377 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
2378 /* [RW 10] if Number of entries in dmae fifo will be higher than this
2379 threshold then has_payload indication will be asserted; the default value
2380 should be equal to > write MBS size! */
2381 #define PXP2_REG_WR_DMAE_TH 0x120368
2382 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2383 buffer reaches this number has_payload will be asserted */
2384 #define PXP2_REG_WR_HC_MPS 0x1205c8
2385 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2386 buffer reaches this number has_payload will be asserted */
2387 #define PXP2_REG_WR_QM_MPS 0x1205dc
2388 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
2389 #define PXP2_REG_WR_REV_MODE 0x120670
2390 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2391 buffer reaches this number has_payload will be asserted */
2392 #define PXP2_REG_WR_SRC_MPS 0x1205e4
2393 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2394 buffer reaches this number has_payload will be asserted */
2395 #define PXP2_REG_WR_TM_MPS 0x1205e0
2396 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2397 buffer reaches this number has_payload will be asserted */
2398 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
2399 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
2400 threshold then has_payload indication will be asserted; the default value
2401 should be equal to > write MBS size! */
2402 #define PXP2_REG_WR_USDMDP_TH 0x120348
2403 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2404 buffer reaches this number has_payload will be asserted */
2405 #define PXP2_REG_WR_USDM_MPS 0x1205cc
2406 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2407 buffer reaches this number has_payload will be asserted */
2408 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
2409 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
2410 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
2411 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2412 this client is waiting for the arbiter. */
2413 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
2414 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
2415 block. Should be used for close the gates. */
2416 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
2417 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
2418 should update accoring to 'hst_discard_doorbells' register when the state
2419 machine is idle */
2420 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
2421 /* [RW 1] When 1; new internal writes arriving to the block are discarded.
2422 Should be used for close the gates. */
2423 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
2424 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
2425 means this PSWHST is discarding inputs from this client. Each bit should
2426 update accoring to 'hst_discard_internal_writes' register when the state
2427 machine is idle. */
2428 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
2429 /* [WB 160] Used for initialization of the inbound interrupts memory */
2430 #define PXP_REG_HST_INBOUND_INT 0x103800
2431 /* [RW 32] Interrupt mask register #0 read/write */
2432 #define PXP_REG_PXP_INT_MASK_0 0x103074
2433 #define PXP_REG_PXP_INT_MASK_1 0x103084
2434 /* [R 32] Interrupt register #0 read */
2435 #define PXP_REG_PXP_INT_STS_0 0x103068
2436 #define PXP_REG_PXP_INT_STS_1 0x103078
2437 /* [RC 32] Interrupt register #0 read clear */
2438 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
2439 /* [RW 26] Parity mask register #0 read/write */
2440 #define PXP_REG_PXP_PRTY_MASK 0x103094
2441 /* [R 26] Parity register #0 read */
2442 #define PXP_REG_PXP_PRTY_STS 0x103088
2443 /* [RW 4] The activity counter initial increment value sent in the load
2444 request */
2445 #define QM_REG_ACTCTRINITVAL_0 0x168040
2446 #define QM_REG_ACTCTRINITVAL_1 0x168044
2447 #define QM_REG_ACTCTRINITVAL_2 0x168048
2448 #define QM_REG_ACTCTRINITVAL_3 0x16804c
2449 /* [RW 32] The base logical address (in bytes) of each physical queue. The
2450 index I represents the physical queue number. The 12 lsbs are ignore and
2451 considered zero so practically there are only 20 bits in this register;
2452 queues 63-0 */
2453 #define QM_REG_BASEADDR 0x168900
2454 /* [RW 32] The base logical address (in bytes) of each physical queue. The
2455 index I represents the physical queue number. The 12 lsbs are ignore and
2456 considered zero so practically there are only 20 bits in this register;
2457 queues 127-64 */
2458 #define QM_REG_BASEADDR_EXT_A 0x16e100
2459 /* [RW 16] The byte credit cost for each task. This value is for both ports */
2460 #define QM_REG_BYTECRDCOST 0x168234
2461 /* [RW 16] The initial byte credit value for both ports. */
2462 #define QM_REG_BYTECRDINITVAL 0x168238
2463 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2464 queue uses port 0 else it uses port 1; queues 31-0 */
2465 #define QM_REG_BYTECRDPORT_LSB 0x168228
2466 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2467 queue uses port 0 else it uses port 1; queues 95-64 */
2468 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
2469 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2470 queue uses port 0 else it uses port 1; queues 63-32 */
2471 #define QM_REG_BYTECRDPORT_MSB 0x168224
2472 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2473 queue uses port 0 else it uses port 1; queues 127-96 */
2474 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
2475 /* [RW 16] The byte credit value that if above the QM is considered almost
2476 full */
2477 #define QM_REG_BYTECREDITAFULLTHR 0x168094
2478 /* [RW 4] The initial credit for interface */
2479 #define QM_REG_CMINITCRD_0 0x1680cc
2480 #define QM_REG_CMINITCRD_1 0x1680d0
2481 #define QM_REG_CMINITCRD_2 0x1680d4
2482 #define QM_REG_CMINITCRD_3 0x1680d8
2483 #define QM_REG_CMINITCRD_4 0x1680dc
2484 #define QM_REG_CMINITCRD_5 0x1680e0
2485 #define QM_REG_CMINITCRD_6 0x1680e4
2486 #define QM_REG_CMINITCRD_7 0x1680e8
2487 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
2488 is masked */
2489 #define QM_REG_CMINTEN 0x1680ec
2490 /* [RW 12] A bit vector which indicates which one of the queues are tied to
2491 interface 0 */
2492 #define QM_REG_CMINTVOQMASK_0 0x1681f4
2493 #define QM_REG_CMINTVOQMASK_1 0x1681f8
2494 #define QM_REG_CMINTVOQMASK_2 0x1681fc
2495 #define QM_REG_CMINTVOQMASK_3 0x168200
2496 #define QM_REG_CMINTVOQMASK_4 0x168204
2497 #define QM_REG_CMINTVOQMASK_5 0x168208
2498 #define QM_REG_CMINTVOQMASK_6 0x16820c
2499 #define QM_REG_CMINTVOQMASK_7 0x168210
2500 /* [RW 20] The number of connections divided by 16 which dictates the size
2501 of each queue which belongs to even function number. */
2502 #define QM_REG_CONNNUM_0 0x168020
2503 /* [R 6] Keep the fill level of the fifo from write client 4 */
2504 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
2505 /* [RW 8] The context regions sent in the CFC load request */
2506 #define QM_REG_CTXREG_0 0x168030
2507 #define QM_REG_CTXREG_1 0x168034
2508 #define QM_REG_CTXREG_2 0x168038
2509 #define QM_REG_CTXREG_3 0x16803c
2510 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
2511 bypass enable */
2512 #define QM_REG_ENBYPVOQMASK 0x16823c
2513 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2514 physical queue uses the byte credit; queues 31-0 */
2515 #define QM_REG_ENBYTECRD_LSB 0x168220
2516 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2517 physical queue uses the byte credit; queues 95-64 */
2518 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
2519 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2520 physical queue uses the byte credit; queues 63-32 */
2521 #define QM_REG_ENBYTECRD_MSB 0x16821c
2522 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2523 physical queue uses the byte credit; queues 127-96 */
2524 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
2525 /* [RW 4] If cleared then the secondary interface will not be served by the
2526 RR arbiter */
2527 #define QM_REG_ENSEC 0x1680f0
2528 /* [RW 32] NA */
2529 #define QM_REG_FUNCNUMSEL_LSB 0x168230
2530 /* [RW 32] NA */
2531 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
2532 /* [RW 32] A mask register to mask the Almost empty signals which will not
2533 be use for the almost empty indication to the HW block; queues 31:0 */
2534 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
2535 /* [RW 32] A mask register to mask the Almost empty signals which will not
2536 be use for the almost empty indication to the HW block; queues 95-64 */
2537 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
2538 /* [RW 32] A mask register to mask the Almost empty signals which will not
2539 be use for the almost empty indication to the HW block; queues 63:32 */
2540 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
2541 /* [RW 32] A mask register to mask the Almost empty signals which will not
2542 be use for the almost empty indication to the HW block; queues 127-96 */
2543 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
2544 /* [RW 4] The number of outstanding request to CFC */
2545 #define QM_REG_OUTLDREQ 0x168804
2546 /* [RC 1] A flag to indicate that overflow error occurred in one of the
2547 queues. */
2548 #define QM_REG_OVFERROR 0x16805c
2549 /* [RC 7] the Q where the overflow occurs */
2550 #define QM_REG_OVFQNUM 0x168058
2551 /* [R 16] Pause state for physical queues 15-0 */
2552 #define QM_REG_PAUSESTATE0 0x168410
2553 /* [R 16] Pause state for physical queues 31-16 */
2554 #define QM_REG_PAUSESTATE1 0x168414
2555 /* [R 16] Pause state for physical queues 47-32 */
2556 #define QM_REG_PAUSESTATE2 0x16e684
2557 /* [R 16] Pause state for physical queues 63-48 */
2558 #define QM_REG_PAUSESTATE3 0x16e688
2559 /* [R 16] Pause state for physical queues 79-64 */
2560 #define QM_REG_PAUSESTATE4 0x16e68c
2561 /* [R 16] Pause state for physical queues 95-80 */
2562 #define QM_REG_PAUSESTATE5 0x16e690
2563 /* [R 16] Pause state for physical queues 111-96 */
2564 #define QM_REG_PAUSESTATE6 0x16e694
2565 /* [R 16] Pause state for physical queues 127-112 */
2566 #define QM_REG_PAUSESTATE7 0x16e698
2567 /* [RW 2] The PCI attributes field used in the PCI request. */
2568 #define QM_REG_PCIREQAT 0x168054
2569 /* [R 16] The byte credit of port 0 */
2570 #define QM_REG_PORT0BYTECRD 0x168300
2571 /* [R 16] The byte credit of port 1 */
2572 #define QM_REG_PORT1BYTECRD 0x168304
2573 /* [RW 3] pci function number of queues 15-0 */
2574 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
2575 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
2576 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
2577 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
2578 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
2579 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
2580 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
2581 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
2582 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
2583 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2584 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2585 #define QM_REG_PTRTBL 0x168a00
2586 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
2587 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2588 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2589 #define QM_REG_PTRTBL_EXT_A 0x16e200
2590 /* [RW 2] Interrupt mask register #0 read/write */
2591 #define QM_REG_QM_INT_MASK 0x168444
2592 /* [R 2] Interrupt register #0 read */
2593 #define QM_REG_QM_INT_STS 0x168438
2594 /* [RW 12] Parity mask register #0 read/write */
2595 #define QM_REG_QM_PRTY_MASK 0x168454
2596 /* [R 12] Parity register #0 read */
2597 #define QM_REG_QM_PRTY_STS 0x168448
2598 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2599 #define QM_REG_QSTATUS_HIGH 0x16802c
2600 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
2601 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
2602 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2603 #define QM_REG_QSTATUS_LOW 0x168028
2604 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
2605 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
2606 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
2607 #define QM_REG_QTASKCTR_0 0x168308
2608 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
2609 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
2610 /* [RW 4] Queue tied to VOQ */
2611 #define QM_REG_QVOQIDX_0 0x1680f4
2612 #define QM_REG_QVOQIDX_10 0x16811c
2613 #define QM_REG_QVOQIDX_100 0x16e49c
2614 #define QM_REG_QVOQIDX_101 0x16e4a0
2615 #define QM_REG_QVOQIDX_102 0x16e4a4
2616 #define QM_REG_QVOQIDX_103 0x16e4a8
2617 #define QM_REG_QVOQIDX_104 0x16e4ac
2618 #define QM_REG_QVOQIDX_105 0x16e4b0
2619 #define QM_REG_QVOQIDX_106 0x16e4b4
2620 #define QM_REG_QVOQIDX_107 0x16e4b8
2621 #define QM_REG_QVOQIDX_108 0x16e4bc
2622 #define QM_REG_QVOQIDX_109 0x16e4c0
2623 #define QM_REG_QVOQIDX_11 0x168120
2624 #define QM_REG_QVOQIDX_110 0x16e4c4
2625 #define QM_REG_QVOQIDX_111 0x16e4c8
2626 #define QM_REG_QVOQIDX_112 0x16e4cc
2627 #define QM_REG_QVOQIDX_113 0x16e4d0
2628 #define QM_REG_QVOQIDX_114 0x16e4d4
2629 #define QM_REG_QVOQIDX_115 0x16e4d8
2630 #define QM_REG_QVOQIDX_116 0x16e4dc
2631 #define QM_REG_QVOQIDX_117 0x16e4e0
2632 #define QM_REG_QVOQIDX_118 0x16e4e4
2633 #define QM_REG_QVOQIDX_119 0x16e4e8
2634 #define QM_REG_QVOQIDX_12 0x168124
2635 #define QM_REG_QVOQIDX_120 0x16e4ec
2636 #define QM_REG_QVOQIDX_121 0x16e4f0
2637 #define QM_REG_QVOQIDX_122 0x16e4f4
2638 #define QM_REG_QVOQIDX_123 0x16e4f8
2639 #define QM_REG_QVOQIDX_124 0x16e4fc
2640 #define QM_REG_QVOQIDX_125 0x16e500
2641 #define QM_REG_QVOQIDX_126 0x16e504
2642 #define QM_REG_QVOQIDX_127 0x16e508
2643 #define QM_REG_QVOQIDX_13 0x168128
2644 #define QM_REG_QVOQIDX_14 0x16812c
2645 #define QM_REG_QVOQIDX_15 0x168130
2646 #define QM_REG_QVOQIDX_16 0x168134
2647 #define QM_REG_QVOQIDX_17 0x168138
2648 #define QM_REG_QVOQIDX_21 0x168148
2649 #define QM_REG_QVOQIDX_22 0x16814c
2650 #define QM_REG_QVOQIDX_23 0x168150
2651 #define QM_REG_QVOQIDX_24 0x168154
2652 #define QM_REG_QVOQIDX_25 0x168158
2653 #define QM_REG_QVOQIDX_26 0x16815c
2654 #define QM_REG_QVOQIDX_27 0x168160
2655 #define QM_REG_QVOQIDX_28 0x168164
2656 #define QM_REG_QVOQIDX_29 0x168168
2657 #define QM_REG_QVOQIDX_30 0x16816c
2658 #define QM_REG_QVOQIDX_31 0x168170
2659 #define QM_REG_QVOQIDX_32 0x168174
2660 #define QM_REG_QVOQIDX_33 0x168178
2661 #define QM_REG_QVOQIDX_34 0x16817c
2662 #define QM_REG_QVOQIDX_35 0x168180
2663 #define QM_REG_QVOQIDX_36 0x168184
2664 #define QM_REG_QVOQIDX_37 0x168188
2665 #define QM_REG_QVOQIDX_38 0x16818c
2666 #define QM_REG_QVOQIDX_39 0x168190
2667 #define QM_REG_QVOQIDX_40 0x168194
2668 #define QM_REG_QVOQIDX_41 0x168198
2669 #define QM_REG_QVOQIDX_42 0x16819c
2670 #define QM_REG_QVOQIDX_43 0x1681a0
2671 #define QM_REG_QVOQIDX_44 0x1681a4
2672 #define QM_REG_QVOQIDX_45 0x1681a8
2673 #define QM_REG_QVOQIDX_46 0x1681ac
2674 #define QM_REG_QVOQIDX_47 0x1681b0
2675 #define QM_REG_QVOQIDX_48 0x1681b4
2676 #define QM_REG_QVOQIDX_49 0x1681b8
2677 #define QM_REG_QVOQIDX_5 0x168108
2678 #define QM_REG_QVOQIDX_50 0x1681bc
2679 #define QM_REG_QVOQIDX_51 0x1681c0
2680 #define QM_REG_QVOQIDX_52 0x1681c4
2681 #define QM_REG_QVOQIDX_53 0x1681c8
2682 #define QM_REG_QVOQIDX_54 0x1681cc
2683 #define QM_REG_QVOQIDX_55 0x1681d0
2684 #define QM_REG_QVOQIDX_56 0x1681d4
2685 #define QM_REG_QVOQIDX_57 0x1681d8
2686 #define QM_REG_QVOQIDX_58 0x1681dc
2687 #define QM_REG_QVOQIDX_59 0x1681e0
2688 #define QM_REG_QVOQIDX_6 0x16810c
2689 #define QM_REG_QVOQIDX_60 0x1681e4
2690 #define QM_REG_QVOQIDX_61 0x1681e8
2691 #define QM_REG_QVOQIDX_62 0x1681ec
2692 #define QM_REG_QVOQIDX_63 0x1681f0
2693 #define QM_REG_QVOQIDX_64 0x16e40c
2694 #define QM_REG_QVOQIDX_65 0x16e410
2695 #define QM_REG_QVOQIDX_69 0x16e420
2696 #define QM_REG_QVOQIDX_7 0x168110
2697 #define QM_REG_QVOQIDX_70 0x16e424
2698 #define QM_REG_QVOQIDX_71 0x16e428
2699 #define QM_REG_QVOQIDX_72 0x16e42c
2700 #define QM_REG_QVOQIDX_73 0x16e430
2701 #define QM_REG_QVOQIDX_74 0x16e434
2702 #define QM_REG_QVOQIDX_75 0x16e438
2703 #define QM_REG_QVOQIDX_76 0x16e43c
2704 #define QM_REG_QVOQIDX_77 0x16e440
2705 #define QM_REG_QVOQIDX_78 0x16e444
2706 #define QM_REG_QVOQIDX_79 0x16e448
2707 #define QM_REG_QVOQIDX_8 0x168114
2708 #define QM_REG_QVOQIDX_80 0x16e44c
2709 #define QM_REG_QVOQIDX_81 0x16e450
2710 #define QM_REG_QVOQIDX_85 0x16e460
2711 #define QM_REG_QVOQIDX_86 0x16e464
2712 #define QM_REG_QVOQIDX_87 0x16e468
2713 #define QM_REG_QVOQIDX_88 0x16e46c
2714 #define QM_REG_QVOQIDX_89 0x16e470
2715 #define QM_REG_QVOQIDX_9 0x168118
2716 #define QM_REG_QVOQIDX_90 0x16e474
2717 #define QM_REG_QVOQIDX_91 0x16e478
2718 #define QM_REG_QVOQIDX_92 0x16e47c
2719 #define QM_REG_QVOQIDX_93 0x16e480
2720 #define QM_REG_QVOQIDX_94 0x16e484
2721 #define QM_REG_QVOQIDX_95 0x16e488
2722 #define QM_REG_QVOQIDX_96 0x16e48c
2723 #define QM_REG_QVOQIDX_97 0x16e490
2724 #define QM_REG_QVOQIDX_98 0x16e494
2725 #define QM_REG_QVOQIDX_99 0x16e498
2726 /* [RW 1] Initialization bit command */
2727 #define QM_REG_SOFT_RESET 0x168428
2728 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
2729 #define QM_REG_TASKCRDCOST_0 0x16809c
2730 #define QM_REG_TASKCRDCOST_1 0x1680a0
2731 #define QM_REG_TASKCRDCOST_2 0x1680a4
2732 #define QM_REG_TASKCRDCOST_4 0x1680ac
2733 #define QM_REG_TASKCRDCOST_5 0x1680b0
2734 /* [R 6] Keep the fill level of the fifo from write client 3 */
2735 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
2736 /* [R 6] Keep the fill level of the fifo from write client 2 */
2737 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
2738 /* [RC 32] Credit update error register */
2739 #define QM_REG_VOQCRDERRREG 0x168408
2740 /* [R 16] The credit value for each VOQ */
2741 #define QM_REG_VOQCREDIT_0 0x1682d0
2742 #define QM_REG_VOQCREDIT_1 0x1682d4
2743 #define QM_REG_VOQCREDIT_4 0x1682e0
2744 /* [RW 16] The credit value that if above the QM is considered almost full */
2745 #define QM_REG_VOQCREDITAFULLTHR 0x168090
2746 /* [RW 16] The init and maximum credit for each VoQ */
2747 #define QM_REG_VOQINITCREDIT_0 0x168060
2748 #define QM_REG_VOQINITCREDIT_1 0x168064
2749 #define QM_REG_VOQINITCREDIT_2 0x168068
2750 #define QM_REG_VOQINITCREDIT_4 0x168070
2751 #define QM_REG_VOQINITCREDIT_5 0x168074
2752 /* [RW 1] The port of which VOQ belongs */
2753 #define QM_REG_VOQPORT_0 0x1682a0
2754 #define QM_REG_VOQPORT_1 0x1682a4
2755 #define QM_REG_VOQPORT_2 0x1682a8
2756 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2757 #define QM_REG_VOQQMASK_0_LSB 0x168240
2758 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2759 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
2760 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2761 #define QM_REG_VOQQMASK_0_MSB 0x168244
2762 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2763 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
2764 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2765 #define QM_REG_VOQQMASK_10_LSB 0x168290
2766 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2767 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
2768 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2769 #define QM_REG_VOQQMASK_10_MSB 0x168294
2770 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2771 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
2772 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2773 #define QM_REG_VOQQMASK_11_LSB 0x168298
2774 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2775 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
2776 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2777 #define QM_REG_VOQQMASK_11_MSB 0x16829c
2778 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2779 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
2780 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2781 #define QM_REG_VOQQMASK_1_LSB 0x168248
2782 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2783 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
2784 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2785 #define QM_REG_VOQQMASK_1_MSB 0x16824c
2786 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2787 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
2788 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2789 #define QM_REG_VOQQMASK_2_LSB 0x168250
2790 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2791 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
2792 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2793 #define QM_REG_VOQQMASK_2_MSB 0x168254
2794 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2795 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
2796 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2797 #define QM_REG_VOQQMASK_3_LSB 0x168258
2798 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2799 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
2800 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2801 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
2802 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2803 #define QM_REG_VOQQMASK_4_LSB 0x168260
2804 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2805 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
2806 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2807 #define QM_REG_VOQQMASK_4_MSB 0x168264
2808 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2809 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
2810 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2811 #define QM_REG_VOQQMASK_5_LSB 0x168268
2812 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2813 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
2814 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2815 #define QM_REG_VOQQMASK_5_MSB 0x16826c
2816 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2817 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
2818 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2819 #define QM_REG_VOQQMASK_6_LSB 0x168270
2820 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2821 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
2822 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2823 #define QM_REG_VOQQMASK_6_MSB 0x168274
2824 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2825 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
2826 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2827 #define QM_REG_VOQQMASK_7_LSB 0x168278
2828 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2829 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
2830 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2831 #define QM_REG_VOQQMASK_7_MSB 0x16827c
2832 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2833 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
2834 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2835 #define QM_REG_VOQQMASK_8_LSB 0x168280
2836 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2837 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
2838 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2839 #define QM_REG_VOQQMASK_8_MSB 0x168284
2840 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2841 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
2842 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2843 #define QM_REG_VOQQMASK_9_LSB 0x168288
2844 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2845 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
2846 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2847 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
2848 /* [RW 32] Wrr weights */
2849 #define QM_REG_WRRWEIGHTS_0 0x16880c
2850 #define QM_REG_WRRWEIGHTS_1 0x168810
2851 #define QM_REG_WRRWEIGHTS_10 0x168814
2852 #define QM_REG_WRRWEIGHTS_11 0x168818
2853 #define QM_REG_WRRWEIGHTS_12 0x16881c
2854 #define QM_REG_WRRWEIGHTS_13 0x168820
2855 #define QM_REG_WRRWEIGHTS_14 0x168824
2856 #define QM_REG_WRRWEIGHTS_15 0x168828
2857 #define QM_REG_WRRWEIGHTS_16 0x16e000
2858 #define QM_REG_WRRWEIGHTS_17 0x16e004
2859 #define QM_REG_WRRWEIGHTS_18 0x16e008
2860 #define QM_REG_WRRWEIGHTS_19 0x16e00c
2861 #define QM_REG_WRRWEIGHTS_2 0x16882c
2862 #define QM_REG_WRRWEIGHTS_20 0x16e010
2863 #define QM_REG_WRRWEIGHTS_21 0x16e014
2864 #define QM_REG_WRRWEIGHTS_22 0x16e018
2865 #define QM_REG_WRRWEIGHTS_23 0x16e01c
2866 #define QM_REG_WRRWEIGHTS_24 0x16e020
2867 #define QM_REG_WRRWEIGHTS_25 0x16e024
2868 #define QM_REG_WRRWEIGHTS_26 0x16e028
2869 #define QM_REG_WRRWEIGHTS_27 0x16e02c
2870 #define QM_REG_WRRWEIGHTS_28 0x16e030
2871 #define QM_REG_WRRWEIGHTS_29 0x16e034
2872 #define QM_REG_WRRWEIGHTS_3 0x168830
2873 #define QM_REG_WRRWEIGHTS_30 0x16e038
2874 #define QM_REG_WRRWEIGHTS_31 0x16e03c
2875 #define QM_REG_WRRWEIGHTS_4 0x168834
2876 #define QM_REG_WRRWEIGHTS_5 0x168838
2877 #define QM_REG_WRRWEIGHTS_6 0x16883c
2878 #define QM_REG_WRRWEIGHTS_7 0x168840
2879 #define QM_REG_WRRWEIGHTS_8 0x168844
2880 #define QM_REG_WRRWEIGHTS_9 0x168848
2881 /* [R 6] Keep the fill level of the fifo from write client 1 */
2882 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
2883 #define SRC_REG_COUNTFREE0 0x40500
2884 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
2885 ports. If set the searcher support 8 functions. */
2886 #define SRC_REG_E1HMF_ENABLE 0x404cc
2887 #define SRC_REG_FIRSTFREE0 0x40510
2888 #define SRC_REG_KEYRSS0_0 0x40408
2889 #define SRC_REG_KEYRSS0_7 0x40424
2890 #define SRC_REG_KEYRSS1_9 0x40454
2891 #define SRC_REG_KEYSEARCH_0 0x40458
2892 #define SRC_REG_KEYSEARCH_1 0x4045c
2893 #define SRC_REG_KEYSEARCH_2 0x40460
2894 #define SRC_REG_KEYSEARCH_3 0x40464
2895 #define SRC_REG_KEYSEARCH_4 0x40468
2896 #define SRC_REG_KEYSEARCH_5 0x4046c
2897 #define SRC_REG_KEYSEARCH_6 0x40470
2898 #define SRC_REG_KEYSEARCH_7 0x40474
2899 #define SRC_REG_KEYSEARCH_8 0x40478
2900 #define SRC_REG_KEYSEARCH_9 0x4047c
2901 #define SRC_REG_LASTFREE0 0x40530
2902 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
2903 /* [RW 1] Reset internal state machines. */
2904 #define SRC_REG_SOFT_RST 0x4049c
2905 /* [R 3] Interrupt register #0 read */
2906 #define SRC_REG_SRC_INT_STS 0x404ac
2907 /* [RW 3] Parity mask register #0 read/write */
2908 #define SRC_REG_SRC_PRTY_MASK 0x404c8
2909 /* [R 3] Parity register #0 read */
2910 #define SRC_REG_SRC_PRTY_STS 0x404bc
2911 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
2912 #define TCM_REG_CAM_OCCUP 0x5017c
2913 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
2914 disregarded; valid output is deasserted; all other signals are treated as
2915 usual; if 1 - normal activity. */
2916 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
2917 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
2918 are disregarded; all other signals are treated as usual; if 1 - normal
2919 activity. */
2920 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
2921 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
2922 disregarded; valid output is deasserted; all other signals are treated as
2923 usual; if 1 - normal activity. */
2924 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
2925 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
2926 input is disregarded; all other signals are treated as usual; if 1 -
2927 normal activity. */
2928 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
2929 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
2930 the initial credit value; read returns the current value of the credit
2931 counter. Must be initialized to 1 at start-up. */
2932 #define TCM_REG_CFC_INIT_CRD 0x50204
2933 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
2934 weight 8 (the most prioritised); 1 stands for weight 1(least
2935 prioritised); 2 stands for weight 2; tc. */
2936 #define TCM_REG_CP_WEIGHT 0x500c0
2937 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
2938 disregarded; acknowledge output is deasserted; all other signals are
2939 treated as usual; if 1 - normal activity. */
2940 #define TCM_REG_CSEM_IFEN 0x5002c
2941 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
2942 interface. */
2943 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
2944 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
2945 weight 8 (the most prioritised); 1 stands for weight 1(least
2946 prioritised); 2 stands for weight 2; tc. */
2947 #define TCM_REG_CSEM_WEIGHT 0x500bc
2948 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
2949 #define TCM_REG_ERR_EVNT_ID 0x500a0
2950 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
2951 #define TCM_REG_ERR_TCM_HDR 0x5009c
2952 /* [RW 8] The Event ID for Timers expiration. */
2953 #define TCM_REG_EXPR_EVNT_ID 0x500a4
2954 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
2955 writes the initial credit value; read returns the current value of the
2956 credit counter. Must be initialized to 64 at start-up. */
2957 #define TCM_REG_FIC0_INIT_CRD 0x5020c
2958 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
2959 writes the initial credit value; read returns the current value of the
2960 credit counter. Must be initialized to 64 at start-up. */
2961 #define TCM_REG_FIC1_INIT_CRD 0x50210
2962 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
2963 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
2964 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
2965 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
2966 #define TCM_REG_GR_ARB_TYPE 0x50114
2967 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
2968 highest priority is 3. It is supposed that the Store channel is the
2969 compliment of the other 3 groups. */
2970 #define TCM_REG_GR_LD0_PR 0x5011c
2971 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
2972 highest priority is 3. It is supposed that the Store channel is the
2973 compliment of the other 3 groups. */
2974 #define TCM_REG_GR_LD1_PR 0x50120
2975 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
2976 sent to STORM; for a specific connection type. The double REG-pairs are
2977 used to align to STORM context row size of 128 bits. The offset of these
2978 data in the STORM context is always 0. Index _i stands for the connection
2979 type (one of 16). */
2980 #define TCM_REG_N_SM_CTX_LD_0 0x50050
2981 #define TCM_REG_N_SM_CTX_LD_1 0x50054
2982 #define TCM_REG_N_SM_CTX_LD_2 0x50058
2983 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
2984 #define TCM_REG_N_SM_CTX_LD_4 0x50060
2985 #define TCM_REG_N_SM_CTX_LD_5 0x50064
2986 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
2987 acknowledge output is deasserted; all other signals are treated as usual;
2988 if 1 - normal activity. */
2989 #define TCM_REG_PBF_IFEN 0x50024
2990 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
2991 interface. */
2992 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
2993 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
2994 weight 8 (the most prioritised); 1 stands for weight 1(least
2995 prioritised); 2 stands for weight 2; tc. */
2996 #define TCM_REG_PBF_WEIGHT 0x500b4
2997 #define TCM_REG_PHYS_QNUM0_0 0x500e0
2998 #define TCM_REG_PHYS_QNUM0_1 0x500e4
2999 #define TCM_REG_PHYS_QNUM1_0 0x500e8
3000 #define TCM_REG_PHYS_QNUM1_1 0x500ec
3001 #define TCM_REG_PHYS_QNUM2_0 0x500f0
3002 #define TCM_REG_PHYS_QNUM2_1 0x500f4
3003 #define TCM_REG_PHYS_QNUM3_0 0x500f8
3004 #define TCM_REG_PHYS_QNUM3_1 0x500fc
3005 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
3006 acknowledge output is deasserted; all other signals are treated as usual;
3007 if 1 - normal activity. */
3008 #define TCM_REG_PRS_IFEN 0x50020
3009 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
3010 interface. */
3011 #define TCM_REG_PRS_LENGTH_MIS 0x50168
3012 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
3013 weight 8 (the most prioritised); 1 stands for weight 1(least
3014 prioritised); 2 stands for weight 2; tc. */
3015 #define TCM_REG_PRS_WEIGHT 0x500b0
3016 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3017 #define TCM_REG_STOP_EVNT_ID 0x500a8
3018 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
3019 interface. */
3020 #define TCM_REG_STORM_LENGTH_MIS 0x50160
3021 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3022 disregarded; acknowledge output is deasserted; all other signals are
3023 treated as usual; if 1 - normal activity. */
3024 #define TCM_REG_STORM_TCM_IFEN 0x50010
3025 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3026 weight 8 (the most prioritised); 1 stands for weight 1(least
3027 prioritised); 2 stands for weight 2; tc. */
3028 #define TCM_REG_STORM_WEIGHT 0x500ac
3029 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3030 acknowledge output is deasserted; all other signals are treated as usual;
3031 if 1 - normal activity. */
3032 #define TCM_REG_TCM_CFC_IFEN 0x50040
3033 /* [RW 11] Interrupt mask register #0 read/write */
3034 #define TCM_REG_TCM_INT_MASK 0x501dc
3035 /* [R 11] Interrupt register #0 read */
3036 #define TCM_REG_TCM_INT_STS 0x501d0
3037 /* [R 27] Parity register #0 read */
3038 #define TCM_REG_TCM_PRTY_STS 0x501e0
3039 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
3040 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3041 Is used to determine the number of the AG context REG-pairs written back;
3042 when the input message Reg1WbFlg isn't set. */
3043 #define TCM_REG_TCM_REG0_SZ 0x500d8
3044 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3045 disregarded; valid is deasserted; all other signals are treated as usual;
3046 if 1 - normal activity. */
3047 #define TCM_REG_TCM_STORM0_IFEN 0x50004
3048 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3049 disregarded; valid is deasserted; all other signals are treated as usual;
3050 if 1 - normal activity. */
3051 #define TCM_REG_TCM_STORM1_IFEN 0x50008
3052 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3053 disregarded; valid is deasserted; all other signals are treated as usual;
3054 if 1 - normal activity. */
3055 #define TCM_REG_TCM_TQM_IFEN 0x5000c
3056 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3057 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
3058 /* [RW 28] The CM header for Timers expiration command. */
3059 #define TCM_REG_TM_TCM_HDR 0x50098
3060 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3061 disregarded; acknowledge output is deasserted; all other signals are
3062 treated as usual; if 1 - normal activity. */
3063 #define TCM_REG_TM_TCM_IFEN 0x5001c
3064 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
3065 weight 8 (the most prioritised); 1 stands for weight 1(least
3066 prioritised); 2 stands for weight 2; tc. */
3067 #define TCM_REG_TM_WEIGHT 0x500d0
3068 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3069 the initial credit value; read returns the current value of the credit
3070 counter. Must be initialized to 32 at start-up. */
3071 #define TCM_REG_TQM_INIT_CRD 0x5021c
3072 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3073 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3074 prioritised); 2 stands for weight 2; tc. */
3075 #define TCM_REG_TQM_P_WEIGHT 0x500c8
3076 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
3077 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3078 prioritised); 2 stands for weight 2; tc. */
3079 #define TCM_REG_TQM_S_WEIGHT 0x500cc
3080 /* [RW 28] The CM header value for QM request (primary). */
3081 #define TCM_REG_TQM_TCM_HDR_P 0x50090
3082 /* [RW 28] The CM header value for QM request (secondary). */
3083 #define TCM_REG_TQM_TCM_HDR_S 0x50094
3084 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3085 acknowledge output is deasserted; all other signals are treated as usual;
3086 if 1 - normal activity. */
3087 #define TCM_REG_TQM_TCM_IFEN 0x50014
3088 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3089 acknowledge output is deasserted; all other signals are treated as usual;
3090 if 1 - normal activity. */
3091 #define TCM_REG_TSDM_IFEN 0x50018
3092 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
3093 interface. */
3094 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
3095 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3096 weight 8 (the most prioritised); 1 stands for weight 1(least
3097 prioritised); 2 stands for weight 2; tc. */
3098 #define TCM_REG_TSDM_WEIGHT 0x500c4
3099 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
3100 disregarded; acknowledge output is deasserted; all other signals are
3101 treated as usual; if 1 - normal activity. */
3102 #define TCM_REG_USEM_IFEN 0x50028
3103 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
3104 interface. */
3105 #define TCM_REG_USEM_LENGTH_MIS 0x50170
3106 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3107 weight 8 (the most prioritised); 1 stands for weight 1(least
3108 prioritised); 2 stands for weight 2; tc. */
3109 #define TCM_REG_USEM_WEIGHT 0x500b8
3110 /* [RW 21] Indirect access to the descriptor table of the XX protection
3111 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
3112 pointer; 20:16] - next pointer. */
3113 #define TCM_REG_XX_DESCR_TABLE 0x50280
3114 #define TCM_REG_XX_DESCR_TABLE_SIZE 32
3115 /* [R 6] Use to read the value of XX protection Free counter. */
3116 #define TCM_REG_XX_FREE 0x50178
3117 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3118 of the Input Stage XX protection buffer by the XX protection pending
3119 messages. Max credit available - 127.Write writes the initial credit
3120 value; read returns the current value of the credit counter. Must be
3121 initialized to 19 at start-up. */
3122 #define TCM_REG_XX_INIT_CRD 0x50220
3123 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
3124 protection. */
3125 #define TCM_REG_XX_MAX_LL_SZ 0x50044
3126 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3127 protection. ~tcm_registers_xx_free.xx_free is read on read. */
3128 #define TCM_REG_XX_MSG_NUM 0x50224
3129 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3130 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
3131 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3132 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
3133 header pointer. */
3134 #define TCM_REG_XX_TABLE 0x50240
3135 /* [RW 4] Load value for cfc ac credit cnt. */
3136 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
3137 /* [RW 4] Load value for cfc cld credit cnt. */
3138 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
3139 /* [RW 8] Client0 context region. */
3140 #define TM_REG_CL0_CONT_REGION 0x164030
3141 /* [RW 8] Client1 context region. */
3142 #define TM_REG_CL1_CONT_REGION 0x164034
3143 /* [RW 8] Client2 context region. */
3144 #define TM_REG_CL2_CONT_REGION 0x164038
3145 /* [RW 2] Client in High priority client number. */
3146 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
3147 /* [RW 4] Load value for clout0 cred cnt. */
3148 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
3149 /* [RW 4] Load value for clout1 cred cnt. */
3150 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
3151 /* [RW 4] Load value for clout2 cred cnt. */
3152 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
3153 /* [RW 1] Enable client0 input. */
3154 #define TM_REG_EN_CL0_INPUT 0x164008
3155 /* [RW 1] Enable client1 input. */
3156 #define TM_REG_EN_CL1_INPUT 0x16400c
3157 /* [RW 1] Enable client2 input. */
3158 #define TM_REG_EN_CL2_INPUT 0x164010
3159 #define TM_REG_EN_LINEAR0_TIMER 0x164014
3160 /* [RW 1] Enable real time counter. */
3161 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
3162 /* [RW 1] Enable for Timers state machines. */
3163 #define TM_REG_EN_TIMERS 0x164000
3164 /* [RW 4] Load value for expiration credit cnt. CFC max number of
3165 outstanding load requests for timers (expiration) context loading. */
3166 #define TM_REG_EXP_CRDCNT_VAL 0x164238
3167 /* [RW 32] Linear0 logic address. */
3168 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
3169 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
3170 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
3171 /* [WB 64] Linear0 phy address. */
3172 #define TM_REG_LIN0_PHY_ADDR 0x164270
3173 /* [RW 1] Linear0 physical address valid. */
3174 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
3175 #define TM_REG_LIN0_SCAN_ON 0x1640d0
3176 /* [RW 24] Linear0 array scan timeout. */
3177 #define TM_REG_LIN0_SCAN_TIME 0x16403c
3178 /* [RW 32] Linear1 logic address. */
3179 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
3180 /* [WB 64] Linear1 phy address. */
3181 #define TM_REG_LIN1_PHY_ADDR 0x164280
3182 /* [RW 1] Linear1 physical address valid. */
3183 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
3184 /* [RW 6] Linear timer set_clear fifo threshold. */
3185 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
3186 /* [RW 2] Load value for pci arbiter credit cnt. */
3187 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
3188 /* [RW 20] The amount of hardware cycles for each timer tick. */
3189 #define TM_REG_TIMER_TICK_SIZE 0x16401c
3190 /* [RW 8] Timers Context region. */
3191 #define TM_REG_TM_CONTEXT_REGION 0x164044
3192 /* [RW 1] Interrupt mask register #0 read/write */
3193 #define TM_REG_TM_INT_MASK 0x1640fc
3194 /* [R 1] Interrupt register #0 read */
3195 #define TM_REG_TM_INT_STS 0x1640f0
3196 /* [RW 8] The event id for aggregated interrupt 0 */
3197 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
3198 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
3199 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
3200 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
3201 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
3202 /* [RW 1] The T bit for aggregated interrupt 0 */
3203 #define TSDM_REG_AGG_INT_T_0 0x420b8
3204 #define TSDM_REG_AGG_INT_T_1 0x420bc
3205 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3206 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
3207 /* [RW 16] The maximum value of the competion counter #0 */
3208 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
3209 /* [RW 16] The maximum value of the competion counter #1 */
3210 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
3211 /* [RW 16] The maximum value of the competion counter #2 */
3212 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
3213 /* [RW 16] The maximum value of the competion counter #3 */
3214 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
3215 /* [RW 13] The start address in the internal RAM for the completion
3216 counters. */
3217 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
3218 #define TSDM_REG_ENABLE_IN1 0x42238
3219 #define TSDM_REG_ENABLE_IN2 0x4223c
3220 #define TSDM_REG_ENABLE_OUT1 0x42240
3221 #define TSDM_REG_ENABLE_OUT2 0x42244
3222 /* [RW 4] The initial number of messages that can be sent to the pxp control
3223 interface without receiving any ACK. */
3224 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
3225 /* [ST 32] The number of ACK after placement messages received */
3226 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
3227 /* [ST 32] The number of packet end messages received from the parser */
3228 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
3229 /* [ST 32] The number of requests received from the pxp async if */
3230 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
3231 /* [ST 32] The number of commands received in queue 0 */
3232 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
3233 /* [ST 32] The number of commands received in queue 10 */
3234 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
3235 /* [ST 32] The number of commands received in queue 11 */
3236 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
3237 /* [ST 32] The number of commands received in queue 1 */
3238 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
3239 /* [ST 32] The number of commands received in queue 3 */
3240 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
3241 /* [ST 32] The number of commands received in queue 4 */
3242 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
3243 /* [ST 32] The number of commands received in queue 5 */
3244 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
3245 /* [ST 32] The number of commands received in queue 6 */
3246 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
3247 /* [ST 32] The number of commands received in queue 7 */
3248 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
3249 /* [ST 32] The number of commands received in queue 8 */
3250 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
3251 /* [ST 32] The number of commands received in queue 9 */
3252 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
3253 /* [RW 13] The start address in the internal RAM for the packet end message */
3254 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
3255 /* [RW 13] The start address in the internal RAM for queue counters */
3256 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
3257 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3258 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
3259 /* [R 1] parser fifo empty in sdm_sync block */
3260 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
3261 /* [R 1] parser serial fifo empty in sdm_sync block */
3262 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
3263 /* [RW 32] Tick for timer counter. Applicable only when
3264 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3265 #define TSDM_REG_TIMER_TICK 0x42000
3266 /* [RW 32] Interrupt mask register #0 read/write */
3267 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
3268 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
3269 /* [R 32] Interrupt register #0 read */
3270 #define TSDM_REG_TSDM_INT_STS_0 0x42290
3271 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
3272 /* [RW 11] Parity mask register #0 read/write */
3273 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
3274 /* [R 11] Parity register #0 read */
3275 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
3276 /* [RW 5] The number of time_slots in the arbitration cycle */
3277 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
3278 /* [RW 3] The source that is associated with arbitration element 0. Source
3279 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3280 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3281 #define TSEM_REG_ARB_ELEMENT0 0x180020
3282 /* [RW 3] The source that is associated with arbitration element 1. Source
3283 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3284 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3285 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
3286 #define TSEM_REG_ARB_ELEMENT1 0x180024
3287 /* [RW 3] The source that is associated with arbitration element 2. Source
3288 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3289 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3290 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3291 and ~tsem_registers_arb_element1.arb_element1 */
3292 #define TSEM_REG_ARB_ELEMENT2 0x180028
3293 /* [RW 3] The source that is associated with arbitration element 3. Source
3294 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3295 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3296 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
3297 ~tsem_registers_arb_element1.arb_element1 and
3298 ~tsem_registers_arb_element2.arb_element2 */
3299 #define TSEM_REG_ARB_ELEMENT3 0x18002c
3300 /* [RW 3] The source that is associated with arbitration element 4. Source
3301 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3302 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3303 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3304 and ~tsem_registers_arb_element1.arb_element1 and
3305 ~tsem_registers_arb_element2.arb_element2 and
3306 ~tsem_registers_arb_element3.arb_element3 */
3307 #define TSEM_REG_ARB_ELEMENT4 0x180030
3308 #define TSEM_REG_ENABLE_IN 0x1800a4
3309 #define TSEM_REG_ENABLE_OUT 0x1800a8
3310 /* [RW 32] This address space contains all registers and memories that are
3311 placed in SEM_FAST block. The SEM_FAST registers are described in
3312 appendix B. In order to access the sem_fast registers the base address
3313 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
3314 #define TSEM_REG_FAST_MEMORY 0x1a0000
3315 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3316 by the microcode */
3317 #define TSEM_REG_FIC0_DISABLE 0x180224
3318 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3319 by the microcode */
3320 #define TSEM_REG_FIC1_DISABLE 0x180234
3321 /* [RW 15] Interrupt table Read and write access to it is not possible in
3322 the middle of the work */
3323 #define TSEM_REG_INT_TABLE 0x180400
3324 /* [ST 24] Statistics register. The number of messages that entered through
3325 FIC0 */
3326 #define TSEM_REG_MSG_NUM_FIC0 0x180000
3327 /* [ST 24] Statistics register. The number of messages that entered through
3328 FIC1 */
3329 #define TSEM_REG_MSG_NUM_FIC1 0x180004
3330 /* [ST 24] Statistics register. The number of messages that were sent to
3331 FOC0 */
3332 #define TSEM_REG_MSG_NUM_FOC0 0x180008
3333 /* [ST 24] Statistics register. The number of messages that were sent to
3334 FOC1 */
3335 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
3336 /* [ST 24] Statistics register. The number of messages that were sent to
3337 FOC2 */
3338 #define TSEM_REG_MSG_NUM_FOC2 0x180010
3339 /* [ST 24] Statistics register. The number of messages that were sent to
3340 FOC3 */
3341 #define TSEM_REG_MSG_NUM_FOC3 0x180014
3342 /* [RW 1] Disables input messages from the passive buffer May be updated
3343 during run_time by the microcode */
3344 #define TSEM_REG_PAS_DISABLE 0x18024c
3345 /* [WB 128] Debug only. Passive buffer memory */
3346 #define TSEM_REG_PASSIVE_BUFFER 0x181000
3347 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3348 #define TSEM_REG_PRAM 0x1c0000
3349 /* [R 8] Valid sleeping threads indication have bit per thread */
3350 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
3351 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3352 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
3353 /* [RW 8] List of free threads . There is a bit per thread. */
3354 #define TSEM_REG_THREADS_LIST 0x1802e4
3355 /* [RW 3] The arbitration scheme of time_slot 0 */
3356 #define TSEM_REG_TS_0_AS 0x180038
3357 /* [RW 3] The arbitration scheme of time_slot 10 */
3358 #define TSEM_REG_TS_10_AS 0x180060
3359 /* [RW 3] The arbitration scheme of time_slot 11 */
3360 #define TSEM_REG_TS_11_AS 0x180064
3361 /* [RW 3] The arbitration scheme of time_slot 12 */
3362 #define TSEM_REG_TS_12_AS 0x180068
3363 /* [RW 3] The arbitration scheme of time_slot 13 */
3364 #define TSEM_REG_TS_13_AS 0x18006c
3365 /* [RW 3] The arbitration scheme of time_slot 14 */
3366 #define TSEM_REG_TS_14_AS 0x180070
3367 /* [RW 3] The arbitration scheme of time_slot 15 */
3368 #define TSEM_REG_TS_15_AS 0x180074
3369 /* [RW 3] The arbitration scheme of time_slot 16 */
3370 #define TSEM_REG_TS_16_AS 0x180078
3371 /* [RW 3] The arbitration scheme of time_slot 17 */
3372 #define TSEM_REG_TS_17_AS 0x18007c
3373 /* [RW 3] The arbitration scheme of time_slot 18 */
3374 #define TSEM_REG_TS_18_AS 0x180080
3375 /* [RW 3] The arbitration scheme of time_slot 1 */
3376 #define TSEM_REG_TS_1_AS 0x18003c
3377 /* [RW 3] The arbitration scheme of time_slot 2 */
3378 #define TSEM_REG_TS_2_AS 0x180040
3379 /* [RW 3] The arbitration scheme of time_slot 3 */
3380 #define TSEM_REG_TS_3_AS 0x180044
3381 /* [RW 3] The arbitration scheme of time_slot 4 */
3382 #define TSEM_REG_TS_4_AS 0x180048
3383 /* [RW 3] The arbitration scheme of time_slot 5 */
3384 #define TSEM_REG_TS_5_AS 0x18004c
3385 /* [RW 3] The arbitration scheme of time_slot 6 */
3386 #define TSEM_REG_TS_6_AS 0x180050
3387 /* [RW 3] The arbitration scheme of time_slot 7 */
3388 #define TSEM_REG_TS_7_AS 0x180054
3389 /* [RW 3] The arbitration scheme of time_slot 8 */
3390 #define TSEM_REG_TS_8_AS 0x180058
3391 /* [RW 3] The arbitration scheme of time_slot 9 */
3392 #define TSEM_REG_TS_9_AS 0x18005c
3393 /* [RW 32] Interrupt mask register #0 read/write */
3394 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
3395 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
3396 /* [R 32] Interrupt register #0 read */
3397 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
3398 #define TSEM_REG_TSEM_INT_STS_1 0x180104
3399 /* [RW 32] Parity mask register #0 read/write */
3400 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
3401 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
3402 /* [R 32] Parity register #0 read */
3403 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
3404 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
3405 /* [R 5] Used to read the XX protection CAM occupancy counter. */
3406 #define UCM_REG_CAM_OCCUP 0xe0170
3407 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3408 disregarded; valid output is deasserted; all other signals are treated as
3409 usual; if 1 - normal activity. */
3410 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
3411 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3412 are disregarded; all other signals are treated as usual; if 1 - normal
3413 activity. */
3414 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
3415 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3416 disregarded; valid output is deasserted; all other signals are treated as
3417 usual; if 1 - normal activity. */
3418 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
3419 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3420 input is disregarded; all other signals are treated as usual; if 1 -
3421 normal activity. */
3422 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
3423 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3424 the initial credit value; read returns the current value of the credit
3425 counter. Must be initialized to 1 at start-up. */
3426 #define UCM_REG_CFC_INIT_CRD 0xe0204
3427 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3428 weight 8 (the most prioritised); 1 stands for weight 1(least
3429 prioritised); 2 stands for weight 2; tc. */
3430 #define UCM_REG_CP_WEIGHT 0xe00c4
3431 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3432 disregarded; acknowledge output is deasserted; all other signals are
3433 treated as usual; if 1 - normal activity. */
3434 #define UCM_REG_CSEM_IFEN 0xe0028
3435 /* [RC 1] Set when the message length mismatch (relative to last indication)
3436 at the csem interface is detected. */
3437 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
3438 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3439 weight 8 (the most prioritised); 1 stands for weight 1(least
3440 prioritised); 2 stands for weight 2; tc. */
3441 #define UCM_REG_CSEM_WEIGHT 0xe00b8
3442 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
3443 disregarded; acknowledge output is deasserted; all other signals are
3444 treated as usual; if 1 - normal activity. */
3445 #define UCM_REG_DORQ_IFEN 0xe0030
3446 /* [RC 1] Set when the message length mismatch (relative to last indication)
3447 at the dorq interface is detected. */
3448 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
3449 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
3450 weight 8 (the most prioritised); 1 stands for weight 1(least
3451 prioritised); 2 stands for weight 2; tc. */
3452 #define UCM_REG_DORQ_WEIGHT 0xe00c0
3453 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
3454 #define UCM_REG_ERR_EVNT_ID 0xe00a4
3455 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3456 #define UCM_REG_ERR_UCM_HDR 0xe00a0
3457 /* [RW 8] The Event ID for Timers expiration. */
3458 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
3459 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3460 writes the initial credit value; read returns the current value of the
3461 credit counter. Must be initialized to 64 at start-up. */
3462 #define UCM_REG_FIC0_INIT_CRD 0xe020c
3463 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3464 writes the initial credit value; read returns the current value of the
3465 credit counter. Must be initialized to 64 at start-up. */
3466 #define UCM_REG_FIC1_INIT_CRD 0xe0210
3467 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3468 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
3469 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
3470 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
3471 #define UCM_REG_GR_ARB_TYPE 0xe0144
3472 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3473 highest priority is 3. It is supposed that the Store channel group is
3474 compliment to the others. */
3475 #define UCM_REG_GR_LD0_PR 0xe014c
3476 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3477 highest priority is 3. It is supposed that the Store channel group is
3478 compliment to the others. */
3479 #define UCM_REG_GR_LD1_PR 0xe0150
3480 /* [RW 2] The queue index for invalidate counter flag decision. */
3481 #define UCM_REG_INV_CFLG_Q 0xe00e4
3482 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
3483 sent to STORM; for a specific connection type. the double REG-pairs are
3484 used in order to align to STORM context row size of 128 bits. The offset
3485 of these data in the STORM context is always 0. Index _i stands for the
3486 connection type (one of 16). */
3487 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
3488 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
3489 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
3490 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
3491 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
3492 #define UCM_REG_N_SM_CTX_LD_5 0xe0068
3493 #define UCM_REG_PHYS_QNUM0_0 0xe0110
3494 #define UCM_REG_PHYS_QNUM0_1 0xe0114
3495 #define UCM_REG_PHYS_QNUM1_0 0xe0118
3496 #define UCM_REG_PHYS_QNUM1_1 0xe011c
3497 #define UCM_REG_PHYS_QNUM2_0 0xe0120
3498 #define UCM_REG_PHYS_QNUM2_1 0xe0124
3499 #define UCM_REG_PHYS_QNUM3_0 0xe0128
3500 #define UCM_REG_PHYS_QNUM3_1 0xe012c
3501 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3502 #define UCM_REG_STOP_EVNT_ID 0xe00ac
3503 /* [RC 1] Set when the message length mismatch (relative to last indication)
3504 at the STORM interface is detected. */
3505 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
3506 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3507 disregarded; acknowledge output is deasserted; all other signals are
3508 treated as usual; if 1 - normal activity. */
3509 #define UCM_REG_STORM_UCM_IFEN 0xe0010
3510 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3511 weight 8 (the most prioritised); 1 stands for weight 1(least
3512 prioritised); 2 stands for weight 2; tc. */
3513 #define UCM_REG_STORM_WEIGHT 0xe00b0
3514 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
3515 writes the initial credit value; read returns the current value of the
3516 credit counter. Must be initialized to 4 at start-up. */
3517 #define UCM_REG_TM_INIT_CRD 0xe021c
3518 /* [RW 28] The CM header for Timers expiration command. */
3519 #define UCM_REG_TM_UCM_HDR 0xe009c
3520 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3521 disregarded; acknowledge output is deasserted; all other signals are
3522 treated as usual; if 1 - normal activity. */
3523 #define UCM_REG_TM_UCM_IFEN 0xe001c
3524 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
3525 weight 8 (the most prioritised); 1 stands for weight 1(least
3526 prioritised); 2 stands for weight 2; tc. */
3527 #define UCM_REG_TM_WEIGHT 0xe00d4
3528 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
3529 disregarded; acknowledge output is deasserted; all other signals are
3530 treated as usual; if 1 - normal activity. */
3531 #define UCM_REG_TSEM_IFEN 0xe0024
3532 /* [RC 1] Set when the message length mismatch (relative to last indication)
3533 at the tsem interface is detected. */
3534 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
3535 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
3536 weight 8 (the most prioritised); 1 stands for weight 1(least
3537 prioritised); 2 stands for weight 2; tc. */
3538 #define UCM_REG_TSEM_WEIGHT 0xe00b4
3539 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3540 acknowledge output is deasserted; all other signals are treated as usual;
3541 if 1 - normal activity. */
3542 #define UCM_REG_UCM_CFC_IFEN 0xe0044
3543 /* [RW 11] Interrupt mask register #0 read/write */
3544 #define UCM_REG_UCM_INT_MASK 0xe01d4
3545 /* [R 11] Interrupt register #0 read */
3546 #define UCM_REG_UCM_INT_STS 0xe01c8
3547 /* [R 27] Parity register #0 read */
3548 #define UCM_REG_UCM_PRTY_STS 0xe01d8
3549 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
3550 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3551 Is used to determine the number of the AG context REG-pairs written back;
3552 when the Reg1WbFlg isn't set. */
3553 #define UCM_REG_UCM_REG0_SZ 0xe00dc
3554 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3555 disregarded; valid is deasserted; all other signals are treated as usual;
3556 if 1 - normal activity. */
3557 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
3558 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3559 disregarded; valid is deasserted; all other signals are treated as usual;
3560 if 1 - normal activity. */
3561 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
3562 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
3563 disregarded; acknowledge output is deasserted; all other signals are
3564 treated as usual; if 1 - normal activity. */
3565 #define UCM_REG_UCM_TM_IFEN 0xe0020
3566 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3567 disregarded; valid is deasserted; all other signals are treated as usual;
3568 if 1 - normal activity. */
3569 #define UCM_REG_UCM_UQM_IFEN 0xe000c
3570 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3571 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
3572 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3573 the initial credit value; read returns the current value of the credit
3574 counter. Must be initialized to 32 at start-up. */
3575 #define UCM_REG_UQM_INIT_CRD 0xe0220
3576 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3577 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3578 prioritised); 2 stands for weight 2; tc. */
3579 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
3580 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
3581 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3582 prioritised); 2 stands for weight 2; tc. */
3583 #define UCM_REG_UQM_S_WEIGHT 0xe00d0
3584 /* [RW 28] The CM header value for QM request (primary). */
3585 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
3586 /* [RW 28] The CM header value for QM request (secondary). */
3587 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
3588 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3589 acknowledge output is deasserted; all other signals are treated as usual;
3590 if 1 - normal activity. */
3591 #define UCM_REG_UQM_UCM_IFEN 0xe0014
3592 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3593 acknowledge output is deasserted; all other signals are treated as usual;
3594 if 1 - normal activity. */
3595 #define UCM_REG_USDM_IFEN 0xe0018
3596 /* [RC 1] Set when the message length mismatch (relative to last indication)
3597 at the SDM interface is detected. */
3598 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
3599 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3600 weight 8 (the most prioritised); 1 stands for weight 1(least
3601 prioritised); 2 stands for weight 2; tc. */
3602 #define UCM_REG_USDM_WEIGHT 0xe00c8
3603 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
3604 disregarded; acknowledge output is deasserted; all other signals are
3605 treated as usual; if 1 - normal activity. */
3606 #define UCM_REG_XSEM_IFEN 0xe002c
3607 /* [RC 1] Set when the message length mismatch (relative to last indication)
3608 at the xsem interface isdetected. */
3609 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
3610 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
3611 weight 8 (the most prioritised); 1 stands for weight 1(least
3612 prioritised); 2 stands for weight 2; tc. */
3613 #define UCM_REG_XSEM_WEIGHT 0xe00bc
3614 /* [RW 20] Indirect access to the descriptor table of the XX protection
3615 mechanism. The fields are:[5:0] - message length; 14:6] - message
3616 pointer; 19:15] - next pointer. */
3617 #define UCM_REG_XX_DESCR_TABLE 0xe0280
3618 #define UCM_REG_XX_DESCR_TABLE_SIZE 32
3619 /* [R 6] Use to read the XX protection Free counter. */
3620 #define UCM_REG_XX_FREE 0xe016c
3621 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3622 of the Input Stage XX protection buffer by the XX protection pending
3623 messages. Write writes the initial credit value; read returns the current
3624 value of the credit counter. Must be initialized to 12 at start-up. */
3625 #define UCM_REG_XX_INIT_CRD 0xe0224
3626 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3627 protection. ~ucm_registers_xx_free.xx_free read on read. */
3628 #define UCM_REG_XX_MSG_NUM 0xe0228
3629 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3630 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
3631 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3632 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
3633 header pointer. */
3634 #define UCM_REG_XX_TABLE 0xe0300
3635 /* [RW 8] The event id for aggregated interrupt 0 */
3636 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
3637 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
3638 #define USDM_REG_AGG_INT_EVENT_2 0xc4040
3639 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
3640 #define USDM_REG_AGG_INT_EVENT_5 0xc404c
3641 #define USDM_REG_AGG_INT_EVENT_6 0xc4050
3642 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3643 or auto-mask-mode (1) */
3644 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
3645 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
3646 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
3647 #define USDM_REG_AGG_INT_MODE_5 0xc41cc
3648 #define USDM_REG_AGG_INT_MODE_6 0xc41d0
3649 /* [RW 1] The T bit for aggregated interrupt 5 */
3650 #define USDM_REG_AGG_INT_T_5 0xc40cc
3651 #define USDM_REG_AGG_INT_T_6 0xc40d0
3652 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3653 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
3654 /* [RW 16] The maximum value of the competion counter #0 */
3655 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
3656 /* [RW 16] The maximum value of the competion counter #1 */
3657 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
3658 /* [RW 16] The maximum value of the competion counter #2 */
3659 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
3660 /* [RW 16] The maximum value of the competion counter #3 */
3661 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
3662 /* [RW 13] The start address in the internal RAM for the completion
3663 counters. */
3664 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
3665 #define USDM_REG_ENABLE_IN1 0xc4238
3666 #define USDM_REG_ENABLE_IN2 0xc423c
3667 #define USDM_REG_ENABLE_OUT1 0xc4240
3668 #define USDM_REG_ENABLE_OUT2 0xc4244
3669 /* [RW 4] The initial number of messages that can be sent to the pxp control
3670 interface without receiving any ACK. */
3671 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
3672 /* [ST 32] The number of ACK after placement messages received */
3673 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
3674 /* [ST 32] The number of packet end messages received from the parser */
3675 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
3676 /* [ST 32] The number of requests received from the pxp async if */
3677 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
3678 /* [ST 32] The number of commands received in queue 0 */
3679 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
3680 /* [ST 32] The number of commands received in queue 10 */
3681 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
3682 /* [ST 32] The number of commands received in queue 11 */
3683 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
3684 /* [ST 32] The number of commands received in queue 1 */
3685 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
3686 /* [ST 32] The number of commands received in queue 2 */
3687 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
3688 /* [ST 32] The number of commands received in queue 3 */
3689 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
3690 /* [ST 32] The number of commands received in queue 4 */
3691 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
3692 /* [ST 32] The number of commands received in queue 5 */
3693 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
3694 /* [ST 32] The number of commands received in queue 6 */
3695 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
3696 /* [ST 32] The number of commands received in queue 7 */
3697 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
3698 /* [ST 32] The number of commands received in queue 8 */
3699 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
3700 /* [ST 32] The number of commands received in queue 9 */
3701 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
3702 /* [RW 13] The start address in the internal RAM for the packet end message */
3703 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
3704 /* [RW 13] The start address in the internal RAM for queue counters */
3705 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
3706 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3707 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
3708 /* [R 1] parser fifo empty in sdm_sync block */
3709 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
3710 /* [R 1] parser serial fifo empty in sdm_sync block */
3711 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
3712 /* [RW 32] Tick for timer counter. Applicable only when
3713 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
3714 #define USDM_REG_TIMER_TICK 0xc4000
3715 /* [RW 32] Interrupt mask register #0 read/write */
3716 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
3717 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
3718 /* [R 32] Interrupt register #0 read */
3719 #define USDM_REG_USDM_INT_STS_0 0xc4294
3720 #define USDM_REG_USDM_INT_STS_1 0xc42a4
3721 /* [RW 11] Parity mask register #0 read/write */
3722 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
3723 /* [R 11] Parity register #0 read */
3724 #define USDM_REG_USDM_PRTY_STS 0xc42b4
3725 /* [RW 5] The number of time_slots in the arbitration cycle */
3726 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
3727 /* [RW 3] The source that is associated with arbitration element 0. Source
3728 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3729 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3730 #define USEM_REG_ARB_ELEMENT0 0x300020
3731 /* [RW 3] The source that is associated with arbitration element 1. Source
3732 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3733 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3734 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
3735 #define USEM_REG_ARB_ELEMENT1 0x300024
3736 /* [RW 3] The source that is associated with arbitration element 2. Source
3737 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3738 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3739 Could not be equal to register ~usem_registers_arb_element0.arb_element0
3740 and ~usem_registers_arb_element1.arb_element1 */
3741 #define USEM_REG_ARB_ELEMENT2 0x300028
3742 /* [RW 3] The source that is associated with arbitration element 3. Source
3743 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3744 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3745 not be equal to register ~usem_registers_arb_element0.arb_element0 and
3746 ~usem_registers_arb_element1.arb_element1 and
3747 ~usem_registers_arb_element2.arb_element2 */
3748 #define USEM_REG_ARB_ELEMENT3 0x30002c
3749 /* [RW 3] The source that is associated with arbitration element 4. Source
3750 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3751 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3752 Could not be equal to register ~usem_registers_arb_element0.arb_element0
3753 and ~usem_registers_arb_element1.arb_element1 and
3754 ~usem_registers_arb_element2.arb_element2 and
3755 ~usem_registers_arb_element3.arb_element3 */
3756 #define USEM_REG_ARB_ELEMENT4 0x300030
3757 #define USEM_REG_ENABLE_IN 0x3000a4
3758 #define USEM_REG_ENABLE_OUT 0x3000a8
3759 /* [RW 32] This address space contains all registers and memories that are
3760 placed in SEM_FAST block. The SEM_FAST registers are described in
3761 appendix B. In order to access the sem_fast registers the base address
3762 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
3763 #define USEM_REG_FAST_MEMORY 0x320000
3764 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3765 by the microcode */
3766 #define USEM_REG_FIC0_DISABLE 0x300224
3767 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3768 by the microcode */
3769 #define USEM_REG_FIC1_DISABLE 0x300234
3770 /* [RW 15] Interrupt table Read and write access to it is not possible in
3771 the middle of the work */
3772 #define USEM_REG_INT_TABLE 0x300400
3773 /* [ST 24] Statistics register. The number of messages that entered through
3774 FIC0 */
3775 #define USEM_REG_MSG_NUM_FIC0 0x300000
3776 /* [ST 24] Statistics register. The number of messages that entered through
3777 FIC1 */
3778 #define USEM_REG_MSG_NUM_FIC1 0x300004
3779 /* [ST 24] Statistics register. The number of messages that were sent to
3780 FOC0 */
3781 #define USEM_REG_MSG_NUM_FOC0 0x300008
3782 /* [ST 24] Statistics register. The number of messages that were sent to
3783 FOC1 */
3784 #define USEM_REG_MSG_NUM_FOC1 0x30000c
3785 /* [ST 24] Statistics register. The number of messages that were sent to
3786 FOC2 */
3787 #define USEM_REG_MSG_NUM_FOC2 0x300010
3788 /* [ST 24] Statistics register. The number of messages that were sent to
3789 FOC3 */
3790 #define USEM_REG_MSG_NUM_FOC3 0x300014
3791 /* [RW 1] Disables input messages from the passive buffer May be updated
3792 during run_time by the microcode */
3793 #define USEM_REG_PAS_DISABLE 0x30024c
3794 /* [WB 128] Debug only. Passive buffer memory */
3795 #define USEM_REG_PASSIVE_BUFFER 0x302000
3796 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3797 #define USEM_REG_PRAM 0x340000
3798 /* [R 16] Valid sleeping threads indication have bit per thread */
3799 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
3800 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3801 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
3802 /* [RW 16] List of free threads . There is a bit per thread. */
3803 #define USEM_REG_THREADS_LIST 0x3002e4
3804 /* [RW 3] The arbitration scheme of time_slot 0 */
3805 #define USEM_REG_TS_0_AS 0x300038
3806 /* [RW 3] The arbitration scheme of time_slot 10 */
3807 #define USEM_REG_TS_10_AS 0x300060
3808 /* [RW 3] The arbitration scheme of time_slot 11 */
3809 #define USEM_REG_TS_11_AS 0x300064
3810 /* [RW 3] The arbitration scheme of time_slot 12 */
3811 #define USEM_REG_TS_12_AS 0x300068
3812 /* [RW 3] The arbitration scheme of time_slot 13 */
3813 #define USEM_REG_TS_13_AS 0x30006c
3814 /* [RW 3] The arbitration scheme of time_slot 14 */
3815 #define USEM_REG_TS_14_AS 0x300070
3816 /* [RW 3] The arbitration scheme of time_slot 15 */
3817 #define USEM_REG_TS_15_AS 0x300074
3818 /* [RW 3] The arbitration scheme of time_slot 16 */
3819 #define USEM_REG_TS_16_AS 0x300078
3820 /* [RW 3] The arbitration scheme of time_slot 17 */
3821 #define USEM_REG_TS_17_AS 0x30007c
3822 /* [RW 3] The arbitration scheme of time_slot 18 */
3823 #define USEM_REG_TS_18_AS 0x300080
3824 /* [RW 3] The arbitration scheme of time_slot 1 */
3825 #define USEM_REG_TS_1_AS 0x30003c
3826 /* [RW 3] The arbitration scheme of time_slot 2 */
3827 #define USEM_REG_TS_2_AS 0x300040
3828 /* [RW 3] The arbitration scheme of time_slot 3 */
3829 #define USEM_REG_TS_3_AS 0x300044
3830 /* [RW 3] The arbitration scheme of time_slot 4 */
3831 #define USEM_REG_TS_4_AS 0x300048
3832 /* [RW 3] The arbitration scheme of time_slot 5 */
3833 #define USEM_REG_TS_5_AS 0x30004c
3834 /* [RW 3] The arbitration scheme of time_slot 6 */
3835 #define USEM_REG_TS_6_AS 0x300050
3836 /* [RW 3] The arbitration scheme of time_slot 7 */
3837 #define USEM_REG_TS_7_AS 0x300054
3838 /* [RW 3] The arbitration scheme of time_slot 8 */
3839 #define USEM_REG_TS_8_AS 0x300058
3840 /* [RW 3] The arbitration scheme of time_slot 9 */
3841 #define USEM_REG_TS_9_AS 0x30005c
3842 /* [RW 32] Interrupt mask register #0 read/write */
3843 #define USEM_REG_USEM_INT_MASK_0 0x300110
3844 #define USEM_REG_USEM_INT_MASK_1 0x300120
3845 /* [R 32] Interrupt register #0 read */
3846 #define USEM_REG_USEM_INT_STS_0 0x300104
3847 #define USEM_REG_USEM_INT_STS_1 0x300114
3848 /* [RW 32] Parity mask register #0 read/write */
3849 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
3850 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
3851 /* [R 32] Parity register #0 read */
3852 #define USEM_REG_USEM_PRTY_STS_0 0x300124
3853 #define USEM_REG_USEM_PRTY_STS_1 0x300134
3854 /* [RW 2] The queue index for registration on Aux1 counter flag. */
3855 #define XCM_REG_AUX1_Q 0x20134
3856 /* [RW 2] Per each decision rule the queue index to register to. */
3857 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
3858 /* [R 5] Used to read the XX protection CAM occupancy counter. */
3859 #define XCM_REG_CAM_OCCUP 0x20244
3860 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3861 disregarded; valid output is deasserted; all other signals are treated as
3862 usual; if 1 - normal activity. */
3863 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
3864 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3865 are disregarded; all other signals are treated as usual; if 1 - normal
3866 activity. */
3867 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
3868 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3869 disregarded; valid output is deasserted; all other signals are treated as
3870 usual; if 1 - normal activity. */
3871 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
3872 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3873 input is disregarded; all other signals are treated as usual; if 1 -
3874 normal activity. */
3875 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
3876 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3877 the initial credit value; read returns the current value of the credit
3878 counter. Must be initialized to 1 at start-up. */
3879 #define XCM_REG_CFC_INIT_CRD 0x20404
3880 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3881 weight 8 (the most prioritised); 1 stands for weight 1(least
3882 prioritised); 2 stands for weight 2; tc. */
3883 #define XCM_REG_CP_WEIGHT 0x200dc
3884 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3885 disregarded; acknowledge output is deasserted; all other signals are
3886 treated as usual; if 1 - normal activity. */
3887 #define XCM_REG_CSEM_IFEN 0x20028
3888 /* [RC 1] Set at message length mismatch (relative to last indication) at
3889 the csem interface. */
3890 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
3891 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3892 weight 8 (the most prioritised); 1 stands for weight 1(least
3893 prioritised); 2 stands for weight 2; tc. */
3894 #define XCM_REG_CSEM_WEIGHT 0x200c4
3895 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
3896 disregarded; acknowledge output is deasserted; all other signals are
3897 treated as usual; if 1 - normal activity. */
3898 #define XCM_REG_DORQ_IFEN 0x20030
3899 /* [RC 1] Set at message length mismatch (relative to last indication) at
3900 the dorq interface. */
3901 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
3902 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
3903 weight 8 (the most prioritised); 1 stands for weight 1(least
3904 prioritised); 2 stands for weight 2; tc. */
3905 #define XCM_REG_DORQ_WEIGHT 0x200cc
3906 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
3907 #define XCM_REG_ERR_EVNT_ID 0x200b0
3908 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3909 #define XCM_REG_ERR_XCM_HDR 0x200ac
3910 /* [RW 8] The Event ID for Timers expiration. */
3911 #define XCM_REG_EXPR_EVNT_ID 0x200b4
3912 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3913 writes the initial credit value; read returns the current value of the
3914 credit counter. Must be initialized to 64 at start-up. */
3915 #define XCM_REG_FIC0_INIT_CRD 0x2040c
3916 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3917 writes the initial credit value; read returns the current value of the
3918 credit counter. Must be initialized to 64 at start-up. */
3919 #define XCM_REG_FIC1_INIT_CRD 0x20410
3920 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
3921 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
3922 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
3923 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
3924 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
3925 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
3926 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
3927 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
3928 #define XCM_REG_GR_ARB_TYPE 0x2020c
3929 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3930 highest priority is 3. It is supposed that the Channel group is the
3931 compliment of the other 3 groups. */
3932 #define XCM_REG_GR_LD0_PR 0x20214
3933 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3934 highest priority is 3. It is supposed that the Channel group is the
3935 compliment of the other 3 groups. */
3936 #define XCM_REG_GR_LD1_PR 0x20218
3937 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
3938 disregarded; acknowledge output is deasserted; all other signals are
3939 treated as usual; if 1 - normal activity. */
3940 #define XCM_REG_NIG0_IFEN 0x20038
3941 /* [RC 1] Set at message length mismatch (relative to last indication) at
3942 the nig0 interface. */
3943 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
3944 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
3945 weight 8 (the most prioritised); 1 stands for weight 1(least
3946 prioritised); 2 stands for weight 2; tc. */
3947 #define XCM_REG_NIG0_WEIGHT 0x200d4
3948 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
3949 disregarded; acknowledge output is deasserted; all other signals are
3950 treated as usual; if 1 - normal activity. */
3951 #define XCM_REG_NIG1_IFEN 0x2003c
3952 /* [RC 1] Set at message length mismatch (relative to last indication) at
3953 the nig1 interface. */
3954 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
3955 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
3956 sent to STORM; for a specific connection type. The double REG-pairs are
3957 used in order to align to STORM context row size of 128 bits. The offset
3958 of these data in the STORM context is always 0. Index _i stands for the
3959 connection type (one of 16). */
3960 #define XCM_REG_N_SM_CTX_LD_0 0x20060
3961 #define XCM_REG_N_SM_CTX_LD_1 0x20064
3962 #define XCM_REG_N_SM_CTX_LD_2 0x20068
3963 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
3964 #define XCM_REG_N_SM_CTX_LD_4 0x20070
3965 #define XCM_REG_N_SM_CTX_LD_5 0x20074
3966 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3967 acknowledge output is deasserted; all other signals are treated as usual;
3968 if 1 - normal activity. */
3969 #define XCM_REG_PBF_IFEN 0x20034
3970 /* [RC 1] Set at message length mismatch (relative to last indication) at
3971 the pbf interface. */
3972 #define XCM_REG_PBF_LENGTH_MIS 0x20234
3973 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3974 weight 8 (the most prioritised); 1 stands for weight 1(least
3975 prioritised); 2 stands for weight 2; tc. */
3976 #define XCM_REG_PBF_WEIGHT 0x200d0
3977 #define XCM_REG_PHYS_QNUM3_0 0x20100
3978 #define XCM_REG_PHYS_QNUM3_1 0x20104
3979 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3980 #define XCM_REG_STOP_EVNT_ID 0x200b8
3981 /* [RC 1] Set at message length mismatch (relative to last indication) at
3982 the STORM interface. */
3983 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
3984 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3985 weight 8 (the most prioritised); 1 stands for weight 1(least
3986 prioritised); 2 stands for weight 2; tc. */
3987 #define XCM_REG_STORM_WEIGHT 0x200bc
3988 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3989 disregarded; acknowledge output is deasserted; all other signals are
3990 treated as usual; if 1 - normal activity. */
3991 #define XCM_REG_STORM_XCM_IFEN 0x20010
3992 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
3993 writes the initial credit value; read returns the current value of the
3994 credit counter. Must be initialized to 4 at start-up. */
3995 #define XCM_REG_TM_INIT_CRD 0x2041c
3996 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
3997 weight 8 (the most prioritised); 1 stands for weight 1(least
3998 prioritised); 2 stands for weight 2; tc. */
3999 #define XCM_REG_TM_WEIGHT 0x200ec
4000 /* [RW 28] The CM header for Timers expiration command. */
4001 #define XCM_REG_TM_XCM_HDR 0x200a8
4002 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4003 disregarded; acknowledge output is deasserted; all other signals are
4004 treated as usual; if 1 - normal activity. */
4005 #define XCM_REG_TM_XCM_IFEN 0x2001c
4006 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4007 disregarded; acknowledge output is deasserted; all other signals are
4008 treated as usual; if 1 - normal activity. */
4009 #define XCM_REG_TSEM_IFEN 0x20024
4010 /* [RC 1] Set at message length mismatch (relative to last indication) at
4011 the tsem interface. */
4012 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
4013 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4014 weight 8 (the most prioritised); 1 stands for weight 1(least
4015 prioritised); 2 stands for weight 2; tc. */
4016 #define XCM_REG_TSEM_WEIGHT 0x200c0
4017 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
4018 #define XCM_REG_UNA_GT_NXT_Q 0x20120
4019 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4020 disregarded; acknowledge output is deasserted; all other signals are
4021 treated as usual; if 1 - normal activity. */
4022 #define XCM_REG_USEM_IFEN 0x2002c
4023 /* [RC 1] Message length mismatch (relative to last indication) at the usem
4024 interface. */
4025 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
4026 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4027 weight 8 (the most prioritised); 1 stands for weight 1(least
4028 prioritised); 2 stands for weight 2; tc. */
4029 #define XCM_REG_USEM_WEIGHT 0x200c8
4030 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
4031 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
4032 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
4033 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
4034 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
4035 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
4036 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
4037 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
4038 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
4039 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
4040 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
4041 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
4042 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4043 acknowledge output is deasserted; all other signals are treated as usual;
4044 if 1 - normal activity. */
4045 #define XCM_REG_XCM_CFC_IFEN 0x20050
4046 /* [RW 14] Interrupt mask register #0 read/write */
4047 #define XCM_REG_XCM_INT_MASK 0x202b4
4048 /* [R 14] Interrupt register #0 read */
4049 #define XCM_REG_XCM_INT_STS 0x202a8
4050 /* [R 30] Parity register #0 read */
4051 #define XCM_REG_XCM_PRTY_STS 0x202b8
4052 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
4053 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4054 Is used to determine the number of the AG context REG-pairs written back;
4055 when the Reg1WbFlg isn't set. */
4056 #define XCM_REG_XCM_REG0_SZ 0x200f4
4057 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4058 disregarded; valid is deasserted; all other signals are treated as usual;
4059 if 1 - normal activity. */
4060 #define XCM_REG_XCM_STORM0_IFEN 0x20004
4061 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4062 disregarded; valid is deasserted; all other signals are treated as usual;
4063 if 1 - normal activity. */
4064 #define XCM_REG_XCM_STORM1_IFEN 0x20008
4065 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4066 disregarded; acknowledge output is deasserted; all other signals are
4067 treated as usual; if 1 - normal activity. */
4068 #define XCM_REG_XCM_TM_IFEN 0x20020
4069 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4070 disregarded; valid is deasserted; all other signals are treated as usual;
4071 if 1 - normal activity. */
4072 #define XCM_REG_XCM_XQM_IFEN 0x2000c
4073 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4074 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
4075 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
4076 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
4077 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4078 the initial credit value; read returns the current value of the credit
4079 counter. Must be initialized to 32 at start-up. */
4080 #define XCM_REG_XQM_INIT_CRD 0x20420
4081 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4082 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4083 prioritised); 2 stands for weight 2; tc. */
4084 #define XCM_REG_XQM_P_WEIGHT 0x200e4
4085 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4086 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4087 prioritised); 2 stands for weight 2; tc. */
4088 #define XCM_REG_XQM_S_WEIGHT 0x200e8
4089 /* [RW 28] The CM header value for QM request (primary). */
4090 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
4091 /* [RW 28] The CM header value for QM request (secondary). */
4092 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
4093 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4094 acknowledge output is deasserted; all other signals are treated as usual;
4095 if 1 - normal activity. */
4096 #define XCM_REG_XQM_XCM_IFEN 0x20014
4097 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4098 acknowledge output is deasserted; all other signals are treated as usual;
4099 if 1 - normal activity. */
4100 #define XCM_REG_XSDM_IFEN 0x20018
4101 /* [RC 1] Set at message length mismatch (relative to last indication) at
4102 the SDM interface. */
4103 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
4104 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4105 weight 8 (the most prioritised); 1 stands for weight 1(least
4106 prioritised); 2 stands for weight 2; tc. */
4107 #define XCM_REG_XSDM_WEIGHT 0x200e0
4108 /* [RW 17] Indirect access to the descriptor table of the XX protection
4109 mechanism. The fields are: [5:0] - message length; 11:6] - message
4110 pointer; 16:12] - next pointer. */
4111 #define XCM_REG_XX_DESCR_TABLE 0x20480
4112 #define XCM_REG_XX_DESCR_TABLE_SIZE 32
4113 /* [R 6] Used to read the XX protection Free counter. */
4114 #define XCM_REG_XX_FREE 0x20240
4115 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4116 of the Input Stage XX protection buffer by the XX protection pending
4117 messages. Max credit available - 3.Write writes the initial credit value;
4118 read returns the current value of the credit counter. Must be initialized
4119 to 2 at start-up. */
4120 #define XCM_REG_XX_INIT_CRD 0x20424
4121 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4122 protection. ~xcm_registers_xx_free.xx_free read on read. */
4123 #define XCM_REG_XX_MSG_NUM 0x20428
4124 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4125 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
4126 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4127 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
4128 header pointer. */
4129 #define XCM_REG_XX_TABLE 0x20500
4130 /* [RW 8] The event id for aggregated interrupt 0 */
4131 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
4132 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
4133 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
4134 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
4135 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
4136 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4137 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
4138 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
4139 #define XSDM_REG_AGG_INT_EVENT_3 0x166044
4140 #define XSDM_REG_AGG_INT_EVENT_4 0x166048
4141 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4142 #define XSDM_REG_AGG_INT_EVENT_6 0x166050
4143 #define XSDM_REG_AGG_INT_EVENT_7 0x166054
4144 #define XSDM_REG_AGG_INT_EVENT_8 0x166058
4145 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c
4146 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4147 or auto-mask-mode (1) */
4148 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
4149 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
4150 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4151 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
4152 /* [RW 16] The maximum value of the competion counter #0 */
4153 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
4154 /* [RW 16] The maximum value of the competion counter #1 */
4155 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
4156 /* [RW 16] The maximum value of the competion counter #2 */
4157 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
4158 /* [RW 16] The maximum value of the competion counter #3 */
4159 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
4160 /* [RW 13] The start address in the internal RAM for the completion
4161 counters. */
4162 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
4163 #define XSDM_REG_ENABLE_IN1 0x166238
4164 #define XSDM_REG_ENABLE_IN2 0x16623c
4165 #define XSDM_REG_ENABLE_OUT1 0x166240
4166 #define XSDM_REG_ENABLE_OUT2 0x166244
4167 /* [RW 4] The initial number of messages that can be sent to the pxp control
4168 interface without receiving any ACK. */
4169 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
4170 /* [ST 32] The number of ACK after placement messages received */
4171 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
4172 /* [ST 32] The number of packet end messages received from the parser */
4173 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
4174 /* [ST 32] The number of requests received from the pxp async if */
4175 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
4176 /* [ST 32] The number of commands received in queue 0 */
4177 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
4178 /* [ST 32] The number of commands received in queue 10 */
4179 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
4180 /* [ST 32] The number of commands received in queue 11 */
4181 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
4182 /* [ST 32] The number of commands received in queue 1 */
4183 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
4184 /* [ST 32] The number of commands received in queue 3 */
4185 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
4186 /* [ST 32] The number of commands received in queue 4 */
4187 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
4188 /* [ST 32] The number of commands received in queue 5 */
4189 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
4190 /* [ST 32] The number of commands received in queue 6 */
4191 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
4192 /* [ST 32] The number of commands received in queue 7 */
4193 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
4194 /* [ST 32] The number of commands received in queue 8 */
4195 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
4196 /* [ST 32] The number of commands received in queue 9 */
4197 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
4198 /* [RW 13] The start address in the internal RAM for queue counters */
4199 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
4200 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4201 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
4202 /* [R 1] parser fifo empty in sdm_sync block */
4203 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
4204 /* [R 1] parser serial fifo empty in sdm_sync block */
4205 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
4206 /* [RW 32] Tick for timer counter. Applicable only when
4207 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4208 #define XSDM_REG_TIMER_TICK 0x166000
4209 /* [RW 32] Interrupt mask register #0 read/write */
4210 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
4211 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
4212 /* [R 32] Interrupt register #0 read */
4213 #define XSDM_REG_XSDM_INT_STS_0 0x166290
4214 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0
4215 /* [RW 11] Parity mask register #0 read/write */
4216 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
4217 /* [R 11] Parity register #0 read */
4218 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
4219 /* [RW 5] The number of time_slots in the arbitration cycle */
4220 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
4221 /* [RW 3] The source that is associated with arbitration element 0. Source
4222 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4223 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4224 #define XSEM_REG_ARB_ELEMENT0 0x280020
4225 /* [RW 3] The source that is associated with arbitration element 1. Source
4226 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4227 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4228 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
4229 #define XSEM_REG_ARB_ELEMENT1 0x280024
4230 /* [RW 3] The source that is associated with arbitration element 2. Source
4231 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4232 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4233 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4234 and ~xsem_registers_arb_element1.arb_element1 */
4235 #define XSEM_REG_ARB_ELEMENT2 0x280028
4236 /* [RW 3] The source that is associated with arbitration element 3. Source
4237 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4238 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4239 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
4240 ~xsem_registers_arb_element1.arb_element1 and
4241 ~xsem_registers_arb_element2.arb_element2 */
4242 #define XSEM_REG_ARB_ELEMENT3 0x28002c
4243 /* [RW 3] The source that is associated with arbitration element 4. Source
4244 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4245 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4246 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4247 and ~xsem_registers_arb_element1.arb_element1 and
4248 ~xsem_registers_arb_element2.arb_element2 and
4249 ~xsem_registers_arb_element3.arb_element3 */
4250 #define XSEM_REG_ARB_ELEMENT4 0x280030
4251 #define XSEM_REG_ENABLE_IN 0x2800a4
4252 #define XSEM_REG_ENABLE_OUT 0x2800a8
4253 /* [RW 32] This address space contains all registers and memories that are
4254 placed in SEM_FAST block. The SEM_FAST registers are described in
4255 appendix B. In order to access the sem_fast registers the base address
4256 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4257 #define XSEM_REG_FAST_MEMORY 0x2a0000
4258 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4259 by the microcode */
4260 #define XSEM_REG_FIC0_DISABLE 0x280224
4261 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4262 by the microcode */
4263 #define XSEM_REG_FIC1_DISABLE 0x280234
4264 /* [RW 15] Interrupt table Read and write access to it is not possible in
4265 the middle of the work */
4266 #define XSEM_REG_INT_TABLE 0x280400
4267 /* [ST 24] Statistics register. The number of messages that entered through
4268 FIC0 */
4269 #define XSEM_REG_MSG_NUM_FIC0 0x280000
4270 /* [ST 24] Statistics register. The number of messages that entered through
4271 FIC1 */
4272 #define XSEM_REG_MSG_NUM_FIC1 0x280004
4273 /* [ST 24] Statistics register. The number of messages that were sent to
4274 FOC0 */
4275 #define XSEM_REG_MSG_NUM_FOC0 0x280008
4276 /* [ST 24] Statistics register. The number of messages that were sent to
4277 FOC1 */
4278 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
4279 /* [ST 24] Statistics register. The number of messages that were sent to
4280 FOC2 */
4281 #define XSEM_REG_MSG_NUM_FOC2 0x280010
4282 /* [ST 24] Statistics register. The number of messages that were sent to
4283 FOC3 */
4284 #define XSEM_REG_MSG_NUM_FOC3 0x280014
4285 /* [RW 1] Disables input messages from the passive buffer May be updated
4286 during run_time by the microcode */
4287 #define XSEM_REG_PAS_DISABLE 0x28024c
4288 /* [WB 128] Debug only. Passive buffer memory */
4289 #define XSEM_REG_PASSIVE_BUFFER 0x282000
4290 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4291 #define XSEM_REG_PRAM 0x2c0000
4292 /* [R 16] Valid sleeping threads indication have bit per thread */
4293 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
4294 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4295 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
4296 /* [RW 16] List of free threads . There is a bit per thread. */
4297 #define XSEM_REG_THREADS_LIST 0x2802e4
4298 /* [RW 3] The arbitration scheme of time_slot 0 */
4299 #define XSEM_REG_TS_0_AS 0x280038
4300 /* [RW 3] The arbitration scheme of time_slot 10 */
4301 #define XSEM_REG_TS_10_AS 0x280060
4302 /* [RW 3] The arbitration scheme of time_slot 11 */
4303 #define XSEM_REG_TS_11_AS 0x280064
4304 /* [RW 3] The arbitration scheme of time_slot 12 */
4305 #define XSEM_REG_TS_12_AS 0x280068
4306 /* [RW 3] The arbitration scheme of time_slot 13 */
4307 #define XSEM_REG_TS_13_AS 0x28006c
4308 /* [RW 3] The arbitration scheme of time_slot 14 */
4309 #define XSEM_REG_TS_14_AS 0x280070
4310 /* [RW 3] The arbitration scheme of time_slot 15 */
4311 #define XSEM_REG_TS_15_AS 0x280074
4312 /* [RW 3] The arbitration scheme of time_slot 16 */
4313 #define XSEM_REG_TS_16_AS 0x280078
4314 /* [RW 3] The arbitration scheme of time_slot 17 */
4315 #define XSEM_REG_TS_17_AS 0x28007c
4316 /* [RW 3] The arbitration scheme of time_slot 18 */
4317 #define XSEM_REG_TS_18_AS 0x280080
4318 /* [RW 3] The arbitration scheme of time_slot 1 */
4319 #define XSEM_REG_TS_1_AS 0x28003c
4320 /* [RW 3] The arbitration scheme of time_slot 2 */
4321 #define XSEM_REG_TS_2_AS 0x280040
4322 /* [RW 3] The arbitration scheme of time_slot 3 */
4323 #define XSEM_REG_TS_3_AS 0x280044
4324 /* [RW 3] The arbitration scheme of time_slot 4 */
4325 #define XSEM_REG_TS_4_AS 0x280048
4326 /* [RW 3] The arbitration scheme of time_slot 5 */
4327 #define XSEM_REG_TS_5_AS 0x28004c
4328 /* [RW 3] The arbitration scheme of time_slot 6 */
4329 #define XSEM_REG_TS_6_AS 0x280050
4330 /* [RW 3] The arbitration scheme of time_slot 7 */
4331 #define XSEM_REG_TS_7_AS 0x280054
4332 /* [RW 3] The arbitration scheme of time_slot 8 */
4333 #define XSEM_REG_TS_8_AS 0x280058
4334 /* [RW 3] The arbitration scheme of time_slot 9 */
4335 #define XSEM_REG_TS_9_AS 0x28005c
4336 /* [RW 32] Interrupt mask register #0 read/write */
4337 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
4338 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
4339 /* [R 32] Interrupt register #0 read */
4340 #define XSEM_REG_XSEM_INT_STS_0 0x280104
4341 #define XSEM_REG_XSEM_INT_STS_1 0x280114
4342 /* [RW 32] Parity mask register #0 read/write */
4343 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
4344 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
4345 /* [R 32] Parity register #0 read */
4346 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
4347 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
4348 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
4349 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
4350 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
4351 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
4352 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
4353 #define MCPR_NVM_COMMAND_DONE (1L<<3)
4354 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
4355 #define MCPR_NVM_COMMAND_LAST (1L<<8)
4356 #define MCPR_NVM_COMMAND_WR (1L<<5)
4357 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
4358 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
4359 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
4360 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
4361 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
4362 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
4363 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
4364 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
4365 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
4366 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
4367 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
4368 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
4369 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
4370 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
4371 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
4372 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
4373 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
4374 #define EMAC_LED_1000MB_OVERRIDE (1L<<1)
4375 #define EMAC_LED_100MB_OVERRIDE (1L<<2)
4376 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
4377 #define EMAC_LED_2500MB_OVERRIDE (1L<<12)
4378 #define EMAC_LED_OVERRIDE (1L<<0)
4379 #define EMAC_LED_TRAFFIC (1L<<6)
4380 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
4381 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
4382 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
4383 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
4384 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
4385 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
4386 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
4387 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
4388 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
4389 #define EMAC_MODE_25G_MODE (1L<<5)
4390 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
4391 #define EMAC_MODE_PORT_GMII (2L<<2)
4392 #define EMAC_MODE_PORT_MII (1L<<2)
4393 #define EMAC_MODE_PORT_MII_10M (3L<<2)
4394 #define EMAC_MODE_RESET (1L<<0)
4395 #define EMAC_REG_EMAC_LED 0xc
4396 #define EMAC_REG_EMAC_MAC_MATCH 0x10
4397 #define EMAC_REG_EMAC_MDIO_COMM 0xac
4398 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
4399 #define EMAC_REG_EMAC_MODE 0x0
4400 #define EMAC_REG_EMAC_RX_MODE 0xc8
4401 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
4402 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
4403 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
4404 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
4405 #define EMAC_REG_EMAC_TX_MODE 0xbc
4406 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
4407 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
4408 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
4409 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
4410 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
4411 #define EMAC_RX_MODE_RESET (1L<<0)
4412 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
4413 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
4414 #define EMAC_TX_MODE_FLOW_EN (1L<<4)
4415 #define EMAC_TX_MODE_RESET (1L<<0)
4416 #define MISC_REGISTERS_GPIO_0 0
4417 #define MISC_REGISTERS_GPIO_1 1
4418 #define MISC_REGISTERS_GPIO_2 2
4419 #define MISC_REGISTERS_GPIO_3 3
4420 #define MISC_REGISTERS_GPIO_CLR_POS 16
4421 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
4422 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
4423 #define MISC_REGISTERS_GPIO_HIGH 1
4424 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
4425 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24
4426 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
4427 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
4428 #define MISC_REGISTERS_GPIO_INT_SET_POS 16
4429 #define MISC_REGISTERS_GPIO_LOW 0
4430 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
4431 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
4432 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
4433 #define MISC_REGISTERS_GPIO_SET_POS 8
4434 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
4435 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
4436 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
4437 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
4438 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
4439 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
4440 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
4441 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
4442 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
4443 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
4444 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
4445 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
4446 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
4447 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
4448 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
4449 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
4450 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
4451 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
4452 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
4453 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
4454 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
4455 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
4456 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
4457 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
4458 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
4459 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
4460 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
4461 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
4462 #define MISC_REGISTERS_SPIO_4 4
4463 #define MISC_REGISTERS_SPIO_5 5
4464 #define MISC_REGISTERS_SPIO_7 7
4465 #define MISC_REGISTERS_SPIO_CLR_POS 16
4466 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
4467 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
4468 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
4469 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
4470 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
4471 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
4472 #define MISC_REGISTERS_SPIO_SET_POS 8
4473 #define HW_LOCK_MAX_RESOURCE_VALUE 31
4474 #define HW_LOCK_RESOURCE_GPIO 1
4475 #define HW_LOCK_RESOURCE_MDIO 0
4476 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
4477 #define HW_LOCK_RESOURCE_RESERVED_08 8
4478 #define HW_LOCK_RESOURCE_SPIO 2
4479 #define HW_LOCK_RESOURCE_UNDI 5
4480 #define PRS_FLAG_OVERETH_IPV4 1
4481 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
4482 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
4483 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
4484 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
4485 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
4486 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
4487 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
4488 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
4489 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
4490 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
4491 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
4492 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
4493 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
4494 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
4495 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5)
4496 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9)
4497 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
4498 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (1<<28)
4499 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (1<<31)
4500 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (1<<29)
4501 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (1<<30)
4502 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
4503 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
4504 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
4505 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
4506 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
4507 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
4508 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
4509 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
4510 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
4511 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
4512 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
4513 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
4514 #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
4515 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
4516 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
4517 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
4518 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
4519 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
4520 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
4521 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
4522 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
4523 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
4524 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
4525 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
4526 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
4527 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
4528 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
4529 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
4530 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
4531 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
4532 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
4533 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
4534 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
4536 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
4537 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
4539 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
4540 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
4541 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
4542 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
4543 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
4544 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
4545 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
4546 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
4547 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
4548 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
4549 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
4550 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
4551 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
4552 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
4553 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
4554 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
4556 /* storm asserts attention bits */
4557 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
4558 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
4559 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
4560 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
4562 /* mcp error attention bit */
4563 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
4565 /*E1H NIG status sync attention mapped to group 4-7*/
4566 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
4567 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
4568 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
4569 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
4570 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
4571 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
4572 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
4573 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
4576 #define LATCHED_ATTN_RBCR 23
4577 #define LATCHED_ATTN_RBCT 24
4578 #define LATCHED_ATTN_RBCN 25
4579 #define LATCHED_ATTN_RBCU 26
4580 #define LATCHED_ATTN_RBCP 27
4581 #define LATCHED_ATTN_TIMEOUT_GRC 28
4582 #define LATCHED_ATTN_RSVD_GRC 29
4583 #define LATCHED_ATTN_ROM_PARITY_MCP 30
4584 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
4585 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
4586 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
4588 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
4589 #define GENERAL_ATTEN_OFFSET(atten_name)\
4590 (1UL << ((94 + atten_name) % 32))
4591 /*
4592 * This file defines GRC base address for every block.
4593 * This file is included by chipsim, asm microcode and cpp microcode.
4594 * These values are used in Design.xml on regBase attribute
4595 * Use the base with the generated offsets of specific registers.
4596 */
4598 #define GRCBASE_PXPCS 0x000000
4599 #define GRCBASE_PCICONFIG 0x002000
4600 #define GRCBASE_PCIREG 0x002400
4601 #define GRCBASE_EMAC0 0x008000
4602 #define GRCBASE_EMAC1 0x008400
4603 #define GRCBASE_DBU 0x008800
4604 #define GRCBASE_MISC 0x00A000
4605 #define GRCBASE_DBG 0x00C000
4606 #define GRCBASE_NIG 0x010000
4607 #define GRCBASE_XCM 0x020000
4608 #define GRCBASE_PRS 0x040000
4609 #define GRCBASE_SRCH 0x040400
4610 #define GRCBASE_TSDM 0x042000
4611 #define GRCBASE_TCM 0x050000
4612 #define GRCBASE_BRB1 0x060000
4613 #define GRCBASE_MCP 0x080000
4614 #define GRCBASE_UPB 0x0C1000
4615 #define GRCBASE_CSDM 0x0C2000
4616 #define GRCBASE_USDM 0x0C4000
4617 #define GRCBASE_CCM 0x0D0000
4618 #define GRCBASE_UCM 0x0E0000
4619 #define GRCBASE_CDU 0x101000
4620 #define GRCBASE_DMAE 0x102000
4621 #define GRCBASE_PXP 0x103000
4622 #define GRCBASE_CFC 0x104000
4623 #define GRCBASE_HC 0x108000
4624 #define GRCBASE_PXP2 0x120000
4625 #define GRCBASE_PBF 0x140000
4626 #define GRCBASE_XPB 0x161000
4627 #define GRCBASE_TIMERS 0x164000
4628 #define GRCBASE_XSDM 0x166000
4629 #define GRCBASE_QM 0x168000
4630 #define GRCBASE_DQ 0x170000
4631 #define GRCBASE_TSEM 0x180000
4632 #define GRCBASE_CSEM 0x200000
4633 #define GRCBASE_XSEM 0x280000
4634 #define GRCBASE_USEM 0x300000
4635 #define GRCBASE_MISC_AEU GRCBASE_MISC
4638 /* offset of configuration space in the pci core register */
4639 #define PCICFG_OFFSET 0x2000
4640 #define PCICFG_VENDOR_ID_OFFSET 0x00
4641 #define PCICFG_DEVICE_ID_OFFSET 0x02
4642 #define PCICFG_COMMAND_OFFSET 0x04
4643 #define PCICFG_COMMAND_IO_SPACE (1<<0)
4644 #define PCICFG_COMMAND_MEM_SPACE (1<<1)
4645 #define PCICFG_COMMAND_BUS_MASTER (1<<2)
4646 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
4647 #define PCICFG_COMMAND_MWI_CYCLES (1<<4)
4648 #define PCICFG_COMMAND_VGA_SNOOP (1<<5)
4649 #define PCICFG_COMMAND_PERR_ENA (1<<6)
4650 #define PCICFG_COMMAND_STEPPING (1<<7)
4651 #define PCICFG_COMMAND_SERR_ENA (1<<8)
4652 #define PCICFG_COMMAND_FAST_B2B (1<<9)
4653 #define PCICFG_COMMAND_INT_DISABLE (1<<10)
4654 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
4655 #define PCICFG_STATUS_OFFSET 0x06
4656 #define PCICFG_REVESION_ID_OFFSET 0x08
4657 #define PCICFG_CACHE_LINE_SIZE 0x0c
4658 #define PCICFG_LATENCY_TIMER 0x0d
4659 #define PCICFG_BAR_1_LOW 0x10
4660 #define PCICFG_BAR_1_HIGH 0x14
4661 #define PCICFG_BAR_2_LOW 0x18
4662 #define PCICFG_BAR_2_HIGH 0x1c
4663 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
4664 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
4665 #define PCICFG_INT_LINE 0x3c
4666 #define PCICFG_INT_PIN 0x3d
4667 #define PCICFG_PM_CAPABILITY 0x48
4668 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
4669 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
4670 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
4671 #define PCICFG_PM_CAPABILITY_DSI (1<<21)
4672 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
4673 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
4674 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
4675 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
4676 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
4677 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
4678 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
4679 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
4680 #define PCICFG_PM_CSR_OFFSET 0x4c
4681 #define PCICFG_PM_CSR_STATE (0x3<<0)
4682 #define PCICFG_PM_CSR_PME_ENABLE (1<<8)
4683 #define PCICFG_PM_CSR_PME_STATUS (1<<15)
4684 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
4685 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
4686 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
4687 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
4688 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
4689 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
4690 #define PCICFG_GRC_ADDRESS 0x78
4691 #define PCICFG_GRC_DATA 0x80
4692 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
4693 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
4694 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
4695 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
4696 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
4698 #define PCICFG_DEVICE_CONTROL 0xb4
4699 #define PCICFG_DEVICE_STATUS 0xb6
4700 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
4701 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
4702 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
4703 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
4704 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
4705 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
4706 #define PCICFG_LINK_CONTROL 0xbc
4709 #define BAR_USTRORM_INTMEM 0x400000
4710 #define BAR_CSTRORM_INTMEM 0x410000
4711 #define BAR_XSTRORM_INTMEM 0x420000
4712 #define BAR_TSTRORM_INTMEM 0x430000
4714 /* for accessing the IGU in case of status block ACK */
4715 #define BAR_IGU_INTMEM 0x440000
4717 #define BAR_DOORBELL_OFFSET 0x800000
4719 #define BAR_ME_REGISTER 0x450000
4721 /* config_2 offset */
4722 #define GRC_CONFIG_2_SIZE_REG 0x408
4723 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
4724 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
4725 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
4726 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
4727 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
4728 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
4729 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
4730 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
4731 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
4732 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
4733 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
4734 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
4735 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
4736 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
4737 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
4738 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
4739 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
4740 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
4741 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
4742 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
4743 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
4744 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
4745 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
4746 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
4747 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
4748 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
4749 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
4750 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
4751 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
4752 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
4753 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
4754 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
4755 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
4756 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
4757 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
4758 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
4759 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
4760 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
4761 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
4762 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
4764 /* config_3 offset */
4765 #define GRC_CONFIG_3_SIZE_REG 0x40c
4766 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
4767 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
4768 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
4769 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
4770 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
4771 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
4772 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
4774 #define GRC_BAR2_CONFIG 0x4e0
4775 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
4776 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
4777 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
4778 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
4779 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
4780 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
4781 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
4782 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
4783 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
4784 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
4785 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
4786 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
4787 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
4788 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
4789 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
4790 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
4791 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
4792 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
4794 #define PCI_PM_DATA_A 0x410
4795 #define PCI_PM_DATA_B 0x414
4796 #define PCI_ID_VAL1 0x434
4797 #define PCI_ID_VAL2 0x438
4800 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
4801 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
4802 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
4803 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
4804 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
4806 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
4807 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
4808 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
4809 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
4810 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
4811 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
4812 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
4813 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
4814 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
4815 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
4816 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
4817 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
4818 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
4819 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
4820 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
4821 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
4823 #define MDIO_REG_BANK_RX0 0x80b0
4824 #define MDIO_RX0_RX_STATUS 0x10
4825 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
4826 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
4827 #define MDIO_RX0_RX_EQ_BOOST 0x1c
4828 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4829 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
4831 #define MDIO_REG_BANK_RX1 0x80c0
4832 #define MDIO_RX1_RX_EQ_BOOST 0x1c
4833 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4834 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
4836 #define MDIO_REG_BANK_RX2 0x80d0
4837 #define MDIO_RX2_RX_EQ_BOOST 0x1c
4838 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4839 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
4841 #define MDIO_REG_BANK_RX3 0x80e0
4842 #define MDIO_RX3_RX_EQ_BOOST 0x1c
4843 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4844 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
4846 #define MDIO_REG_BANK_RX_ALL 0x80f0
4847 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
4848 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4849 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
4851 #define MDIO_REG_BANK_TX0 0x8060
4852 #define MDIO_TX0_TX_DRIVER 0x17
4853 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
4854 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
4855 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
4856 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
4857 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
4858 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
4859 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
4860 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
4861 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
4863 #define MDIO_REG_BANK_TX1 0x8070
4864 #define MDIO_TX1_TX_DRIVER 0x17
4865 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
4866 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
4867 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
4868 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
4869 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
4870 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
4871 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
4872 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
4873 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
4875 #define MDIO_REG_BANK_TX2 0x8080
4876 #define MDIO_TX2_TX_DRIVER 0x17
4877 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
4878 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
4879 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
4880 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
4881 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
4882 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
4883 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
4884 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
4885 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
4887 #define MDIO_REG_BANK_TX3 0x8090
4888 #define MDIO_TX3_TX_DRIVER 0x17
4889 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
4890 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
4891 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
4892 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
4893 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
4894 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
4895 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
4896 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
4897 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
4899 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
4900 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
4902 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
4903 #define MDIO_BLOCK1_LANE_CTRL0 0x15
4904 #define MDIO_BLOCK1_LANE_CTRL1 0x16
4905 #define MDIO_BLOCK1_LANE_CTRL2 0x17
4906 #define MDIO_BLOCK1_LANE_PRBS 0x19
4908 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
4909 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
4910 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
4911 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
4912 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
4913 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
4914 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
4915 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
4916 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
4917 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
4919 #define MDIO_REG_BANK_GP_STATUS 0x8120
4920 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
4921 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
4922 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
4923 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
4924 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
4925 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
4926 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
4927 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
4928 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
4929 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
4930 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
4931 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
4932 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
4933 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
4934 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
4935 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
4936 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
4937 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
4938 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
4939 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
4940 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
4941 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
4942 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
4943 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
4944 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
4947 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
4948 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
4949 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
4950 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
4951 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
4952 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
4953 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
4955 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
4956 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
4957 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
4958 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
4959 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
4960 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
4961 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
4962 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
4963 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
4964 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
4965 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
4966 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
4967 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
4968 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
4969 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
4970 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
4971 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
4972 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
4973 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
4974 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
4975 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
4976 #define MDIO_SERDES_DIGITAL_MISC1 0x18
4977 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
4978 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
4979 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
4980 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
4981 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
4982 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
4983 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
4984 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
4985 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
4986 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
4987 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
4988 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
4989 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
4990 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
4991 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
4992 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
4993 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
4994 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
4996 #define MDIO_REG_BANK_OVER_1G 0x8320
4997 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
4998 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
4999 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
5000 #define MDIO_OVER_1G_UP1 0x19
5001 #define MDIO_OVER_1G_UP1_2_5G 0x0001
5002 #define MDIO_OVER_1G_UP1_5G 0x0002
5003 #define MDIO_OVER_1G_UP1_6G 0x0004
5004 #define MDIO_OVER_1G_UP1_10G 0x0010
5005 #define MDIO_OVER_1G_UP1_10GH 0x0008
5006 #define MDIO_OVER_1G_UP1_12G 0x0020
5007 #define MDIO_OVER_1G_UP1_12_5G 0x0040
5008 #define MDIO_OVER_1G_UP1_13G 0x0080
5009 #define MDIO_OVER_1G_UP1_15G 0x0100
5010 #define MDIO_OVER_1G_UP1_16G 0x0200
5011 #define MDIO_OVER_1G_UP2 0x1A
5012 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
5013 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
5014 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
5015 #define MDIO_OVER_1G_UP3 0x1B
5016 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
5017 #define MDIO_OVER_1G_LP_UP1 0x1C
5018 #define MDIO_OVER_1G_LP_UP2 0x1D
5019 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
5020 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
5021 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
5022 #define MDIO_OVER_1G_LP_UP3 0x1E
5024 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
5025 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
5026 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
5027 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
5029 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
5030 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
5031 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
5032 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
5034 #define MDIO_REG_BANK_CL73_USERB0 0x8370
5035 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
5036 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
5037 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
5038 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
5039 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
5040 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
5041 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
5042 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
5043 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
5044 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
5045 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
5047 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
5048 #define MDIO_AER_BLOCK_AER_REG 0x1E
5050 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
5051 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
5052 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
5053 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
5054 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
5055 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
5056 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
5057 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
5058 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
5059 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
5060 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
5061 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
5062 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
5063 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
5064 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
5065 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
5066 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
5067 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
5068 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
5069 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
5070 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
5071 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
5072 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
5073 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
5074 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
5075 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
5076 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
5077 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
5078 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
5079 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
5080 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
5081 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
5082 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
5083 Theotherbitsarereservedandshouldbezero*/
5084 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
5087 #define MDIO_PMA_DEVAD 0x1
5088 /*ieee*/
5089 #define MDIO_PMA_REG_CTRL 0x0
5090 #define MDIO_PMA_REG_STATUS 0x1
5091 #define MDIO_PMA_REG_10G_CTRL2 0x7
5092 #define MDIO_PMA_REG_RX_SD 0xa
5093 /*bcm*/
5094 #define MDIO_PMA_REG_BCM_CTRL 0x0096
5095 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
5096 #define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
5097 #define MDIO_PMA_REG_LASI_CTRL 0x9002
5098 #define MDIO_PMA_REG_RX_ALARM 0x9003
5099 #define MDIO_PMA_REG_TX_ALARM 0x9004
5100 #define MDIO_PMA_REG_LASI_STATUS 0x9005
5101 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
5102 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
5103 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
5104 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
5105 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
5106 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
5107 #define MDIO_PMA_REG_GEN_CTRL 0xca10
5108 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
5109 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
5110 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
5111 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
5112 #define MDIO_PMA_REG_ROM_VER1 0xca19
5113 #define MDIO_PMA_REG_ROM_VER2 0xca1a
5114 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
5115 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
5116 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
5117 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
5118 #define MDIO_PMA_REG_LRM_MODE 0xca3f
5119 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
5120 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
5122 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
5123 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
5124 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
5125 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
5126 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
5127 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
5128 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
5129 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
5130 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
5131 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
5132 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
5133 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
5135 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
5136 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
5137 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
5138 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
5139 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
5140 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
5141 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
5142 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
5144 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
5145 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
5146 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
5148 #define MDIO_PMA_REG_7101_RESET 0xc000
5149 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
5150 #define MDIO_PMA_REG_7101_VER1 0xc026
5151 #define MDIO_PMA_REG_7101_VER2 0xc027
5153 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
5154 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
5155 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
5156 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
5157 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
5158 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
5159 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
5162 #define MDIO_WIS_DEVAD 0x2
5163 /*bcm*/
5164 #define MDIO_WIS_REG_LASI_CNTL 0x9002
5165 #define MDIO_WIS_REG_LASI_STATUS 0x9005
5167 #define MDIO_PCS_DEVAD 0x3
5168 #define MDIO_PCS_REG_STATUS 0x0020
5169 #define MDIO_PCS_REG_LASI_STATUS 0x9005
5170 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
5171 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
5172 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
5173 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
5174 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
5175 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
5176 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
5177 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
5178 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
5181 #define MDIO_XS_DEVAD 0x4
5182 #define MDIO_XS_PLL_SEQUENCER 0x8000
5183 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
5185 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
5186 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
5187 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
5188 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
5189 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
5191 #define MDIO_AN_DEVAD 0x7
5192 /*ieee*/
5193 #define MDIO_AN_REG_CTRL 0x0000
5194 #define MDIO_AN_REG_STATUS 0x0001
5195 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
5196 #define MDIO_AN_REG_ADV_PAUSE 0x0010
5197 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
5198 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
5199 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
5200 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
5201 #define MDIO_AN_REG_ADV 0x0011
5202 #define MDIO_AN_REG_ADV2 0x0012
5203 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
5204 #define MDIO_AN_REG_MASTER_STATUS 0x0021
5205 /*bcm*/
5206 #define MDIO_AN_REG_LINK_STATUS 0x8304
5207 #define MDIO_AN_REG_CL37_CL73 0x8370
5208 #define MDIO_AN_REG_CL37_AN 0xffe0
5209 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
5210 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
5212 #define MDIO_AN_REG_8073_2_5G 0x8329
5214 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
5215 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
5216 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
5217 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
5218 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
5219 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
5221 #define IGU_FUNC_BASE 0x0400
5223 #define IGU_ADDR_MSIX 0x0000
5224 #define IGU_ADDR_INT_ACK 0x0200
5225 #define IGU_ADDR_PROD_UPD 0x0201
5226 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
5227 #define IGU_ADDR_ATTN_BITS_SET 0x0203
5228 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
5229 #define IGU_ADDR_COALESCE_NOW 0x0205
5230 #define IGU_ADDR_SIMD_MASK 0x0206
5231 #define IGU_ADDR_SIMD_NOMASK 0x0207
5232 #define IGU_ADDR_MSI_CTL 0x0210
5233 #define IGU_ADDR_MSI_ADDR_LO 0x0211
5234 #define IGU_ADDR_MSI_ADDR_HI 0x0212
5235 #define IGU_ADDR_MSI_DATA 0x0213
5237 #define IGU_INT_ENABLE 0
5238 #define IGU_INT_DISABLE 1
5239 #define IGU_INT_NOP 2
5240 #define IGU_INT_NOP2 3
5242 #define COMMAND_REG_INT_ACK 0x0
5243 #define COMMAND_REG_PROD_UPD 0x4
5244 #define COMMAND_REG_ATTN_BITS_UPD 0x8
5245 #define COMMAND_REG_ATTN_BITS_SET 0xc
5246 #define COMMAND_REG_ATTN_BITS_CLR 0x10
5247 #define COMMAND_REG_COALESCE_NOW 0x14
5248 #define COMMAND_REG_SIMD_MASK 0x18
5249 #define COMMAND_REG_SIMD_NOMASK 0x1c
5252 #define IGU_MEM_BASE 0x0000
5254 #define IGU_MEM_MSIX_BASE 0x0000
5255 #define IGU_MEM_MSIX_UPPER 0x007f
5256 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
5258 #define IGU_MEM_PBA_MSIX_BASE 0x0200
5259 #define IGU_MEM_PBA_MSIX_UPPER 0x0200
5261 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
5262 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
5264 #define IGU_CMD_INT_ACK_BASE 0x0400
5265 #define IGU_CMD_INT_ACK_UPPER\
5266 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
5267 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
5269 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500
5270 #define IGU_CMD_E2_PROD_UPD_UPPER\
5271 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
5272 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
5274 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
5275 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
5276 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
5278 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
5279 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
5280 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
5281 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
5283 #define IGU_REG_RESERVED_UPPER 0x05ff
5286 #define CDU_REGION_NUMBER_XCM_AG 2
5287 #define CDU_REGION_NUMBER_UCM_AG 4
5290 /**
5291 * String-to-compress [31:8] = CID (all 24 bits)
5292 * String-to-compress [7:4] = Region
5293 * String-to-compress [3:0] = Type
5294 */
5295 #define CDU_VALID_DATA(_cid, _region, _type)\
5296 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
5297 #define CDU_CRC8(_cid, _region, _type)\
5298 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
5299 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
5300 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
5301 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
5302 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
5303 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
5305 /******************************************************************************
5306 * Description:
5307 * Calculates crc 8 on a word value: polynomial 0-1-2-8
5308 * Code was translated from Verilog.
5309 * Return:
5310 *****************************************************************************/
5312 {
5316 u8 crc_res;
5317 u8 i;
5319 /* split the data into 31 bits */
5323 }
5325 /* split the crc into 8 bits */
5329 }
5362 }