USB: xhci: Make endpoint interval debugging clearer.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / host / xhci-mem.c
blobbba9b19ed1b934f85f89149194d4c22fb023c861
1 /*
2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/dmapool.h>
27 #include "xhci.h"
30 * Allocates a generic ring segment from the ring pool, sets the dma address,
31 * initializes the segment to zero, and sets the private next pointer to NULL.
33 * Section 4.11.1.1:
34 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
36 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
38 struct xhci_segment *seg;
39 dma_addr_t dma;
41 seg = kzalloc(sizeof *seg, flags);
42 if (!seg)
43 return 0;
44 xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
46 seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
47 if (!seg->trbs) {
48 kfree(seg);
49 return 0;
51 xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
52 seg->trbs, (unsigned long long)dma);
54 memset(seg->trbs, 0, SEGMENT_SIZE);
55 seg->dma = dma;
56 seg->next = NULL;
58 return seg;
61 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
63 if (!seg)
64 return;
65 if (seg->trbs) {
66 xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
67 seg->trbs, (unsigned long long)seg->dma);
68 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
69 seg->trbs = NULL;
71 xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
72 kfree(seg);
76 * Make the prev segment point to the next segment.
78 * Change the last TRB in the prev segment to be a Link TRB which points to the
79 * DMA address of the next segment. The caller needs to set any Link TRB
80 * related flags, such as End TRB, Toggle Cycle, and no snoop.
82 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
83 struct xhci_segment *next, bool link_trbs)
85 u32 val;
87 if (!prev || !next)
88 return;
89 prev->next = next;
90 if (link_trbs) {
91 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = next->dma;
93 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
94 val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
95 val &= ~TRB_TYPE_BITMASK;
96 val |= TRB_TYPE(TRB_LINK);
97 /* Always set the chain bit with 0.95 hardware */
98 if (xhci_link_trb_quirk(xhci))
99 val |= TRB_CHAIN;
100 prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
102 xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
103 (unsigned long long)prev->dma,
104 (unsigned long long)next->dma);
107 /* XXX: Do we need the hcd structure in all these functions? */
108 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
110 struct xhci_segment *seg;
111 struct xhci_segment *first_seg;
113 if (!ring || !ring->first_seg)
114 return;
115 first_seg = ring->first_seg;
116 seg = first_seg->next;
117 xhci_dbg(xhci, "Freeing ring at %p\n", ring);
118 while (seg != first_seg) {
119 struct xhci_segment *next = seg->next;
120 xhci_segment_free(xhci, seg);
121 seg = next;
123 xhci_segment_free(xhci, first_seg);
124 ring->first_seg = NULL;
125 kfree(ring);
128 static void xhci_initialize_ring_info(struct xhci_ring *ring)
130 /* The ring is empty, so the enqueue pointer == dequeue pointer */
131 ring->enqueue = ring->first_seg->trbs;
132 ring->enq_seg = ring->first_seg;
133 ring->dequeue = ring->enqueue;
134 ring->deq_seg = ring->first_seg;
135 /* The ring is initialized to 0. The producer must write 1 to the cycle
136 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
137 * compare CCS to the cycle bit to check ownership, so CCS = 1.
139 ring->cycle_state = 1;
140 /* Not necessary for new rings, but needed for re-initialized rings */
141 ring->enq_updates = 0;
142 ring->deq_updates = 0;
146 * Create a new ring with zero or more segments.
148 * Link each segment together into a ring.
149 * Set the end flag and the cycle toggle bit on the last segment.
150 * See section 4.9.1 and figures 15 and 16.
152 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
153 unsigned int num_segs, bool link_trbs, gfp_t flags)
155 struct xhci_ring *ring;
156 struct xhci_segment *prev;
158 ring = kzalloc(sizeof *(ring), flags);
159 xhci_dbg(xhci, "Allocating ring at %p\n", ring);
160 if (!ring)
161 return 0;
163 INIT_LIST_HEAD(&ring->td_list);
164 if (num_segs == 0)
165 return ring;
167 ring->first_seg = xhci_segment_alloc(xhci, flags);
168 if (!ring->first_seg)
169 goto fail;
170 num_segs--;
172 prev = ring->first_seg;
173 while (num_segs > 0) {
174 struct xhci_segment *next;
176 next = xhci_segment_alloc(xhci, flags);
177 if (!next)
178 goto fail;
179 xhci_link_segments(xhci, prev, next, link_trbs);
181 prev = next;
182 num_segs--;
184 xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
186 if (link_trbs) {
187 /* See section 4.9.2.1 and 6.4.4.1 */
188 prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE);
189 xhci_dbg(xhci, "Wrote link toggle flag to"
190 " segment %p (virtual), 0x%llx (DMA)\n",
191 prev, (unsigned long long)prev->dma);
193 xhci_initialize_ring_info(ring);
194 return ring;
196 fail:
197 xhci_ring_free(xhci, ring);
198 return 0;
201 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
202 struct xhci_virt_device *virt_dev,
203 unsigned int ep_index)
205 int rings_cached;
207 rings_cached = virt_dev->num_rings_cached;
208 if (rings_cached < XHCI_MAX_RINGS_CACHED) {
209 virt_dev->num_rings_cached++;
210 rings_cached = virt_dev->num_rings_cached;
211 virt_dev->ring_cache[rings_cached] =
212 virt_dev->eps[ep_index].ring;
213 xhci_dbg(xhci, "Cached old ring, "
214 "%d ring%s cached\n",
215 rings_cached,
216 (rings_cached > 1) ? "s" : "");
217 } else {
218 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
219 xhci_dbg(xhci, "Ring cache full (%d rings), "
220 "freeing ring\n",
221 virt_dev->num_rings_cached);
223 virt_dev->eps[ep_index].ring = NULL;
226 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
227 * pointers to the beginning of the ring.
229 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
230 struct xhci_ring *ring)
232 struct xhci_segment *seg = ring->first_seg;
233 do {
234 memset(seg->trbs, 0,
235 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
236 /* All endpoint rings have link TRBs */
237 xhci_link_segments(xhci, seg, seg->next, 1);
238 seg = seg->next;
239 } while (seg != ring->first_seg);
240 xhci_initialize_ring_info(ring);
241 /* td list should be empty since all URBs have been cancelled,
242 * but just in case...
244 INIT_LIST_HEAD(&ring->td_list);
247 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
249 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
250 int type, gfp_t flags)
252 struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
253 if (!ctx)
254 return NULL;
256 BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
257 ctx->type = type;
258 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
259 if (type == XHCI_CTX_TYPE_INPUT)
260 ctx->size += CTX_SIZE(xhci->hcc_params);
262 ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
263 memset(ctx->bytes, 0, ctx->size);
264 return ctx;
267 void xhci_free_container_ctx(struct xhci_hcd *xhci,
268 struct xhci_container_ctx *ctx)
270 if (!ctx)
271 return;
272 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
273 kfree(ctx);
276 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
277 struct xhci_container_ctx *ctx)
279 BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
280 return (struct xhci_input_control_ctx *)ctx->bytes;
283 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
284 struct xhci_container_ctx *ctx)
286 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
287 return (struct xhci_slot_ctx *)ctx->bytes;
289 return (struct xhci_slot_ctx *)
290 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
293 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
294 struct xhci_container_ctx *ctx,
295 unsigned int ep_index)
297 /* increment ep index by offset of start of ep ctx array */
298 ep_index++;
299 if (ctx->type == XHCI_CTX_TYPE_INPUT)
300 ep_index++;
302 return (struct xhci_ep_ctx *)
303 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
306 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
307 struct xhci_virt_ep *ep)
309 init_timer(&ep->stop_cmd_timer);
310 ep->stop_cmd_timer.data = (unsigned long) ep;
311 ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
312 ep->xhci = xhci;
315 /* All the xhci_tds in the ring's TD list should be freed at this point */
316 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
318 struct xhci_virt_device *dev;
319 int i;
321 /* Slot ID 0 is reserved */
322 if (slot_id == 0 || !xhci->devs[slot_id])
323 return;
325 dev = xhci->devs[slot_id];
326 xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
327 if (!dev)
328 return;
330 for (i = 0; i < 31; ++i)
331 if (dev->eps[i].ring)
332 xhci_ring_free(xhci, dev->eps[i].ring);
334 if (dev->ring_cache) {
335 for (i = 0; i < dev->num_rings_cached; i++)
336 xhci_ring_free(xhci, dev->ring_cache[i]);
337 kfree(dev->ring_cache);
340 if (dev->in_ctx)
341 xhci_free_container_ctx(xhci, dev->in_ctx);
342 if (dev->out_ctx)
343 xhci_free_container_ctx(xhci, dev->out_ctx);
345 kfree(xhci->devs[slot_id]);
346 xhci->devs[slot_id] = 0;
349 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
350 struct usb_device *udev, gfp_t flags)
352 struct xhci_virt_device *dev;
353 int i;
355 /* Slot ID 0 is reserved */
356 if (slot_id == 0 || xhci->devs[slot_id]) {
357 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
358 return 0;
361 xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
362 if (!xhci->devs[slot_id])
363 return 0;
364 dev = xhci->devs[slot_id];
366 /* Allocate the (output) device context that will be used in the HC. */
367 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
368 if (!dev->out_ctx)
369 goto fail;
371 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
372 (unsigned long long)dev->out_ctx->dma);
374 /* Allocate the (input) device context for address device command */
375 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
376 if (!dev->in_ctx)
377 goto fail;
379 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
380 (unsigned long long)dev->in_ctx->dma);
382 /* Initialize the cancellation list and watchdog timers for each ep */
383 for (i = 0; i < 31; i++) {
384 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
385 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
388 /* Allocate endpoint 0 ring */
389 dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags);
390 if (!dev->eps[0].ring)
391 goto fail;
393 /* Allocate pointers to the ring cache */
394 dev->ring_cache = kzalloc(
395 sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
396 flags);
397 if (!dev->ring_cache)
398 goto fail;
399 dev->num_rings_cached = 0;
401 init_completion(&dev->cmd_completion);
402 INIT_LIST_HEAD(&dev->cmd_list);
404 /* Point to output device context in dcbaa. */
405 xhci->dcbaa->dev_context_ptrs[slot_id] = dev->out_ctx->dma;
406 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
407 slot_id,
408 &xhci->dcbaa->dev_context_ptrs[slot_id],
409 (unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]);
411 return 1;
412 fail:
413 xhci_free_virt_device(xhci, slot_id);
414 return 0;
417 /* Setup an xHCI virtual device for a Set Address command */
418 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
420 struct xhci_virt_device *dev;
421 struct xhci_ep_ctx *ep0_ctx;
422 struct usb_device *top_dev;
423 struct xhci_slot_ctx *slot_ctx;
424 struct xhci_input_control_ctx *ctrl_ctx;
426 dev = xhci->devs[udev->slot_id];
427 /* Slot ID 0 is reserved */
428 if (udev->slot_id == 0 || !dev) {
429 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
430 udev->slot_id);
431 return -EINVAL;
433 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
434 ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx);
435 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
437 /* 2) New slot context and endpoint 0 context are valid*/
438 ctrl_ctx->add_flags = SLOT_FLAG | EP0_FLAG;
440 /* 3) Only the control endpoint is valid - one endpoint context */
441 slot_ctx->dev_info |= LAST_CTX(1);
443 slot_ctx->dev_info |= (u32) udev->route;
444 switch (udev->speed) {
445 case USB_SPEED_SUPER:
446 slot_ctx->dev_info |= (u32) SLOT_SPEED_SS;
447 break;
448 case USB_SPEED_HIGH:
449 slot_ctx->dev_info |= (u32) SLOT_SPEED_HS;
450 break;
451 case USB_SPEED_FULL:
452 slot_ctx->dev_info |= (u32) SLOT_SPEED_FS;
453 break;
454 case USB_SPEED_LOW:
455 slot_ctx->dev_info |= (u32) SLOT_SPEED_LS;
456 break;
457 case USB_SPEED_WIRELESS:
458 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
459 return -EINVAL;
460 break;
461 default:
462 /* Speed was set earlier, this shouldn't happen. */
463 BUG();
465 /* Find the root hub port this device is under */
466 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
467 top_dev = top_dev->parent)
468 /* Found device below root hub */;
469 slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum);
470 xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum);
472 /* Is this a LS/FS device under a HS hub? */
473 if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) &&
474 udev->tt) {
475 slot_ctx->tt_info = udev->tt->hub->slot_id;
476 slot_ctx->tt_info |= udev->ttport << 8;
477 if (udev->tt->multi)
478 slot_ctx->dev_info |= DEV_MTT;
480 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
481 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
483 /* Step 4 - ring already allocated */
484 /* Step 5 */
485 ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP);
487 * XXX: Not sure about wireless USB devices.
489 switch (udev->speed) {
490 case USB_SPEED_SUPER:
491 ep0_ctx->ep_info2 |= MAX_PACKET(512);
492 break;
493 case USB_SPEED_HIGH:
494 /* USB core guesses at a 64-byte max packet first for FS devices */
495 case USB_SPEED_FULL:
496 ep0_ctx->ep_info2 |= MAX_PACKET(64);
497 break;
498 case USB_SPEED_LOW:
499 ep0_ctx->ep_info2 |= MAX_PACKET(8);
500 break;
501 case USB_SPEED_WIRELESS:
502 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
503 return -EINVAL;
504 break;
505 default:
506 /* New speed? */
507 BUG();
509 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
510 ep0_ctx->ep_info2 |= MAX_BURST(0);
511 ep0_ctx->ep_info2 |= ERROR_COUNT(3);
513 ep0_ctx->deq =
514 dev->eps[0].ring->first_seg->dma;
515 ep0_ctx->deq |= dev->eps[0].ring->cycle_state;
517 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
519 return 0;
522 /* Return the polling or NAK interval.
524 * The polling interval is expressed in "microframes". If xHCI's Interval field
525 * is set to N, it will service the endpoint every 2^(Interval)*125us.
527 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
528 * is set to 0.
530 static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
531 struct usb_host_endpoint *ep)
533 unsigned int interval = 0;
535 switch (udev->speed) {
536 case USB_SPEED_HIGH:
537 /* Max NAK rate */
538 if (usb_endpoint_xfer_control(&ep->desc) ||
539 usb_endpoint_xfer_bulk(&ep->desc))
540 interval = ep->desc.bInterval;
541 /* Fall through - SS and HS isoc/int have same decoding */
542 case USB_SPEED_SUPER:
543 if (usb_endpoint_xfer_int(&ep->desc) ||
544 usb_endpoint_xfer_isoc(&ep->desc)) {
545 if (ep->desc.bInterval == 0)
546 interval = 0;
547 else
548 interval = ep->desc.bInterval - 1;
549 if (interval > 15)
550 interval = 15;
551 if (interval != ep->desc.bInterval + 1)
552 dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n",
553 ep->desc.bEndpointAddress, 1 << interval);
555 break;
556 /* Convert bInterval (in 1-255 frames) to microframes and round down to
557 * nearest power of 2.
559 case USB_SPEED_FULL:
560 case USB_SPEED_LOW:
561 if (usb_endpoint_xfer_int(&ep->desc) ||
562 usb_endpoint_xfer_isoc(&ep->desc)) {
563 interval = fls(8*ep->desc.bInterval) - 1;
564 if (interval > 10)
565 interval = 10;
566 if (interval < 3)
567 interval = 3;
568 if ((1 << interval) != 8*ep->desc.bInterval)
569 dev_warn(&udev->dev,
570 "ep %#x - rounding interval"
571 " to %d microframes, "
572 "ep desc says %d microframes\n",
573 ep->desc.bEndpointAddress,
574 1 << interval,
575 8*ep->desc.bInterval);
577 break;
578 default:
579 BUG();
581 return EP_INTERVAL(interval);
584 static inline u32 xhci_get_endpoint_type(struct usb_device *udev,
585 struct usb_host_endpoint *ep)
587 int in;
588 u32 type;
590 in = usb_endpoint_dir_in(&ep->desc);
591 if (usb_endpoint_xfer_control(&ep->desc)) {
592 type = EP_TYPE(CTRL_EP);
593 } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
594 if (in)
595 type = EP_TYPE(BULK_IN_EP);
596 else
597 type = EP_TYPE(BULK_OUT_EP);
598 } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
599 if (in)
600 type = EP_TYPE(ISOC_IN_EP);
601 else
602 type = EP_TYPE(ISOC_OUT_EP);
603 } else if (usb_endpoint_xfer_int(&ep->desc)) {
604 if (in)
605 type = EP_TYPE(INT_IN_EP);
606 else
607 type = EP_TYPE(INT_OUT_EP);
608 } else {
609 BUG();
611 return type;
614 int xhci_endpoint_init(struct xhci_hcd *xhci,
615 struct xhci_virt_device *virt_dev,
616 struct usb_device *udev,
617 struct usb_host_endpoint *ep,
618 gfp_t mem_flags)
620 unsigned int ep_index;
621 struct xhci_ep_ctx *ep_ctx;
622 struct xhci_ring *ep_ring;
623 unsigned int max_packet;
624 unsigned int max_burst;
626 ep_index = xhci_get_endpoint_index(&ep->desc);
627 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
629 /* Set up the endpoint ring */
630 virt_dev->eps[ep_index].new_ring =
631 xhci_ring_alloc(xhci, 1, true, mem_flags);
632 if (!virt_dev->eps[ep_index].new_ring) {
633 /* Attempt to use the ring cache */
634 if (virt_dev->num_rings_cached == 0)
635 return -ENOMEM;
636 virt_dev->eps[ep_index].new_ring =
637 virt_dev->ring_cache[virt_dev->num_rings_cached];
638 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
639 virt_dev->num_rings_cached--;
640 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring);
642 ep_ring = virt_dev->eps[ep_index].new_ring;
643 ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state;
645 ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep);
647 /* FIXME dig Mult and streams info out of ep companion desc */
649 /* Allow 3 retries for everything but isoc;
650 * error count = 0 means infinite retries.
652 if (!usb_endpoint_xfer_isoc(&ep->desc))
653 ep_ctx->ep_info2 = ERROR_COUNT(3);
654 else
655 ep_ctx->ep_info2 = ERROR_COUNT(1);
657 ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep);
659 /* Set the max packet size and max burst */
660 switch (udev->speed) {
661 case USB_SPEED_SUPER:
662 max_packet = ep->desc.wMaxPacketSize;
663 ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
664 /* dig out max burst from ep companion desc */
665 if (!ep->ss_ep_comp) {
666 xhci_warn(xhci, "WARN no SS endpoint companion descriptor.\n");
667 max_packet = 0;
668 } else {
669 max_packet = ep->ss_ep_comp->desc.bMaxBurst;
671 ep_ctx->ep_info2 |= MAX_BURST(max_packet);
672 break;
673 case USB_SPEED_HIGH:
674 /* bits 11:12 specify the number of additional transaction
675 * opportunities per microframe (USB 2.0, section 9.6.6)
677 if (usb_endpoint_xfer_isoc(&ep->desc) ||
678 usb_endpoint_xfer_int(&ep->desc)) {
679 max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;
680 ep_ctx->ep_info2 |= MAX_BURST(max_burst);
682 /* Fall through */
683 case USB_SPEED_FULL:
684 case USB_SPEED_LOW:
685 max_packet = ep->desc.wMaxPacketSize & 0x3ff;
686 ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
687 break;
688 default:
689 BUG();
691 /* FIXME Debug endpoint context */
692 return 0;
695 void xhci_endpoint_zero(struct xhci_hcd *xhci,
696 struct xhci_virt_device *virt_dev,
697 struct usb_host_endpoint *ep)
699 unsigned int ep_index;
700 struct xhci_ep_ctx *ep_ctx;
702 ep_index = xhci_get_endpoint_index(&ep->desc);
703 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
705 ep_ctx->ep_info = 0;
706 ep_ctx->ep_info2 = 0;
707 ep_ctx->deq = 0;
708 ep_ctx->tx_info = 0;
709 /* Don't free the endpoint ring until the set interface or configuration
710 * request succeeds.
714 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
715 * Useful when you want to change one particular aspect of the endpoint and then
716 * issue a configure endpoint command.
718 void xhci_endpoint_copy(struct xhci_hcd *xhci,
719 struct xhci_container_ctx *in_ctx,
720 struct xhci_container_ctx *out_ctx,
721 unsigned int ep_index)
723 struct xhci_ep_ctx *out_ep_ctx;
724 struct xhci_ep_ctx *in_ep_ctx;
726 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
727 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
729 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
730 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
731 in_ep_ctx->deq = out_ep_ctx->deq;
732 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
735 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
736 * Useful when you want to change one particular aspect of the endpoint and then
737 * issue a configure endpoint command. Only the context entries field matters,
738 * but we'll copy the whole thing anyway.
740 void xhci_slot_copy(struct xhci_hcd *xhci,
741 struct xhci_container_ctx *in_ctx,
742 struct xhci_container_ctx *out_ctx)
744 struct xhci_slot_ctx *in_slot_ctx;
745 struct xhci_slot_ctx *out_slot_ctx;
747 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
748 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
750 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
751 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
752 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
753 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
756 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
757 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
759 int i;
760 struct device *dev = xhci_to_hcd(xhci)->self.controller;
761 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
763 xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
765 if (!num_sp)
766 return 0;
768 xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
769 if (!xhci->scratchpad)
770 goto fail_sp;
772 xhci->scratchpad->sp_array =
773 pci_alloc_consistent(to_pci_dev(dev),
774 num_sp * sizeof(u64),
775 &xhci->scratchpad->sp_dma);
776 if (!xhci->scratchpad->sp_array)
777 goto fail_sp2;
779 xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
780 if (!xhci->scratchpad->sp_buffers)
781 goto fail_sp3;
783 xhci->scratchpad->sp_dma_buffers =
784 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
786 if (!xhci->scratchpad->sp_dma_buffers)
787 goto fail_sp4;
789 xhci->dcbaa->dev_context_ptrs[0] = xhci->scratchpad->sp_dma;
790 for (i = 0; i < num_sp; i++) {
791 dma_addr_t dma;
792 void *buf = pci_alloc_consistent(to_pci_dev(dev),
793 xhci->page_size, &dma);
794 if (!buf)
795 goto fail_sp5;
797 xhci->scratchpad->sp_array[i] = dma;
798 xhci->scratchpad->sp_buffers[i] = buf;
799 xhci->scratchpad->sp_dma_buffers[i] = dma;
802 return 0;
804 fail_sp5:
805 for (i = i - 1; i >= 0; i--) {
806 pci_free_consistent(to_pci_dev(dev), xhci->page_size,
807 xhci->scratchpad->sp_buffers[i],
808 xhci->scratchpad->sp_dma_buffers[i]);
810 kfree(xhci->scratchpad->sp_dma_buffers);
812 fail_sp4:
813 kfree(xhci->scratchpad->sp_buffers);
815 fail_sp3:
816 pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64),
817 xhci->scratchpad->sp_array,
818 xhci->scratchpad->sp_dma);
820 fail_sp2:
821 kfree(xhci->scratchpad);
822 xhci->scratchpad = NULL;
824 fail_sp:
825 return -ENOMEM;
828 static void scratchpad_free(struct xhci_hcd *xhci)
830 int num_sp;
831 int i;
832 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
834 if (!xhci->scratchpad)
835 return;
837 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
839 for (i = 0; i < num_sp; i++) {
840 pci_free_consistent(pdev, xhci->page_size,
841 xhci->scratchpad->sp_buffers[i],
842 xhci->scratchpad->sp_dma_buffers[i]);
844 kfree(xhci->scratchpad->sp_dma_buffers);
845 kfree(xhci->scratchpad->sp_buffers);
846 pci_free_consistent(pdev, num_sp * sizeof(u64),
847 xhci->scratchpad->sp_array,
848 xhci->scratchpad->sp_dma);
849 kfree(xhci->scratchpad);
850 xhci->scratchpad = NULL;
853 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
854 bool allocate_in_ctx, bool allocate_completion,
855 gfp_t mem_flags)
857 struct xhci_command *command;
859 command = kzalloc(sizeof(*command), mem_flags);
860 if (!command)
861 return NULL;
863 if (allocate_in_ctx) {
864 command->in_ctx =
865 xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
866 mem_flags);
867 if (!command->in_ctx) {
868 kfree(command);
869 return NULL;
873 if (allocate_completion) {
874 command->completion =
875 kzalloc(sizeof(struct completion), mem_flags);
876 if (!command->completion) {
877 xhci_free_container_ctx(xhci, command->in_ctx);
878 kfree(command);
879 return NULL;
881 init_completion(command->completion);
884 command->status = 0;
885 INIT_LIST_HEAD(&command->cmd_list);
886 return command;
889 void xhci_free_command(struct xhci_hcd *xhci,
890 struct xhci_command *command)
892 xhci_free_container_ctx(xhci,
893 command->in_ctx);
894 kfree(command->completion);
895 kfree(command);
898 void xhci_mem_cleanup(struct xhci_hcd *xhci)
900 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
901 int size;
902 int i;
904 /* Free the Event Ring Segment Table and the actual Event Ring */
905 if (xhci->ir_set) {
906 xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
907 xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
908 xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
910 size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
911 if (xhci->erst.entries)
912 pci_free_consistent(pdev, size,
913 xhci->erst.entries, xhci->erst.erst_dma_addr);
914 xhci->erst.entries = NULL;
915 xhci_dbg(xhci, "Freed ERST\n");
916 if (xhci->event_ring)
917 xhci_ring_free(xhci, xhci->event_ring);
918 xhci->event_ring = NULL;
919 xhci_dbg(xhci, "Freed event ring\n");
921 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
922 if (xhci->cmd_ring)
923 xhci_ring_free(xhci, xhci->cmd_ring);
924 xhci->cmd_ring = NULL;
925 xhci_dbg(xhci, "Freed command ring\n");
927 for (i = 1; i < MAX_HC_SLOTS; ++i)
928 xhci_free_virt_device(xhci, i);
930 if (xhci->segment_pool)
931 dma_pool_destroy(xhci->segment_pool);
932 xhci->segment_pool = NULL;
933 xhci_dbg(xhci, "Freed segment pool\n");
935 if (xhci->device_pool)
936 dma_pool_destroy(xhci->device_pool);
937 xhci->device_pool = NULL;
938 xhci_dbg(xhci, "Freed device context pool\n");
940 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
941 if (xhci->dcbaa)
942 pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
943 xhci->dcbaa, xhci->dcbaa->dma);
944 xhci->dcbaa = NULL;
946 scratchpad_free(xhci);
947 xhci->page_size = 0;
948 xhci->page_shift = 0;
951 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
952 struct xhci_segment *input_seg,
953 union xhci_trb *start_trb,
954 union xhci_trb *end_trb,
955 dma_addr_t input_dma,
956 struct xhci_segment *result_seg,
957 char *test_name, int test_number)
959 unsigned long long start_dma;
960 unsigned long long end_dma;
961 struct xhci_segment *seg;
963 start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
964 end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
966 seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
967 if (seg != result_seg) {
968 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
969 test_name, test_number);
970 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
971 "input DMA 0x%llx\n",
972 input_seg,
973 (unsigned long long) input_dma);
974 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
975 "ending TRB %p (0x%llx DMA)\n",
976 start_trb, start_dma,
977 end_trb, end_dma);
978 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
979 result_seg, seg);
980 return -1;
982 return 0;
985 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
986 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
988 struct {
989 dma_addr_t input_dma;
990 struct xhci_segment *result_seg;
991 } simple_test_vector [] = {
992 /* A zeroed DMA field should fail */
993 { 0, NULL },
994 /* One TRB before the ring start should fail */
995 { xhci->event_ring->first_seg->dma - 16, NULL },
996 /* One byte before the ring start should fail */
997 { xhci->event_ring->first_seg->dma - 1, NULL },
998 /* Starting TRB should succeed */
999 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1000 /* Ending TRB should succeed */
1001 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1002 xhci->event_ring->first_seg },
1003 /* One byte after the ring end should fail */
1004 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1005 /* One TRB after the ring end should fail */
1006 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1007 /* An address of all ones should fail */
1008 { (dma_addr_t) (~0), NULL },
1010 struct {
1011 struct xhci_segment *input_seg;
1012 union xhci_trb *start_trb;
1013 union xhci_trb *end_trb;
1014 dma_addr_t input_dma;
1015 struct xhci_segment *result_seg;
1016 } complex_test_vector [] = {
1017 /* Test feeding a valid DMA address from a different ring */
1018 { .input_seg = xhci->event_ring->first_seg,
1019 .start_trb = xhci->event_ring->first_seg->trbs,
1020 .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1021 .input_dma = xhci->cmd_ring->first_seg->dma,
1022 .result_seg = NULL,
1024 /* Test feeding a valid end TRB from a different ring */
1025 { .input_seg = xhci->event_ring->first_seg,
1026 .start_trb = xhci->event_ring->first_seg->trbs,
1027 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1028 .input_dma = xhci->cmd_ring->first_seg->dma,
1029 .result_seg = NULL,
1031 /* Test feeding a valid start and end TRB from a different ring */
1032 { .input_seg = xhci->event_ring->first_seg,
1033 .start_trb = xhci->cmd_ring->first_seg->trbs,
1034 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1035 .input_dma = xhci->cmd_ring->first_seg->dma,
1036 .result_seg = NULL,
1038 /* TRB in this ring, but after this TD */
1039 { .input_seg = xhci->event_ring->first_seg,
1040 .start_trb = &xhci->event_ring->first_seg->trbs[0],
1041 .end_trb = &xhci->event_ring->first_seg->trbs[3],
1042 .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1043 .result_seg = NULL,
1045 /* TRB in this ring, but before this TD */
1046 { .input_seg = xhci->event_ring->first_seg,
1047 .start_trb = &xhci->event_ring->first_seg->trbs[3],
1048 .end_trb = &xhci->event_ring->first_seg->trbs[6],
1049 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1050 .result_seg = NULL,
1052 /* TRB in this ring, but after this wrapped TD */
1053 { .input_seg = xhci->event_ring->first_seg,
1054 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1055 .end_trb = &xhci->event_ring->first_seg->trbs[1],
1056 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1057 .result_seg = NULL,
1059 /* TRB in this ring, but before this wrapped TD */
1060 { .input_seg = xhci->event_ring->first_seg,
1061 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1062 .end_trb = &xhci->event_ring->first_seg->trbs[1],
1063 .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1064 .result_seg = NULL,
1066 /* TRB not in this ring, and we have a wrapped TD */
1067 { .input_seg = xhci->event_ring->first_seg,
1068 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1069 .end_trb = &xhci->event_ring->first_seg->trbs[1],
1070 .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1071 .result_seg = NULL,
1075 unsigned int num_tests;
1076 int i, ret;
1078 num_tests = sizeof(simple_test_vector) / sizeof(simple_test_vector[0]);
1079 for (i = 0; i < num_tests; i++) {
1080 ret = xhci_test_trb_in_td(xhci,
1081 xhci->event_ring->first_seg,
1082 xhci->event_ring->first_seg->trbs,
1083 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1084 simple_test_vector[i].input_dma,
1085 simple_test_vector[i].result_seg,
1086 "Simple", i);
1087 if (ret < 0)
1088 return ret;
1091 num_tests = sizeof(complex_test_vector) / sizeof(complex_test_vector[0]);
1092 for (i = 0; i < num_tests; i++) {
1093 ret = xhci_test_trb_in_td(xhci,
1094 complex_test_vector[i].input_seg,
1095 complex_test_vector[i].start_trb,
1096 complex_test_vector[i].end_trb,
1097 complex_test_vector[i].input_dma,
1098 complex_test_vector[i].result_seg,
1099 "Complex", i);
1100 if (ret < 0)
1101 return ret;
1103 xhci_dbg(xhci, "TRB math tests passed.\n");
1104 return 0;
1108 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
1110 dma_addr_t dma;
1111 struct device *dev = xhci_to_hcd(xhci)->self.controller;
1112 unsigned int val, val2;
1113 u64 val_64;
1114 struct xhci_segment *seg;
1115 u32 page_size;
1116 int i;
1118 page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
1119 xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
1120 for (i = 0; i < 16; i++) {
1121 if ((0x1 & page_size) != 0)
1122 break;
1123 page_size = page_size >> 1;
1125 if (i < 16)
1126 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
1127 else
1128 xhci_warn(xhci, "WARN: no supported page size\n");
1129 /* Use 4K pages, since that's common and the minimum the HC supports */
1130 xhci->page_shift = 12;
1131 xhci->page_size = 1 << xhci->page_shift;
1132 xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
1135 * Program the Number of Device Slots Enabled field in the CONFIG
1136 * register with the max value of slots the HC can handle.
1138 val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
1139 xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
1140 (unsigned int) val);
1141 val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
1142 val |= (val2 & ~HCS_SLOTS_MASK);
1143 xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
1144 (unsigned int) val);
1145 xhci_writel(xhci, val, &xhci->op_regs->config_reg);
1148 * Section 5.4.8 - doorbell array must be
1149 * "physically contiguous and 64-byte (cache line) aligned".
1151 xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
1152 sizeof(*xhci->dcbaa), &dma);
1153 if (!xhci->dcbaa)
1154 goto fail;
1155 memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
1156 xhci->dcbaa->dma = dma;
1157 xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
1158 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
1159 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
1162 * Initialize the ring segment pool. The ring must be a contiguous
1163 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
1164 * however, the command ring segment needs 64-byte aligned segments,
1165 * so we pick the greater alignment need.
1167 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
1168 SEGMENT_SIZE, 64, xhci->page_size);
1170 /* See Table 46 and Note on Figure 55 */
1171 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
1172 2112, 64, xhci->page_size);
1173 if (!xhci->segment_pool || !xhci->device_pool)
1174 goto fail;
1176 /* Set up the command ring to have one segments for now. */
1177 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
1178 if (!xhci->cmd_ring)
1179 goto fail;
1180 xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
1181 xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
1182 (unsigned long long)xhci->cmd_ring->first_seg->dma);
1184 /* Set the address in the Command Ring Control register */
1185 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1186 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
1187 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
1188 xhci->cmd_ring->cycle_state;
1189 xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
1190 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
1191 xhci_dbg_cmd_ptrs(xhci);
1193 val = xhci_readl(xhci, &xhci->cap_regs->db_off);
1194 val &= DBOFF_MASK;
1195 xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
1196 " from cap regs base addr\n", val);
1197 xhci->dba = (void *) xhci->cap_regs + val;
1198 xhci_dbg_regs(xhci);
1199 xhci_print_run_regs(xhci);
1200 /* Set ir_set to interrupt register set 0 */
1201 xhci->ir_set = (void *) xhci->run_regs->ir_set;
1204 * Event ring setup: Allocate a normal ring, but also setup
1205 * the event ring segment table (ERST). Section 4.9.3.
1207 xhci_dbg(xhci, "// Allocating event ring\n");
1208 xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
1209 if (!xhci->event_ring)
1210 goto fail;
1211 if (xhci_check_trb_in_td_math(xhci, flags) < 0)
1212 goto fail;
1214 xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
1215 sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
1216 if (!xhci->erst.entries)
1217 goto fail;
1218 xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
1219 (unsigned long long)dma);
1221 memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
1222 xhci->erst.num_entries = ERST_NUM_SEGS;
1223 xhci->erst.erst_dma_addr = dma;
1224 xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
1225 xhci->erst.num_entries,
1226 xhci->erst.entries,
1227 (unsigned long long)xhci->erst.erst_dma_addr);
1229 /* set ring base address and size for each segment table entry */
1230 for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
1231 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
1232 entry->seg_addr = seg->dma;
1233 entry->seg_size = TRBS_PER_SEGMENT;
1234 entry->rsvd = 0;
1235 seg = seg->next;
1238 /* set ERST count with the number of entries in the segment table */
1239 val = xhci_readl(xhci, &xhci->ir_set->erst_size);
1240 val &= ERST_SIZE_MASK;
1241 val |= ERST_NUM_SEGS;
1242 xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
1243 val);
1244 xhci_writel(xhci, val, &xhci->ir_set->erst_size);
1246 xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
1247 /* set the segment table base address */
1248 xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
1249 (unsigned long long)xhci->erst.erst_dma_addr);
1250 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
1251 val_64 &= ERST_PTR_MASK;
1252 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
1253 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
1255 /* Set the event ring dequeue address */
1256 xhci_set_hc_event_deq(xhci);
1257 xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
1258 xhci_print_ir_set(xhci, xhci->ir_set, 0);
1261 * XXX: Might need to set the Interrupter Moderation Register to
1262 * something other than the default (~1ms minimum between interrupts).
1263 * See section 5.5.1.2.
1265 init_completion(&xhci->addr_dev);
1266 for (i = 0; i < MAX_HC_SLOTS; ++i)
1267 xhci->devs[i] = 0;
1269 if (scratchpad_alloc(xhci, flags))
1270 goto fail;
1272 return 0;
1274 fail:
1275 xhci_warn(xhci, "Couldn't initialize memory\n");
1276 xhci_mem_cleanup(xhci);
1277 return -ENOMEM;