3 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4 # Licensed and distributed under the GPL
8 bool "EDAC (Error Detection And Correction) reporting"
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
14 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
18 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
21 <http://bluesmoke.sourceforge.net/>
25 <http://buttersideup.com/edacwiki>
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
32 comment "Reporting subsystems"
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
42 config EDAC_DECODE_MCE
43 tristate "Decode MCEs in human-readable form (only on AMD for now)"
44 depends on CPU_SUP_AMD && X86_MCE
47 Enable this option if you want to decode Machine Check Exceptions
48 occuring on your machine in human-readable form.
50 You should definitely say Y here in case you want to decode MCEs
51 which occur really early upon boot, before the module infrastructure
55 tristate "Simple MCE injection interface over /sysfs"
56 depends on EDAC_DECODE_MCE
59 This is a simple interface to inject MCEs over /sysfs and test
60 the MCE decoding code in EDAC.
62 This is currently AMD-only.
65 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
67 Some systems are able to detect and correct errors in main
68 memory. EDAC can report statistics on memory error
69 detection and correction (EDAC - or commonly referred to ECC
70 errors). EDAC will also try to decode where these errors
71 occurred so that a particular failing memory module can be
72 replaced. If unsure, select 'Y'.
78 tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
79 depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
81 Support for error detection and correction on the AMD 64
82 Families of Memory Controllers (K8, F10h and F11h)
84 config EDAC_AMD64_ERROR_INJECTION
85 bool "Sysfs HW Error injection facilities"
88 Recent Opterons (Family 10h and later) provide for Memory Error
89 Injection into the ECC detection circuits. The amd64_edac module
90 allows the operator/user to inject Uncorrectable and Correctable
93 When enabled, in each of the respective memory controller directories
94 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
104 tristate "AMD 76x (760, 762, 768)"
105 depends on EDAC_MM_EDAC && PCI && X86_32
107 Support for error detection and correction on the AMD 76x
108 series of chipsets used with the Athlon processor.
111 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
112 depends on EDAC_MM_EDAC && PCI && X86_32
114 Support for error detection and correction on the Intel
115 E7205, E7500, E7501 and E7505 server chipsets.
118 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
119 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
121 Support for error detection and correction on the Intel
122 E7520, E7525, E7320 server chipsets.
124 config EDAC_I82443BXGX
125 tristate "Intel 82443BX/GX (440BX/GX)"
126 depends on EDAC_MM_EDAC && PCI && X86_32
129 Support for error detection and correction on the Intel
130 82443BX/GX memory controllers (440BX/GX chipsets).
133 tristate "Intel 82875p (D82875P, E7210)"
134 depends on EDAC_MM_EDAC && PCI && X86_32
136 Support for error detection and correction on the Intel
137 DP82785P and E7210 server chipsets.
140 tristate "Intel 82975x (D82975x)"
141 depends on EDAC_MM_EDAC && PCI && X86
143 Support for error detection and correction on the Intel
144 DP82975x server chipsets.
147 tristate "Intel 3000/3010"
148 depends on EDAC_MM_EDAC && PCI && X86
150 Support for error detection and correction on the Intel
151 3000 and 3010 server chipsets.
154 tristate "Intel 3200"
155 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
157 Support for error detection and correction on the Intel
158 3200 and 3210 server chipsets.
162 depends on EDAC_MM_EDAC && PCI && X86
164 Support for error detection and correction on the Intel
168 tristate "Intel 5400 (Seaburg) chipsets"
169 depends on EDAC_MM_EDAC && PCI && X86
171 Support for error detection and correction the Intel
172 i5400 MCH chipset (Seaburg).
175 tristate "Intel i7 Core (Nehalem) processors"
176 depends on EDAC_MM_EDAC && PCI && X86
179 Support for error detection and correction the Intel
180 i7 Core (Nehalem) Integrated Memory Controller that exists on
181 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
182 and Xeon 55xx processors.
185 tristate "Intel 82860"
186 depends on EDAC_MM_EDAC && PCI && X86_32
188 Support for error detection and correction on the Intel
192 tristate "Radisys 82600 embedded chipset"
193 depends on EDAC_MM_EDAC && PCI && X86_32
195 Support for error detection and correction on the Radisys
196 82600 embedded chipset.
199 tristate "Intel Greencreek/Blackford chipset"
200 depends on EDAC_MM_EDAC && X86 && PCI
202 Support for error detection and correction the Intel
203 Greekcreek/Blackford chipsets.
206 tristate "Intel San Clemente MCH"
207 depends on EDAC_MM_EDAC && X86 && PCI
209 Support for error detection and correction the Intel
213 tristate "Freescale MPC83xx / MPC85xx"
214 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
216 Support for error detection and correction on the Freescale
217 MPC8349, MPC8560, MPC8540, MPC8548
220 tristate "Marvell MV64x60"
221 depends on EDAC_MM_EDAC && MV64X60
223 Support for error detection and correction on the Marvell
224 MV64360 and MV64460 chipsets.
227 tristate "PA Semi PWRficient"
228 depends on EDAC_MM_EDAC && PCI
229 depends on PPC_PASEMI
231 Support for error detection and correction on PA Semi
235 tristate "Cell Broadband Engine memory controller"
236 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
238 Support for error detection and correction on the
239 Cell Broadband Engine internal memory controller
240 on platform without a hypervisor
243 tristate "PPC4xx IBM DDR2 Memory Controller"
244 depends on EDAC_MM_EDAC && 4xx
246 This enables support for EDAC on the ECC memory used
247 with the IBM DDR2 memory controller found in various
248 PowerPC 4xx embedded processors such as the 405EX[r],
249 440SP, 440SPe, 460EX, 460GT and 460SX.
252 tristate "AMD8131 HyperTransport PCI-X Tunnel"
253 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
255 Support for error detection and correction on the
256 AMD8131 HyperTransport PCI-X Tunnel chip.
257 Note, add more Kconfig dependency if it's adopted
258 on some machine other than Maple.
261 tristate "AMD8111 HyperTransport I/O Hub"
262 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
264 Support for error detection and correction on the
265 AMD8111 HyperTransport I/O Hub chip.
266 Note, add more Kconfig dependency if it's adopted
267 on some machine other than Maple.
270 tristate "IBM CPC925 Memory Controller (PPC970FX)"
271 depends on EDAC_MM_EDAC && PPC64
273 Support for error detection and correction on the
274 IBM CPC925 Bridge and Memory Controller, which is
275 a companion chip to the PowerPC 970 family of