drivers/char/rocket.c

   1 /*
   2  * RocketPort device driver for Linux
   3  *
   4  * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
   5  *
   6  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of the
  11  * License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Kernel Synchronization:
  25  *
  26  * This driver has 2 kernel control paths - exception handlers (calls into the driver
  27  * from user mode) and the timer bottom half (tasklet).  This is a polled driver, interrupts
  28  * are not used.
  29  *
  30  * Critical data:
  31  * -  rp_table[], accessed through passed "info" pointers, is a global (static) array of
  32  *    serial port state information and the xmit_buf circular buffer.  Protected by
  33  *    a per port spinlock.
  34  * -  xmit_flags[], an array of ints indexed by line (port) number, indicating that there
  35  *    is data to be transmitted.  Protected by atomic bit operations.
  36  * -  rp_num_ports, int indicating number of open ports, protected by atomic operations.
  37  *
  38  * rp_write() and rp_write_char() functions use a per port semaphore to protect against
  39  * simultaneous access to the same port by more than one process.
  40  */
  41
  42 /****** Defines ******/
  43 #ifdef PCI_NUM_RESOURCES
  44 #define PCI_BASE_ADDRESS(dev, r) ((dev)->resource[r].start)
  45 #else
  46 #define PCI_BASE_ADDRESS(dev, r) ((dev)->base_address[r])
  47 #endif
  48
  49 #define ROCKET_PARANOIA_CHECK
  50 #define ROCKET_DISABLE_SIMUSAGE
  51
  52 #undef ROCKET_SOFT_FLOW
  53 #undef ROCKET_DEBUG_OPEN
  54 #undef ROCKET_DEBUG_INTR
  55 #undef ROCKET_DEBUG_WRITE
  56 #undef ROCKET_DEBUG_FLOW
  57 #undef ROCKET_DEBUG_THROTTLE
  58 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
  59 #undef ROCKET_DEBUG_RECEIVE
  60 #undef ROCKET_DEBUG_HANGUP
  61 #undef REV_PCI_ORDER
  62 #undef ROCKET_DEBUG_IO
  63
  64 #define POLL_PERIOD HZ/100      /*  Polling period .01 seconds (10ms) */
  65
  66 /****** Kernel includes ******/
  67
  68 #include <linux/module.h>
  69 #include <linux/errno.h>
  70 #include <linux/major.h>
  71 #include <linux/kernel.h>
  72 #include <linux/signal.h>
  73 #include <linux/slab.h>
  74 #include <linux/mm.h>
  75 #include <linux/sched.h>
  76 #include <linux/timer.h>
  77 #include <linux/interrupt.h>
  78 #include <linux/tty.h>
  79 #include <linux/tty_driver.h>
  80 #include <linux/tty_flip.h>
  81 #include <linux/string.h>
  82 #include <linux/fcntl.h>
  83 #include <linux/ptrace.h>
  84 #include <linux/mutex.h>
  85 #include <linux/ioport.h>
  86 #include <linux/delay.h>
  87 #include <linux/wait.h>
  88 #include <linux/pci.h>
  89 #include <asm/uaccess.h>
  90 #include <asm/atomic.h>
  91 #include <linux/bitops.h>
  92 #include <linux/spinlock.h>
  93 #include <linux/init.h>
  94
  95 /****** RocketPort includes ******/
  96
  97 #include "rocket_int.h"
  98 #include "rocket.h"
  99
 100 #define ROCKET_VERSION "2.09"
 101 #define ROCKET_DATE "12-June-2003"
 102
 103 /****** RocketPort Local Variables ******/
 104
 105 static void rp_do_poll(unsigned long dummy);
 106
 107 static struct tty_driver *rocket_driver;
 108
 109 static struct rocket_version driver_version = {
 110         ROCKET_VERSION, ROCKET_DATE
 111 };
 112
 113 static struct r_port *rp_table[MAX_RP_PORTS];          /*  The main repository of serial port state information. */
 114 static unsigned int xmit_flags[NUM_BOARDS];            /*  Bit significant, indicates port had data to transmit. */
 115                                                        /*  eg.  Bit 0 indicates port 0 has xmit data, ...        */
 116 static atomic_t rp_num_ports_open;                     /*  Number of serial ports open                           */
 117 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
 118
 119 static unsigned long board1;                           /* ISA addresses, retrieved from rocketport.conf          */
 120 static unsigned long board2;
 121 static unsigned long board3;
 122 static unsigned long board4;
 123 static unsigned long controller;
 124 static int support_low_speed;
 125 static unsigned long modem1;
 126 static unsigned long modem2;
 127 static unsigned long modem3;
 128 static unsigned long modem4;
 129 static unsigned long pc104_1[8];
 130 static unsigned long pc104_2[8];
 131 static unsigned long pc104_3[8];
 132 static unsigned long pc104_4[8];
 133 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
 134
 135 static int rp_baud_base[NUM_BOARDS];                   /*  Board config info (Someday make a per-board structure)  */
 136 static unsigned long rcktpt_io_addr[NUM_BOARDS];
 137 static int rcktpt_type[NUM_BOARDS];
 138 static int is_PCI[NUM_BOARDS];
 139 static rocketModel_t rocketModel[NUM_BOARDS];
 140 static int max_board;
 141
 142 /*
 143  * The following arrays define the interrupt bits corresponding to each AIOP.
 144  * These bits are different between the ISA and regular PCI boards and the
 145  * Universal PCI boards.
 146  */
 147
 148 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
 149         AIOP_INTR_BIT_0,
 150         AIOP_INTR_BIT_1,
 151         AIOP_INTR_BIT_2,
 152         AIOP_INTR_BIT_3
 153 };
 154
 155 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
 156         UPCI_AIOP_INTR_BIT_0,
 157         UPCI_AIOP_INTR_BIT_1,
 158         UPCI_AIOP_INTR_BIT_2,
 159         UPCI_AIOP_INTR_BIT_3
 160 };
 161
 162 static Byte_t RData[RDATASIZE] = {
 163         0x00, 0x09, 0xf6, 0x82,
 164         0x02, 0x09, 0x86, 0xfb,
 165         0x04, 0x09, 0x00, 0x0a,
 166         0x06, 0x09, 0x01, 0x0a,
 167         0x08, 0x09, 0x8a, 0x13,
 168         0x0a, 0x09, 0xc5, 0x11,
 169         0x0c, 0x09, 0x86, 0x85,
 170         0x0e, 0x09, 0x20, 0x0a,
 171         0x10, 0x09, 0x21, 0x0a,
 172         0x12, 0x09, 0x41, 0xff,
 173         0x14, 0x09, 0x82, 0x00,
 174         0x16, 0x09, 0x82, 0x7b,
 175         0x18, 0x09, 0x8a, 0x7d,
 176         0x1a, 0x09, 0x88, 0x81,
 177         0x1c, 0x09, 0x86, 0x7a,
 178         0x1e, 0x09, 0x84, 0x81,
 179         0x20, 0x09, 0x82, 0x7c,
 180         0x22, 0x09, 0x0a, 0x0a
 181 };
 182
 183 static Byte_t RRegData[RREGDATASIZE] = {
 184         0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
 185         0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
 186         0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
 187         0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
 188         0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
 189         0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
 190         0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
 191         0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
 192         0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
 193         0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
 194         0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
 195         0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
 196         0x22, 0x09, 0x0a, 0x0a  /* 30: Rx FIFO Enable */
 197 };
 198
 199 static CONTROLLER_T sController[CTL_SIZE] = {
 200         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 201          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 202         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 203          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 204         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 205          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 206         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 207          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
 208 };
 209
 210 static Byte_t sBitMapClrTbl[8] = {
 211         0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
 212 };
 213
 214 static Byte_t sBitMapSetTbl[8] = {
 215         0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
 216 };
 217
 218 static int sClockPrescale = 0x14;
 219
 220 /*
 221  *  Line number is the ttySIx number (x), the Minor number.  We
 222  *  assign them sequentially, starting at zero.  The following
 223  *  array keeps track of the line number assigned to a given board/aiop/channel.
 224  */
 225 static unsigned char lineNumbers[MAX_RP_PORTS];
 226 static unsigned long nextLineNumber;
 227
 228 /*****  RocketPort Static Prototypes   *********/
 229 static int __init init_ISA(int i);
 230 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
 231 static void rp_flush_buffer(struct tty_struct *tty);
 232 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
 233 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
 234 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
 235 static void rp_start(struct tty_struct *tty);
 236 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
 237                      int ChanNum);
 238 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
 239 static void sFlushRxFIFO(CHANNEL_T * ChP);
 240 static void sFlushTxFIFO(CHANNEL_T * ChP);
 241 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
 242 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
 243 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
 244 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
 245 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
 246 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
 247                               ByteIO_t * AiopIOList, int AiopIOListSize,
 248                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
 249                               int PeriodicOnly, int altChanRingIndicator,
 250                               int UPCIRingInd);
 251 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
 252                            ByteIO_t * AiopIOList, int AiopIOListSize,
 253                            int IRQNum, Byte_t Frequency, int PeriodicOnly);
 254 static int sReadAiopID(ByteIO_t io);
 255 static int sReadAiopNumChan(WordIO_t io);
 256
 257 MODULE_AUTHOR("Theodore Ts'o");
 258 MODULE_DESCRIPTION("Comtrol RocketPort driver");
 259 module_param(board1, ulong, 0);
 260 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
 261 module_param(board2, ulong, 0);
 262 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
 263 module_param(board3, ulong, 0);
 264 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
 265 module_param(board4, ulong, 0);
 266 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
 267 module_param(controller, ulong, 0);
 268 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
 269 module_param(support_low_speed, bool, 0);
 270 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
 271 module_param(modem1, ulong, 0);
 272 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
 273 module_param(modem2, ulong, 0);
 274 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
 275 module_param(modem3, ulong, 0);
 276 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
 277 module_param(modem4, ulong, 0);
 278 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
 279 module_param_array(pc104_1, ulong, NULL, 0);
 280 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
 281 module_param_array(pc104_2, ulong, NULL, 0);
 282 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
 283 module_param_array(pc104_3, ulong, NULL, 0);
 284 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
 285 module_param_array(pc104_4, ulong, NULL, 0);
 286 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
 287
 288 static int rp_init(void);
 289 static void rp_cleanup_module(void);
 290
 291 module_init(rp_init);
 292 module_exit(rp_cleanup_module);
 293
 294
 295 MODULE_LICENSE("Dual BSD/GPL");
 296
 297 /*************************************************************************/
 298 /*                     Module code starts here                           */
 299
 300 static inline int rocket_paranoia_check(struct r_port *info,
 301                                         const char *routine)
 302 {
 303 #ifdef ROCKET_PARANOIA_CHECK
 304         if (!info)
 305                 return 1;
 306         if (info->magic != RPORT_MAGIC) {
 307                 printk(KERN_INFO "Warning: bad magic number for rocketport struct in %s\n",
 308                      routine);
 309                 return 1;
 310         }
 311 #endif
 312         return 0;
 313 }
 314
 315
 316 /*  Serial port receive data function.  Called (from timer poll) when an AIOPIC signals
 317  *  that receive data is present on a serial port.  Pulls data from FIFO, moves it into the
 318  *  tty layer.
 319  */
 320 static void rp_do_receive(struct r_port *info,
 321                           struct tty_struct *tty,
 322                           CHANNEL_t * cp, unsigned int ChanStatus)
 323 {
 324         unsigned int CharNStat;
 325         int ToRecv, wRecv, space;
 326         unsigned char *cbuf;
 327
 328         ToRecv = sGetRxCnt(cp);
 329 #ifdef ROCKET_DEBUG_INTR
 330         printk(KERN_INFO "rp_do_receive(%d)...", ToRecv);
 331 #endif
 332         if (ToRecv == 0)
 333                 return;
 334
 335         /*
 336          * if status indicates there are errored characters in the
 337          * FIFO, then enter status mode (a word in FIFO holds
 338          * character and status).
 339          */
 340         if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
 341                 if (!(ChanStatus & STATMODE)) {
 342 #ifdef ROCKET_DEBUG_RECEIVE
 343                         printk(KERN_INFO "Entering STATMODE...");
 344 #endif
 345                         ChanStatus |= STATMODE;
 346                         sEnRxStatusMode(cp);
 347                 }
 348         }
 349
 350         /*
 351          * if we previously entered status mode, then read down the
 352          * FIFO one word at a time, pulling apart the character and
 353          * the status.  Update error counters depending on status
 354          */
 355         if (ChanStatus & STATMODE) {
 356 #ifdef ROCKET_DEBUG_RECEIVE
 357                 printk(KERN_INFO "Ignore %x, read %x...", info->ignore_status_mask,
 358                        info->read_status_mask);
 359 #endif
 360                 while (ToRecv) {
 361                         char flag;
 362
 363                         CharNStat = sInW(sGetTxRxDataIO(cp));
 364 #ifdef ROCKET_DEBUG_RECEIVE
 365                         printk(KERN_INFO "%x...", CharNStat);
 366 #endif
 367                         if (CharNStat & STMBREAKH)
 368                                 CharNStat &= ~(STMFRAMEH | STMPARITYH);
 369                         if (CharNStat & info->ignore_status_mask) {
 370                                 ToRecv--;
 371                                 continue;
 372                         }
 373                         CharNStat &= info->read_status_mask;
 374                         if (CharNStat & STMBREAKH)
 375                                 flag = TTY_BREAK;
 376                         else if (CharNStat & STMPARITYH)
 377                                 flag = TTY_PARITY;
 378                         else if (CharNStat & STMFRAMEH)
 379                                 flag = TTY_FRAME;
 380                         else if (CharNStat & STMRCVROVRH)
 381                                 flag = TTY_OVERRUN;
 382                         else
 383                                 flag = TTY_NORMAL;
 384                         tty_insert_flip_char(tty, CharNStat & 0xff, flag);
 385                         ToRecv--;
 386                 }
 387
 388                 /*
 389                  * after we've emptied the FIFO in status mode, turn
 390                  * status mode back off
 391                  */
 392                 if (sGetRxCnt(cp) == 0) {
 393 #ifdef ROCKET_DEBUG_RECEIVE
 394                         printk(KERN_INFO "Status mode off.\n");
 395 #endif
 396                         sDisRxStatusMode(cp);
 397                 }
 398         } else {
 399                 /*
 400                  * we aren't in status mode, so read down the FIFO two
 401                  * characters at time by doing repeated word IO
 402                  * transfer.
 403                  */
 404                 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
 405                 if (space < ToRecv) {
 406 #ifdef ROCKET_DEBUG_RECEIVE
 407                         printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
 408 #endif
 409                         if (space <= 0)
 410                                 return;
 411                         ToRecv = space;
 412                 }
 413                 wRecv = ToRecv >> 1;
 414                 if (wRecv)
 415                         sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
 416                 if (ToRecv & 1)
 417                         cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
 418         }
 419         /*  Push the data up to the tty layer */
 420         tty_flip_buffer_push(tty);
 421 }
 422
 423 /*
 424  *  Serial port transmit data function.  Called from the timer polling loop as a
 425  *  result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
 426  *  to be sent out the serial port.  Data is buffered in rp_table[line].xmit_buf, it is
 427  *  moved to the port's xmit FIFO.  *info is critical data, protected by spinlocks.
 428  */
 429 static void rp_do_transmit(struct r_port *info)
 430 {
 431         int c;
 432         CHANNEL_t *cp = &info->channel;
 433         struct tty_struct *tty;
 434         unsigned long flags;
 435
 436 #ifdef ROCKET_DEBUG_INTR
 437         printk(KERN_INFO "rp_do_transmit ");
 438 #endif
 439         if (!info)
 440                 return;
 441         if (!info->tty) {
 442                 printk(KERN_INFO  "rp: WARNING rp_do_transmit called with info->tty==NULL\n");
 443                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 444                 return;
 445         }
 446
 447         spin_lock_irqsave(&info->slock, flags);
 448         tty = info->tty;
 449         info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
 450
 451         /*  Loop sending data to FIFO until done or FIFO full */
 452         while (1) {
 453                 if (tty->stopped || tty->hw_stopped)
 454                         break;
 455                 c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
 456                 if (c <= 0 || info->xmit_fifo_room <= 0)
 457                         break;
 458                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
 459                 if (c & 1)
 460                         sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
 461                 info->xmit_tail += c;
 462                 info->xmit_tail &= XMIT_BUF_SIZE - 1;
 463                 info->xmit_cnt -= c;
 464                 info->xmit_fifo_room -= c;
 465 #ifdef ROCKET_DEBUG_INTR
 466                 printk(KERN_INFO "tx %d chars...", c);
 467 #endif
 468         }
 469
 470         if (info->xmit_cnt == 0)
 471                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 472
 473         if (info->xmit_cnt < WAKEUP_CHARS) {
 474                 tty_wakeup(tty);
 475 #ifdef ROCKETPORT_HAVE_POLL_WAIT
 476                 wake_up_interruptible(&tty->poll_wait);
 477 #endif
 478         }
 479
 480         spin_unlock_irqrestore(&info->slock, flags);
 481
 482 #ifdef ROCKET_DEBUG_INTR
 483         printk(KERN_INFO "(%d,%d,%d,%d)...", info->xmit_cnt, info->xmit_head,
 484                info->xmit_tail, info->xmit_fifo_room);
 485 #endif
 486 }
 487
 488 /*
 489  *  Called when a serial port signals it has read data in it's RX FIFO.
 490  *  It checks what interrupts are pending and services them, including
 491  *  receiving serial data.
 492  */
 493 static void rp_handle_port(struct r_port *info)
 494 {
 495         CHANNEL_t *cp;
 496         struct tty_struct *tty;
 497         unsigned int IntMask, ChanStatus;
 498
 499         if (!info)
 500                 return;
 501
 502         if ((info->flags & ROCKET_INITIALIZED) == 0) {
 503                 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->flags & NOT_INIT\n");
 504                 return;
 505         }
 506         if (!info->tty) {
 507                 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->tty==NULL\n");
 508                 return;
 509         }
 510         cp = &info->channel;
 511         tty = info->tty;
 512
 513         IntMask = sGetChanIntID(cp) & info->intmask;
 514 #ifdef ROCKET_DEBUG_INTR
 515         printk(KERN_INFO "rp_interrupt %02x...", IntMask);
 516 #endif
 517         ChanStatus = sGetChanStatus(cp);
 518         if (IntMask & RXF_TRIG) {       /* Rx FIFO trigger level */
 519                 rp_do_receive(info, tty, cp, ChanStatus);
 520         }
 521         if (IntMask & DELTA_CD) {       /* CD change  */
 522 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
 523                 printk(KERN_INFO "ttyR%d CD now %s...", info->line,
 524                        (ChanStatus & CD_ACT) ? "on" : "off");
 525 #endif
 526                 if (!(ChanStatus & CD_ACT) && info->cd_status) {
 527 #ifdef ROCKET_DEBUG_HANGUP
 528                         printk(KERN_INFO "CD drop, calling hangup.\n");
 529 #endif
 530                         tty_hangup(tty);
 531                 }
 532                 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
 533                 wake_up_interruptible(&info->open_wait);
 534         }
 535 #ifdef ROCKET_DEBUG_INTR
 536         if (IntMask & DELTA_CTS) {      /* CTS change */
 537                 printk(KERN_INFO "CTS change...\n");
 538         }
 539         if (IntMask & DELTA_DSR) {      /* DSR change */
 540                 printk(KERN_INFO "DSR change...\n");
 541         }
 542 #endif
 543 }
 544
 545 /*
 546  *  The top level polling routine.  Repeats every 1/100 HZ (10ms).
 547  */
 548 static void rp_do_poll(unsigned long dummy)
 549 {
 550         CONTROLLER_t *ctlp;
 551         int ctrl, aiop, ch, line, i;
 552         unsigned int xmitmask;
 553         unsigned int CtlMask;
 554         unsigned char AiopMask;
 555         Word_t bit;
 556
 557         /*  Walk through all the boards (ctrl's) */
 558         for (ctrl = 0; ctrl < max_board; ctrl++) {
 559                 if (rcktpt_io_addr[ctrl] <= 0)
 560                         continue;
 561
 562                 /*  Get a ptr to the board's control struct */
 563                 ctlp = sCtlNumToCtlPtr(ctrl);
 564
 565                 /*  Get the interupt status from the board */
 566 #ifdef CONFIG_PCI
 567                 if (ctlp->BusType == isPCI)
 568                         CtlMask = sPCIGetControllerIntStatus(ctlp);
 569                 else
 570 #endif
 571                         CtlMask = sGetControllerIntStatus(ctlp);
 572
 573                 /*  Check if any AIOP read bits are set */
 574                 for (aiop = 0; CtlMask; aiop++) {
 575                         bit = ctlp->AiopIntrBits[aiop];
 576                         if (CtlMask & bit) {
 577                                 CtlMask &= ~bit;
 578                                 AiopMask = sGetAiopIntStatus(ctlp, aiop);
 579
 580                                 /*  Check if any port read bits are set */
 581                                 for (ch = 0; AiopMask;  AiopMask >>= 1, ch++) {
 582                                         if (AiopMask & 1) {
 583
 584                                                 /*  Get the line number (/dev/ttyRx number). */
 585                                                 /*  Read the data from the port. */
 586                                                 line = GetLineNumber(ctrl, aiop, ch);
 587                                                 rp_handle_port(rp_table[line]);
 588                                         }
 589                                 }
 590                         }
 591                 }
 592
 593                 xmitmask = xmit_flags[ctrl];
 594
 595                 /*
 596                  *  xmit_flags contains bit-significant flags, indicating there is data
 597                  *  to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
 598                  *  1, ... (32 total possible).  The variable i has the aiop and ch
 599                  *  numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
 600                  */
 601                 if (xmitmask) {
 602                         for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
 603                                 if (xmitmask & (1 << i)) {
 604                                         aiop = (i & 0x18) >> 3;
 605                                         ch = i & 0x07;
 606                                         line = GetLineNumber(ctrl, aiop, ch);
 607                                         rp_do_transmit(rp_table[line]);
 608                                 }
 609                         }
 610                 }
 611         }
 612
 613         /*
 614          * Reset the timer so we get called at the next clock tick (10ms).
 615          */
 616         if (atomic_read(&rp_num_ports_open))
 617                 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
 618 }
 619
 620 /*
 621  *  Initializes the r_port structure for a port, as well as enabling the port on
 622  *  the board.
 623  *  Inputs:  board, aiop, chan numbers
 624  */
 625 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
 626 {
 627         unsigned rocketMode;
 628         struct r_port *info;
 629         int line;
 630         CONTROLLER_T *ctlp;
 631
 632         /*  Get the next available line number */
 633         line = SetLineNumber(board, aiop, chan);
 634
 635         ctlp = sCtlNumToCtlPtr(board);
 636
 637         /*  Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
 638         info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
 639         if (!info) {
 640                 printk(KERN_INFO "Couldn't allocate info struct for line #%d\n", line);
 641                 return;
 642         }
 643
 644         info->magic = RPORT_MAGIC;
 645         info->line = line;
 646         info->ctlp = ctlp;
 647         info->board = board;
 648         info->aiop = aiop;
 649         info->chan = chan;
 650         info->closing_wait = 3000;
 651         info->close_delay = 50;
 652         init_waitqueue_head(&info->open_wait);
 653         init_waitqueue_head(&info->close_wait);
 654         info->flags &= ~ROCKET_MODE_MASK;
 655         switch (pc104[board][line]) {
 656         case 422:
 657                 info->flags |= ROCKET_MODE_RS422;
 658                 break;
 659         case 485:
 660                 info->flags |= ROCKET_MODE_RS485;
 661                 break;
 662         case 232:
 663         default:
 664                 info->flags |= ROCKET_MODE_RS232;
 665                 break;
 666         }
 667
 668         info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
 669         if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
 670                 printk(KERN_INFO "RocketPort sInitChan(%d, %d, %d) failed!\n", board, aiop, chan);
 671                 kfree(info);
 672                 return;
 673         }
 674
 675         rocketMode = info->flags & ROCKET_MODE_MASK;
 676
 677         if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
 678                 sEnRTSToggle(&info->channel);
 679         else
 680                 sDisRTSToggle(&info->channel);
 681
 682         if (ctlp->boardType == ROCKET_TYPE_PC104) {
 683                 switch (rocketMode) {
 684                 case ROCKET_MODE_RS485:
 685                         sSetInterfaceMode(&info->channel, InterfaceModeRS485);
 686                         break;
 687                 case ROCKET_MODE_RS422:
 688                         sSetInterfaceMode(&info->channel, InterfaceModeRS422);
 689                         break;
 690                 case ROCKET_MODE_RS232:
 691                 default:
 692                         if (info->flags & ROCKET_RTS_TOGGLE)
 693                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
 694                         else
 695                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
 696                         break;
 697                 }
 698         }
 699         spin_lock_init(&info->slock);
 700         mutex_init(&info->write_mtx);
 701         rp_table[line] = info;
 702         if (pci_dev)
 703                 tty_register_device(rocket_driver, line, &pci_dev->dev);
 704 }
 705
 706 /*
 707  *  Configures a rocketport port according to its termio settings.  Called from
 708  *  user mode into the driver (exception handler).  *info CD manipulation is spinlock protected.
 709  */
 710 static void configure_r_port(struct r_port *info,
 711                              struct ktermios *old_termios)
 712 {
 713         unsigned cflag;
 714         unsigned long flags;
 715         unsigned rocketMode;
 716         int bits, baud, divisor;
 717         CHANNEL_t *cp;
 718
 719         if (!info->tty || !info->tty->termios)
 720                 return;
 721         cp = &info->channel;
 722         cflag = info->tty->termios->c_cflag;
 723
 724         /* Byte size and parity */
 725         if ((cflag & CSIZE) == CS8) {
 726                 sSetData8(cp);
 727                 bits = 10;
 728         } else {
 729                 sSetData7(cp);
 730                 bits = 9;
 731         }
 732         if (cflag & CSTOPB) {
 733                 sSetStop2(cp);
 734                 bits++;
 735         } else {
 736                 sSetStop1(cp);
 737         }
 738
 739         if (cflag & PARENB) {
 740                 sEnParity(cp);
 741                 bits++;
 742                 if (cflag & PARODD) {
 743                         sSetOddParity(cp);
 744                 } else {
 745                         sSetEvenParity(cp);
 746                 }
 747         } else {
 748                 sDisParity(cp);
 749         }
 750
 751         /* baud rate */
 752         baud = tty_get_baud_rate(info->tty);
 753         if (!baud)
 754                 baud = 9600;
 755         divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
 756         if ((divisor >= 8192 || divisor < 0) && old_termios) {
 757                 info->tty->termios->c_cflag &= ~CBAUD;
 758                 info->tty->termios->c_cflag |=
 759                     (old_termios->c_cflag & CBAUD);
 760                 baud = tty_get_baud_rate(info->tty);
 761                 if (!baud)
 762                         baud = 9600;
 763                 divisor = (rp_baud_base[info->board] / baud) - 1;
 764         }
 765         if (divisor >= 8192 || divisor < 0) {
 766                 baud = 9600;
 767                 divisor = (rp_baud_base[info->board] / baud) - 1;
 768         }
 769         info->cps = baud / bits;
 770         sSetBaud(cp, divisor);
 771
 772         if (cflag & CRTSCTS) {
 773                 info->intmask |= DELTA_CTS;
 774                 sEnCTSFlowCtl(cp);
 775         } else {
 776                 info->intmask &= ~DELTA_CTS;
 777                 sDisCTSFlowCtl(cp);
 778         }
 779         if (cflag & CLOCAL) {
 780                 info->intmask &= ~DELTA_CD;
 781         } else {
 782                 spin_lock_irqsave(&info->slock, flags);
 783                 if (sGetChanStatus(cp) & CD_ACT)
 784                         info->cd_status = 1;
 785                 else
 786                         info->cd_status = 0;
 787                 info->intmask |= DELTA_CD;
 788                 spin_unlock_irqrestore(&info->slock, flags);
 789         }
 790
 791         /*
 792          * Handle software flow control in the board
 793          */
 794 #ifdef ROCKET_SOFT_FLOW
 795         if (I_IXON(info->tty)) {
 796                 sEnTxSoftFlowCtl(cp);
 797                 if (I_IXANY(info->tty)) {
 798                         sEnIXANY(cp);
 799                 } else {
 800                         sDisIXANY(cp);
 801                 }
 802                 sSetTxXONChar(cp, START_CHAR(info->tty));
 803                 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
 804         } else {
 805                 sDisTxSoftFlowCtl(cp);
 806                 sDisIXANY(cp);
 807                 sClrTxXOFF(cp);
 808         }
 809 #endif
 810
 811         /*
 812          * Set up ignore/read mask words
 813          */
 814         info->read_status_mask = STMRCVROVRH | 0xFF;
 815         if (I_INPCK(info->tty))
 816                 info->read_status_mask |= STMFRAMEH | STMPARITYH;
 817         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
 818                 info->read_status_mask |= STMBREAKH;
 819
 820         /*
 821          * Characters to ignore
 822          */
 823         info->ignore_status_mask = 0;
 824         if (I_IGNPAR(info->tty))
 825                 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
 826         if (I_IGNBRK(info->tty)) {
 827                 info->ignore_status_mask |= STMBREAKH;
 828                 /*
 829                  * If we're ignoring parity and break indicators,
 830                  * ignore overruns too.  (For real raw support).
 831                  */
 832                 if (I_IGNPAR(info->tty))
 833                         info->ignore_status_mask |= STMRCVROVRH;
 834         }
 835
 836         rocketMode = info->flags & ROCKET_MODE_MASK;
 837
 838         if ((info->flags & ROCKET_RTS_TOGGLE)
 839             || (rocketMode == ROCKET_MODE_RS485))
 840                 sEnRTSToggle(cp);
 841         else
 842                 sDisRTSToggle(cp);
 843
 844         sSetRTS(&info->channel);
 845
 846         if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
 847                 switch (rocketMode) {
 848                 case ROCKET_MODE_RS485:
 849                         sSetInterfaceMode(cp, InterfaceModeRS485);
 850                         break;
 851                 case ROCKET_MODE_RS422:
 852                         sSetInterfaceMode(cp, InterfaceModeRS422);
 853                         break;
 854                 case ROCKET_MODE_RS232:
 855                 default:
 856                         if (info->flags & ROCKET_RTS_TOGGLE)
 857                                 sSetInterfaceMode(cp, InterfaceModeRS232T);
 858                         else
 859                                 sSetInterfaceMode(cp, InterfaceModeRS232);
 860                         break;
 861                 }
 862         }
 863 }
 864
 865 /*  info->count is considered critical, protected by spinlocks.  */
 866 static int block_til_ready(struct tty_struct *tty, struct file *filp,
 867                            struct r_port *info)
 868 {
 869         DECLARE_WAITQUEUE(wait, current);
 870         int retval;
 871         int do_clocal = 0, extra_count = 0;
 872         unsigned long flags;
 873
 874         /*
 875          * If the device is in the middle of being closed, then block
 876          * until it's done, and then try again.
 877          */
 878         if (tty_hung_up_p(filp))
 879                 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
 880         if (info->flags & ROCKET_CLOSING) {
 881                 interruptible_sleep_on(&info->close_wait);
 882                 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
 883         }
 884
 885         /*
 886          * If non-blocking mode is set, or the port is not enabled,
 887          * then make the check up front and then exit.
 888          */
 889         if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
 890                 info->flags |= ROCKET_NORMAL_ACTIVE;
 891                 return 0;
 892         }
 893         if (tty->termios->c_cflag & CLOCAL)
 894                 do_clocal = 1;
 895
 896         /*
 897          * Block waiting for the carrier detect and the line to become free.  While we are in
 898          * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
 899          * We restore it upon exit, either normal or abnormal.
 900          */
 901         retval = 0;
 902         add_wait_queue(&info->open_wait, &wait);
 903 #ifdef ROCKET_DEBUG_OPEN
 904         printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
 905 #endif
 906         spin_lock_irqsave(&info->slock, flags);
 907
 908 #ifdef ROCKET_DISABLE_SIMUSAGE
 909         info->flags |= ROCKET_NORMAL_ACTIVE;
 910 #else
 911         if (!tty_hung_up_p(filp)) {
 912                 extra_count = 1;
 913                 info->count--;
 914         }
 915 #endif
 916         info->blocked_open++;
 917
 918         spin_unlock_irqrestore(&info->slock, flags);
 919
 920         while (1) {
 921                 if (tty->termios->c_cflag & CBAUD) {
 922                         sSetDTR(&info->channel);
 923                         sSetRTS(&info->channel);
 924                 }
 925                 set_current_state(TASK_INTERRUPTIBLE);
 926                 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
 927                         if (info->flags & ROCKET_HUP_NOTIFY)
 928                                 retval = -EAGAIN;
 929                         else
 930                                 retval = -ERESTARTSYS;
 931                         break;
 932                 }
 933                 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
 934                         break;
 935                 if (signal_pending(current)) {
 936                         retval = -ERESTARTSYS;
 937                         break;
 938                 }
 939 #ifdef ROCKET_DEBUG_OPEN
 940                 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
 941                      info->line, info->count, info->flags);
 942 #endif
 943                 schedule();     /*  Don't hold spinlock here, will hang PC */
 944         }
 945         __set_current_state(TASK_RUNNING);
 946         remove_wait_queue(&info->open_wait, &wait);
 947
 948         spin_lock_irqsave(&info->slock, flags);
 949
 950         if (extra_count)
 951                 info->count++;
 952         info->blocked_open--;
 953
 954         spin_unlock_irqrestore(&info->slock, flags);
 955
 956 #ifdef ROCKET_DEBUG_OPEN
 957         printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
 958                info->line, info->count);
 959 #endif
 960         if (retval)
 961                 return retval;
 962         info->flags |= ROCKET_NORMAL_ACTIVE;
 963         return 0;
 964 }
 965
 966 /*
 967  *  Exception handler that opens a serial port.  Creates xmit_buf storage, fills in
 968  *  port's r_port struct.  Initializes the port hardware.
 969  */
 970 static int rp_open(struct tty_struct *tty, struct file *filp)
 971 {
 972         struct r_port *info;
 973         int line = 0, retval;
 974         CHANNEL_t *cp;
 975         unsigned long page;
 976
 977         line = TTY_GET_LINE(tty);
 978         if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
 979                 return -ENXIO;
 980
 981         page = __get_free_page(GFP_KERNEL);
 982         if (!page)
 983                 return -ENOMEM;
 984
 985         if (info->flags & ROCKET_CLOSING) {
 986                 interruptible_sleep_on(&info->close_wait);
 987                 free_page(page);
 988                 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
 989         }
 990
 991         /*
 992          * We must not sleep from here until the port is marked fully in use.
 993          */
 994         if (info->xmit_buf)
 995                 free_page(page);
 996         else
 997                 info->xmit_buf = (unsigned char *) page;
 998
 999         tty->driver_data = info;
1000         info->tty = tty;
1001
1002         if (info->count++ == 0) {
1003                 atomic_inc(&rp_num_ports_open);
1004
1005 #ifdef ROCKET_DEBUG_OPEN
1006                 printk(KERN_INFO "rocket mod++ = %d...", atomic_read(&rp_num_ports_open));
1007 #endif
1008         }
1009 #ifdef ROCKET_DEBUG_OPEN
1010         printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
1011 #endif
1012
1013         /*
1014          * Info->count is now 1; so it's safe to sleep now.
1015          */
1016         if ((info->flags & ROCKET_INITIALIZED) == 0) {
1017                 cp = &info->channel;
1018                 sSetRxTrigger(cp, TRIG_1);
1019                 if (sGetChanStatus(cp) & CD_ACT)
1020                         info->cd_status = 1;
1021                 else
1022                         info->cd_status = 0;
1023                 sDisRxStatusMode(cp);
1024                 sFlushRxFIFO(cp);
1025                 sFlushTxFIFO(cp);
1026
1027                 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1028                 sSetRxTrigger(cp, TRIG_1);
1029
1030                 sGetChanStatus(cp);
1031                 sDisRxStatusMode(cp);
1032                 sClrTxXOFF(cp);
1033
1034                 sDisCTSFlowCtl(cp);
1035                 sDisTxSoftFlowCtl(cp);
1036
1037                 sEnRxFIFO(cp);
1038                 sEnTransmit(cp);
1039
1040                 info->flags |= ROCKET_INITIALIZED;
1041
1042                 /*
1043                  * Set up the tty->alt_speed kludge
1044                  */
1045                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1046                         info->tty->alt_speed = 57600;
1047                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1048                         info->tty->alt_speed = 115200;
1049                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1050                         info->tty->alt_speed = 230400;
1051                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1052                         info->tty->alt_speed = 460800;
1053
1054                 configure_r_port(info, NULL);
1055                 if (tty->termios->c_cflag & CBAUD) {
1056                         sSetDTR(cp);
1057                         sSetRTS(cp);
1058                 }
1059         }
1060         /*  Starts (or resets) the maint polling loop */
1061         mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1062
1063         retval = block_til_ready(tty, filp, info);
1064         if (retval) {
1065 #ifdef ROCKET_DEBUG_OPEN
1066                 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1067 #endif
1068                 return retval;
1069         }
1070         return 0;
1071 }
1072
1073 /*
1074  *  Exception handler that closes a serial port. info->count is considered critical.
1075  */
1076 static void rp_close(struct tty_struct *tty, struct file *filp)
1077 {
1078         struct r_port *info = (struct r_port *) tty->driver_data;
1079         unsigned long flags;
1080         int timeout;
1081         CHANNEL_t *cp;
1082
1083         if (rocket_paranoia_check(info, "rp_close"))
1084                 return;
1085
1086 #ifdef ROCKET_DEBUG_OPEN
1087         printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1088 #endif
1089
1090         if (tty_hung_up_p(filp))
1091                 return;
1092         spin_lock_irqsave(&info->slock, flags);
1093
1094         if ((tty->count == 1) && (info->count != 1)) {
1095                 /*
1096                  * Uh, oh.  tty->count is 1, which means that the tty
1097                  * structure will be freed.  Info->count should always
1098                  * be one in these conditions.  If it's greater than
1099                  * one, we've got real problems, since it means the
1100                  * serial port won't be shutdown.
1101                  */
1102                 printk(KERN_INFO "rp_close: bad serial port count; tty->count is 1, "
1103                        "info->count is %d\n", info->count);
1104                 info->count = 1;
1105         }
1106         if (--info->count < 0) {
1107                 printk(KERN_INFO "rp_close: bad serial port count for ttyR%d: %d\n",
1108                        info->line, info->count);
1109                 info->count = 0;
1110         }
1111         if (info->count) {
1112                 spin_unlock_irqrestore(&info->slock, flags);
1113                 return;
1114         }
1115         info->flags |= ROCKET_CLOSING;
1116         spin_unlock_irqrestore(&info->slock, flags);
1117
1118         cp = &info->channel;
1119
1120         /*
1121          * Notify the line discpline to only process XON/XOFF characters
1122          */
1123         tty->closing = 1;
1124
1125         /*
1126          * If transmission was throttled by the application request,
1127          * just flush the xmit buffer.
1128          */
1129         if (tty->flow_stopped)
1130                 rp_flush_buffer(tty);
1131
1132         /*
1133          * Wait for the transmit buffer to clear
1134          */
1135         if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1136                 tty_wait_until_sent(tty, info->closing_wait);
1137         /*
1138          * Before we drop DTR, make sure the UART transmitter
1139          * has completely drained; this is especially
1140          * important if there is a transmit FIFO!
1141          */
1142         timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1143         if (timeout == 0)
1144                 timeout = 1;
1145         rp_wait_until_sent(tty, timeout);
1146         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1147
1148         sDisTransmit(cp);
1149         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1150         sDisCTSFlowCtl(cp);
1151         sDisTxSoftFlowCtl(cp);
1152         sClrTxXOFF(cp);
1153         sFlushRxFIFO(cp);
1154         sFlushTxFIFO(cp);
1155         sClrRTS(cp);
1156         if (C_HUPCL(tty))
1157                 sClrDTR(cp);
1158
1159         if (TTY_DRIVER_FLUSH_BUFFER_EXISTS(tty))
1160                 TTY_DRIVER_FLUSH_BUFFER(tty);
1161
1162         tty_ldisc_flush(tty);
1163
1164         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1165
1166         if (info->blocked_open) {
1167                 if (info->close_delay) {
1168                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
1169                 }
1170                 wake_up_interruptible(&info->open_wait);
1171         } else {
1172                 if (info->xmit_buf) {
1173                         free_page((unsigned long) info->xmit_buf);
1174                         info->xmit_buf = NULL;
1175                 }
1176         }
1177         info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1178         tty->closing = 0;
1179         wake_up_interruptible(&info->close_wait);
1180         atomic_dec(&rp_num_ports_open);
1181
1182 #ifdef ROCKET_DEBUG_OPEN
1183         printk(KERN_INFO "rocket mod-- = %d...", atomic_read(&rp_num_ports_open));
1184         printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1185 #endif
1186
1187 }
1188
1189 static void rp_set_termios(struct tty_struct *tty,
1190                            struct ktermios *old_termios)
1191 {
1192         struct r_port *info = (struct r_port *) tty->driver_data;
1193         CHANNEL_t *cp;
1194         unsigned cflag;
1195
1196         if (rocket_paranoia_check(info, "rp_set_termios"))
1197                 return;
1198
1199         cflag = tty->termios->c_cflag;
1200
1201         if (cflag == old_termios->c_cflag)
1202                 return;
1203
1204         /*
1205          * This driver doesn't support CS5 or CS6
1206          */
1207         if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1208                 tty->termios->c_cflag =
1209                     ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1210
1211         configure_r_port(info, old_termios);
1212
1213         cp = &info->channel;
1214
1215         /* Handle transition to B0 status */
1216         if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1217                 sClrDTR(cp);
1218                 sClrRTS(cp);
1219         }
1220
1221         /* Handle transition away from B0 status */
1222         if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1223                 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1224                         sSetRTS(cp);
1225                 sSetDTR(cp);
1226         }
1227
1228         if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1229                 tty->hw_stopped = 0;
1230                 rp_start(tty);
1231         }
1232 }
1233
1234 static void rp_break(struct tty_struct *tty, int break_state)
1235 {
1236         struct r_port *info = (struct r_port *) tty->driver_data;
1237         unsigned long flags;
1238
1239         if (rocket_paranoia_check(info, "rp_break"))
1240                 return;
1241
1242         spin_lock_irqsave(&info->slock, flags);
1243         if (break_state == -1)
1244                 sSendBreak(&info->channel);
1245         else
1246                 sClrBreak(&info->channel);
1247         spin_unlock_irqrestore(&info->slock, flags);
1248 }
1249
1250 /*
1251  * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1252  * the UPCI boards was added, it was decided to make this a function because
1253  * the macro was getting too complicated. All cases except the first one
1254  * (UPCIRingInd) are taken directly from the original macro.
1255  */
1256 static int sGetChanRI(CHANNEL_T * ChP)
1257 {
1258         CONTROLLER_t *CtlP = ChP->CtlP;
1259         int ChanNum = ChP->ChanNum;
1260         int RingInd = 0;
1261
1262         if (CtlP->UPCIRingInd)
1263                 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1264         else if (CtlP->AltChanRingIndicator)
1265                 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1266         else if (CtlP->boardType == ROCKET_TYPE_PC104)
1267                 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1268
1269         return RingInd;
1270 }
1271
1272 /********************************************************************************************/
1273 /*  Here are the routines used by rp_ioctl.  These are all called from exception handlers.  */
1274
1275 /*
1276  *  Returns the state of the serial modem control lines.  These next 2 functions
1277  *  are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1278  */
1279 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1280 {
1281         struct r_port *info = (struct r_port *)tty->driver_data;
1282         unsigned int control, result, ChanStatus;
1283
1284         ChanStatus = sGetChanStatusLo(&info->channel);
1285         control = info->channel.TxControl[3];
1286         result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1287                 ((control & SET_DTR) ?  TIOCM_DTR : 0) |
1288                 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1289                 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1290                 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1291                 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1292
1293         return result;
1294 }
1295
1296 /*
1297  *  Sets the modem control lines
1298  */
1299 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1300                     unsigned int set, unsigned int clear)
1301 {
1302         struct r_port *info = (struct r_port *)tty->driver_data;
1303
1304         if (set & TIOCM_RTS)
1305                 info->channel.TxControl[3] |= SET_RTS;
1306         if (set & TIOCM_DTR)
1307                 info->channel.TxControl[3] |= SET_DTR;
1308         if (clear & TIOCM_RTS)
1309                 info->channel.TxControl[3] &= ~SET_RTS;
1310         if (clear & TIOCM_DTR)
1311                 info->channel.TxControl[3] &= ~SET_DTR;
1312
1313         sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0]));
1314         return 0;
1315 }
1316
1317 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1318 {
1319         struct rocket_config tmp;
1320
1321         if (!retinfo)
1322                 return -EFAULT;
1323         memset(&tmp, 0, sizeof (tmp));
1324         tmp.line = info->line;
1325         tmp.flags = info->flags;
1326         tmp.close_delay = info->close_delay;
1327         tmp.closing_wait = info->closing_wait;
1328         tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1329
1330         if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1331                 return -EFAULT;
1332         return 0;
1333 }
1334
1335 static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1336 {
1337         struct rocket_config new_serial;
1338
1339         if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1340                 return -EFAULT;
1341
1342         if (!capable(CAP_SYS_ADMIN))
1343         {
1344                 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1345                         return -EPERM;
1346                 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1347                 configure_r_port(info, NULL);
1348                 return 0;
1349         }
1350
1351         info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1352         info->close_delay = new_serial.close_delay;
1353         info->closing_wait = new_serial.closing_wait;
1354
1355         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1356                 info->tty->alt_speed = 57600;
1357         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1358                 info->tty->alt_speed = 115200;
1359         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1360                 info->tty->alt_speed = 230400;
1361         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1362                 info->tty->alt_speed = 460800;
1363
1364         configure_r_port(info, NULL);
1365         return 0;
1366 }
1367
1368 /*
1369  *  This function fills in a rocket_ports struct with information
1370  *  about what boards/ports are in the system.  This info is passed
1371  *  to user space.  See setrocket.c where the info is used to create
1372  *  the /dev/ttyRx ports.
1373  */
1374 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1375 {
1376         struct rocket_ports tmp;
1377         int board;
1378
1379         if (!retports)
1380                 return -EFAULT;
1381         memset(&tmp, 0, sizeof (tmp));
1382         tmp.tty_major = rocket_driver->major;
1383
1384         for (board = 0; board < 4; board++) {
1385                 tmp.rocketModel[board].model = rocketModel[board].model;
1386                 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1387                 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1388                 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1389                 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1390         }
1391         if (copy_to_user(retports, &tmp, sizeof (*retports)))
1392                 return -EFAULT;
1393         return 0;
1394 }
1395
1396 static int reset_rm2(struct r_port *info, void __user *arg)
1397 {
1398         int reset;
1399
1400         if (copy_from_user(&reset, arg, sizeof (int)))
1401                 return -EFAULT;
1402         if (reset)
1403                 reset = 1;
1404
1405         if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1406             rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1407                 return -EINVAL;
1408
1409         if (info->ctlp->BusType == isISA)
1410                 sModemReset(info->ctlp, info->chan, reset);
1411         else
1412                 sPCIModemReset(info->ctlp, info->chan, reset);
1413
1414         return 0;
1415 }
1416
1417 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1418 {
1419         if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1420                 return -EFAULT;
1421         return 0;
1422 }
1423
1424 /*  IOCTL call handler into the driver */
1425 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1426                     unsigned int cmd, unsigned long arg)
1427 {
1428         struct r_port *info = (struct r_port *) tty->driver_data;
1429         void __user *argp = (void __user *)arg;
1430
1431         if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1432                 return -ENXIO;
1433
1434         switch (cmd) {
1435         case RCKP_GET_STRUCT:
1436                 if (copy_to_user(argp, info, sizeof (struct r_port)))
1437                         return -EFAULT;
1438                 return 0;
1439         case RCKP_GET_CONFIG:
1440                 return get_config(info, argp);
1441         case RCKP_SET_CONFIG:
1442                 return set_config(info, argp);
1443         case RCKP_GET_PORTS:
1444                 return get_ports(info, argp);
1445         case RCKP_RESET_RM2:
1446                 return reset_rm2(info, argp);
1447         case RCKP_GET_VERSION:
1448                 return get_version(info, argp);
1449         default:
1450                 return -ENOIOCTLCMD;
1451         }
1452         return 0;
1453 }
1454
1455 static void rp_send_xchar(struct tty_struct *tty, char ch)
1456 {
1457         struct r_port *info = (struct r_port *) tty->driver_data;
1458         CHANNEL_t *cp;
1459
1460         if (rocket_paranoia_check(info, "rp_send_xchar"))
1461                 return;
1462
1463         cp = &info->channel;
1464         if (sGetTxCnt(cp))
1465                 sWriteTxPrioByte(cp, ch);
1466         else
1467                 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1468 }
1469
1470 static void rp_throttle(struct tty_struct *tty)
1471 {
1472         struct r_port *info = (struct r_port *) tty->driver_data;
1473         CHANNEL_t *cp;
1474
1475 #ifdef ROCKET_DEBUG_THROTTLE
1476         printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1477                tty->ldisc.chars_in_buffer(tty));
1478 #endif
1479
1480         if (rocket_paranoia_check(info, "rp_throttle"))
1481                 return;
1482
1483         cp = &info->channel;
1484         if (I_IXOFF(tty))
1485                 rp_send_xchar(tty, STOP_CHAR(tty));
1486
1487         sClrRTS(&info->channel);
1488 }
1489
1490 static void rp_unthrottle(struct tty_struct *tty)
1491 {
1492         struct r_port *info = (struct r_port *) tty->driver_data;
1493         CHANNEL_t *cp;
1494 #ifdef ROCKET_DEBUG_THROTTLE
1495         printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1496                tty->ldisc.chars_in_buffer(tty));
1497 #endif
1498
1499         if (rocket_paranoia_check(info, "rp_throttle"))
1500                 return;
1501
1502         cp = &info->channel;
1503         if (I_IXOFF(tty))
1504                 rp_send_xchar(tty, START_CHAR(tty));
1505
1506         sSetRTS(&info->channel);
1507 }
1508
1509 /*
1510  * ------------------------------------------------------------
1511  * rp_stop() and rp_start()
1512  *
1513  * This routines are called before setting or resetting tty->stopped.
1514  * They enable or disable transmitter interrupts, as necessary.
1515  * ------------------------------------------------------------
1516  */
1517 static void rp_stop(struct tty_struct *tty)
1518 {
1519         struct r_port *info = (struct r_port *) tty->driver_data;
1520
1521 #ifdef ROCKET_DEBUG_FLOW
1522         printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1523                info->xmit_cnt, info->xmit_fifo_room);
1524 #endif
1525
1526         if (rocket_paranoia_check(info, "rp_stop"))
1527                 return;
1528
1529         if (sGetTxCnt(&info->channel))
1530                 sDisTransmit(&info->channel);
1531 }
1532
1533 static void rp_start(struct tty_struct *tty)
1534 {
1535         struct r_port *info = (struct r_port *) tty->driver_data;
1536
1537 #ifdef ROCKET_DEBUG_FLOW
1538         printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1539                info->xmit_cnt, info->xmit_fifo_room);
1540 #endif
1541
1542         if (rocket_paranoia_check(info, "rp_stop"))
1543                 return;
1544
1545         sEnTransmit(&info->channel);
1546         set_bit((info->aiop * 8) + info->chan,
1547                 (void *) &xmit_flags[info->board]);
1548 }
1549
1550 /*
1551  * rp_wait_until_sent() --- wait until the transmitter is empty
1552  */
1553 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1554 {
1555         struct r_port *info = (struct r_port *) tty->driver_data;
1556         CHANNEL_t *cp;
1557         unsigned long orig_jiffies;
1558         int check_time, exit_time;
1559         int txcnt;
1560
1561         if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1562                 return;
1563
1564         cp = &info->channel;
1565
1566         orig_jiffies = jiffies;
1567 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1568         printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...", timeout,
1569                jiffies);
1570         printk(KERN_INFO "cps=%d...", info->cps);
1571 #endif
1572         while (1) {
1573                 txcnt = sGetTxCnt(cp);
1574                 if (!txcnt) {
1575                         if (sGetChanStatusLo(cp) & TXSHRMT)
1576                                 break;
1577                         check_time = (HZ / info->cps) / 5;
1578                 } else {
1579                         check_time = HZ * txcnt / info->cps;
1580                 }
1581                 if (timeout) {
1582                         exit_time = orig_jiffies + timeout - jiffies;
1583                         if (exit_time <= 0)
1584                                 break;
1585                         if (exit_time < check_time)
1586                                 check_time = exit_time;
1587                 }
1588                 if (check_time == 0)
1589                         check_time = 1;
1590 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1591                 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...", txcnt, jiffies, check_time);
1592 #endif
1593                 msleep_interruptible(jiffies_to_msecs(check_time));
1594                 if (signal_pending(current))
1595                         break;
1596         }
1597         __set_current_state(TASK_RUNNING);
1598 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1599         printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1600 #endif
1601 }
1602
1603 /*
1604  * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1605  */
1606 static void rp_hangup(struct tty_struct *tty)
1607 {
1608         CHANNEL_t *cp;
1609         struct r_port *info = (struct r_port *) tty->driver_data;
1610
1611         if (rocket_paranoia_check(info, "rp_hangup"))
1612                 return;
1613
1614 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1615         printk(KERN_INFO "rp_hangup of ttyR%d...", info->line);
1616 #endif
1617         rp_flush_buffer(tty);
1618         if (info->flags & ROCKET_CLOSING)
1619                 return;
1620         if (info->count)
1621                 atomic_dec(&rp_num_ports_open);
1622         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1623
1624         info->count = 0;
1625         info->flags &= ~ROCKET_NORMAL_ACTIVE;
1626         info->tty = NULL;
1627
1628         cp = &info->channel;
1629         sDisRxFIFO(cp);
1630         sDisTransmit(cp);
1631         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1632         sDisCTSFlowCtl(cp);
1633         sDisTxSoftFlowCtl(cp);
1634         sClrTxXOFF(cp);
1635         info->flags &= ~ROCKET_INITIALIZED;
1636
1637         wake_up_interruptible(&info->open_wait);
1638 }
1639
1640 /*
1641  *  Exception handler - write char routine.  The RocketPort driver uses a
1642  *  double-buffering strategy, with the twist that if the in-memory CPU
1643  *  buffer is empty, and there's space in the transmit FIFO, the
1644  *  writing routines will write directly to transmit FIFO.
1645  *  Write buffer and counters protected by spinlocks
1646  */
1647 static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1648 {
1649         struct r_port *info = (struct r_port *) tty->driver_data;
1650         CHANNEL_t *cp;
1651         unsigned long flags;
1652
1653         if (rocket_paranoia_check(info, "rp_put_char"))
1654                 return;
1655
1656         /*
1657          * Grab the port write mutex, locking out other processes that try to
1658          * write to this port
1659          */
1660         mutex_lock(&info->write_mtx);
1661
1662 #ifdef ROCKET_DEBUG_WRITE
1663         printk(KERN_INFO "rp_put_char %c...", ch);
1664 #endif
1665
1666         spin_lock_irqsave(&info->slock, flags);
1667         cp = &info->channel;
1668
1669         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1670                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1671
1672         if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1673                 info->xmit_buf[info->xmit_head++] = ch;
1674                 info->xmit_head &= XMIT_BUF_SIZE - 1;
1675                 info->xmit_cnt++;
1676                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1677         } else {
1678                 sOutB(sGetTxRxDataIO(cp), ch);
1679                 info->xmit_fifo_room--;
1680         }
1681         spin_unlock_irqrestore(&info->slock, flags);
1682         mutex_unlock(&info->write_mtx);
1683 }
1684
1685 /*
1686  *  Exception handler - write routine, called when user app writes to the device.
1687  *  A per port write mutex is used to protect from another process writing to
1688  *  this port at the same time.  This other process could be running on the other CPU
1689  *  or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1690  *  Spinlocks protect the info xmit members.
1691  */
1692 static int rp_write(struct tty_struct *tty,
1693                     const unsigned char *buf, int count)
1694 {
1695         struct r_port *info = (struct r_port *) tty->driver_data;
1696         CHANNEL_t *cp;
1697         const unsigned char *b;
1698         int c, retval = 0;
1699         unsigned long flags;
1700
1701         if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1702                 return 0;
1703
1704         if (mutex_lock_interruptible(&info->write_mtx))
1705                 return -ERESTARTSYS;
1706
1707 #ifdef ROCKET_DEBUG_WRITE
1708         printk(KERN_INFO "rp_write %d chars...", count);
1709 #endif
1710         cp = &info->channel;
1711
1712         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1713                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1714
1715         /*
1716          *  If the write queue for the port is empty, and there is FIFO space, stuff bytes
1717          *  into FIFO.  Use the write queue for temp storage.
1718          */
1719         if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1720                 c = min(count, info->xmit_fifo_room);
1721                 b = buf;
1722
1723                 /*  Push data into FIFO, 2 bytes at a time */
1724                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1725
1726                 /*  If there is a byte remaining, write it */
1727                 if (c & 1)
1728                         sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1729
1730                 retval += c;
1731                 buf += c;
1732                 count -= c;
1733
1734                 spin_lock_irqsave(&info->slock, flags);
1735                 info->xmit_fifo_room -= c;
1736                 spin_unlock_irqrestore(&info->slock, flags);
1737         }
1738
1739         /* If count is zero, we wrote it all and are done */
1740         if (!count)
1741                 goto end;
1742
1743         /*  Write remaining data into the port's xmit_buf */
1744         while (1) {
1745                 if (info->tty == 0)     /*   Seemingly obligatory check... */
1746                         goto end;
1747
1748                 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1749                 if (c <= 0)
1750                         break;
1751
1752                 b = buf;
1753                 memcpy(info->xmit_buf + info->xmit_head, b, c);
1754
1755                 spin_lock_irqsave(&info->slock, flags);
1756                 info->xmit_head =
1757                     (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1758                 info->xmit_cnt += c;
1759                 spin_unlock_irqrestore(&info->slock, flags);
1760
1761                 buf += c;
1762                 count -= c;
1763                 retval += c;
1764         }
1765
1766         if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1767                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1768
1769 end:
1770         if (info->xmit_cnt < WAKEUP_CHARS) {
1771                 tty_wakeup(tty);
1772 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1773                 wake_up_interruptible(&tty->poll_wait);
1774 #endif
1775         }
1776         mutex_unlock(&info->write_mtx);
1777         return retval;
1778 }
1779
1780 /*
1781  * Return the number of characters that can be sent.  We estimate
1782  * only using the in-memory transmit buffer only, and ignore the
1783  * potential space in the transmit FIFO.
1784  */
1785 static int rp_write_room(struct tty_struct *tty)
1786 {
1787         struct r_port *info = (struct r_port *) tty->driver_data;
1788         int ret;
1789
1790         if (rocket_paranoia_check(info, "rp_write_room"))
1791                 return 0;
1792
1793         ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1794         if (ret < 0)
1795                 ret = 0;
1796 #ifdef ROCKET_DEBUG_WRITE
1797         printk(KERN_INFO "rp_write_room returns %d...", ret);
1798 #endif
1799         return ret;
1800 }
1801
1802 /*
1803  * Return the number of characters in the buffer.  Again, this only
1804  * counts those characters in the in-memory transmit buffer.
1805  */
1806 static int rp_chars_in_buffer(struct tty_struct *tty)
1807 {
1808         struct r_port *info = (struct r_port *) tty->driver_data;
1809         CHANNEL_t *cp;
1810
1811         if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1812                 return 0;
1813
1814         cp = &info->channel;
1815
1816 #ifdef ROCKET_DEBUG_WRITE
1817         printk(KERN_INFO "rp_chars_in_buffer returns %d...", info->xmit_cnt);
1818 #endif
1819         return info->xmit_cnt;
1820 }
1821
1822 /*
1823  *  Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1824  *  r_port struct for the port.  Note that spinlock are used to protect info members,
1825  *  do not call this function if the spinlock is already held.
1826  */
1827 static void rp_flush_buffer(struct tty_struct *tty)
1828 {
1829         struct r_port *info = (struct r_port *) tty->driver_data;
1830         CHANNEL_t *cp;
1831         unsigned long flags;
1832
1833         if (rocket_paranoia_check(info, "rp_flush_buffer"))
1834                 return;
1835
1836         spin_lock_irqsave(&info->slock, flags);
1837         info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1838         spin_unlock_irqrestore(&info->slock, flags);
1839
1840 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1841         wake_up_interruptible(&tty->poll_wait);
1842 #endif
1843         tty_wakeup(tty);
1844
1845         cp = &info->channel;
1846         sFlushTxFIFO(cp);
1847 }
1848
1849 #ifdef CONFIG_PCI
1850
1851 static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1852         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1853         { }
1854 };
1855 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1856
1857 /*
1858  *  Called when a PCI card is found.  Retrieves and stores model information,
1859  *  init's aiopic and serial port hardware.
1860  *  Inputs:  i is the board number (0-n)
1861  */
1862 static __init int register_PCI(int i, struct pci_dev *dev)
1863 {
1864         int num_aiops, aiop, max_num_aiops, num_chan, chan;
1865         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1866         char *str, *board_type;
1867         CONTROLLER_t *ctlp;
1868
1869         int fast_clock = 0;
1870         int altChanRingIndicator = 0;
1871         int ports_per_aiop = 8;
1872         int ret;
1873         unsigned int class_rev;
1874         WordIO_t ConfigIO = 0;
1875         ByteIO_t UPCIRingInd = 0;
1876
1877         if (!dev || pci_enable_device(dev))
1878                 return 0;
1879
1880         rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1881         ret = pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1882
1883         if (ret) {
1884                 printk(KERN_INFO "  Error during register_PCI(), unable to read config dword \n");
1885                 return 0;
1886         }
1887
1888         rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1889         rocketModel[i].loadrm2 = 0;
1890         rocketModel[i].startingPortNumber = nextLineNumber;
1891
1892         /*  Depending on the model, set up some config variables */
1893         switch (dev->device) {
1894         case PCI_DEVICE_ID_RP4QUAD:
1895                 str = "Quadcable";
1896                 max_num_aiops = 1;
1897                 ports_per_aiop = 4;
1898                 rocketModel[i].model = MODEL_RP4QUAD;
1899                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1900                 rocketModel[i].numPorts = 4;
1901                 break;
1902         case PCI_DEVICE_ID_RP8OCTA:
1903                 str = "Octacable";
1904                 max_num_aiops = 1;
1905                 rocketModel[i].model = MODEL_RP8OCTA;
1906                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1907                 rocketModel[i].numPorts = 8;
1908                 break;
1909         case PCI_DEVICE_ID_URP8OCTA:
1910                 str = "Octacable";
1911                 max_num_aiops = 1;
1912                 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1913                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1914                 rocketModel[i].numPorts = 8;
1915                 break;
1916         case PCI_DEVICE_ID_RP8INTF:
1917                 str = "8";
1918                 max_num_aiops = 1;
1919                 rocketModel[i].model = MODEL_RP8INTF;
1920                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1921                 rocketModel[i].numPorts = 8;
1922                 break;
1923         case PCI_DEVICE_ID_URP8INTF:
1924                 str = "8";
1925                 max_num_aiops = 1;
1926                 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1927                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1928                 rocketModel[i].numPorts = 8;
1929                 break;
1930         case PCI_DEVICE_ID_RP8J:
1931                 str = "8J";
1932                 max_num_aiops = 1;
1933                 rocketModel[i].model = MODEL_RP8J;
1934                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1935                 rocketModel[i].numPorts = 8;
1936                 break;
1937         case PCI_DEVICE_ID_RP4J:
1938                 str = "4J";
1939                 max_num_aiops = 1;
1940                 ports_per_aiop = 4;
1941                 rocketModel[i].model = MODEL_RP4J;
1942                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1943                 rocketModel[i].numPorts = 4;
1944                 break;
1945         case PCI_DEVICE_ID_RP8SNI:
1946                 str = "8 (DB78 Custom)";
1947                 max_num_aiops = 1;
1948                 rocketModel[i].model = MODEL_RP8SNI;
1949                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1950                 rocketModel[i].numPorts = 8;
1951                 break;
1952         case PCI_DEVICE_ID_RP16SNI:
1953                 str = "16 (DB78 Custom)";
1954                 max_num_aiops = 2;
1955                 rocketModel[i].model = MODEL_RP16SNI;
1956                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1957                 rocketModel[i].numPorts = 16;
1958                 break;
1959         case PCI_DEVICE_ID_RP16INTF:
1960                 str = "16";
1961                 max_num_aiops = 2;
1962                 rocketModel[i].model = MODEL_RP16INTF;
1963                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1964                 rocketModel[i].numPorts = 16;
1965                 break;
1966         case PCI_DEVICE_ID_URP16INTF:
1967                 str = "16";
1968                 max_num_aiops = 2;
1969                 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1970                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1971                 rocketModel[i].numPorts = 16;
1972                 break;
1973         case PCI_DEVICE_ID_CRP16INTF:
1974                 str = "16";
1975                 max_num_aiops = 2;
1976                 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1977                 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1978                 rocketModel[i].numPorts = 16;
1979                 break;
1980         case PCI_DEVICE_ID_RP32INTF:
1981                 str = "32";
1982                 max_num_aiops = 4;
1983                 rocketModel[i].model = MODEL_RP32INTF;
1984                 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1985                 rocketModel[i].numPorts = 32;
1986                 break;
1987         case PCI_DEVICE_ID_URP32INTF:
1988                 str = "32";
1989                 max_num_aiops = 4;
1990                 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1991                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1992                 rocketModel[i].numPorts = 32;
1993                 break;
1994         case PCI_DEVICE_ID_RPP4:
1995                 str = "Plus Quadcable";
1996                 max_num_aiops = 1;
1997                 ports_per_aiop = 4;
1998                 altChanRingIndicator++;
1999                 fast_clock++;
2000                 rocketModel[i].model = MODEL_RPP4;
2001                 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2002                 rocketModel[i].numPorts = 4;
2003                 break;
2004         case PCI_DEVICE_ID_RPP8:
2005                 str = "Plus Octacable";
2006                 max_num_aiops = 2;
2007                 ports_per_aiop = 4;
2008                 altChanRingIndicator++;
2009                 fast_clock++;
2010                 rocketModel[i].model = MODEL_RPP8;
2011                 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2012                 rocketModel[i].numPorts = 8;
2013                 break;
2014         case PCI_DEVICE_ID_RP2_232:
2015                 str = "Plus 2 (RS-232)";
2016                 max_num_aiops = 1;
2017                 ports_per_aiop = 2;
2018                 altChanRingIndicator++;
2019                 fast_clock++;
2020                 rocketModel[i].model = MODEL_RP2_232;
2021                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2022                 rocketModel[i].numPorts = 2;
2023                 break;
2024         case PCI_DEVICE_ID_RP2_422:
2025                 str = "Plus 2 (RS-422)";
2026                 max_num_aiops = 1;
2027                 ports_per_aiop = 2;
2028                 altChanRingIndicator++;
2029                 fast_clock++;
2030                 rocketModel[i].model = MODEL_RP2_422;
2031                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2032                 rocketModel[i].numPorts = 2;
2033                 break;
2034         case PCI_DEVICE_ID_RP6M:
2035
2036                 max_num_aiops = 1;
2037                 ports_per_aiop = 6;
2038                 str = "6-port";
2039
2040                 /*  If class_rev is 1, the rocketmodem flash must be loaded.  If it is 2 it is a "socketed" version. */
2041                 if ((class_rev & 0xFF) == 1) {
2042                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2043                         rocketModel[i].loadrm2 = 1;
2044                 } else {
2045                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2046                 }
2047
2048                 rocketModel[i].model = MODEL_RP6M;
2049                 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2050                 rocketModel[i].numPorts = 6;
2051                 break;
2052         case PCI_DEVICE_ID_RP4M:
2053                 max_num_aiops = 1;
2054                 ports_per_aiop = 4;
2055                 str = "4-port";
2056                 if ((class_rev & 0xFF) == 1) {
2057                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2058                         rocketModel[i].loadrm2 = 1;
2059                 } else {
2060                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2061                 }
2062
2063                 rocketModel[i].model = MODEL_RP4M;
2064                 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2065                 rocketModel[i].numPorts = 4;
2066                 break;
2067         default:
2068                 str = "(unknown/unsupported)";
2069                 max_num_aiops = 0;
2070                 break;
2071         }
2072
2073         /*
2074          * Check for UPCI boards.
2075          */
2076
2077         switch (dev->device) {
2078         case PCI_DEVICE_ID_URP32INTF:
2079         case PCI_DEVICE_ID_URP8INTF:
2080         case PCI_DEVICE_ID_URP16INTF:
2081         case PCI_DEVICE_ID_CRP16INTF:
2082         case PCI_DEVICE_ID_URP8OCTA:
2083                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2084                 ConfigIO = pci_resource_start(dev, 1);
2085                 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2086                         UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2087
2088                         /*
2089                          * Check for octa or quad cable.
2090                          */
2091                         if (!
2092                             (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2093                              PCI_GPIO_CTRL_8PORT)) {
2094                                 str = "Quadcable";
2095                                 ports_per_aiop = 4;
2096                                 rocketModel[i].numPorts = 4;
2097                         }
2098                 }
2099                 break;
2100         case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2101                 str = "8 ports";
2102                 max_num_aiops = 1;
2103                 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2104                 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2105                 rocketModel[i].numPorts = 8;
2106                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2107                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2108                 ConfigIO = pci_resource_start(dev, 1);
2109                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2110                 break;
2111         case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2112                 str = "4 ports";
2113                 max_num_aiops = 1;
2114                 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2115                 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2116                 rocketModel[i].numPorts = 4;
2117                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2118                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2119                 ConfigIO = pci_resource_start(dev, 1);
2120                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2121                 break;
2122         default:
2123                 break;
2124         }
2125
2126         switch (rcktpt_type[i]) {
2127         case ROCKET_TYPE_MODEM:
2128                 board_type = "RocketModem";
2129                 break;
2130         case ROCKET_TYPE_MODEMII:
2131                 board_type = "RocketModem II";
2132                 break;
2133         case ROCKET_TYPE_MODEMIII:
2134                 board_type = "RocketModem III";
2135                 break;
2136         default:
2137                 board_type = "RocketPort";
2138                 break;
2139         }
2140
2141         if (fast_clock) {
2142                 sClockPrescale = 0x12;  /* mod 2 (divide by 3) */
2143                 rp_baud_base[i] = 921600;
2144         } else {
2145                 /*
2146                  * If support_low_speed is set, use the slow clock
2147                  * prescale, which supports 50 bps
2148                  */
2149                 if (support_low_speed) {
2150                         /* mod 9 (divide by 10) prescale */
2151                         sClockPrescale = 0x19;
2152                         rp_baud_base[i] = 230400;
2153                 } else {
2154                         /* mod 4 (devide by 5) prescale */
2155                         sClockPrescale = 0x14;
2156                         rp_baud_base[i] = 460800;
2157                 }
2158         }
2159
2160         for (aiop = 0; aiop < max_num_aiops; aiop++)
2161                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2162         ctlp = sCtlNumToCtlPtr(i);
2163         num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2164         for (aiop = 0; aiop < max_num_aiops; aiop++)
2165                 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2166
2167         printk("Comtrol PCI controller #%d ID 0x%x found in bus:slot:fn %s at address %04lx, "
2168              "%d AIOP(s) (%s)\n", i, dev->device, pci_name(dev),
2169              rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString);
2170         printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2171                rocketModel[i].modelString,
2172                rocketModel[i].startingPortNumber,
2173                rocketModel[i].startingPortNumber +
2174                rocketModel[i].numPorts - 1);
2175
2176         if (num_aiops <= 0) {
2177                 rcktpt_io_addr[i] = 0;
2178                 return (0);
2179         }
2180         is_PCI[i] = 1;
2181
2182         /*  Reset the AIOPIC, init the serial ports */
2183         for (aiop = 0; aiop < num_aiops; aiop++) {
2184                 sResetAiopByNum(ctlp, aiop);
2185                 num_chan = ports_per_aiop;
2186                 for (chan = 0; chan < num_chan; chan++)
2187                         init_r_port(i, aiop, chan, dev);
2188         }
2189
2190         /*  Rocket modems must be reset */
2191         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2192             (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2193             (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2194                 num_chan = ports_per_aiop;
2195                 for (chan = 0; chan < num_chan; chan++)
2196                         sPCIModemReset(ctlp, chan, 1);
2197                 mdelay(500);
2198                 for (chan = 0; chan < num_chan; chan++)
2199                         sPCIModemReset(ctlp, chan, 0);
2200                 mdelay(500);
2201                 rmSpeakerReset(ctlp, rocketModel[i].model);
2202         }
2203         return (1);
2204 }
2205
2206 /*
2207  *  Probes for PCI cards, inits them if found
2208  *  Input:   board_found = number of ISA boards already found, or the
2209  *           starting board number
2210  *  Returns: Number of PCI boards found
2211  */
2212 static int __init init_PCI(int boards_found)
2213 {
2214         struct pci_dev *dev = NULL;
2215         int count = 0;
2216
2217         /*  Work through the PCI device list, pulling out ours */
2218         while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2219                 if (register_PCI(count + boards_found, dev))
2220                         count++;
2221         }
2222         return (count);
2223 }
2224
2225 #endif                          /* CONFIG_PCI */
2226
2227 /*
2228  *  Probes for ISA cards
2229  *  Input:   i = the board number to look for
2230  *  Returns: 1 if board found, 0 else
2231  */
2232 static int __init init_ISA(int i)
2233 {
2234         int num_aiops, num_chan = 0, total_num_chan = 0;
2235         int aiop, chan;
2236         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2237         CONTROLLER_t *ctlp;
2238         char *type_string;
2239
2240         /*  If io_addr is zero, no board configured */
2241         if (rcktpt_io_addr[i] == 0)
2242                 return (0);
2243
2244         /*  Reserve the IO region */
2245         if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2246                 printk(KERN_INFO "Unable to reserve IO region for configured ISA RocketPort at address 0x%lx, board not installed...\n", rcktpt_io_addr[i]);
2247                 rcktpt_io_addr[i] = 0;
2248                 return (0);
2249         }
2250
2251         ctlp = sCtlNumToCtlPtr(i);
2252
2253         ctlp->boardType = rcktpt_type[i];
2254
2255         switch (rcktpt_type[i]) {
2256         case ROCKET_TYPE_PC104:
2257                 type_string = "(PC104)";
2258                 break;
2259         case ROCKET_TYPE_MODEM:
2260                 type_string = "(RocketModem)";
2261                 break;
2262         case ROCKET_TYPE_MODEMII:
2263                 type_string = "(RocketModem II)";
2264                 break;
2265         default:
2266                 type_string = "";
2267                 break;
2268         }
2269
2270         /*
2271          * If support_low_speed is set, use the slow clock prescale,
2272          * which supports 50 bps
2273          */
2274         if (support_low_speed) {
2275                 sClockPrescale = 0x19;  /* mod 9 (divide by 10) prescale */
2276                 rp_baud_base[i] = 230400;
2277         } else {
2278                 sClockPrescale = 0x14;  /* mod 4 (devide by 5) prescale */
2279                 rp_baud_base[i] = 460800;
2280         }
2281
2282         for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2283                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2284
2285         num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio,  MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2286
2287         if (ctlp->boardType == ROCKET_TYPE_PC104) {
2288                 sEnAiop(ctlp, 2);       /* only one AIOPIC, but these */
2289                 sEnAiop(ctlp, 3);       /* CSels used for other stuff */
2290         }
2291
2292         /*  If something went wrong initing the AIOP's release the ISA IO memory */
2293         if (num_aiops <= 0) {
2294                 release_region(rcktpt_io_addr[i], 64);
2295                 rcktpt_io_addr[i] = 0;
2296                 return (0);
2297         }
2298
2299         rocketModel[i].startingPortNumber = nextLineNumber;
2300
2301         for (aiop = 0; aiop < num_aiops; aiop++) {
2302                 sResetAiopByNum(ctlp, aiop);
2303                 sEnAiop(ctlp, aiop);
2304                 num_chan = sGetAiopNumChan(ctlp, aiop);
2305                 total_num_chan += num_chan;
2306                 for (chan = 0; chan < num_chan; chan++)
2307                         init_r_port(i, aiop, chan, NULL);
2308         }
2309         is_PCI[i] = 0;
2310         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2311                 num_chan = sGetAiopNumChan(ctlp, 0);
2312                 total_num_chan = num_chan;
2313                 for (chan = 0; chan < num_chan; chan++)
2314                         sModemReset(ctlp, chan, 1);
2315                 mdelay(500);
2316                 for (chan = 0; chan < num_chan; chan++)
2317                         sModemReset(ctlp, chan, 0);
2318                 mdelay(500);
2319                 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2320         } else {
2321                 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2322         }
2323         rocketModel[i].numPorts = total_num_chan;
2324         rocketModel[i].model = MODEL_ISA;
2325
2326         printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2327                i, rcktpt_io_addr[i], num_aiops, type_string);
2328
2329         printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2330                rocketModel[i].modelString,
2331                rocketModel[i].startingPortNumber,
2332                rocketModel[i].startingPortNumber +
2333                rocketModel[i].numPorts - 1);
2334
2335         return (1);
2336 }
2337
2338 static const struct tty_operations rocket_ops = {
2339         .open = rp_open,
2340         .close = rp_close,
2341         .write = rp_write,
2342         .put_char = rp_put_char,
2343         .write_room = rp_write_room,
2344         .chars_in_buffer = rp_chars_in_buffer,
2345         .flush_buffer = rp_flush_buffer,
2346         .ioctl = rp_ioctl,
2347         .throttle = rp_throttle,
2348         .unthrottle = rp_unthrottle,
2349         .set_termios = rp_set_termios,
2350         .stop = rp_stop,
2351         .start = rp_start,
2352         .hangup = rp_hangup,
2353         .break_ctl = rp_break,
2354         .send_xchar = rp_send_xchar,
2355         .wait_until_sent = rp_wait_until_sent,
2356         .tiocmget = rp_tiocmget,
2357         .tiocmset = rp_tiocmset,
2358 };
2359
2360 /*
2361  * The module "startup" routine; it's run when the module is loaded.
2362  */
2363 static int __init rp_init(void)
2364 {
2365         int retval, pci_boards_found, isa_boards_found, i;
2366
2367         printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2368                ROCKET_VERSION, ROCKET_DATE);
2369
2370         rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2371         if (!rocket_driver)
2372                 return -ENOMEM;
2373
2374         /*
2375          * Initialize the array of pointers to our own internal state
2376          * structures.
2377          */
2378         memset(rp_table, 0, sizeof (rp_table));
2379         memset(xmit_flags, 0, sizeof (xmit_flags));
2380
2381         for (i = 0; i < MAX_RP_PORTS; i++)
2382                 lineNumbers[i] = 0;
2383         nextLineNumber = 0;
2384         memset(rocketModel, 0, sizeof (rocketModel));
2385
2386         /*
2387          *  If board 1 is non-zero, there is at least one ISA configured.  If controller is
2388          *  zero, use the default controller IO address of board1 + 0x40.
2389          */
2390         if (board1) {
2391                 if (controller == 0)
2392                         controller = board1 + 0x40;
2393         } else {
2394                 controller = 0;  /*  Used as a flag, meaning no ISA boards */
2395         }
2396
2397         /*  If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2398         if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2399                 printk(KERN_INFO "Unable to reserve IO region for first configured ISA RocketPort controller 0x%lx.  Driver exiting \n", controller);
2400                 return -EBUSY;
2401         }
2402
2403         /*  Store ISA variable retrieved from command line or .conf file. */
2404         rcktpt_io_addr[0] = board1;
2405         rcktpt_io_addr[1] = board2;
2406         rcktpt_io_addr[2] = board3;
2407         rcktpt_io_addr[3] = board4;
2408
2409         rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2410         rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2411         rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2412         rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2413         rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2414         rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2415         rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2416         rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2417
2418         /*
2419          * Set up the tty driver structure and then register this
2420          * driver with the tty layer.
2421          */
2422
2423         rocket_driver->owner = THIS_MODULE;
2424         rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2425         rocket_driver->name = "ttyR";
2426         rocket_driver->driver_name = "Comtrol RocketPort";
2427         rocket_driver->major = TTY_ROCKET_MAJOR;
2428         rocket_driver->minor_start = 0;
2429         rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2430         rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2431         rocket_driver->init_termios = tty_std_termios;
2432         rocket_driver->init_termios.c_cflag =
2433             B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2434         rocket_driver->init_termios.c_ispeed = 9600;
2435         rocket_driver->init_termios.c_ospeed = 9600;
2436 #ifdef ROCKET_SOFT_FLOW
2437         rocket_driver->flags |= TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
2438 #endif
2439         tty_set_operations(rocket_driver, &rocket_ops);
2440
2441         retval = tty_register_driver(rocket_driver);
2442         if (retval < 0) {
2443                 printk(KERN_INFO "Couldn't install tty RocketPort driver (error %d)\n", -retval);
2444                 put_tty_driver(rocket_driver);
2445                 return -1;
2446         }
2447
2448 #ifdef ROCKET_DEBUG_OPEN
2449         printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2450 #endif
2451
2452         /*
2453          *  OK, let's probe each of the controllers looking for boards.  Any boards found
2454          *  will be initialized here.
2455          */
2456         isa_boards_found = 0;
2457         pci_boards_found = 0;
2458
2459         for (i = 0; i < NUM_BOARDS; i++) {
2460                 if (init_ISA(i))
2461                         isa_boards_found++;
2462         }
2463
2464 #ifdef CONFIG_PCI
2465         if (isa_boards_found < NUM_BOARDS)
2466                 pci_boards_found = init_PCI(isa_boards_found);
2467 #endif
2468
2469         max_board = pci_boards_found + isa_boards_found;
2470
2471         if (max_board == 0) {
2472                 printk(KERN_INFO "No rocketport ports found; unloading driver.\n");
2473                 del_timer_sync(&rocket_timer);
2474                 tty_unregister_driver(rocket_driver);
2475                 put_tty_driver(rocket_driver);
2476                 return -ENXIO;
2477         }
2478
2479         return 0;
2480 }
2481
2482
2483 static void rp_cleanup_module(void)
2484 {
2485         int retval;
2486         int i;
2487
2488         del_timer_sync(&rocket_timer);
2489
2490         retval = tty_unregister_driver(rocket_driver);
2491         if (retval)
2492                 printk(KERN_INFO "Error %d while trying to unregister "
2493                        "rocketport driver\n", -retval);
2494         put_tty_driver(rocket_driver);
2495
2496         for (i = 0; i < MAX_RP_PORTS; i++)
2497                 kfree(rp_table[i]);
2498
2499         for (i = 0; i < NUM_BOARDS; i++) {
2500                 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2501                         continue;
2502                 release_region(rcktpt_io_addr[i], 64);
2503         }
2504         if (controller)
2505                 release_region(controller, 4);
2506 }
2507
2508 /***************************************************************************
2509 Function: sInitController
2510 Purpose:  Initialization of controller global registers and controller
2511           structure.
2512 Call:     sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2513                           IRQNum,Frequency,PeriodicOnly)
2514           CONTROLLER_T *CtlP; Ptr to controller structure
2515           int CtlNum; Controller number
2516           ByteIO_t MudbacIO; Mudbac base I/O address.
2517           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2518              This list must be in the order the AIOPs will be found on the
2519              controller.  Once an AIOP in the list is not found, it is
2520              assumed that there are no more AIOPs on the controller.
2521           int AiopIOListSize; Number of addresses in AiopIOList
2522           int IRQNum; Interrupt Request number.  Can be any of the following:
2523                          0: Disable global interrupts
2524                          3: IRQ 3
2525                          4: IRQ 4
2526                          5: IRQ 5
2527                          9: IRQ 9
2528                          10: IRQ 10
2529                          11: IRQ 11
2530                          12: IRQ 12
2531                          15: IRQ 15
2532           Byte_t Frequency: A flag identifying the frequency
2533                    of the periodic interrupt, can be any one of the following:
2534                       FREQ_DIS - periodic interrupt disabled
2535                       FREQ_137HZ - 137 Hertz
2536                       FREQ_69HZ - 69 Hertz
2537                       FREQ_34HZ - 34 Hertz
2538                       FREQ_17HZ - 17 Hertz
2539                       FREQ_9HZ - 9 Hertz
2540                       FREQ_4HZ - 4 Hertz
2541                    If IRQNum is set to 0 the Frequency parameter is
2542                    overidden, it is forced to a value of FREQ_DIS.
2543           int PeriodicOnly: 1 if all interrupts except the periodic
2544                                interrupt are to be blocked.
2545                             0 is both the periodic interrupt and
2546                                other channel interrupts are allowed.
2547                             If IRQNum is set to 0 the PeriodicOnly parameter is
2548                                overidden, it is forced to a value of 0.
2549 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2550                initialization failed.
2551
2552 Comments:
2553           If periodic interrupts are to be disabled but AIOP interrupts
2554           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2555
2556           If interrupts are to be completely disabled set IRQNum to 0.
2557
2558           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2559           invalid combination.
2560
2561           This function performs initialization of global interrupt modes,
2562           but it does not actually enable global interrupts.  To enable
2563           and disable global interrupts use functions sEnGlobalInt() and
2564           sDisGlobalInt().  Enabling of global interrupts is normally not
2565           done until all other initializations are complete.
2566
2567           Even if interrupts are globally enabled, they must also be
2568           individually enabled for each channel that is to generate
2569           interrupts.
2570
2571 Warnings: No range checking on any of the parameters is done.
2572
2573           No context switches are allowed while executing this function.
2574
2575           After this function all AIOPs on the controller are disabled,
2576           they can be enabled with sEnAiop().
2577 */
2578 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2579                            ByteIO_t * AiopIOList, int AiopIOListSize,
2580                            int IRQNum, Byte_t Frequency, int PeriodicOnly)
2581 {
2582         int i;
2583         ByteIO_t io;
2584         int done;
2585
2586         CtlP->AiopIntrBits = aiop_intr_bits;
2587         CtlP->AltChanRingIndicator = 0;
2588         CtlP->CtlNum = CtlNum;
2589         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2590         CtlP->BusType = isISA;
2591         CtlP->MBaseIO = MudbacIO;
2592         CtlP->MReg1IO = MudbacIO + 1;
2593         CtlP->MReg2IO = MudbacIO + 2;
2594         CtlP->MReg3IO = MudbacIO + 3;
2595 #if 1
2596         CtlP->MReg2 = 0;        /* interrupt disable */
2597         CtlP->MReg3 = 0;        /* no periodic interrupts */
2598 #else
2599         if (sIRQMap[IRQNum] == 0) {     /* interrupts globally disabled */
2600                 CtlP->MReg2 = 0;        /* interrupt disable */
2601                 CtlP->MReg3 = 0;        /* no periodic interrupts */
2602         } else {
2603                 CtlP->MReg2 = sIRQMap[IRQNum];  /* set IRQ number */
2604                 CtlP->MReg3 = Frequency;        /* set frequency */
2605                 if (PeriodicOnly) {     /* periodic interrupt only */
2606                         CtlP->MReg3 |= PERIODIC_ONLY;
2607                 }
2608         }
2609 #endif
2610         sOutB(CtlP->MReg2IO, CtlP->MReg2);
2611         sOutB(CtlP->MReg3IO, CtlP->MReg3);
2612         sControllerEOI(CtlP);   /* clear EOI if warm init */
2613         /* Init AIOPs */
2614         CtlP->NumAiop = 0;
2615         for (i = done = 0; i < AiopIOListSize; i++) {
2616                 io = AiopIOList[i];
2617                 CtlP->AiopIO[i] = (WordIO_t) io;
2618                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2619                 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2620                 sOutB(MudbacIO, (Byte_t) (io >> 6));    /* set up AIOP I/O in MUDBAC */
2621                 if (done)
2622                         continue;
2623                 sEnAiop(CtlP, i);       /* enable the AIOP */
2624                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2625                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2626                         done = 1;       /* done looking for AIOPs */
2627                 else {
2628                         CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2629                         sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2630                         sOutB(io + _INDX_DATA, sClockPrescale);
2631                         CtlP->NumAiop++;        /* bump count of AIOPs */
2632                 }
2633                 sDisAiop(CtlP, i);      /* disable AIOP */
2634         }
2635
2636         if (CtlP->NumAiop == 0)
2637                 return (-1);
2638         else
2639                 return (CtlP->NumAiop);
2640 }
2641
2642 /***************************************************************************
2643 Function: sPCIInitController
2644 Purpose:  Initialization of controller global registers and controller
2645           structure.
2646 Call:     sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2647                           IRQNum,Frequency,PeriodicOnly)
2648           CONTROLLER_T *CtlP; Ptr to controller structure
2649           int CtlNum; Controller number
2650           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2651              This list must be in the order the AIOPs will be found on the
2652              controller.  Once an AIOP in the list is not found, it is
2653              assumed that there are no more AIOPs on the controller.
2654           int AiopIOListSize; Number of addresses in AiopIOList
2655           int IRQNum; Interrupt Request number.  Can be any of the following:
2656                          0: Disable global interrupts
2657                          3: IRQ 3
2658                          4: IRQ 4
2659                          5: IRQ 5
2660                          9: IRQ 9
2661                          10: IRQ 10
2662                          11: IRQ 11
2663                          12: IRQ 12
2664                          15: IRQ 15
2665           Byte_t Frequency: A flag identifying the frequency
2666                    of the periodic interrupt, can be any one of the following:
2667                       FREQ_DIS - periodic interrupt disabled
2668                       FREQ_137HZ - 137 Hertz
2669                       FREQ_69HZ - 69 Hertz
2670                       FREQ_34HZ - 34 Hertz
2671                       FREQ_17HZ - 17 Hertz
2672                       FREQ_9HZ - 9 Hertz
2673                       FREQ_4HZ - 4 Hertz
2674                    If IRQNum is set to 0 the Frequency parameter is
2675                    overidden, it is forced to a value of FREQ_DIS.
2676           int PeriodicOnly: 1 if all interrupts except the periodic
2677                                interrupt are to be blocked.
2678                             0 is both the periodic interrupt and
2679                                other channel interrupts are allowed.
2680                             If IRQNum is set to 0 the PeriodicOnly parameter is
2681                                overidden, it is forced to a value of 0.
2682 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2683                initialization failed.
2684
2685 Comments:
2686           If periodic interrupts are to be disabled but AIOP interrupts
2687           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2688
2689           If interrupts are to be completely disabled set IRQNum to 0.
2690
2691           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2692           invalid combination.
2693
2694           This function performs initialization of global interrupt modes,
2695           but it does not actually enable global interrupts.  To enable
2696           and disable global interrupts use functions sEnGlobalInt() and
2697           sDisGlobalInt().  Enabling of global interrupts is normally not
2698           done until all other initializations are complete.
2699
2700           Even if interrupts are globally enabled, they must also be
2701           individually enabled for each channel that is to generate
2702           interrupts.
2703
2704 Warnings: No range checking on any of the parameters is done.
2705
2706           No context switches are allowed while executing this function.
2707
2708           After this function all AIOPs on the controller are disabled,
2709           they can be enabled with sEnAiop().
2710 */
2711 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2712                               ByteIO_t * AiopIOList, int AiopIOListSize,
2713                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2714                               int PeriodicOnly, int altChanRingIndicator,
2715                               int UPCIRingInd)
2716 {
2717         int i;
2718         ByteIO_t io;
2719
2720         CtlP->AltChanRingIndicator = altChanRingIndicator;
2721         CtlP->UPCIRingInd = UPCIRingInd;
2722         CtlP->CtlNum = CtlNum;
2723         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2724         CtlP->BusType = isPCI;  /* controller release 1 */
2725
2726         if (ConfigIO) {
2727                 CtlP->isUPCI = 1;
2728                 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2729                 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2730                 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2731         } else {
2732                 CtlP->isUPCI = 0;
2733                 CtlP->PCIIO =
2734                     (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2735                 CtlP->AiopIntrBits = aiop_intr_bits;
2736         }
2737
2738         sPCIControllerEOI(CtlP);        /* clear EOI if warm init */
2739         /* Init AIOPs */
2740         CtlP->NumAiop = 0;
2741         for (i = 0; i < AiopIOListSize; i++) {
2742                 io = AiopIOList[i];
2743                 CtlP->AiopIO[i] = (WordIO_t) io;
2744                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2745
2746                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2747                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2748                         break;  /* done looking for AIOPs */
2749
2750                 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2751                 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2752                 sOutB(io + _INDX_DATA, sClockPrescale);
2753                 CtlP->NumAiop++;        /* bump count of AIOPs */
2754         }
2755
2756         if (CtlP->NumAiop == 0)
2757                 return (-1);
2758         else
2759                 return (CtlP->NumAiop);
2760 }
2761
2762 /***************************************************************************
2763 Function: sReadAiopID
2764 Purpose:  Read the AIOP idenfication number directly from an AIOP.
2765 Call:     sReadAiopID(io)
2766           ByteIO_t io: AIOP base I/O address
2767 Return:   int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2768                  is replace by an identifying number.
2769           Flag AIOPID_NULL if no valid AIOP is found
2770 Warnings: No context switches are allowed while executing this function.
2771
2772 */
2773 static int sReadAiopID(ByteIO_t io)
2774 {
2775         Byte_t AiopID;          /* ID byte from AIOP */
2776
2777         sOutB(io + _CMD_REG, RESET_ALL);        /* reset AIOP */
2778         sOutB(io + _CMD_REG, 0x0);
2779         AiopID = sInW(io + _CHN_STAT0) & 0x07;
2780         if (AiopID == 0x06)
2781                 return (1);
2782         else                    /* AIOP does not exist */
2783                 return (-1);
2784 }
2785
2786 /***************************************************************************
2787 Function: sReadAiopNumChan
2788 Purpose:  Read the number of channels available in an AIOP directly from
2789           an AIOP.
2790 Call:     sReadAiopNumChan(io)
2791           WordIO_t io: AIOP base I/O address
2792 Return:   int: The number of channels available
2793 Comments: The number of channels is determined by write/reads from identical
2794           offsets within the SRAM address spaces for channels 0 and 4.
2795           If the channel 4 space is mirrored to channel 0 it is a 4 channel
2796           AIOP, otherwise it is an 8 channel.
2797 Warnings: No context switches are allowed while executing this function.
2798 */
2799 static int sReadAiopNumChan(WordIO_t io)
2800 {
2801         Word_t x;
2802         static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2803
2804         /* write to chan 0 SRAM */
2805         sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0]));
2806         sOutW(io + _INDX_ADDR, 0);      /* read from SRAM, chan 0 */
2807         x = sInW(io + _INDX_DATA);
2808         sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2809         if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2810                 return (8);
2811         else
2812                 return (4);
2813 }
2814
2815 /***************************************************************************
2816 Function: sInitChan
2817 Purpose:  Initialization of a channel and channel structure
2818 Call:     sInitChan(CtlP,ChP,AiopNum,ChanNum)
2819           CONTROLLER_T *CtlP; Ptr to controller structure
2820           CHANNEL_T *ChP; Ptr to channel structure
2821           int AiopNum; AIOP number within controller
2822           int ChanNum; Channel number within AIOP
2823 Return:   int: 1 if initialization succeeded, 0 if it fails because channel
2824                number exceeds number of channels available in AIOP.
2825 Comments: This function must be called before a channel can be used.
2826 Warnings: No range checking on any of the parameters is done.
2827
2828           No context switches are allowed while executing this function.
2829 */
2830 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2831                      int ChanNum)
2832 {
2833         int i;
2834         WordIO_t AiopIO;
2835         WordIO_t ChIOOff;
2836         Byte_t *ChR;
2837         Word_t ChOff;
2838         static Byte_t R[4];
2839         int brd9600;
2840
2841         if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2842                 return 0;       /* exceeds num chans in AIOP */
2843
2844         /* Channel, AIOP, and controller identifiers */
2845         ChP->CtlP = CtlP;
2846         ChP->ChanID = CtlP->AiopID[AiopNum];
2847         ChP->AiopNum = AiopNum;
2848         ChP->ChanNum = ChanNum;
2849
2850         /* Global direct addresses */
2851         AiopIO = CtlP->AiopIO[AiopNum];
2852         ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2853         ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2854         ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2855         ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2856         ChP->IndexData = AiopIO + _INDX_DATA;
2857
2858         /* Channel direct addresses */
2859         ChIOOff = AiopIO + ChP->ChanNum * 2;
2860         ChP->TxRxData = ChIOOff + _TD0;
2861         ChP->ChanStat = ChIOOff + _CHN_STAT0;
2862         ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2863         ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2864
2865         /* Initialize the channel from the RData array */
2866         for (i = 0; i < RDATASIZE; i += 4) {
2867                 R[0] = RData[i];
2868                 R[1] = RData[i + 1] + 0x10 * ChanNum;
2869                 R[2] = RData[i + 2];
2870                 R[3] = RData[i + 3];
2871                 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0]));
2872         }
2873
2874         ChR = ChP->R;
2875         for (i = 0; i < RREGDATASIZE; i += 4) {
2876                 ChR[i] = RRegData[i];
2877                 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2878                 ChR[i + 2] = RRegData[i + 2];
2879                 ChR[i + 3] = RRegData[i + 3];
2880         }
2881
2882         /* Indexed registers */
2883         ChOff = (Word_t) ChanNum *0x1000;
2884
2885         if (sClockPrescale == 0x14)
2886                 brd9600 = 47;
2887         else
2888                 brd9600 = 23;
2889
2890         ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2891         ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2892         ChP->BaudDiv[2] = (Byte_t) brd9600;
2893         ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2894         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]);
2895
2896         ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2897         ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2898         ChP->TxControl[2] = 0;
2899         ChP->TxControl[3] = 0;
2900         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
2901
2902         ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2903         ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2904         ChP->RxControl[2] = 0;
2905         ChP->RxControl[3] = 0;
2906         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
2907
2908         ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2909         ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2910         ChP->TxEnables[2] = 0;
2911         ChP->TxEnables[3] = 0;
2912         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]);
2913
2914         ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2915         ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2916         ChP->TxCompare[2] = 0;
2917         ChP->TxCompare[3] = 0;
2918         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]);
2919
2920         ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2921         ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2922         ChP->TxReplace1[2] = 0;
2923         ChP->TxReplace1[3] = 0;
2924         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]);
2925
2926         ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2927         ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2928         ChP->TxReplace2[2] = 0;
2929         ChP->TxReplace2[3] = 0;
2930         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]);
2931
2932         ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2933         ChP->TxFIFO = ChOff + _TX_FIFO;
2934
2935         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT);  /* apply reset Tx FIFO count */
2936         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Tx FIFO count */
2937         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2938         sOutW(ChP->IndexData, 0);
2939         ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2940         ChP->RxFIFO = ChOff + _RX_FIFO;
2941
2942         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT);  /* apply reset Rx FIFO count */
2943         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Rx FIFO count */
2944         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2945         sOutW(ChP->IndexData, 0);
2946         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2947         sOutW(ChP->IndexData, 0);
2948         ChP->TxPrioCnt = ChOff + _TXP_CNT;
2949         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2950         sOutB(ChP->IndexData, 0);
2951         ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2952         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2953         sOutB(ChP->IndexData, 0);
2954         ChP->TxPrioBuf = ChOff + _TXP_BUF;
2955         sEnRxProcessor(ChP);    /* start the Rx processor */
2956
2957         return 1;
2958 }
2959
2960 /***************************************************************************
2961 Function: sStopRxProcessor
2962 Purpose:  Stop the receive processor from processing a channel.
2963 Call:     sStopRxProcessor(ChP)
2964           CHANNEL_T *ChP; Ptr to channel structure
2965
2966 Comments: The receive processor can be started again with sStartRxProcessor().
2967           This function causes the receive processor to skip over the
2968           stopped channel.  It does not stop it from processing other channels.
2969
2970 Warnings: No context switches are allowed while executing this function.
2971
2972           Do not leave the receive processor stopped for more than one
2973           character time.
2974
2975           After calling this function a delay of 4 uS is required to ensure
2976           that the receive processor is no longer processing this channel.
2977 */
2978 static void sStopRxProcessor(CHANNEL_T * ChP)
2979 {
2980         Byte_t R[4];
2981
2982         R[0] = ChP->R[0];
2983         R[1] = ChP->R[1];
2984         R[2] = 0x0a;
2985         R[3] = ChP->R[3];
2986         sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]);
2987 }
2988
2989 /***************************************************************************
2990 Function: sFlushRxFIFO
2991 Purpose:  Flush the Rx FIFO
2992 Call:     sFlushRxFIFO(ChP)
2993           CHANNEL_T *ChP; Ptr to channel structure
2994 Return:   void
2995 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2996           while it is being flushed the receive processor is stopped
2997           and the transmitter is disabled.  After these operations a
2998           4 uS delay is done before clearing the pointers to allow
2999           the receive processor to stop.  These items are handled inside
3000           this function.
3001 Warnings: No context switches are allowed while executing this function.
3002 */
3003 static void sFlushRxFIFO(CHANNEL_T * ChP)
3004 {
3005         int i;
3006         Byte_t Ch;              /* channel number within AIOP */
3007         int RxFIFOEnabled;      /* 1 if Rx FIFO enabled */
3008
3009         if (sGetRxCnt(ChP) == 0)        /* Rx FIFO empty */
3010                 return;         /* don't need to flush */
3011
3012         RxFIFOEnabled = 0;
3013         if (ChP->R[0x32] == 0x08) {     /* Rx FIFO is enabled */
3014                 RxFIFOEnabled = 1;
3015                 sDisRxFIFO(ChP);        /* disable it */
3016                 for (i = 0; i < 2000 / 200; i++)        /* delay 2 uS to allow proc to disable FIFO */
3017                         sInB(ChP->IntChan);     /* depends on bus i/o timing */
3018         }
3019         sGetChanStatus(ChP);    /* clear any pending Rx errors in chan stat */
3020         Ch = (Byte_t) sGetChanNum(ChP);
3021         sOutB(ChP->Cmd, Ch | RESRXFCNT);        /* apply reset Rx FIFO count */
3022         sOutB(ChP->Cmd, Ch);    /* remove reset Rx FIFO count */
3023         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
3024         sOutW(ChP->IndexData, 0);
3025         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
3026         sOutW(ChP->IndexData, 0);
3027         if (RxFIFOEnabled)
3028                 sEnRxFIFO(ChP); /* enable Rx FIFO */
3029 }
3030
3031 /***************************************************************************
3032 Function: sFlushTxFIFO
3033 Purpose:  Flush the Tx FIFO
3034 Call:     sFlushTxFIFO(ChP)
3035           CHANNEL_T *ChP; Ptr to channel structure
3036 Return:   void
3037 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3038           while it is being flushed the receive processor is stopped
3039           and the transmitter is disabled.  After these operations a
3040           4 uS delay is done before clearing the pointers to allow
3041           the receive processor to stop.  These items are handled inside
3042           this function.
3043 Warnings: No context switches are allowed while executing this function.
3044 */
3045 static void sFlushTxFIFO(CHANNEL_T * ChP)
3046 {
3047         int i;
3048         Byte_t Ch;              /* channel number within AIOP */
3049         int TxEnabled;          /* 1 if transmitter enabled */
3050
3051         if (sGetTxCnt(ChP) == 0)        /* Tx FIFO empty */
3052                 return;         /* don't need to flush */
3053
3054         TxEnabled = 0;
3055         if (ChP->TxControl[3] & TX_ENABLE) {
3056                 TxEnabled = 1;
3057                 sDisTransmit(ChP);      /* disable transmitter */
3058         }
3059         sStopRxProcessor(ChP);  /* stop Rx processor */
3060         for (i = 0; i < 4000 / 200; i++)        /* delay 4 uS to allow proc to stop */
3061                 sInB(ChP->IntChan);     /* depends on bus i/o timing */
3062         Ch = (Byte_t) sGetChanNum(ChP);
3063         sOutB(ChP->Cmd, Ch | RESTXFCNT);        /* apply reset Tx FIFO count */
3064         sOutB(ChP->Cmd, Ch);    /* remove reset Tx FIFO count */
3065         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
3066         sOutW(ChP->IndexData, 0);
3067         if (TxEnabled)
3068                 sEnTransmit(ChP);       /* enable transmitter */
3069         sStartRxProcessor(ChP); /* restart Rx processor */
3070 }
3071
3072 /***************************************************************************
3073 Function: sWriteTxPrioByte
3074 Purpose:  Write a byte of priority transmit data to a channel
3075 Call:     sWriteTxPrioByte(ChP,Data)
3076           CHANNEL_T *ChP; Ptr to channel structure
3077           Byte_t Data; The transmit data byte
3078
3079 Return:   int: 1 if the bytes is successfully written, otherwise 0.
3080
3081 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3082
3083 Warnings: No context switches are allowed while executing this function.
3084 */
3085 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3086 {
3087         Byte_t DWBuf[4];        /* buffer for double word writes */
3088         Word_t *WordPtr;        /* must be far because Win SS != DS */
3089         register DWordIO_t IndexAddr;
3090
3091         if (sGetTxCnt(ChP) > 1) {       /* write it to Tx priority buffer */
3092                 IndexAddr = ChP->IndexAddr;
3093                 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt);    /* get priority buffer status */
3094                 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3095                         return (0);     /* nothing sent */
3096
3097                 WordPtr = (Word_t *) (&DWBuf[0]);
3098                 *WordPtr = ChP->TxPrioBuf;      /* data byte address */
3099
3100                 DWBuf[2] = Data;        /* data byte value */
3101                 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0])));  /* write it out */
3102
3103                 *WordPtr = ChP->TxPrioCnt;      /* Tx priority count address */
3104
3105                 DWBuf[2] = PRI_PEND + 1;        /* indicate 1 byte pending */
3106                 DWBuf[3] = 0;   /* priority buffer pointer */
3107                 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0])));  /* write it out */
3108         } else {                /* write it to Tx FIFO */
3109
3110                 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3111         }
3112         return (1);             /* 1 byte sent */
3113 }
3114
3115 /***************************************************************************
3116 Function: sEnInterrupts
3117 Purpose:  Enable one or more interrupts for a channel
3118 Call:     sEnInterrupts(ChP,Flags)
3119           CHANNEL_T *ChP; Ptr to channel structure
3120           Word_t Flags: Interrupt enable flags, can be any combination
3121              of the following flags:
3122                 TXINT_EN:   Interrupt on Tx FIFO empty
3123                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3124                             sSetRxTrigger())
3125                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3126                 MCINT_EN:   Interrupt on modem input change
3127                 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3128                             Interrupt Channel Register.
3129 Return:   void
3130 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3131           enabled.  If an interrupt enable flag is not set in Flags, that
3132           interrupt will not be changed.  Interrupts can be disabled with
3133           function sDisInterrupts().
3134
3135           This function sets the appropriate bit for the channel in the AIOP's
3136           Interrupt Mask Register if the CHANINT_EN flag is set.  This allows
3137           this channel's bit to be set in the AIOP's Interrupt Channel Register.
3138
3139           Interrupts must also be globally enabled before channel interrupts
3140           will be passed on to the host.  This is done with function
3141           sEnGlobalInt().
3142
3143           In some cases it may be desirable to disable interrupts globally but
3144           enable channel interrupts.  This would allow the global interrupt
3145           status register to be used to determine which AIOPs need service.
3146 */
3147 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3148 {
3149         Byte_t Mask;            /* Interrupt Mask Register */
3150
3151         ChP->RxControl[2] |=
3152             ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3153
3154         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3155
3156         ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3157
3158         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3159
3160         if (Flags & CHANINT_EN) {
3161                 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3162                 sOutB(ChP->IntMask, Mask);
3163         }
3164 }
3165
3166 /***************************************************************************
3167 Function: sDisInterrupts
3168 Purpose:  Disable one or more interrupts for a channel
3169 Call:     sDisInterrupts(ChP,Flags)
3170           CHANNEL_T *ChP; Ptr to channel structure
3171           Word_t Flags: Interrupt flags, can be any combination
3172              of the following flags:
3173                 TXINT_EN:   Interrupt on Tx FIFO empty
3174                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3175                             sSetRxTrigger())
3176                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3177                 MCINT_EN:   Interrupt on modem input change
3178                 CHANINT_EN: Disable channel interrupt signal to the
3179                             AIOP's Interrupt Channel Register.
3180 Return:   void
3181 Comments: If an interrupt flag is set in Flags, that interrupt will be
3182           disabled.  If an interrupt flag is not set in Flags, that
3183           interrupt will not be changed.  Interrupts can be enabled with
3184           function sEnInterrupts().
3185
3186           This function clears the appropriate bit for the channel in the AIOP's
3187           Interrupt Mask Register if the CHANINT_EN flag is set.  This blocks
3188           this channel's bit from being set in the AIOP's Interrupt Channel
3189           Register.
3190 */
3191 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3192 {
3193         Byte_t Mask;            /* Interrupt Mask Register */
3194
3195         ChP->RxControl[2] &=
3196             ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3197         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3198         ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3199         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3200
3201         if (Flags & CHANINT_EN) {
3202                 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3203                 sOutB(ChP->IntMask, Mask);
3204         }
3205 }
3206
3207 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3208 {
3209         sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3210 }
3211
3212 /*
3213  *  Not an official SSCI function, but how to reset RocketModems.
3214  *  ISA bus version
3215  */
3216 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3217 {
3218         ByteIO_t addr;
3219         Byte_t val;
3220
3221         addr = CtlP->AiopIO[0] + 0x400;
3222         val = sInB(CtlP->MReg3IO);
3223         /* if AIOP[1] is not enabled, enable it */
3224         if ((val & 2) == 0) {
3225                 val = sInB(CtlP->MReg2IO);
3226                 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3227                 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3228         }
3229
3230         sEnAiop(CtlP, 1);
3231         if (!on)
3232                 addr += 8;
3233         sOutB(addr + chan, 0);  /* apply or remove reset */
3234         sDisAiop(CtlP, 1);
3235 }
3236
3237 /*
3238  *  Not an official SSCI function, but how to reset RocketModems.
3239  *  PCI bus version
3240  */
3241 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3242 {
3243         ByteIO_t addr;
3244
3245         addr = CtlP->AiopIO[0] + 0x40;  /* 2nd AIOP */
3246         if (!on)
3247                 addr += 8;
3248         sOutB(addr + chan, 0);  /* apply or remove reset */
3249 }
3250
3251 /*  Resets the speaker controller on RocketModem II and III devices */
3252 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3253 {
3254         ByteIO_t addr;
3255
3256         /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3257         if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3258                 addr = CtlP->AiopIO[0] + 0x4F;
3259                 sOutB(addr, 0);
3260         }
3261
3262         /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3263         if ((model == MODEL_UPCI_RM3_8PORT)
3264             || (model == MODEL_UPCI_RM3_4PORT)) {
3265                 addr = CtlP->AiopIO[0] + 0x88;
3266                 sOutB(addr, 0);
3267         }
3268 }
3269
3270 /*  Returns the line number given the controller (board), aiop and channel number */
3271 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3272 {
3273         return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3274 }
3275
3276 /*
3277  *  Stores the line number associated with a given controller (board), aiop
3278  *  and channel number.
3279  *  Returns:  The line number assigned
3280  */
3281 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3282 {
3283         lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3284         return (nextLineNumber - 1);
3285 }