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drm/i915: Add frame buffer compression on Sandybridge
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
blob3f7b20392e26a5eb4a5c56dfe3cb32eeb0e4cada
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include <linux/pci.h>
38 #include <linux/vgaarb.h>
39 #include <linux/acpi.h>
40 #include <linux/pnp.h>
41 #include <linux/vga_switcheroo.h>
42 #include <linux/slab.h>
43 #include <acpi/video.h>
44
45 /**
46 * Sets up the hardware status page for devices that need a physical address
47 * in the register.
48 */
49 static int i915_init_phys_hws(struct drm_device *dev)
50 {
51 drm_i915_private_t *dev_priv = dev->dev_private;
52 struct intel_ring_buffer *ring = LP_RING(dev_priv);
53
54 /* Program Hardware Status Page */
55 dev_priv->status_page_dmah =
56 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
57
58 if (!dev_priv->status_page_dmah) {
59 DRM_ERROR("Can not allocate hardware status page\n");
60 return -ENOMEM;
61 }
62 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
63 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
64
65 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
66
67 if (INTEL_INFO(dev)->gen >= 4)
68 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
69 0xf0;
70
71 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
72 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
73 return 0;
74 }
75
76 /**
77 * Frees the hardware status page, whether it's a physical address or a virtual
78 * address set up by the X Server.
79 */
80 static void i915_free_hws(struct drm_device *dev)
81 {
82 drm_i915_private_t *dev_priv = dev->dev_private;
83 struct intel_ring_buffer *ring = LP_RING(dev_priv);
84
85 if (dev_priv->status_page_dmah) {
86 drm_pci_free(dev, dev_priv->status_page_dmah);
87 dev_priv->status_page_dmah = NULL;
88 }
89
90 if (ring->status_page.gfx_addr) {
91 ring->status_page.gfx_addr = 0;
92 drm_core_ioremapfree(&dev_priv->hws_map, dev);
93 }
94
95 /* Need to rewrite hardware status page */
96 I915_WRITE(HWS_PGA, 0x1ffff000);
97 }
98
99 void i915_kernel_lost_context(struct drm_device * dev)
100 {
101 drm_i915_private_t *dev_priv = dev->dev_private;
102 struct drm_i915_master_private *master_priv;
103 struct intel_ring_buffer *ring = LP_RING(dev_priv);
104
105 /*
106 * We should never lose context on the ring with modesetting
107 * as we don't expose it to userspace
108 */
109 if (drm_core_check_feature(dev, DRIVER_MODESET))
110 return;
111
112 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
113 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
114 ring->space = ring->head - (ring->tail + 8);
115 if (ring->space < 0)
116 ring->space += ring->size;
117
118 if (!dev->primary->master)
119 return;
120
121 master_priv = dev->primary->master->driver_priv;
122 if (ring->head == ring->tail && master_priv->sarea_priv)
123 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
124 }
125
126 static int i915_dma_cleanup(struct drm_device * dev)
127 {
128 drm_i915_private_t *dev_priv = dev->dev_private;
129 int i;
130
131 /* Make sure interrupts are disabled here because the uninstall ioctl
132 * may not have been called from userspace and after dev_private
133 * is freed, it's too late.
134 */
135 if (dev->irq_enabled)
136 drm_irq_uninstall(dev);
137
138 mutex_lock(&dev->struct_mutex);
139 for (i = 0; i < I915_NUM_RINGS; i++)
140 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
141 mutex_unlock(&dev->struct_mutex);
142
143 /* Clear the HWS virtual address at teardown */
144 if (I915_NEED_GFX_HWS(dev))
145 i915_free_hws(dev);
146
147 return 0;
148 }
149
150 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
151 {
152 drm_i915_private_t *dev_priv = dev->dev_private;
153 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
154 struct intel_ring_buffer *ring = LP_RING(dev_priv);
155
156 master_priv->sarea = drm_getsarea(dev);
157 if (master_priv->sarea) {
158 master_priv->sarea_priv = (drm_i915_sarea_t *)
159 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
160 } else {
161 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
162 }
163
164 if (init->ring_size != 0) {
165 if (ring->obj != NULL) {
166 i915_dma_cleanup(dev);
167 DRM_ERROR("Client tried to initialize ringbuffer in "
168 "GEM mode\n");
169 return -EINVAL;
170 }
171
172 ring->size = init->ring_size;
173
174 ring->map.offset = init->ring_start;
175 ring->map.size = init->ring_size;
176 ring->map.type = 0;
177 ring->map.flags = 0;
178 ring->map.mtrr = 0;
179
180 drm_core_ioremap_wc(&ring->map, dev);
181
182 if (ring->map.handle == NULL) {
183 i915_dma_cleanup(dev);
184 DRM_ERROR("can not ioremap virtual address for"
185 " ring buffer\n");
186 return -ENOMEM;
187 }
188 }
189
190 ring->virtual_start = ring->map.handle;
191
192 dev_priv->cpp = init->cpp;
193 dev_priv->back_offset = init->back_offset;
194 dev_priv->front_offset = init->front_offset;
195 dev_priv->current_page = 0;
196 if (master_priv->sarea_priv)
197 master_priv->sarea_priv->pf_current_page = 0;
198
199 /* Allow hardware batchbuffers unless told otherwise.
200 */
201 dev_priv->allow_batchbuffer = 1;
202
203 return 0;
204 }
205
206 static int i915_dma_resume(struct drm_device * dev)
207 {
208 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
209 struct intel_ring_buffer *ring = LP_RING(dev_priv);
210
211 DRM_DEBUG_DRIVER("%s\n", __func__);
212
213 if (ring->map.handle == NULL) {
214 DRM_ERROR("can not ioremap virtual address for"
215 " ring buffer\n");
216 return -ENOMEM;
217 }
218
219 /* Program Hardware Status Page */
220 if (!ring->status_page.page_addr) {
221 DRM_ERROR("Can not find hardware status page\n");
222 return -EINVAL;
223 }
224 DRM_DEBUG_DRIVER("hw status page @ %p\n",
225 ring->status_page.page_addr);
226 if (ring->status_page.gfx_addr != 0)
227 intel_ring_setup_status_page(ring);
228 else
229 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
230
231 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
232
233 return 0;
234 }
235
236 static int i915_dma_init(struct drm_device *dev, void *data,
237 struct drm_file *file_priv)
238 {
239 drm_i915_init_t *init = data;
240 int retcode = 0;
241
242 switch (init->func) {
243 case I915_INIT_DMA:
244 retcode = i915_initialize(dev, init);
245 break;
246 case I915_CLEANUP_DMA:
247 retcode = i915_dma_cleanup(dev);
248 break;
249 case I915_RESUME_DMA:
250 retcode = i915_dma_resume(dev);
251 break;
252 default:
253 retcode = -EINVAL;
254 break;
255 }
256
257 return retcode;
258 }
259
260 /* Implement basically the same security restrictions as hardware does
261 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
262 *
263 * Most of the calculations below involve calculating the size of a
264 * particular instruction. It's important to get the size right as
265 * that tells us where the next instruction to check is. Any illegal
266 * instruction detected will be given a size of zero, which is a
267 * signal to abort the rest of the buffer.
268 */
269 static int validate_cmd(int cmd)
270 {
271 switch (((cmd >> 29) & 0x7)) {
272 case 0x0:
273 switch ((cmd >> 23) & 0x3f) {
274 case 0x0:
275 return 1; /* MI_NOOP */
276 case 0x4:
277 return 1; /* MI_FLUSH */
278 default:
279 return 0; /* disallow everything else */
280 }
281 break;
282 case 0x1:
283 return 0; /* reserved */
284 case 0x2:
285 return (cmd & 0xff) + 2; /* 2d commands */
286 case 0x3:
287 if (((cmd >> 24) & 0x1f) <= 0x18)
288 return 1;
289
290 switch ((cmd >> 24) & 0x1f) {
291 case 0x1c:
292 return 1;
293 case 0x1d:
294 switch ((cmd >> 16) & 0xff) {
295 case 0x3:
296 return (cmd & 0x1f) + 2;
297 case 0x4:
298 return (cmd & 0xf) + 2;
299 default:
300 return (cmd & 0xffff) + 2;
301 }
302 case 0x1e:
303 if (cmd & (1 << 23))
304 return (cmd & 0xffff) + 1;
305 else
306 return 1;
307 case 0x1f:
308 if ((cmd & (1 << 23)) == 0) /* inline vertices */
309 return (cmd & 0x1ffff) + 2;
310 else if (cmd & (1 << 17)) /* indirect random */
311 if ((cmd & 0xffff) == 0)
312 return 0; /* unknown length, too hard */
313 else
314 return (((cmd & 0xffff) + 1) / 2) + 1;
315 else
316 return 2; /* indirect sequential */
317 default:
318 return 0;
319 }
320 default:
321 return 0;
322 }
323
324 return 0;
325 }
326
327 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
328 {
329 drm_i915_private_t *dev_priv = dev->dev_private;
330 int i, ret;
331
332 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
333 return -EINVAL;
334
335 for (i = 0; i < dwords;) {
336 int sz = validate_cmd(buffer[i]);
337 if (sz == 0 || i + sz > dwords)
338 return -EINVAL;
339 i += sz;
340 }
341
342 ret = BEGIN_LP_RING((dwords+1)&~1);
343 if (ret)
344 return ret;
345
346 for (i = 0; i < dwords; i++)
347 OUT_RING(buffer[i]);
348 if (dwords & 1)
349 OUT_RING(0);
350
351 ADVANCE_LP_RING();
352
353 return 0;
354 }
355
356 int
357 i915_emit_box(struct drm_device *dev,
358 struct drm_clip_rect *box,
359 int DR1, int DR4)
360 {
361 struct drm_i915_private *dev_priv = dev->dev_private;
362 int ret;
363
364 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
365 box->y2 <= 0 || box->x2 <= 0) {
366 DRM_ERROR("Bad box %d,%d..%d,%d\n",
367 box->x1, box->y1, box->x2, box->y2);
368 return -EINVAL;
369 }
370
371 if (INTEL_INFO(dev)->gen >= 4) {
372 ret = BEGIN_LP_RING(4);
373 if (ret)
374 return ret;
375
376 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
377 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
378 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
379 OUT_RING(DR4);
380 } else {
381 ret = BEGIN_LP_RING(6);
382 if (ret)
383 return ret;
384
385 OUT_RING(GFX_OP_DRAWRECT_INFO);
386 OUT_RING(DR1);
387 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
388 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
389 OUT_RING(DR4);
390 OUT_RING(0);
391 }
392 ADVANCE_LP_RING();
393
394 return 0;
395 }
396
397 /* XXX: Emitting the counter should really be moved to part of the IRQ
398 * emit. For now, do it in both places:
399 */
400
401 static void i915_emit_breadcrumb(struct drm_device *dev)
402 {
403 drm_i915_private_t *dev_priv = dev->dev_private;
404 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
405
406 dev_priv->counter++;
407 if (dev_priv->counter > 0x7FFFFFFFUL)
408 dev_priv->counter = 0;
409 if (master_priv->sarea_priv)
410 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
411
412 if (BEGIN_LP_RING(4) == 0) {
413 OUT_RING(MI_STORE_DWORD_INDEX);
414 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
415 OUT_RING(dev_priv->counter);
416 OUT_RING(0);
417 ADVANCE_LP_RING();
418 }
419 }
420
421 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
422 drm_i915_cmdbuffer_t *cmd,
423 struct drm_clip_rect *cliprects,
424 void *cmdbuf)
425 {
426 int nbox = cmd->num_cliprects;
427 int i = 0, count, ret;
428
429 if (cmd->sz & 0x3) {
430 DRM_ERROR("alignment");
431 return -EINVAL;
432 }
433
434 i915_kernel_lost_context(dev);
435
436 count = nbox ? nbox : 1;
437
438 for (i = 0; i < count; i++) {
439 if (i < nbox) {
440 ret = i915_emit_box(dev, &cliprects[i],
441 cmd->DR1, cmd->DR4);
442 if (ret)
443 return ret;
444 }
445
446 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
447 if (ret)
448 return ret;
449 }
450
451 i915_emit_breadcrumb(dev);
452 return 0;
453 }
454
455 static int i915_dispatch_batchbuffer(struct drm_device * dev,
456 drm_i915_batchbuffer_t * batch,
457 struct drm_clip_rect *cliprects)
458 {
459 struct drm_i915_private *dev_priv = dev->dev_private;
460 int nbox = batch->num_cliprects;
461 int i, count, ret;
462
463 if ((batch->start | batch->used) & 0x7) {
464 DRM_ERROR("alignment");
465 return -EINVAL;
466 }
467
468 i915_kernel_lost_context(dev);
469
470 count = nbox ? nbox : 1;
471 for (i = 0; i < count; i++) {
472 if (i < nbox) {
473 ret = i915_emit_box(dev, &cliprects[i],
474 batch->DR1, batch->DR4);
475 if (ret)
476 return ret;
477 }
478
479 if (!IS_I830(dev) && !IS_845G(dev)) {
480 ret = BEGIN_LP_RING(2);
481 if (ret)
482 return ret;
483
484 if (INTEL_INFO(dev)->gen >= 4) {
485 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
486 OUT_RING(batch->start);
487 } else {
488 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
489 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
490 }
491 } else {
492 ret = BEGIN_LP_RING(4);
493 if (ret)
494 return ret;
495
496 OUT_RING(MI_BATCH_BUFFER);
497 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
498 OUT_RING(batch->start + batch->used - 4);
499 OUT_RING(0);
500 }
501 ADVANCE_LP_RING();
502 }
503
504
505 if (IS_G4X(dev) || IS_GEN5(dev)) {
506 if (BEGIN_LP_RING(2) == 0) {
507 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
508 OUT_RING(MI_NOOP);
509 ADVANCE_LP_RING();
510 }
511 }
512
513 i915_emit_breadcrumb(dev);
514 return 0;
515 }
516
517 static int i915_dispatch_flip(struct drm_device * dev)
518 {
519 drm_i915_private_t *dev_priv = dev->dev_private;
520 struct drm_i915_master_private *master_priv =
521 dev->primary->master->driver_priv;
522 int ret;
523
524 if (!master_priv->sarea_priv)
525 return -EINVAL;
526
527 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
528 __func__,
529 dev_priv->current_page,
530 master_priv->sarea_priv->pf_current_page);
531
532 i915_kernel_lost_context(dev);
533
534 ret = BEGIN_LP_RING(10);
535 if (ret)
536 return ret;
537
538 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
539 OUT_RING(0);
540
541 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
542 OUT_RING(0);
543 if (dev_priv->current_page == 0) {
544 OUT_RING(dev_priv->back_offset);
545 dev_priv->current_page = 1;
546 } else {
547 OUT_RING(dev_priv->front_offset);
548 dev_priv->current_page = 0;
549 }
550 OUT_RING(0);
551
552 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
553 OUT_RING(0);
554
555 ADVANCE_LP_RING();
556
557 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
558
559 if (BEGIN_LP_RING(4) == 0) {
560 OUT_RING(MI_STORE_DWORD_INDEX);
561 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
562 OUT_RING(dev_priv->counter);
563 OUT_RING(0);
564 ADVANCE_LP_RING();
565 }
566
567 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
568 return 0;
569 }
570
571 static int i915_quiescent(struct drm_device *dev)
572 {
573 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
574
575 i915_kernel_lost_context(dev);
576 return intel_wait_ring_buffer(ring, ring->size - 8);
577 }
578
579 static int i915_flush_ioctl(struct drm_device *dev, void *data,
580 struct drm_file *file_priv)
581 {
582 int ret;
583
584 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
585
586 mutex_lock(&dev->struct_mutex);
587 ret = i915_quiescent(dev);
588 mutex_unlock(&dev->struct_mutex);
589
590 return ret;
591 }
592
593 static int i915_batchbuffer(struct drm_device *dev, void *data,
594 struct drm_file *file_priv)
595 {
596 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
597 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
598 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
599 master_priv->sarea_priv;
600 drm_i915_batchbuffer_t *batch = data;
601 int ret;
602 struct drm_clip_rect *cliprects = NULL;
603
604 if (!dev_priv->allow_batchbuffer) {
605 DRM_ERROR("Batchbuffer ioctl disabled\n");
606 return -EINVAL;
607 }
608
609 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
610 batch->start, batch->used, batch->num_cliprects);
611
612 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
613
614 if (batch->num_cliprects < 0)
615 return -EINVAL;
616
617 if (batch->num_cliprects) {
618 cliprects = kcalloc(batch->num_cliprects,
619 sizeof(struct drm_clip_rect),
620 GFP_KERNEL);
621 if (cliprects == NULL)
622 return -ENOMEM;
623
624 ret = copy_from_user(cliprects, batch->cliprects,
625 batch->num_cliprects *
626 sizeof(struct drm_clip_rect));
627 if (ret != 0) {
628 ret = -EFAULT;
629 goto fail_free;
630 }
631 }
632
633 mutex_lock(&dev->struct_mutex);
634 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
635 mutex_unlock(&dev->struct_mutex);
636
637 if (sarea_priv)
638 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
639
640 fail_free:
641 kfree(cliprects);
642
643 return ret;
644 }
645
646 static int i915_cmdbuffer(struct drm_device *dev, void *data,
647 struct drm_file *file_priv)
648 {
649 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
650 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
651 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
652 master_priv->sarea_priv;
653 drm_i915_cmdbuffer_t *cmdbuf = data;
654 struct drm_clip_rect *cliprects = NULL;
655 void *batch_data;
656 int ret;
657
658 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
659 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
660
661 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
662
663 if (cmdbuf->num_cliprects < 0)
664 return -EINVAL;
665
666 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
667 if (batch_data == NULL)
668 return -ENOMEM;
669
670 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
671 if (ret != 0) {
672 ret = -EFAULT;
673 goto fail_batch_free;
674 }
675
676 if (cmdbuf->num_cliprects) {
677 cliprects = kcalloc(cmdbuf->num_cliprects,
678 sizeof(struct drm_clip_rect), GFP_KERNEL);
679 if (cliprects == NULL) {
680 ret = -ENOMEM;
681 goto fail_batch_free;
682 }
683
684 ret = copy_from_user(cliprects, cmdbuf->cliprects,
685 cmdbuf->num_cliprects *
686 sizeof(struct drm_clip_rect));
687 if (ret != 0) {
688 ret = -EFAULT;
689 goto fail_clip_free;
690 }
691 }
692
693 mutex_lock(&dev->struct_mutex);
694 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
695 mutex_unlock(&dev->struct_mutex);
696 if (ret) {
697 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
698 goto fail_clip_free;
699 }
700
701 if (sarea_priv)
702 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
703
704 fail_clip_free:
705 kfree(cliprects);
706 fail_batch_free:
707 kfree(batch_data);
708
709 return ret;
710 }
711
712 static int i915_flip_bufs(struct drm_device *dev, void *data,
713 struct drm_file *file_priv)
714 {
715 int ret;
716
717 DRM_DEBUG_DRIVER("%s\n", __func__);
718
719 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
720
721 mutex_lock(&dev->struct_mutex);
722 ret = i915_dispatch_flip(dev);
723 mutex_unlock(&dev->struct_mutex);
724
725 return ret;
726 }
727
728 static int i915_getparam(struct drm_device *dev, void *data,
729 struct drm_file *file_priv)
730 {
731 drm_i915_private_t *dev_priv = dev->dev_private;
732 drm_i915_getparam_t *param = data;
733 int value;
734
735 if (!dev_priv) {
736 DRM_ERROR("called with no initialization\n");
737 return -EINVAL;
738 }
739
740 switch (param->param) {
741 case I915_PARAM_IRQ_ACTIVE:
742 value = dev->pdev->irq ? 1 : 0;
743 break;
744 case I915_PARAM_ALLOW_BATCHBUFFER:
745 value = dev_priv->allow_batchbuffer ? 1 : 0;
746 break;
747 case I915_PARAM_LAST_DISPATCH:
748 value = READ_BREADCRUMB(dev_priv);
749 break;
750 case I915_PARAM_CHIPSET_ID:
751 value = dev->pci_device;
752 break;
753 case I915_PARAM_HAS_GEM:
754 value = dev_priv->has_gem;
755 break;
756 case I915_PARAM_NUM_FENCES_AVAIL:
757 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
758 break;
759 case I915_PARAM_HAS_OVERLAY:
760 value = dev_priv->overlay ? 1 : 0;
761 break;
762 case I915_PARAM_HAS_PAGEFLIPPING:
763 value = 1;
764 break;
765 case I915_PARAM_HAS_EXECBUF2:
766 /* depends on GEM */
767 value = dev_priv->has_gem;
768 break;
769 case I915_PARAM_HAS_BSD:
770 value = HAS_BSD(dev);
771 break;
772 case I915_PARAM_HAS_BLT:
773 value = HAS_BLT(dev);
774 break;
775 case I915_PARAM_HAS_RELAXED_FENCING:
776 value = 1;
777 break;
778 case I915_PARAM_HAS_COHERENT_RINGS:
779 value = 1;
780 break;
781 default:
782 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
783 param->param);
784 return -EINVAL;
785 }
786
787 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
788 DRM_ERROR("DRM_COPY_TO_USER failed\n");
789 return -EFAULT;
790 }
791
792 return 0;
793 }
794
795 static int i915_setparam(struct drm_device *dev, void *data,
796 struct drm_file *file_priv)
797 {
798 drm_i915_private_t *dev_priv = dev->dev_private;
799 drm_i915_setparam_t *param = data;
800
801 if (!dev_priv) {
802 DRM_ERROR("called with no initialization\n");
803 return -EINVAL;
804 }
805
806 switch (param->param) {
807 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
808 break;
809 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
810 dev_priv->tex_lru_log_granularity = param->value;
811 break;
812 case I915_SETPARAM_ALLOW_BATCHBUFFER:
813 dev_priv->allow_batchbuffer = param->value;
814 break;
815 case I915_SETPARAM_NUM_USED_FENCES:
816 if (param->value > dev_priv->num_fence_regs ||
817 param->value < 0)
818 return -EINVAL;
819 /* Userspace can use first N regs */
820 dev_priv->fence_reg_start = param->value;
821 break;
822 default:
823 DRM_DEBUG_DRIVER("unknown parameter %d\n",
824 param->param);
825 return -EINVAL;
826 }
827
828 return 0;
829 }
830
831 static int i915_set_status_page(struct drm_device *dev, void *data,
832 struct drm_file *file_priv)
833 {
834 drm_i915_private_t *dev_priv = dev->dev_private;
835 drm_i915_hws_addr_t *hws = data;
836 struct intel_ring_buffer *ring = LP_RING(dev_priv);
837
838 if (!I915_NEED_GFX_HWS(dev))
839 return -EINVAL;
840
841 if (!dev_priv) {
842 DRM_ERROR("called with no initialization\n");
843 return -EINVAL;
844 }
845
846 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
847 WARN(1, "tried to set status page when mode setting active\n");
848 return 0;
849 }
850
851 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
852
853 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
854
855 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
856 dev_priv->hws_map.size = 4*1024;
857 dev_priv->hws_map.type = 0;
858 dev_priv->hws_map.flags = 0;
859 dev_priv->hws_map.mtrr = 0;
860
861 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
862 if (dev_priv->hws_map.handle == NULL) {
863 i915_dma_cleanup(dev);
864 ring->status_page.gfx_addr = 0;
865 DRM_ERROR("can not ioremap virtual address for"
866 " G33 hw status page\n");
867 return -ENOMEM;
868 }
869 ring->status_page.page_addr = dev_priv->hws_map.handle;
870 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
871 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
872
873 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
874 ring->status_page.gfx_addr);
875 DRM_DEBUG_DRIVER("load hws at %p\n",
876 ring->status_page.page_addr);
877 return 0;
878 }
879
880 static int i915_get_bridge_dev(struct drm_device *dev)
881 {
882 struct drm_i915_private *dev_priv = dev->dev_private;
883
884 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
885 if (!dev_priv->bridge_dev) {
886 DRM_ERROR("bridge device not found\n");
887 return -1;
888 }
889 return 0;
890 }
891
892 #define MCHBAR_I915 0x44
893 #define MCHBAR_I965 0x48
894 #define MCHBAR_SIZE (4*4096)
895
896 #define DEVEN_REG 0x54
897 #define DEVEN_MCHBAR_EN (1 << 28)
898
899 /* Allocate space for the MCH regs if needed, return nonzero on error */
900 static int
901 intel_alloc_mchbar_resource(struct drm_device *dev)
902 {
903 drm_i915_private_t *dev_priv = dev->dev_private;
904 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
905 u32 temp_lo, temp_hi = 0;
906 u64 mchbar_addr;
907 int ret;
908
909 if (INTEL_INFO(dev)->gen >= 4)
910 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
911 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
912 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
913
914 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
915 #ifdef CONFIG_PNP
916 if (mchbar_addr &&
917 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
918 return 0;
919 #endif
920
921 /* Get some space for it */
922 dev_priv->mch_res.name = "i915 MCHBAR";
923 dev_priv->mch_res.flags = IORESOURCE_MEM;
924 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
925 &dev_priv->mch_res,
926 MCHBAR_SIZE, MCHBAR_SIZE,
927 PCIBIOS_MIN_MEM,
928 0, pcibios_align_resource,
929 dev_priv->bridge_dev);
930 if (ret) {
931 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
932 dev_priv->mch_res.start = 0;
933 return ret;
934 }
935
936 if (INTEL_INFO(dev)->gen >= 4)
937 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
938 upper_32_bits(dev_priv->mch_res.start));
939
940 pci_write_config_dword(dev_priv->bridge_dev, reg,
941 lower_32_bits(dev_priv->mch_res.start));
942 return 0;
943 }
944
945 /* Setup MCHBAR if possible, return true if we should disable it again */
946 static void
947 intel_setup_mchbar(struct drm_device *dev)
948 {
949 drm_i915_private_t *dev_priv = dev->dev_private;
950 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
951 u32 temp;
952 bool enabled;
953
954 dev_priv->mchbar_need_disable = false;
955
956 if (IS_I915G(dev) || IS_I915GM(dev)) {
957 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
958 enabled = !!(temp & DEVEN_MCHBAR_EN);
959 } else {
960 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
961 enabled = temp & 1;
962 }
963
964 /* If it's already enabled, don't have to do anything */
965 if (enabled)
966 return;
967
968 if (intel_alloc_mchbar_resource(dev))
969 return;
970
971 dev_priv->mchbar_need_disable = true;
972
973 /* Space is allocated or reserved, so enable it. */
974 if (IS_I915G(dev) || IS_I915GM(dev)) {
975 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
976 temp | DEVEN_MCHBAR_EN);
977 } else {
978 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
979 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
980 }
981 }
982
983 static void
984 intel_teardown_mchbar(struct drm_device *dev)
985 {
986 drm_i915_private_t *dev_priv = dev->dev_private;
987 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
988 u32 temp;
989
990 if (dev_priv->mchbar_need_disable) {
991 if (IS_I915G(dev) || IS_I915GM(dev)) {
992 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
993 temp &= ~DEVEN_MCHBAR_EN;
994 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
995 } else {
996 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
997 temp &= ~1;
998 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
999 }
1000 }
1001
1002 if (dev_priv->mch_res.start)
1003 release_resource(&dev_priv->mch_res);
1004 }
1005
1006 #define PTE_ADDRESS_MASK 0xfffff000
1007 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1008 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1009 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1010 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1011 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1012 #define PTE_VALID (1 << 0)
1013
1014 /**
1015 * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1016 * a physical one
1017 * @dev: drm device
1018 * @offset: address to translate
1019 *
1020 * Some chip functions require allocations from stolen space and need the
1021 * physical address of the memory in question.
1022 */
1023 static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
1024 {
1025 struct drm_i915_private *dev_priv = dev->dev_private;
1026 struct pci_dev *pdev = dev_priv->bridge_dev;
1027 u32 base;
1028
1029 #if 0
1030 /* On the machines I have tested the Graphics Base of Stolen Memory
1031 * is unreliable, so compute the base by subtracting the stolen memory
1032 * from the Top of Low Usable DRAM which is where the BIOS places
1033 * the graphics stolen memory.
1034 */
1035 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1036 /* top 32bits are reserved = 0 */
1037 pci_read_config_dword(pdev, 0xA4, &base);
1038 } else {
1039 /* XXX presume 8xx is the same as i915 */
1040 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1041 }
1042 #else
1043 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1044 u16 val;
1045 pci_read_config_word(pdev, 0xb0, &val);
1046 base = val >> 4 << 20;
1047 } else {
1048 u8 val;
1049 pci_read_config_byte(pdev, 0x9c, &val);
1050 base = val >> 3 << 27;
1051 }
1052 base -= dev_priv->mm.gtt->stolen_size;
1053 #endif
1054
1055 return base + offset;
1056 }
1057
1058 static void i915_warn_stolen(struct drm_device *dev)
1059 {
1060 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1061 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1062 }
1063
1064 static void i915_setup_compression(struct drm_device *dev, int size)
1065 {
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1068 unsigned long cfb_base;
1069 unsigned long ll_base = 0;
1070
1071 compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1072 if (compressed_fb)
1073 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1074 if (!compressed_fb)
1075 goto err;
1076
1077 cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1078 if (!cfb_base)
1079 goto err_fb;
1080
1081 if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
1082 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1083 4096, 4096, 0);
1084 if (compressed_llb)
1085 compressed_llb = drm_mm_get_block(compressed_llb,
1086 4096, 4096);
1087 if (!compressed_llb)
1088 goto err_fb;
1089
1090 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1091 if (!ll_base)
1092 goto err_llb;
1093 }
1094
1095 dev_priv->cfb_size = size;
1096
1097 intel_disable_fbc(dev);
1098 dev_priv->compressed_fb = compressed_fb;
1099 if (HAS_PCH_SPLIT(dev))
1100 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1101 else if (IS_GM45(dev)) {
1102 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1103 } else {
1104 I915_WRITE(FBC_CFB_BASE, cfb_base);
1105 I915_WRITE(FBC_LL_BASE, ll_base);
1106 dev_priv->compressed_llb = compressed_llb;
1107 }
1108
1109 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1110 cfb_base, ll_base, size >> 20);
1111 return;
1112
1113 err_llb:
1114 drm_mm_put_block(compressed_llb);
1115 err_fb:
1116 drm_mm_put_block(compressed_fb);
1117 err:
1118 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1119 i915_warn_stolen(dev);
1120 }
1121
1122 static void i915_cleanup_compression(struct drm_device *dev)
1123 {
1124 struct drm_i915_private *dev_priv = dev->dev_private;
1125
1126 drm_mm_put_block(dev_priv->compressed_fb);
1127 if (dev_priv->compressed_llb)
1128 drm_mm_put_block(dev_priv->compressed_llb);
1129 }
1130
1131 /* true = enable decode, false = disable decoder */
1132 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1133 {
1134 struct drm_device *dev = cookie;
1135
1136 intel_modeset_vga_set_state(dev, state);
1137 if (state)
1138 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1139 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1140 else
1141 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1142 }
1143
1144 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1145 {
1146 struct drm_device *dev = pci_get_drvdata(pdev);
1147 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1148 if (state == VGA_SWITCHEROO_ON) {
1149 printk(KERN_INFO "i915: switched on\n");
1150 /* i915 resume handler doesn't set to D0 */
1151 pci_set_power_state(dev->pdev, PCI_D0);
1152 i915_resume(dev);
1153 } else {
1154 printk(KERN_ERR "i915: switched off\n");
1155 i915_suspend(dev, pmm);
1156 }
1157 }
1158
1159 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1160 {
1161 struct drm_device *dev = pci_get_drvdata(pdev);
1162 bool can_switch;
1163
1164 spin_lock(&dev->count_lock);
1165 can_switch = (dev->open_count == 0);
1166 spin_unlock(&dev->count_lock);
1167 return can_switch;
1168 }
1169
1170 static int i915_load_modeset_init(struct drm_device *dev)
1171 {
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 unsigned long prealloc_size, gtt_size, mappable_size;
1174 int ret = 0;
1175
1176 prealloc_size = dev_priv->mm.gtt->stolen_size;
1177 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1178 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1179
1180 /* Basic memrange allocator for stolen space */
1181 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1182
1183 /* Let GEM Manage all of the aperture.
1184 *
1185 * However, leave one page at the end still bound to the scratch page.
1186 * There are a number of places where the hardware apparently
1187 * prefetches past the end of the object, and we've seen multiple
1188 * hangs with the GPU head pointer stuck in a batchbuffer bound
1189 * at the last page of the aperture. One page should be enough to
1190 * keep any prefetching inside of the aperture.
1191 */
1192 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1193
1194 mutex_lock(&dev->struct_mutex);
1195 ret = i915_gem_init_ringbuffer(dev);
1196 mutex_unlock(&dev->struct_mutex);
1197 if (ret)
1198 goto out;
1199
1200 /* Try to set up FBC with a reasonable compressed buffer size */
1201 if (I915_HAS_FBC(dev) && i915_powersave) {
1202 int cfb_size;
1203
1204 /* Leave 1M for line length buffer & misc. */
1205
1206 /* Try to get a 32M buffer... */
1207 if (prealloc_size > (36*1024*1024))
1208 cfb_size = 32*1024*1024;
1209 else /* fall back to 7/8 of the stolen space */
1210 cfb_size = prealloc_size * 7 / 8;
1211 i915_setup_compression(dev, cfb_size);
1212 }
1213
1214 /* Allow hardware batchbuffers unless told otherwise. */
1215 dev_priv->allow_batchbuffer = 1;
1216
1217 ret = intel_parse_bios(dev);
1218 if (ret)
1219 DRM_INFO("failed to find VBIOS tables\n");
1220
1221 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1222 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1223 if (ret)
1224 goto cleanup_ringbuffer;
1225
1226 intel_register_dsm_handler();
1227
1228 ret = vga_switcheroo_register_client(dev->pdev,
1229 i915_switcheroo_set_state,
1230 i915_switcheroo_can_switch);
1231 if (ret)
1232 goto cleanup_vga_client;
1233
1234 /* IIR "flip pending" bit means done if this bit is set */
1235 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1236 dev_priv->flip_pending_is_done = true;
1237
1238 intel_modeset_init(dev);
1239
1240 ret = drm_irq_install(dev);
1241 if (ret)
1242 goto cleanup_vga_switcheroo;
1243
1244 /* Always safe in the mode setting case. */
1245 /* FIXME: do pre/post-mode set stuff in core KMS code */
1246 dev->vblank_disable_allowed = 1;
1247
1248 ret = intel_fbdev_init(dev);
1249 if (ret)
1250 goto cleanup_irq;
1251
1252 drm_kms_helper_poll_init(dev);
1253
1254 /* We're off and running w/KMS */
1255 dev_priv->mm.suspended = 0;
1256
1257 return 0;
1258
1259 cleanup_irq:
1260 drm_irq_uninstall(dev);
1261 cleanup_vga_switcheroo:
1262 vga_switcheroo_unregister_client(dev->pdev);
1263 cleanup_vga_client:
1264 vga_client_register(dev->pdev, NULL, NULL, NULL);
1265 cleanup_ringbuffer:
1266 mutex_lock(&dev->struct_mutex);
1267 i915_gem_cleanup_ringbuffer(dev);
1268 mutex_unlock(&dev->struct_mutex);
1269 out:
1270 return ret;
1271 }
1272
1273 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1274 {
1275 struct drm_i915_master_private *master_priv;
1276
1277 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1278 if (!master_priv)
1279 return -ENOMEM;
1280
1281 master->driver_priv = master_priv;
1282 return 0;
1283 }
1284
1285 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1286 {
1287 struct drm_i915_master_private *master_priv = master->driver_priv;
1288
1289 if (!master_priv)
1290 return;
1291
1292 kfree(master_priv);
1293
1294 master->driver_priv = NULL;
1295 }
1296
1297 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1298 {
1299 drm_i915_private_t *dev_priv = dev->dev_private;
1300 u32 tmp;
1301
1302 tmp = I915_READ(CLKCFG);
1303
1304 switch (tmp & CLKCFG_FSB_MASK) {
1305 case CLKCFG_FSB_533:
1306 dev_priv->fsb_freq = 533; /* 133*4 */
1307 break;
1308 case CLKCFG_FSB_800:
1309 dev_priv->fsb_freq = 800; /* 200*4 */
1310 break;
1311 case CLKCFG_FSB_667:
1312 dev_priv->fsb_freq = 667; /* 167*4 */
1313 break;
1314 case CLKCFG_FSB_400:
1315 dev_priv->fsb_freq = 400; /* 100*4 */
1316 break;
1317 }
1318
1319 switch (tmp & CLKCFG_MEM_MASK) {
1320 case CLKCFG_MEM_533:
1321 dev_priv->mem_freq = 533;
1322 break;
1323 case CLKCFG_MEM_667:
1324 dev_priv->mem_freq = 667;
1325 break;
1326 case CLKCFG_MEM_800:
1327 dev_priv->mem_freq = 800;
1328 break;
1329 }
1330
1331 /* detect pineview DDR3 setting */
1332 tmp = I915_READ(CSHRDDR3CTL);
1333 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1334 }
1335
1336 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1337 {
1338 drm_i915_private_t *dev_priv = dev->dev_private;
1339 u16 ddrpll, csipll;
1340
1341 ddrpll = I915_READ16(DDRMPLL1);
1342 csipll = I915_READ16(CSIPLL0);
1343
1344 switch (ddrpll & 0xff) {
1345 case 0xc:
1346 dev_priv->mem_freq = 800;
1347 break;
1348 case 0x10:
1349 dev_priv->mem_freq = 1066;
1350 break;
1351 case 0x14:
1352 dev_priv->mem_freq = 1333;
1353 break;
1354 case 0x18:
1355 dev_priv->mem_freq = 1600;
1356 break;
1357 default:
1358 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1359 ddrpll & 0xff);
1360 dev_priv->mem_freq = 0;
1361 break;
1362 }
1363
1364 dev_priv->r_t = dev_priv->mem_freq;
1365
1366 switch (csipll & 0x3ff) {
1367 case 0x00c:
1368 dev_priv->fsb_freq = 3200;
1369 break;
1370 case 0x00e:
1371 dev_priv->fsb_freq = 3733;
1372 break;
1373 case 0x010:
1374 dev_priv->fsb_freq = 4266;
1375 break;
1376 case 0x012:
1377 dev_priv->fsb_freq = 4800;
1378 break;
1379 case 0x014:
1380 dev_priv->fsb_freq = 5333;
1381 break;
1382 case 0x016:
1383 dev_priv->fsb_freq = 5866;
1384 break;
1385 case 0x018:
1386 dev_priv->fsb_freq = 6400;
1387 break;
1388 default:
1389 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1390 csipll & 0x3ff);
1391 dev_priv->fsb_freq = 0;
1392 break;
1393 }
1394
1395 if (dev_priv->fsb_freq == 3200) {
1396 dev_priv->c_m = 0;
1397 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1398 dev_priv->c_m = 1;
1399 } else {
1400 dev_priv->c_m = 2;
1401 }
1402 }
1403
1404 static const struct cparams {
1405 u16 i;
1406 u16 t;
1407 u16 m;
1408 u16 c;
1409 } cparams[] = {
1410 { 1, 1333, 301, 28664 },
1411 { 1, 1066, 294, 24460 },
1412 { 1, 800, 294, 25192 },
1413 { 0, 1333, 276, 27605 },
1414 { 0, 1066, 276, 27605 },
1415 { 0, 800, 231, 23784 },
1416 };
1417
1418 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1419 {
1420 u64 total_count, diff, ret;
1421 u32 count1, count2, count3, m = 0, c = 0;
1422 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1423 int i;
1424
1425 diff1 = now - dev_priv->last_time1;
1426
1427 count1 = I915_READ(DMIEC);
1428 count2 = I915_READ(DDREC);
1429 count3 = I915_READ(CSIEC);
1430
1431 total_count = count1 + count2 + count3;
1432
1433 /* FIXME: handle per-counter overflow */
1434 if (total_count < dev_priv->last_count1) {
1435 diff = ~0UL - dev_priv->last_count1;
1436 diff += total_count;
1437 } else {
1438 diff = total_count - dev_priv->last_count1;
1439 }
1440
1441 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1442 if (cparams[i].i == dev_priv->c_m &&
1443 cparams[i].t == dev_priv->r_t) {
1444 m = cparams[i].m;
1445 c = cparams[i].c;
1446 break;
1447 }
1448 }
1449
1450 diff = div_u64(diff, diff1);
1451 ret = ((m * diff) + c);
1452 ret = div_u64(ret, 10);
1453
1454 dev_priv->last_count1 = total_count;
1455 dev_priv->last_time1 = now;
1456
1457 return ret;
1458 }
1459
1460 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1461 {
1462 unsigned long m, x, b;
1463 u32 tsfs;
1464
1465 tsfs = I915_READ(TSFS);
1466
1467 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1468 x = I915_READ8(TR1);
1469
1470 b = tsfs & TSFS_INTR_MASK;
1471
1472 return ((m * x) / 127) - b;
1473 }
1474
1475 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1476 {
1477 static const struct v_table {
1478 u16 vd; /* in .1 mil */
1479 u16 vm; /* in .1 mil */
1480 } v_table[] = {
1481 { 0, 0, },
1482 { 375, 0, },
1483 { 500, 0, },
1484 { 625, 0, },
1485 { 750, 0, },
1486 { 875, 0, },
1487 { 1000, 0, },
1488 { 1125, 0, },
1489 { 4125, 3000, },
1490 { 4125, 3000, },
1491 { 4125, 3000, },
1492 { 4125, 3000, },
1493 { 4125, 3000, },
1494 { 4125, 3000, },
1495 { 4125, 3000, },
1496 { 4125, 3000, },
1497 { 4125, 3000, },
1498 { 4125, 3000, },
1499 { 4125, 3000, },
1500 { 4125, 3000, },
1501 { 4125, 3000, },
1502 { 4125, 3000, },
1503 { 4125, 3000, },
1504 { 4125, 3000, },
1505 { 4125, 3000, },
1506 { 4125, 3000, },
1507 { 4125, 3000, },
1508 { 4125, 3000, },
1509 { 4125, 3000, },
1510 { 4125, 3000, },
1511 { 4125, 3000, },
1512 { 4125, 3000, },
1513 { 4250, 3125, },
1514 { 4375, 3250, },
1515 { 4500, 3375, },
1516 { 4625, 3500, },
1517 { 4750, 3625, },
1518 { 4875, 3750, },
1519 { 5000, 3875, },
1520 { 5125, 4000, },
1521 { 5250, 4125, },
1522 { 5375, 4250, },
1523 { 5500, 4375, },
1524 { 5625, 4500, },
1525 { 5750, 4625, },
1526 { 5875, 4750, },
1527 { 6000, 4875, },
1528 { 6125, 5000, },
1529 { 6250, 5125, },
1530 { 6375, 5250, },
1531 { 6500, 5375, },
1532 { 6625, 5500, },
1533 { 6750, 5625, },
1534 { 6875, 5750, },
1535 { 7000, 5875, },
1536 { 7125, 6000, },
1537 { 7250, 6125, },
1538 { 7375, 6250, },
1539 { 7500, 6375, },
1540 { 7625, 6500, },
1541 { 7750, 6625, },
1542 { 7875, 6750, },
1543 { 8000, 6875, },
1544 { 8125, 7000, },
1545 { 8250, 7125, },
1546 { 8375, 7250, },
1547 { 8500, 7375, },
1548 { 8625, 7500, },
1549 { 8750, 7625, },
1550 { 8875, 7750, },
1551 { 9000, 7875, },
1552 { 9125, 8000, },
1553 { 9250, 8125, },
1554 { 9375, 8250, },
1555 { 9500, 8375, },
1556 { 9625, 8500, },
1557 { 9750, 8625, },
1558 { 9875, 8750, },
1559 { 10000, 8875, },
1560 { 10125, 9000, },
1561 { 10250, 9125, },
1562 { 10375, 9250, },
1563 { 10500, 9375, },
1564 { 10625, 9500, },
1565 { 10750, 9625, },
1566 { 10875, 9750, },
1567 { 11000, 9875, },
1568 { 11125, 10000, },
1569 { 11250, 10125, },
1570 { 11375, 10250, },
1571 { 11500, 10375, },
1572 { 11625, 10500, },
1573 { 11750, 10625, },
1574 { 11875, 10750, },
1575 { 12000, 10875, },
1576 { 12125, 11000, },
1577 { 12250, 11125, },
1578 { 12375, 11250, },
1579 { 12500, 11375, },
1580 { 12625, 11500, },
1581 { 12750, 11625, },
1582 { 12875, 11750, },
1583 { 13000, 11875, },
1584 { 13125, 12000, },
1585 { 13250, 12125, },
1586 { 13375, 12250, },
1587 { 13500, 12375, },
1588 { 13625, 12500, },
1589 { 13750, 12625, },
1590 { 13875, 12750, },
1591 { 14000, 12875, },
1592 { 14125, 13000, },
1593 { 14250, 13125, },
1594 { 14375, 13250, },
1595 { 14500, 13375, },
1596 { 14625, 13500, },
1597 { 14750, 13625, },
1598 { 14875, 13750, },
1599 { 15000, 13875, },
1600 { 15125, 14000, },
1601 { 15250, 14125, },
1602 { 15375, 14250, },
1603 { 15500, 14375, },
1604 { 15625, 14500, },
1605 { 15750, 14625, },
1606 { 15875, 14750, },
1607 { 16000, 14875, },
1608 { 16125, 15000, },
1609 };
1610 if (dev_priv->info->is_mobile)
1611 return v_table[pxvid].vm;
1612 else
1613 return v_table[pxvid].vd;
1614 }
1615
1616 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1617 {
1618 struct timespec now, diff1;
1619 u64 diff;
1620 unsigned long diffms;
1621 u32 count;
1622
1623 getrawmonotonic(&now);
1624 diff1 = timespec_sub(now, dev_priv->last_time2);
1625
1626 /* Don't divide by 0 */
1627 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1628 if (!diffms)
1629 return;
1630
1631 count = I915_READ(GFXEC);
1632
1633 if (count < dev_priv->last_count2) {
1634 diff = ~0UL - dev_priv->last_count2;
1635 diff += count;
1636 } else {
1637 diff = count - dev_priv->last_count2;
1638 }
1639
1640 dev_priv->last_count2 = count;
1641 dev_priv->last_time2 = now;
1642
1643 /* More magic constants... */
1644 diff = diff * 1181;
1645 diff = div_u64(diff, diffms * 10);
1646 dev_priv->gfx_power = diff;
1647 }
1648
1649 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1650 {
1651 unsigned long t, corr, state1, corr2, state2;
1652 u32 pxvid, ext_v;
1653
1654 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1655 pxvid = (pxvid >> 24) & 0x7f;
1656 ext_v = pvid_to_extvid(dev_priv, pxvid);
1657
1658 state1 = ext_v;
1659
1660 t = i915_mch_val(dev_priv);
1661
1662 /* Revel in the empirically derived constants */
1663
1664 /* Correction factor in 1/100000 units */
1665 if (t > 80)
1666 corr = ((t * 2349) + 135940);
1667 else if (t >= 50)
1668 corr = ((t * 964) + 29317);
1669 else /* < 50 */
1670 corr = ((t * 301) + 1004);
1671
1672 corr = corr * ((150142 * state1) / 10000 - 78642);
1673 corr /= 100000;
1674 corr2 = (corr * dev_priv->corr);
1675
1676 state2 = (corr2 * state1) / 10000;
1677 state2 /= 100; /* convert to mW */
1678
1679 i915_update_gfx_val(dev_priv);
1680
1681 return dev_priv->gfx_power + state2;
1682 }
1683
1684 /* Global for IPS driver to get at the current i915 device */
1685 static struct drm_i915_private *i915_mch_dev;
1686 /*
1687 * Lock protecting IPS related data structures
1688 * - i915_mch_dev
1689 * - dev_priv->max_delay
1690 * - dev_priv->min_delay
1691 * - dev_priv->fmax
1692 * - dev_priv->gpu_busy
1693 */
1694 static DEFINE_SPINLOCK(mchdev_lock);
1695
1696 /**
1697 * i915_read_mch_val - return value for IPS use
1698 *
1699 * Calculate and return a value for the IPS driver to use when deciding whether
1700 * we have thermal and power headroom to increase CPU or GPU power budget.
1701 */
1702 unsigned long i915_read_mch_val(void)
1703 {
1704 struct drm_i915_private *dev_priv;
1705 unsigned long chipset_val, graphics_val, ret = 0;
1706
1707 spin_lock(&mchdev_lock);
1708 if (!i915_mch_dev)
1709 goto out_unlock;
1710 dev_priv = i915_mch_dev;
1711
1712 chipset_val = i915_chipset_val(dev_priv);
1713 graphics_val = i915_gfx_val(dev_priv);
1714
1715 ret = chipset_val + graphics_val;
1716
1717 out_unlock:
1718 spin_unlock(&mchdev_lock);
1719
1720 return ret;
1721 }
1722 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1723
1724 /**
1725 * i915_gpu_raise - raise GPU frequency limit
1726 *
1727 * Raise the limit; IPS indicates we have thermal headroom.
1728 */
1729 bool i915_gpu_raise(void)
1730 {
1731 struct drm_i915_private *dev_priv;
1732 bool ret = true;
1733
1734 spin_lock(&mchdev_lock);
1735 if (!i915_mch_dev) {
1736 ret = false;
1737 goto out_unlock;
1738 }
1739 dev_priv = i915_mch_dev;
1740
1741 if (dev_priv->max_delay > dev_priv->fmax)
1742 dev_priv->max_delay--;
1743
1744 out_unlock:
1745 spin_unlock(&mchdev_lock);
1746
1747 return ret;
1748 }
1749 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1750
1751 /**
1752 * i915_gpu_lower - lower GPU frequency limit
1753 *
1754 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1755 * frequency maximum.
1756 */
1757 bool i915_gpu_lower(void)
1758 {
1759 struct drm_i915_private *dev_priv;
1760 bool ret = true;
1761
1762 spin_lock(&mchdev_lock);
1763 if (!i915_mch_dev) {
1764 ret = false;
1765 goto out_unlock;
1766 }
1767 dev_priv = i915_mch_dev;
1768
1769 if (dev_priv->max_delay < dev_priv->min_delay)
1770 dev_priv->max_delay++;
1771
1772 out_unlock:
1773 spin_unlock(&mchdev_lock);
1774
1775 return ret;
1776 }
1777 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1778
1779 /**
1780 * i915_gpu_busy - indicate GPU business to IPS
1781 *
1782 * Tell the IPS driver whether or not the GPU is busy.
1783 */
1784 bool i915_gpu_busy(void)
1785 {
1786 struct drm_i915_private *dev_priv;
1787 bool ret = false;
1788
1789 spin_lock(&mchdev_lock);
1790 if (!i915_mch_dev)
1791 goto out_unlock;
1792 dev_priv = i915_mch_dev;
1793
1794 ret = dev_priv->busy;
1795
1796 out_unlock:
1797 spin_unlock(&mchdev_lock);
1798
1799 return ret;
1800 }
1801 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1802
1803 /**
1804 * i915_gpu_turbo_disable - disable graphics turbo
1805 *
1806 * Disable graphics turbo by resetting the max frequency and setting the
1807 * current frequency to the default.
1808 */
1809 bool i915_gpu_turbo_disable(void)
1810 {
1811 struct drm_i915_private *dev_priv;
1812 bool ret = true;
1813
1814 spin_lock(&mchdev_lock);
1815 if (!i915_mch_dev) {
1816 ret = false;
1817 goto out_unlock;
1818 }
1819 dev_priv = i915_mch_dev;
1820
1821 dev_priv->max_delay = dev_priv->fstart;
1822
1823 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1824 ret = false;
1825
1826 out_unlock:
1827 spin_unlock(&mchdev_lock);
1828
1829 return ret;
1830 }
1831 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1832
1833 /**
1834 * i915_driver_load - setup chip and create an initial config
1835 * @dev: DRM device
1836 * @flags: startup flags
1837 *
1838 * The driver load routine has to do several things:
1839 * - drive output discovery via intel_modeset_init()
1840 * - initialize the memory manager
1841 * - allocate initial config memory
1842 * - setup the DRM framebuffer with the allocated memory
1843 */
1844 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1845 {
1846 struct drm_i915_private *dev_priv;
1847 int ret = 0, mmio_bar;
1848 uint32_t agp_size;
1849
1850 /* i915 has 4 more counters */
1851 dev->counters += 4;
1852 dev->types[6] = _DRM_STAT_IRQ;
1853 dev->types[7] = _DRM_STAT_PRIMARY;
1854 dev->types[8] = _DRM_STAT_SECONDARY;
1855 dev->types[9] = _DRM_STAT_DMA;
1856
1857 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1858 if (dev_priv == NULL)
1859 return -ENOMEM;
1860
1861 dev->dev_private = (void *)dev_priv;
1862 dev_priv->dev = dev;
1863 dev_priv->info = (struct intel_device_info *) flags;
1864
1865 if (i915_get_bridge_dev(dev)) {
1866 ret = -EIO;
1867 goto free_priv;
1868 }
1869
1870 /* overlay on gen2 is broken and can't address above 1G */
1871 if (IS_GEN2(dev))
1872 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1873
1874 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1875 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1876 if (!dev_priv->regs) {
1877 DRM_ERROR("failed to map registers\n");
1878 ret = -EIO;
1879 goto put_bridge;
1880 }
1881
1882 dev_priv->mm.gtt = intel_gtt_get();
1883 if (!dev_priv->mm.gtt) {
1884 DRM_ERROR("Failed to initialize GTT\n");
1885 ret = -ENODEV;
1886 goto out_iomapfree;
1887 }
1888
1889 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1890
1891 dev_priv->mm.gtt_mapping =
1892 io_mapping_create_wc(dev->agp->base, agp_size);
1893 if (dev_priv->mm.gtt_mapping == NULL) {
1894 ret = -EIO;
1895 goto out_rmmap;
1896 }
1897
1898 /* Set up a WC MTRR for non-PAT systems. This is more common than
1899 * one would think, because the kernel disables PAT on first
1900 * generation Core chips because WC PAT gets overridden by a UC
1901 * MTRR if present. Even if a UC MTRR isn't present.
1902 */
1903 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1904 agp_size,
1905 MTRR_TYPE_WRCOMB, 1);
1906 if (dev_priv->mm.gtt_mtrr < 0) {
1907 DRM_INFO("MTRR allocation failed. Graphics "
1908 "performance may suffer.\n");
1909 }
1910
1911 /* The i915 workqueue is primarily used for batched retirement of
1912 * requests (and thus managing bo) once the task has been completed
1913 * by the GPU. i915_gem_retire_requests() is called directly when we
1914 * need high-priority retirement, such as waiting for an explicit
1915 * bo.
1916 *
1917 * It is also used for periodic low-priority events, such as
1918 * idle-timers and recording error state.
1919 *
1920 * All tasks on the workqueue are expected to acquire the dev mutex
1921 * so there is no point in running more than one instance of the
1922 * workqueue at any time: max_active = 1 and NON_REENTRANT.
1923 */
1924 dev_priv->wq = alloc_workqueue("i915",
1925 WQ_UNBOUND | WQ_NON_REENTRANT,
1926 1);
1927 if (dev_priv->wq == NULL) {
1928 DRM_ERROR("Failed to create our workqueue.\n");
1929 ret = -ENOMEM;
1930 goto out_iomapfree;
1931 }
1932
1933 /* enable GEM by default */
1934 dev_priv->has_gem = 1;
1935
1936 if (dev_priv->has_gem == 0 &&
1937 drm_core_check_feature(dev, DRIVER_MODESET)) {
1938 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
1939 ret = -ENODEV;
1940 goto out_workqueue_free;
1941 }
1942
1943 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1944 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1945 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
1946 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1947 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1948 }
1949
1950 /* Try to make sure MCHBAR is enabled before poking at it */
1951 intel_setup_mchbar(dev);
1952 intel_setup_gmbus(dev);
1953 intel_opregion_setup(dev);
1954
1955 /* Make sure the bios did its job and set up vital registers */
1956 intel_setup_bios(dev);
1957
1958 i915_gem_load(dev);
1959
1960 /* Init HWS */
1961 if (!I915_NEED_GFX_HWS(dev)) {
1962 ret = i915_init_phys_hws(dev);
1963 if (ret)
1964 goto out_gem_unload;
1965 }
1966
1967 if (IS_PINEVIEW(dev))
1968 i915_pineview_get_mem_freq(dev);
1969 else if (IS_GEN5(dev))
1970 i915_ironlake_get_mem_freq(dev);
1971
1972 /* On the 945G/GM, the chipset reports the MSI capability on the
1973 * integrated graphics even though the support isn't actually there
1974 * according to the published specs. It doesn't appear to function
1975 * correctly in testing on 945G.
1976 * This may be a side effect of MSI having been made available for PEG
1977 * and the registers being closely associated.
1978 *
1979 * According to chipset errata, on the 965GM, MSI interrupts may
1980 * be lost or delayed, but we use them anyways to avoid
1981 * stuck interrupts on some machines.
1982 */
1983 if (!IS_I945G(dev) && !IS_I945GM(dev))
1984 pci_enable_msi(dev->pdev);
1985
1986 spin_lock_init(&dev_priv->irq_lock);
1987 spin_lock_init(&dev_priv->error_lock);
1988 dev_priv->trace_irq_seqno = 0;
1989
1990 ret = drm_vblank_init(dev, I915_NUM_PIPE);
1991 if (ret)
1992 goto out_gem_unload;
1993
1994 /* Start out suspended */
1995 dev_priv->mm.suspended = 1;
1996
1997 intel_detect_pch(dev);
1998
1999 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2000 ret = i915_load_modeset_init(dev);
2001 if (ret < 0) {
2002 DRM_ERROR("failed to init modeset\n");
2003 goto out_gem_unload;
2004 }
2005 }
2006
2007 /* Must be done after probing outputs */
2008 intel_opregion_init(dev);
2009 acpi_video_register();
2010
2011 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2012 (unsigned long) dev);
2013
2014 spin_lock(&mchdev_lock);
2015 i915_mch_dev = dev_priv;
2016 dev_priv->mchdev_lock = &mchdev_lock;
2017 spin_unlock(&mchdev_lock);
2018
2019 return 0;
2020
2021 out_gem_unload:
2022 if (dev->pdev->msi_enabled)
2023 pci_disable_msi(dev->pdev);
2024
2025 intel_teardown_gmbus(dev);
2026 intel_teardown_mchbar(dev);
2027 out_workqueue_free:
2028 destroy_workqueue(dev_priv->wq);
2029 out_iomapfree:
2030 io_mapping_free(dev_priv->mm.gtt_mapping);
2031 out_rmmap:
2032 pci_iounmap(dev->pdev, dev_priv->regs);
2033 put_bridge:
2034 pci_dev_put(dev_priv->bridge_dev);
2035 free_priv:
2036 kfree(dev_priv);
2037 return ret;
2038 }
2039
2040 int i915_driver_unload(struct drm_device *dev)
2041 {
2042 struct drm_i915_private *dev_priv = dev->dev_private;
2043 int ret;
2044
2045 spin_lock(&mchdev_lock);
2046 i915_mch_dev = NULL;
2047 spin_unlock(&mchdev_lock);
2048
2049 if (dev_priv->mm.inactive_shrinker.shrink)
2050 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2051
2052 mutex_lock(&dev->struct_mutex);
2053 ret = i915_gpu_idle(dev);
2054 if (ret)
2055 DRM_ERROR("failed to idle hardware: %d\n", ret);
2056 mutex_unlock(&dev->struct_mutex);
2057
2058 /* Cancel the retire work handler, which should be idle now. */
2059 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2060
2061 io_mapping_free(dev_priv->mm.gtt_mapping);
2062 if (dev_priv->mm.gtt_mtrr >= 0) {
2063 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2064 dev->agp->agp_info.aper_size * 1024 * 1024);
2065 dev_priv->mm.gtt_mtrr = -1;
2066 }
2067
2068 acpi_video_unregister();
2069
2070 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2071 intel_fbdev_fini(dev);
2072 intel_modeset_cleanup(dev);
2073
2074 /*
2075 * free the memory space allocated for the child device
2076 * config parsed from VBT
2077 */
2078 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2079 kfree(dev_priv->child_dev);
2080 dev_priv->child_dev = NULL;
2081 dev_priv->child_dev_num = 0;
2082 }
2083
2084 vga_switcheroo_unregister_client(dev->pdev);
2085 vga_client_register(dev->pdev, NULL, NULL, NULL);
2086 }
2087
2088 /* Free error state after interrupts are fully disabled. */
2089 del_timer_sync(&dev_priv->hangcheck_timer);
2090 cancel_work_sync(&dev_priv->error_work);
2091 i915_destroy_error_state(dev);
2092
2093 if (dev->pdev->msi_enabled)
2094 pci_disable_msi(dev->pdev);
2095
2096 intel_opregion_fini(dev);
2097
2098 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2099 /* Flush any outstanding unpin_work. */
2100 flush_workqueue(dev_priv->wq);
2101
2102 i915_gem_free_all_phys_object(dev);
2103
2104 mutex_lock(&dev->struct_mutex);
2105 i915_gem_cleanup_ringbuffer(dev);
2106 mutex_unlock(&dev->struct_mutex);
2107 if (I915_HAS_FBC(dev) && i915_powersave)
2108 i915_cleanup_compression(dev);
2109 drm_mm_takedown(&dev_priv->mm.stolen);
2110
2111 intel_cleanup_overlay(dev);
2112
2113 if (!I915_NEED_GFX_HWS(dev))
2114 i915_free_hws(dev);
2115 }
2116
2117 if (dev_priv->regs != NULL)
2118 pci_iounmap(dev->pdev, dev_priv->regs);
2119
2120 intel_teardown_gmbus(dev);
2121 intel_teardown_mchbar(dev);
2122
2123 destroy_workqueue(dev_priv->wq);
2124
2125 pci_dev_put(dev_priv->bridge_dev);
2126 kfree(dev->dev_private);
2127
2128 return 0;
2129 }
2130
2131 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2132 {
2133 struct drm_i915_file_private *file_priv;
2134
2135 DRM_DEBUG_DRIVER("\n");
2136 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2137 if (!file_priv)
2138 return -ENOMEM;
2139
2140 file->driver_priv = file_priv;
2141
2142 spin_lock_init(&file_priv->mm.lock);
2143 INIT_LIST_HEAD(&file_priv->mm.request_list);
2144
2145 return 0;
2146 }
2147
2148 /**
2149 * i915_driver_lastclose - clean up after all DRM clients have exited
2150 * @dev: DRM device
2151 *
2152 * Take care of cleaning up after all DRM clients have exited. In the
2153 * mode setting case, we want to restore the kernel's initial mode (just
2154 * in case the last client left us in a bad state).
2155 *
2156 * Additionally, in the non-mode setting case, we'll tear down the AGP
2157 * and DMA structures, since the kernel won't be using them, and clea
2158 * up any GEM state.
2159 */
2160 void i915_driver_lastclose(struct drm_device * dev)
2161 {
2162 drm_i915_private_t *dev_priv = dev->dev_private;
2163
2164 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2165 drm_fb_helper_restore();
2166 vga_switcheroo_process_delayed_switch();
2167 return;
2168 }
2169
2170 i915_gem_lastclose(dev);
2171
2172 if (dev_priv->agp_heap)
2173 i915_mem_takedown(&(dev_priv->agp_heap));
2174
2175 i915_dma_cleanup(dev);
2176 }
2177
2178 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2179 {
2180 drm_i915_private_t *dev_priv = dev->dev_private;
2181 i915_gem_release(dev, file_priv);
2182 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2183 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2184 }
2185
2186 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2187 {
2188 struct drm_i915_file_private *file_priv = file->driver_priv;
2189
2190 kfree(file_priv);
2191 }
2192
2193 struct drm_ioctl_desc i915_ioctls[] = {
2194 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2195 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2196 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2197 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2198 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2199 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2200 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2201 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2202 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2203 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2204 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2205 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2206 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2207 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2208 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2209 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2210 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2211 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2212 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2213 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2214 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2215 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2216 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2217 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2218 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2219 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2220 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2221 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2222 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2223 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2224 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2225 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2226 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2227 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2228 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2229 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2230 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2231 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2232 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2233 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2234 };
2235
2236 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2237
2238 /**
2239 * Determine if the device really is AGP or not.
2240 *
2241 * All Intel graphics chipsets are treated as AGP, even if they are really
2242 * PCI-e.
2243 *
2244 * \param dev The device to be tested.
2245 *
2246 * \returns
2247 * A value of 1 is always retured to indictate every i9x5 is AGP.
2248 */
2249 int i915_driver_device_is_agp(struct drm_device * dev)
2250 {
2251 return 1;
2252 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree