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drm/i915: Turn on a required 3D clock gating bit on Sandybridge.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blob6ebfbb6a5590575d0e2ce5a20198d8cc8dbef929
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include "drmP.h"
35 #include "intel_drv.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "i915_trace.h"
39 #include "drm_dp_helper.h"
40
41 #include "drm_crtc_helper.h"
42
43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44
45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
46 static void intel_update_watermarks(struct drm_device *dev);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
86 static bool
87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
89
90 static bool
91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
93 static bool
94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
96
97 static inline u32 /* units of 100MHz */
98 intel_fdi_link_freq(struct drm_device *dev)
99 {
100 if (IS_GEN5(dev)) {
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
103 } else
104 return 27;
105 }
106
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
118 .find_pll = intel_find_best_PLL,
119 };
120
121 static const intel_limit_t intel_limits_i8xx_lvds = {
122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
132 .find_pll = intel_find_best_PLL,
133 };
134
135 static const intel_limit_t intel_limits_i9xx_sdvo = {
136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
146 .find_pll = intel_find_best_PLL,
147 };
148
149 static const intel_limit_t intel_limits_i9xx_lvds = {
150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
160 .find_pll = intel_find_best_PLL,
161 };
162
163
164 static const intel_limit_t intel_limits_g4x_sdvo = {
165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
174 .p2_slow = 10,
175 .p2_fast = 10
176 },
177 .find_pll = intel_g4x_find_best_PLL,
178 };
179
180 static const intel_limit_t intel_limits_g4x_hdmi = {
181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
191 .find_pll = intel_g4x_find_best_PLL,
192 };
193
194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
205 },
206 .find_pll = intel_g4x_find_best_PLL,
207 };
208
209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
220 },
221 .find_pll = intel_g4x_find_best_PLL,
222 };
223
224 static const intel_limit_t intel_limits_g4x_display_port = {
225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
235 .find_pll = intel_find_pll_g4x_dp,
236 };
237
238 static const intel_limit_t intel_limits_pineview_sdvo = {
239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
251 .find_pll = intel_find_best_PLL,
252 };
253
254 static const intel_limit_t intel_limits_pineview_lvds = {
255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
265 .find_pll = intel_find_best_PLL,
266 };
267
268 /* Ironlake / Sandybridge
269 *
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
272 */
273 static const intel_limit_t intel_limits_ironlake_dac = {
274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_g4x_find_best_PLL,
285 };
286
287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_g4x_find_best_PLL,
299 };
300
301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
312 .find_pll = intel_g4x_find_best_PLL,
313 };
314
315 /* LVDS 100mhz refclk limits. */
316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 .find_pll = intel_g4x_find_best_PLL,
328 };
329
330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341 .find_pll = intel_g4x_find_best_PLL,
342 };
343
344 static const intel_limit_t intel_limits_ironlake_display_port = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
355 .find_pll = intel_find_pll_ironlake_dp,
356 };
357
358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359 int refclk)
360 {
361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
363 const intel_limit_t *limit;
364
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
369 if (refclk == 100000)
370 limit = &intel_limits_ironlake_dual_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_dual_lvds;
373 } else {
374 if (refclk == 100000)
375 limit = &intel_limits_ironlake_single_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_single_lvds;
378 }
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
380 HAS_eDP)
381 limit = &intel_limits_ironlake_display_port;
382 else
383 limit = &intel_limits_ironlake_dac;
384
385 return limit;
386 }
387
388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
389 {
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
393
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
396 LVDS_CLKB_POWER_UP)
397 /* LVDS with dual channel */
398 limit = &intel_limits_g4x_dual_channel_lvds;
399 else
400 /* LVDS with dual channel */
401 limit = &intel_limits_g4x_single_channel_lvds;
402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
404 limit = &intel_limits_g4x_hdmi;
405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
406 limit = &intel_limits_g4x_sdvo;
407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
408 limit = &intel_limits_g4x_display_port;
409 } else /* The option is for other outputs */
410 limit = &intel_limits_i9xx_sdvo;
411
412 return limit;
413 }
414
415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
416 {
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
419
420 if (HAS_PCH_SPLIT(dev))
421 limit = intel_ironlake_limit(crtc, refclk);
422 else if (IS_G4X(dev)) {
423 limit = intel_g4x_limit(crtc);
424 } else if (IS_PINEVIEW(dev)) {
425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
426 limit = &intel_limits_pineview_lvds;
427 else
428 limit = &intel_limits_pineview_sdvo;
429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
432 else
433 limit = &intel_limits_i9xx_sdvo;
434 } else {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i8xx_lvds;
437 else
438 limit = &intel_limits_i8xx_dvo;
439 }
440 return limit;
441 }
442
443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
444 static void pineview_clock(int refclk, intel_clock_t *clock)
445 {
446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
450 }
451
452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
453 {
454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
456 return;
457 }
458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
462 }
463
464 /**
465 * Returns whether any output on the specified pipe is of the specified type
466 */
467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
468 {
469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
472
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
475 return true;
476
477 return false;
478 }
479
480 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
481 /**
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
484 */
485
486 static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
489 {
490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
508 */
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
511
512 return true;
513 }
514
515 static bool
516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
518
519 {
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
522 intel_clock_t clock;
523 int err = target;
524
525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
526 (I915_READ(LVDS)) != 0) {
527 /*
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
531 * even can.
532 */
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534 LVDS_CLKB_POWER_UP)
535 clock.p2 = limit->p2.p2_fast;
536 else
537 clock.p2 = limit->p2.p2_slow;
538 } else {
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
541 else
542 clock.p2 = limit->p2.p2_fast;
543 }
544
545 memset (best_clock, 0, sizeof (*best_clock));
546
547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548 clock.m1++) {
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
553 break;
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
558 int this_err;
559
560 intel_clock(dev, refclk, &clock);
561 if (!intel_PLL_is_valid(dev, limit,
562 &clock))
563 continue;
564
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
567 *best_clock = clock;
568 err = this_err;
569 }
570 }
571 }
572 }
573 }
574
575 return (err != target);
576 }
577
578 static bool
579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
581 {
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 intel_clock_t clock;
585 int max_n;
586 bool found;
587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
589 found = false;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
592 int lvds_reg;
593
594 if (HAS_PCH_SPLIT(dev))
595 lvds_reg = PCH_LVDS;
596 else
597 lvds_reg = LVDS;
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
599 LVDS_CLKB_POWER_UP)
600 clock.p2 = limit->p2.p2_fast;
601 else
602 clock.p2 = limit->p2.p2_slow;
603 } else {
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
606 else
607 clock.p2 = limit->p2.p2_fast;
608 }
609
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
612 /* based on hardware requirement, prefer smaller n to precision */
613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
614 /* based on hardware requirement, prefere larger m1,m2 */
615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
621 int this_err;
622
623 intel_clock(dev, refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627
628 this_err = abs(clock.dot - target);
629 if (this_err < err_most) {
630 *best_clock = clock;
631 err_most = this_err;
632 max_n = clock.n;
633 found = true;
634 }
635 }
636 }
637 }
638 }
639 return found;
640 }
641
642 static bool
643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
645 {
646 struct drm_device *dev = crtc->dev;
647 intel_clock_t clock;
648
649 if (target < 200000) {
650 clock.n = 1;
651 clock.p1 = 2;
652 clock.p2 = 10;
653 clock.m1 = 12;
654 clock.m2 = 9;
655 } else {
656 clock.n = 2;
657 clock.p1 = 1;
658 clock.p2 = 10;
659 clock.m1 = 14;
660 clock.m2 = 8;
661 }
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
664 return true;
665 }
666
667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
668 static bool
669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
671 {
672 intel_clock_t clock;
673 if (target < 200000) {
674 clock.p1 = 2;
675 clock.p2 = 10;
676 clock.n = 2;
677 clock.m1 = 23;
678 clock.m2 = 8;
679 } else {
680 clock.p1 = 1;
681 clock.p2 = 10;
682 clock.n = 1;
683 clock.m1 = 14;
684 clock.m2 = 2;
685 }
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
689 clock.vco = 0;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
691 return true;
692 }
693
694 /**
695 * intel_wait_for_vblank - wait for vblank on a given pipe
696 * @dev: drm device
697 * @pipe: pipe to wait for
698 *
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
700 * mode setting code.
701 */
702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
703 {
704 struct drm_i915_private *dev_priv = dev->dev_private;
705 int pipestat_reg = PIPESTAT(pipe);
706
707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
709 *
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
716 * vblanks...
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
719 */
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
722
723 /* Wait for vblank interrupt bit to set */
724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
726 50))
727 DRM_DEBUG_KMS("vblank wait timed out\n");
728 }
729
730 /*
731 * intel_wait_for_pipe_off - wait for pipe to turn off
732 * @dev: drm device
733 * @pipe: pipe to wait for
734 *
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
738 *
739 * On Gen4 and above:
740 * wait for the pipe register state bit to turn off
741 *
742 * Otherwise:
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
745 *
746 */
747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
748 {
749 struct drm_i915_private *dev_priv = dev->dev_private;
750
751 if (INTEL_INFO(dev)->gen >= 4) {
752 int reg = PIPECONF(pipe);
753
754 /* Wait for the Pipe State to go off */
755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
756 100))
757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
758 } else {
759 u32 last_line;
760 int reg = PIPEDSL(pipe);
761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
762
763 /* Wait for the display line to settle */
764 do {
765 last_line = I915_READ(reg) & DSL_LINEMASK;
766 mdelay(5);
767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
771 }
772 }
773
774 static const char *state_string(bool enabled)
775 {
776 return enabled ? "on" : "off";
777 }
778
779 /* Only for pre-ILK configs */
780 static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
782 {
783 int reg;
784 u32 val;
785 bool cur_state;
786
787 reg = DPLL(pipe);
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
793 }
794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
796
797 /* For ILK+ */
798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
800 {
801 int reg;
802 u32 val;
803 bool cur_state;
804
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
811 }
812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814
815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
817 {
818 int reg;
819 u32 val;
820 bool cur_state;
821
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
828 }
829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831
832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
834 {
835 int reg;
836 u32 val;
837 bool cur_state;
838
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
845 }
846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848
849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
850 enum pipe pipe)
851 {
852 int reg;
853 u32 val;
854
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
857 return;
858
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
862 }
863
864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
865 enum pipe pipe)
866 {
867 int reg;
868 u32 val;
869
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
873 }
874
875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
876 enum pipe pipe)
877 {
878 int pp_reg, lvds_reg;
879 u32 val;
880 enum pipe panel_pipe = PIPE_A;
881 bool locked = true;
882
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
885 lvds_reg = PCH_LVDS;
886 } else {
887 pp_reg = PP_CONTROL;
888 lvds_reg = LVDS;
889 }
890
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
894 locked = false;
895
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
897 panel_pipe = PIPE_B;
898
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
901 pipe_name(pipe));
902 }
903
904 static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
906 {
907 int reg;
908 u32 val;
909 bool cur_state;
910
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
916 pipe_name(pipe), state_string(state), state_string(cur_state));
917 }
918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
920
921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
922 enum plane plane)
923 {
924 int reg;
925 u32 val;
926
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
931 plane_name(plane));
932 }
933
934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
935 enum pipe pipe)
936 {
937 int reg, i;
938 u32 val;
939 int cur_pipe;
940
941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
943 return;
944
945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
947 reg = DSPCNTR(i);
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
954 }
955 }
956
957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
958 {
959 u32 val;
960 bool enabled;
961
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
966 }
967
968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
969 enum pipe pipe)
970 {
971 int reg;
972 u32 val;
973 bool enabled;
974
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
978 WARN(enabled,
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
980 pipe_name(pipe));
981 }
982
983 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
984 enum pipe pipe, u32 port_sel, u32 val)
985 {
986 if ((val & DP_PORT_EN) == 0)
987 return false;
988
989 if (HAS_PCH_CPT(dev_priv->dev)) {
990 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
991 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
992 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
993 return false;
994 } else {
995 if ((val & DP_PIPE_MASK) != (pipe << 30))
996 return false;
997 }
998 return true;
999 }
1000
1001 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe, u32 val)
1003 {
1004 if ((val & PORT_ENABLE) == 0)
1005 return false;
1006
1007 if (HAS_PCH_CPT(dev_priv->dev)) {
1008 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1009 return false;
1010 } else {
1011 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1012 return false;
1013 }
1014 return true;
1015 }
1016
1017 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, u32 val)
1019 {
1020 if ((val & LVDS_PORT_EN) == 0)
1021 return false;
1022
1023 if (HAS_PCH_CPT(dev_priv->dev)) {
1024 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1025 return false;
1026 } else {
1027 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1028 return false;
1029 }
1030 return true;
1031 }
1032
1033 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, u32 val)
1035 {
1036 if ((val & ADPA_DAC_ENABLE) == 0)
1037 return false;
1038 if (HAS_PCH_CPT(dev_priv->dev)) {
1039 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1040 return false;
1041 } else {
1042 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1043 return false;
1044 }
1045 return true;
1046 }
1047
1048 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1049 enum pipe pipe, int reg, u32 port_sel)
1050 {
1051 u32 val = I915_READ(reg);
1052 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1053 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1054 reg, pipe_name(pipe));
1055 }
1056
1057 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1058 enum pipe pipe, int reg)
1059 {
1060 u32 val = I915_READ(reg);
1061 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1062 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1063 reg, pipe_name(pipe));
1064 }
1065
1066 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1067 enum pipe pipe)
1068 {
1069 int reg;
1070 u32 val;
1071
1072 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1073 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1074 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1075
1076 reg = PCH_ADPA;
1077 val = I915_READ(reg);
1078 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1079 "PCH VGA enabled on transcoder %c, should be disabled\n",
1080 pipe_name(pipe));
1081
1082 reg = PCH_LVDS;
1083 val = I915_READ(reg);
1084 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1085 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1086 pipe_name(pipe));
1087
1088 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1089 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1090 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1091 }
1092
1093 /**
1094 * intel_enable_pll - enable a PLL
1095 * @dev_priv: i915 private structure
1096 * @pipe: pipe PLL to enable
1097 *
1098 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1099 * make sure the PLL reg is writable first though, since the panel write
1100 * protect mechanism may be enabled.
1101 *
1102 * Note! This is for pre-ILK only.
1103 */
1104 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1105 {
1106 int reg;
1107 u32 val;
1108
1109 /* No really, not for ILK+ */
1110 BUG_ON(dev_priv->info->gen >= 5);
1111
1112 /* PLL is protected by panel, make sure we can write it */
1113 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1114 assert_panel_unlocked(dev_priv, pipe);
1115
1116 reg = DPLL(pipe);
1117 val = I915_READ(reg);
1118 val |= DPLL_VCO_ENABLE;
1119
1120 /* We do this three times for luck */
1121 I915_WRITE(reg, val);
1122 POSTING_READ(reg);
1123 udelay(150); /* wait for warmup */
1124 I915_WRITE(reg, val);
1125 POSTING_READ(reg);
1126 udelay(150); /* wait for warmup */
1127 I915_WRITE(reg, val);
1128 POSTING_READ(reg);
1129 udelay(150); /* wait for warmup */
1130 }
1131
1132 /**
1133 * intel_disable_pll - disable a PLL
1134 * @dev_priv: i915 private structure
1135 * @pipe: pipe PLL to disable
1136 *
1137 * Disable the PLL for @pipe, making sure the pipe is off first.
1138 *
1139 * Note! This is for pre-ILK only.
1140 */
1141 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1142 {
1143 int reg;
1144 u32 val;
1145
1146 /* Don't disable pipe A or pipe A PLLs if needed */
1147 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1148 return;
1149
1150 /* Make sure the pipe isn't still relying on us */
1151 assert_pipe_disabled(dev_priv, pipe);
1152
1153 reg = DPLL(pipe);
1154 val = I915_READ(reg);
1155 val &= ~DPLL_VCO_ENABLE;
1156 I915_WRITE(reg, val);
1157 POSTING_READ(reg);
1158 }
1159
1160 /**
1161 * intel_enable_pch_pll - enable PCH PLL
1162 * @dev_priv: i915 private structure
1163 * @pipe: pipe PLL to enable
1164 *
1165 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1166 * drives the transcoder clock.
1167 */
1168 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1169 enum pipe pipe)
1170 {
1171 int reg;
1172 u32 val;
1173
1174 /* PCH only available on ILK+ */
1175 BUG_ON(dev_priv->info->gen < 5);
1176
1177 /* PCH refclock must be enabled first */
1178 assert_pch_refclk_enabled(dev_priv);
1179
1180 reg = PCH_DPLL(pipe);
1181 val = I915_READ(reg);
1182 val |= DPLL_VCO_ENABLE;
1183 I915_WRITE(reg, val);
1184 POSTING_READ(reg);
1185 udelay(200);
1186 }
1187
1188 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190 {
1191 int reg;
1192 u32 val;
1193
1194 /* PCH only available on ILK+ */
1195 BUG_ON(dev_priv->info->gen < 5);
1196
1197 /* Make sure transcoder isn't still depending on us */
1198 assert_transcoder_disabled(dev_priv, pipe);
1199
1200 reg = PCH_DPLL(pipe);
1201 val = I915_READ(reg);
1202 val &= ~DPLL_VCO_ENABLE;
1203 I915_WRITE(reg, val);
1204 POSTING_READ(reg);
1205 udelay(200);
1206 }
1207
1208 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1209 enum pipe pipe)
1210 {
1211 int reg;
1212 u32 val;
1213
1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1216
1217 /* Make sure PCH DPLL is enabled */
1218 assert_pch_pll_enabled(dev_priv, pipe);
1219
1220 /* FDI must be feeding us bits for PCH ports */
1221 assert_fdi_tx_enabled(dev_priv, pipe);
1222 assert_fdi_rx_enabled(dev_priv, pipe);
1223
1224 reg = TRANSCONF(pipe);
1225 val = I915_READ(reg);
1226
1227 if (HAS_PCH_IBX(dev_priv->dev)) {
1228 /*
1229 * make the BPC in transcoder be consistent with
1230 * that in pipeconf reg.
1231 */
1232 val &= ~PIPE_BPC_MASK;
1233 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1234 }
1235 I915_WRITE(reg, val | TRANS_ENABLE);
1236 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1237 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1238 }
1239
1240 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1241 enum pipe pipe)
1242 {
1243 int reg;
1244 u32 val;
1245
1246 /* FDI relies on the transcoder */
1247 assert_fdi_tx_disabled(dev_priv, pipe);
1248 assert_fdi_rx_disabled(dev_priv, pipe);
1249
1250 /* Ports must be off as well */
1251 assert_pch_ports_disabled(dev_priv, pipe);
1252
1253 reg = TRANSCONF(pipe);
1254 val = I915_READ(reg);
1255 val &= ~TRANS_ENABLE;
1256 I915_WRITE(reg, val);
1257 /* wait for PCH transcoder off, transcoder state */
1258 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1259 DRM_ERROR("failed to disable transcoder\n");
1260 }
1261
1262 /**
1263 * intel_enable_pipe - enable a pipe, asserting requirements
1264 * @dev_priv: i915 private structure
1265 * @pipe: pipe to enable
1266 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1267 *
1268 * Enable @pipe, making sure that various hardware specific requirements
1269 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1270 *
1271 * @pipe should be %PIPE_A or %PIPE_B.
1272 *
1273 * Will wait until the pipe is actually running (i.e. first vblank) before
1274 * returning.
1275 */
1276 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1277 bool pch_port)
1278 {
1279 int reg;
1280 u32 val;
1281
1282 /*
1283 * A pipe without a PLL won't actually be able to drive bits from
1284 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1285 * need the check.
1286 */
1287 if (!HAS_PCH_SPLIT(dev_priv->dev))
1288 assert_pll_enabled(dev_priv, pipe);
1289 else {
1290 if (pch_port) {
1291 /* if driving the PCH, we need FDI enabled */
1292 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1293 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1294 }
1295 /* FIXME: assert CPU port conditions for SNB+ */
1296 }
1297
1298 reg = PIPECONF(pipe);
1299 val = I915_READ(reg);
1300 if (val & PIPECONF_ENABLE)
1301 return;
1302
1303 I915_WRITE(reg, val | PIPECONF_ENABLE);
1304 intel_wait_for_vblank(dev_priv->dev, pipe);
1305 }
1306
1307 /**
1308 * intel_disable_pipe - disable a pipe, asserting requirements
1309 * @dev_priv: i915 private structure
1310 * @pipe: pipe to disable
1311 *
1312 * Disable @pipe, making sure that various hardware specific requirements
1313 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1314 *
1315 * @pipe should be %PIPE_A or %PIPE_B.
1316 *
1317 * Will wait until the pipe has shut down before returning.
1318 */
1319 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1320 enum pipe pipe)
1321 {
1322 int reg;
1323 u32 val;
1324
1325 /*
1326 * Make sure planes won't keep trying to pump pixels to us,
1327 * or we might hang the display.
1328 */
1329 assert_planes_disabled(dev_priv, pipe);
1330
1331 /* Don't disable pipe A or pipe A PLLs if needed */
1332 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1333 return;
1334
1335 reg = PIPECONF(pipe);
1336 val = I915_READ(reg);
1337 if ((val & PIPECONF_ENABLE) == 0)
1338 return;
1339
1340 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1341 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1342 }
1343
1344 /*
1345 * Plane regs are double buffered, going from enabled->disabled needs a
1346 * trigger in order to latch. The display address reg provides this.
1347 */
1348 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1349 enum plane plane)
1350 {
1351 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1352 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1353 }
1354
1355 /**
1356 * intel_enable_plane - enable a display plane on a given pipe
1357 * @dev_priv: i915 private structure
1358 * @plane: plane to enable
1359 * @pipe: pipe being fed
1360 *
1361 * Enable @plane on @pipe, making sure that @pipe is running first.
1362 */
1363 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1364 enum plane plane, enum pipe pipe)
1365 {
1366 int reg;
1367 u32 val;
1368
1369 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1370 assert_pipe_enabled(dev_priv, pipe);
1371
1372 reg = DSPCNTR(plane);
1373 val = I915_READ(reg);
1374 if (val & DISPLAY_PLANE_ENABLE)
1375 return;
1376
1377 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1378 intel_flush_display_plane(dev_priv, plane);
1379 intel_wait_for_vblank(dev_priv->dev, pipe);
1380 }
1381
1382 /**
1383 * intel_disable_plane - disable a display plane
1384 * @dev_priv: i915 private structure
1385 * @plane: plane to disable
1386 * @pipe: pipe consuming the data
1387 *
1388 * Disable @plane; should be an independent operation.
1389 */
1390 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1391 enum plane plane, enum pipe pipe)
1392 {
1393 int reg;
1394 u32 val;
1395
1396 reg = DSPCNTR(plane);
1397 val = I915_READ(reg);
1398 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1399 return;
1400
1401 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1402 intel_flush_display_plane(dev_priv, plane);
1403 intel_wait_for_vblank(dev_priv->dev, pipe);
1404 }
1405
1406 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, int reg, u32 port_sel)
1408 {
1409 u32 val = I915_READ(reg);
1410 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1411 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1412 I915_WRITE(reg, val & ~DP_PORT_EN);
1413 }
1414 }
1415
1416 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, int reg)
1418 {
1419 u32 val = I915_READ(reg);
1420 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1421 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1422 reg, pipe);
1423 I915_WRITE(reg, val & ~PORT_ENABLE);
1424 }
1425 }
1426
1427 /* Disable any ports connected to this transcoder */
1428 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1429 enum pipe pipe)
1430 {
1431 u32 reg, val;
1432
1433 val = I915_READ(PCH_PP_CONTROL);
1434 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1435
1436 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1437 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1438 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1439
1440 reg = PCH_ADPA;
1441 val = I915_READ(reg);
1442 if (adpa_pipe_enabled(dev_priv, val, pipe))
1443 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1444
1445 reg = PCH_LVDS;
1446 val = I915_READ(reg);
1447 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1448 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1449 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1450 POSTING_READ(reg);
1451 udelay(100);
1452 }
1453
1454 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1455 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1456 disable_pch_hdmi(dev_priv, pipe, HDMID);
1457 }
1458
1459 static void i8xx_disable_fbc(struct drm_device *dev)
1460 {
1461 struct drm_i915_private *dev_priv = dev->dev_private;
1462 u32 fbc_ctl;
1463
1464 /* Disable compression */
1465 fbc_ctl = I915_READ(FBC_CONTROL);
1466 if ((fbc_ctl & FBC_CTL_EN) == 0)
1467 return;
1468
1469 fbc_ctl &= ~FBC_CTL_EN;
1470 I915_WRITE(FBC_CONTROL, fbc_ctl);
1471
1472 /* Wait for compressing bit to clear */
1473 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1474 DRM_DEBUG_KMS("FBC idle timed out\n");
1475 return;
1476 }
1477
1478 DRM_DEBUG_KMS("disabled FBC\n");
1479 }
1480
1481 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1482 {
1483 struct drm_device *dev = crtc->dev;
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 struct drm_framebuffer *fb = crtc->fb;
1486 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1487 struct drm_i915_gem_object *obj = intel_fb->obj;
1488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1489 int cfb_pitch;
1490 int plane, i;
1491 u32 fbc_ctl, fbc_ctl2;
1492
1493 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1494 if (fb->pitch < cfb_pitch)
1495 cfb_pitch = fb->pitch;
1496
1497 /* FBC_CTL wants 64B units */
1498 cfb_pitch = (cfb_pitch / 64) - 1;
1499 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1500
1501 /* Clear old tags */
1502 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1503 I915_WRITE(FBC_TAG + (i * 4), 0);
1504
1505 /* Set it up... */
1506 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1507 fbc_ctl2 |= plane;
1508 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1509 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1510
1511 /* enable it... */
1512 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1513 if (IS_I945GM(dev))
1514 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1515 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1516 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1517 fbc_ctl |= obj->fence_reg;
1518 I915_WRITE(FBC_CONTROL, fbc_ctl);
1519
1520 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1521 cfb_pitch, crtc->y, intel_crtc->plane);
1522 }
1523
1524 static bool i8xx_fbc_enabled(struct drm_device *dev)
1525 {
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527
1528 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1529 }
1530
1531 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1532 {
1533 struct drm_device *dev = crtc->dev;
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 struct drm_framebuffer *fb = crtc->fb;
1536 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1537 struct drm_i915_gem_object *obj = intel_fb->obj;
1538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1539 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1540 unsigned long stall_watermark = 200;
1541 u32 dpfc_ctl;
1542
1543 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1544 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1545 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1546
1547 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1548 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1549 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1550 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1551
1552 /* enable it... */
1553 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1554
1555 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1556 }
1557
1558 static void g4x_disable_fbc(struct drm_device *dev)
1559 {
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 u32 dpfc_ctl;
1562
1563 /* Disable compression */
1564 dpfc_ctl = I915_READ(DPFC_CONTROL);
1565 if (dpfc_ctl & DPFC_CTL_EN) {
1566 dpfc_ctl &= ~DPFC_CTL_EN;
1567 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1568
1569 DRM_DEBUG_KMS("disabled FBC\n");
1570 }
1571 }
1572
1573 static bool g4x_fbc_enabled(struct drm_device *dev)
1574 {
1575 struct drm_i915_private *dev_priv = dev->dev_private;
1576
1577 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1578 }
1579
1580 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1581 {
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 u32 blt_ecoskpd;
1584
1585 /* Make sure blitter notifies FBC of writes */
1586 gen6_gt_force_wake_get(dev_priv);
1587 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1588 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1589 GEN6_BLITTER_LOCK_SHIFT;
1590 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1591 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1592 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1593 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1594 GEN6_BLITTER_LOCK_SHIFT);
1595 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1596 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1597 gen6_gt_force_wake_put(dev_priv);
1598 }
1599
1600 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1601 {
1602 struct drm_device *dev = crtc->dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 struct drm_framebuffer *fb = crtc->fb;
1605 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1606 struct drm_i915_gem_object *obj = intel_fb->obj;
1607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1608 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1609 unsigned long stall_watermark = 200;
1610 u32 dpfc_ctl;
1611
1612 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1613 dpfc_ctl &= DPFC_RESERVED;
1614 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1615 /* Set persistent mode for front-buffer rendering, ala X. */
1616 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1617 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1618 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1619
1620 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1621 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1622 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1623 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1624 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1625 /* enable it... */
1626 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1627
1628 if (IS_GEN6(dev)) {
1629 I915_WRITE(SNB_DPFC_CTL_SA,
1630 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1631 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1632 sandybridge_blit_fbc_update(dev);
1633 }
1634
1635 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1636 }
1637
1638 static void ironlake_disable_fbc(struct drm_device *dev)
1639 {
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 u32 dpfc_ctl;
1642
1643 /* Disable compression */
1644 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1645 if (dpfc_ctl & DPFC_CTL_EN) {
1646 dpfc_ctl &= ~DPFC_CTL_EN;
1647 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1648
1649 DRM_DEBUG_KMS("disabled FBC\n");
1650 }
1651 }
1652
1653 static bool ironlake_fbc_enabled(struct drm_device *dev)
1654 {
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656
1657 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1658 }
1659
1660 bool intel_fbc_enabled(struct drm_device *dev)
1661 {
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663
1664 if (!dev_priv->display.fbc_enabled)
1665 return false;
1666
1667 return dev_priv->display.fbc_enabled(dev);
1668 }
1669
1670 static void intel_fbc_work_fn(struct work_struct *__work)
1671 {
1672 struct intel_fbc_work *work =
1673 container_of(to_delayed_work(__work),
1674 struct intel_fbc_work, work);
1675 struct drm_device *dev = work->crtc->dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677
1678 mutex_lock(&dev->struct_mutex);
1679 if (work == dev_priv->fbc_work) {
1680 /* Double check that we haven't switched fb without cancelling
1681 * the prior work.
1682 */
1683 if (work->crtc->fb == work->fb) {
1684 dev_priv->display.enable_fbc(work->crtc,
1685 work->interval);
1686
1687 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1688 dev_priv->cfb_fb = work->crtc->fb->base.id;
1689 dev_priv->cfb_y = work->crtc->y;
1690 }
1691
1692 dev_priv->fbc_work = NULL;
1693 }
1694 mutex_unlock(&dev->struct_mutex);
1695
1696 kfree(work);
1697 }
1698
1699 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1700 {
1701 if (dev_priv->fbc_work == NULL)
1702 return;
1703
1704 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1705
1706 /* Synchronisation is provided by struct_mutex and checking of
1707 * dev_priv->fbc_work, so we can perform the cancellation
1708 * entirely asynchronously.
1709 */
1710 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1711 /* tasklet was killed before being run, clean up */
1712 kfree(dev_priv->fbc_work);
1713
1714 /* Mark the work as no longer wanted so that if it does
1715 * wake-up (because the work was already running and waiting
1716 * for our mutex), it will discover that is no longer
1717 * necessary to run.
1718 */
1719 dev_priv->fbc_work = NULL;
1720 }
1721
1722 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1723 {
1724 struct intel_fbc_work *work;
1725 struct drm_device *dev = crtc->dev;
1726 struct drm_i915_private *dev_priv = dev->dev_private;
1727
1728 if (!dev_priv->display.enable_fbc)
1729 return;
1730
1731 intel_cancel_fbc_work(dev_priv);
1732
1733 work = kzalloc(sizeof *work, GFP_KERNEL);
1734 if (work == NULL) {
1735 dev_priv->display.enable_fbc(crtc, interval);
1736 return;
1737 }
1738
1739 work->crtc = crtc;
1740 work->fb = crtc->fb;
1741 work->interval = interval;
1742 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1743
1744 dev_priv->fbc_work = work;
1745
1746 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1747
1748 /* Delay the actual enabling to let pageflipping cease and the
1749 * display to settle before starting the compression. Note that
1750 * this delay also serves a second purpose: it allows for a
1751 * vblank to pass after disabling the FBC before we attempt
1752 * to modify the control registers.
1753 *
1754 * A more complicated solution would involve tracking vblanks
1755 * following the termination of the page-flipping sequence
1756 * and indeed performing the enable as a co-routine and not
1757 * waiting synchronously upon the vblank.
1758 */
1759 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1760 }
1761
1762 void intel_disable_fbc(struct drm_device *dev)
1763 {
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765
1766 intel_cancel_fbc_work(dev_priv);
1767
1768 if (!dev_priv->display.disable_fbc)
1769 return;
1770
1771 dev_priv->display.disable_fbc(dev);
1772 dev_priv->cfb_plane = -1;
1773 }
1774
1775 /**
1776 * intel_update_fbc - enable/disable FBC as needed
1777 * @dev: the drm_device
1778 *
1779 * Set up the framebuffer compression hardware at mode set time. We
1780 * enable it if possible:
1781 * - plane A only (on pre-965)
1782 * - no pixel mulitply/line duplication
1783 * - no alpha buffer discard
1784 * - no dual wide
1785 * - framebuffer <= 2048 in width, 1536 in height
1786 *
1787 * We can't assume that any compression will take place (worst case),
1788 * so the compressed buffer has to be the same size as the uncompressed
1789 * one. It also must reside (along with the line length buffer) in
1790 * stolen memory.
1791 *
1792 * We need to enable/disable FBC on a global basis.
1793 */
1794 static void intel_update_fbc(struct drm_device *dev)
1795 {
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797 struct drm_crtc *crtc = NULL, *tmp_crtc;
1798 struct intel_crtc *intel_crtc;
1799 struct drm_framebuffer *fb;
1800 struct intel_framebuffer *intel_fb;
1801 struct drm_i915_gem_object *obj;
1802 int enable_fbc;
1803
1804 DRM_DEBUG_KMS("\n");
1805
1806 if (!i915_powersave)
1807 return;
1808
1809 if (!I915_HAS_FBC(dev))
1810 return;
1811
1812 /*
1813 * If FBC is already on, we just have to verify that we can
1814 * keep it that way...
1815 * Need to disable if:
1816 * - more than one pipe is active
1817 * - changing FBC params (stride, fence, mode)
1818 * - new fb is too large to fit in compressed buffer
1819 * - going to an unsupported config (interlace, pixel multiply, etc.)
1820 */
1821 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1822 if (tmp_crtc->enabled && tmp_crtc->fb) {
1823 if (crtc) {
1824 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1825 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1826 goto out_disable;
1827 }
1828 crtc = tmp_crtc;
1829 }
1830 }
1831
1832 if (!crtc || crtc->fb == NULL) {
1833 DRM_DEBUG_KMS("no output, disabling\n");
1834 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1835 goto out_disable;
1836 }
1837
1838 intel_crtc = to_intel_crtc(crtc);
1839 fb = crtc->fb;
1840 intel_fb = to_intel_framebuffer(fb);
1841 obj = intel_fb->obj;
1842
1843 enable_fbc = i915_enable_fbc;
1844 if (enable_fbc < 0) {
1845 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1846 enable_fbc = 1;
1847 if (INTEL_INFO(dev)->gen <= 5)
1848 enable_fbc = 0;
1849 }
1850 if (!enable_fbc) {
1851 DRM_DEBUG_KMS("fbc disabled per module param\n");
1852 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1853 goto out_disable;
1854 }
1855 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1856 DRM_DEBUG_KMS("framebuffer too large, disabling "
1857 "compression\n");
1858 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1859 goto out_disable;
1860 }
1861 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1862 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1863 DRM_DEBUG_KMS("mode incompatible with compression, "
1864 "disabling\n");
1865 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1866 goto out_disable;
1867 }
1868 if ((crtc->mode.hdisplay > 2048) ||
1869 (crtc->mode.vdisplay > 1536)) {
1870 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1871 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1872 goto out_disable;
1873 }
1874 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1875 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1876 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1877 goto out_disable;
1878 }
1879
1880 /* The use of a CPU fence is mandatory in order to detect writes
1881 * by the CPU to the scanout and trigger updates to the FBC.
1882 */
1883 if (obj->tiling_mode != I915_TILING_X ||
1884 obj->fence_reg == I915_FENCE_REG_NONE) {
1885 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1886 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1887 goto out_disable;
1888 }
1889
1890 /* If the kernel debugger is active, always disable compression */
1891 if (in_dbg_master())
1892 goto out_disable;
1893
1894 /* If the scanout has not changed, don't modify the FBC settings.
1895 * Note that we make the fundamental assumption that the fb->obj
1896 * cannot be unpinned (and have its GTT offset and fence revoked)
1897 * without first being decoupled from the scanout and FBC disabled.
1898 */
1899 if (dev_priv->cfb_plane == intel_crtc->plane &&
1900 dev_priv->cfb_fb == fb->base.id &&
1901 dev_priv->cfb_y == crtc->y)
1902 return;
1903
1904 if (intel_fbc_enabled(dev)) {
1905 /* We update FBC along two paths, after changing fb/crtc
1906 * configuration (modeswitching) and after page-flipping
1907 * finishes. For the latter, we know that not only did
1908 * we disable the FBC at the start of the page-flip
1909 * sequence, but also more than one vblank has passed.
1910 *
1911 * For the former case of modeswitching, it is possible
1912 * to switch between two FBC valid configurations
1913 * instantaneously so we do need to disable the FBC
1914 * before we can modify its control registers. We also
1915 * have to wait for the next vblank for that to take
1916 * effect. However, since we delay enabling FBC we can
1917 * assume that a vblank has passed since disabling and
1918 * that we can safely alter the registers in the deferred
1919 * callback.
1920 *
1921 * In the scenario that we go from a valid to invalid
1922 * and then back to valid FBC configuration we have
1923 * no strict enforcement that a vblank occurred since
1924 * disabling the FBC. However, along all current pipe
1925 * disabling paths we do need to wait for a vblank at
1926 * some point. And we wait before enabling FBC anyway.
1927 */
1928 DRM_DEBUG_KMS("disabling active FBC for update\n");
1929 intel_disable_fbc(dev);
1930 }
1931
1932 intel_enable_fbc(crtc, 500);
1933 return;
1934
1935 out_disable:
1936 /* Multiple disables should be harmless */
1937 if (intel_fbc_enabled(dev)) {
1938 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1939 intel_disable_fbc(dev);
1940 }
1941 }
1942
1943 int
1944 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1945 struct drm_i915_gem_object *obj,
1946 struct intel_ring_buffer *pipelined)
1947 {
1948 struct drm_i915_private *dev_priv = dev->dev_private;
1949 u32 alignment;
1950 int ret;
1951
1952 switch (obj->tiling_mode) {
1953 case I915_TILING_NONE:
1954 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1955 alignment = 128 * 1024;
1956 else if (INTEL_INFO(dev)->gen >= 4)
1957 alignment = 4 * 1024;
1958 else
1959 alignment = 64 * 1024;
1960 break;
1961 case I915_TILING_X:
1962 /* pin() will align the object as required by fence */
1963 alignment = 0;
1964 break;
1965 case I915_TILING_Y:
1966 /* FIXME: Is this true? */
1967 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1968 return -EINVAL;
1969 default:
1970 BUG();
1971 }
1972
1973 dev_priv->mm.interruptible = false;
1974 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1975 if (ret)
1976 goto err_interruptible;
1977
1978 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1979 * fence, whereas 965+ only requires a fence if using
1980 * framebuffer compression. For simplicity, we always install
1981 * a fence as the cost is not that onerous.
1982 */
1983 if (obj->tiling_mode != I915_TILING_NONE) {
1984 ret = i915_gem_object_get_fence(obj, pipelined);
1985 if (ret)
1986 goto err_unpin;
1987 }
1988
1989 dev_priv->mm.interruptible = true;
1990 return 0;
1991
1992 err_unpin:
1993 i915_gem_object_unpin(obj);
1994 err_interruptible:
1995 dev_priv->mm.interruptible = true;
1996 return ret;
1997 }
1998
1999 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2000 int x, int y)
2001 {
2002 struct drm_device *dev = crtc->dev;
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2005 struct intel_framebuffer *intel_fb;
2006 struct drm_i915_gem_object *obj;
2007 int plane = intel_crtc->plane;
2008 unsigned long Start, Offset;
2009 u32 dspcntr;
2010 u32 reg;
2011
2012 switch (plane) {
2013 case 0:
2014 case 1:
2015 break;
2016 default:
2017 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2018 return -EINVAL;
2019 }
2020
2021 intel_fb = to_intel_framebuffer(fb);
2022 obj = intel_fb->obj;
2023
2024 reg = DSPCNTR(plane);
2025 dspcntr = I915_READ(reg);
2026 /* Mask out pixel format bits in case we change it */
2027 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2028 switch (fb->bits_per_pixel) {
2029 case 8:
2030 dspcntr |= DISPPLANE_8BPP;
2031 break;
2032 case 16:
2033 if (fb->depth == 15)
2034 dspcntr |= DISPPLANE_15_16BPP;
2035 else
2036 dspcntr |= DISPPLANE_16BPP;
2037 break;
2038 case 24:
2039 case 32:
2040 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2041 break;
2042 default:
2043 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2044 return -EINVAL;
2045 }
2046 if (INTEL_INFO(dev)->gen >= 4) {
2047 if (obj->tiling_mode != I915_TILING_NONE)
2048 dspcntr |= DISPPLANE_TILED;
2049 else
2050 dspcntr &= ~DISPPLANE_TILED;
2051 }
2052
2053 I915_WRITE(reg, dspcntr);
2054
2055 Start = obj->gtt_offset;
2056 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2057
2058 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2059 Start, Offset, x, y, fb->pitch);
2060 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2061 if (INTEL_INFO(dev)->gen >= 4) {
2062 I915_WRITE(DSPSURF(plane), Start);
2063 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2064 I915_WRITE(DSPADDR(plane), Offset);
2065 } else
2066 I915_WRITE(DSPADDR(plane), Start + Offset);
2067 POSTING_READ(reg);
2068
2069 return 0;
2070 }
2071
2072 static int ironlake_update_plane(struct drm_crtc *crtc,
2073 struct drm_framebuffer *fb, int x, int y)
2074 {
2075 struct drm_device *dev = crtc->dev;
2076 struct drm_i915_private *dev_priv = dev->dev_private;
2077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2078 struct intel_framebuffer *intel_fb;
2079 struct drm_i915_gem_object *obj;
2080 int plane = intel_crtc->plane;
2081 unsigned long Start, Offset;
2082 u32 dspcntr;
2083 u32 reg;
2084
2085 switch (plane) {
2086 case 0:
2087 case 1:
2088 break;
2089 default:
2090 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2091 return -EINVAL;
2092 }
2093
2094 intel_fb = to_intel_framebuffer(fb);
2095 obj = intel_fb->obj;
2096
2097 reg = DSPCNTR(plane);
2098 dspcntr = I915_READ(reg);
2099 /* Mask out pixel format bits in case we change it */
2100 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2101 switch (fb->bits_per_pixel) {
2102 case 8:
2103 dspcntr |= DISPPLANE_8BPP;
2104 break;
2105 case 16:
2106 if (fb->depth != 16)
2107 return -EINVAL;
2108
2109 dspcntr |= DISPPLANE_16BPP;
2110 break;
2111 case 24:
2112 case 32:
2113 if (fb->depth == 24)
2114 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2115 else if (fb->depth == 30)
2116 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2117 else
2118 return -EINVAL;
2119 break;
2120 default:
2121 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2122 return -EINVAL;
2123 }
2124
2125 if (obj->tiling_mode != I915_TILING_NONE)
2126 dspcntr |= DISPPLANE_TILED;
2127 else
2128 dspcntr &= ~DISPPLANE_TILED;
2129
2130 /* must disable */
2131 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2132
2133 I915_WRITE(reg, dspcntr);
2134
2135 Start = obj->gtt_offset;
2136 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2137
2138 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2139 Start, Offset, x, y, fb->pitch);
2140 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2141 I915_WRITE(DSPSURF(plane), Start);
2142 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2143 I915_WRITE(DSPADDR(plane), Offset);
2144 POSTING_READ(reg);
2145
2146 return 0;
2147 }
2148
2149 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2150 static int
2151 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2152 int x, int y, enum mode_set_atomic state)
2153 {
2154 struct drm_device *dev = crtc->dev;
2155 struct drm_i915_private *dev_priv = dev->dev_private;
2156 int ret;
2157
2158 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2159 if (ret)
2160 return ret;
2161
2162 intel_update_fbc(dev);
2163 intel_increase_pllclock(crtc);
2164
2165 return 0;
2166 }
2167
2168 static int
2169 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2170 struct drm_framebuffer *old_fb)
2171 {
2172 struct drm_device *dev = crtc->dev;
2173 struct drm_i915_master_private *master_priv;
2174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2175 int ret;
2176
2177 /* no fb bound */
2178 if (!crtc->fb) {
2179 DRM_ERROR("No FB bound\n");
2180 return 0;
2181 }
2182
2183 switch (intel_crtc->plane) {
2184 case 0:
2185 case 1:
2186 break;
2187 default:
2188 DRM_ERROR("no plane for crtc\n");
2189 return -EINVAL;
2190 }
2191
2192 mutex_lock(&dev->struct_mutex);
2193 ret = intel_pin_and_fence_fb_obj(dev,
2194 to_intel_framebuffer(crtc->fb)->obj,
2195 NULL);
2196 if (ret != 0) {
2197 mutex_unlock(&dev->struct_mutex);
2198 DRM_ERROR("pin & fence failed\n");
2199 return ret;
2200 }
2201
2202 if (old_fb) {
2203 struct drm_i915_private *dev_priv = dev->dev_private;
2204 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2205
2206 wait_event(dev_priv->pending_flip_queue,
2207 atomic_read(&dev_priv->mm.wedged) ||
2208 atomic_read(&obj->pending_flip) == 0);
2209
2210 /* Big Hammer, we also need to ensure that any pending
2211 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2212 * current scanout is retired before unpinning the old
2213 * framebuffer.
2214 *
2215 * This should only fail upon a hung GPU, in which case we
2216 * can safely continue.
2217 */
2218 ret = i915_gem_object_finish_gpu(obj);
2219 (void) ret;
2220 }
2221
2222 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2223 LEAVE_ATOMIC_MODE_SET);
2224 if (ret) {
2225 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2226 mutex_unlock(&dev->struct_mutex);
2227 DRM_ERROR("failed to update base address\n");
2228 return ret;
2229 }
2230
2231 if (old_fb) {
2232 intel_wait_for_vblank(dev, intel_crtc->pipe);
2233 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2234 }
2235
2236 mutex_unlock(&dev->struct_mutex);
2237
2238 if (!dev->primary->master)
2239 return 0;
2240
2241 master_priv = dev->primary->master->driver_priv;
2242 if (!master_priv->sarea_priv)
2243 return 0;
2244
2245 if (intel_crtc->pipe) {
2246 master_priv->sarea_priv->pipeB_x = x;
2247 master_priv->sarea_priv->pipeB_y = y;
2248 } else {
2249 master_priv->sarea_priv->pipeA_x = x;
2250 master_priv->sarea_priv->pipeA_y = y;
2251 }
2252
2253 return 0;
2254 }
2255
2256 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2257 {
2258 struct drm_device *dev = crtc->dev;
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 u32 dpa_ctl;
2261
2262 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2263 dpa_ctl = I915_READ(DP_A);
2264 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2265
2266 if (clock < 200000) {
2267 u32 temp;
2268 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2269 /* workaround for 160Mhz:
2270 1) program 0x4600c bits 15:0 = 0x8124
2271 2) program 0x46010 bit 0 = 1
2272 3) program 0x46034 bit 24 = 1
2273 4) program 0x64000 bit 14 = 1
2274 */
2275 temp = I915_READ(0x4600c);
2276 temp &= 0xffff0000;
2277 I915_WRITE(0x4600c, temp | 0x8124);
2278
2279 temp = I915_READ(0x46010);
2280 I915_WRITE(0x46010, temp | 1);
2281
2282 temp = I915_READ(0x46034);
2283 I915_WRITE(0x46034, temp | (1 << 24));
2284 } else {
2285 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2286 }
2287 I915_WRITE(DP_A, dpa_ctl);
2288
2289 POSTING_READ(DP_A);
2290 udelay(500);
2291 }
2292
2293 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2294 {
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298 int pipe = intel_crtc->pipe;
2299 u32 reg, temp;
2300
2301 /* enable normal train */
2302 reg = FDI_TX_CTL(pipe);
2303 temp = I915_READ(reg);
2304 if (IS_IVYBRIDGE(dev)) {
2305 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2306 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2307 } else {
2308 temp &= ~FDI_LINK_TRAIN_NONE;
2309 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2310 }
2311 I915_WRITE(reg, temp);
2312
2313 reg = FDI_RX_CTL(pipe);
2314 temp = I915_READ(reg);
2315 if (HAS_PCH_CPT(dev)) {
2316 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2317 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2318 } else {
2319 temp &= ~FDI_LINK_TRAIN_NONE;
2320 temp |= FDI_LINK_TRAIN_NONE;
2321 }
2322 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2323
2324 /* wait one idle pattern time */
2325 POSTING_READ(reg);
2326 udelay(1000);
2327
2328 /* IVB wants error correction enabled */
2329 if (IS_IVYBRIDGE(dev))
2330 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2331 FDI_FE_ERRC_ENABLE);
2332 }
2333
2334 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2335 {
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 u32 flags = I915_READ(SOUTH_CHICKEN1);
2338
2339 flags |= FDI_PHASE_SYNC_OVR(pipe);
2340 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2341 flags |= FDI_PHASE_SYNC_EN(pipe);
2342 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2343 POSTING_READ(SOUTH_CHICKEN1);
2344 }
2345
2346 /* The FDI link training functions for ILK/Ibexpeak. */
2347 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2348 {
2349 struct drm_device *dev = crtc->dev;
2350 struct drm_i915_private *dev_priv = dev->dev_private;
2351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2352 int pipe = intel_crtc->pipe;
2353 int plane = intel_crtc->plane;
2354 u32 reg, temp, tries;
2355
2356 /* FDI needs bits from pipe & plane first */
2357 assert_pipe_enabled(dev_priv, pipe);
2358 assert_plane_enabled(dev_priv, plane);
2359
2360 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2361 for train result */
2362 reg = FDI_RX_IMR(pipe);
2363 temp = I915_READ(reg);
2364 temp &= ~FDI_RX_SYMBOL_LOCK;
2365 temp &= ~FDI_RX_BIT_LOCK;
2366 I915_WRITE(reg, temp);
2367 I915_READ(reg);
2368 udelay(150);
2369
2370 /* enable CPU FDI TX and PCH FDI RX */
2371 reg = FDI_TX_CTL(pipe);
2372 temp = I915_READ(reg);
2373 temp &= ~(7 << 19);
2374 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2375 temp &= ~FDI_LINK_TRAIN_NONE;
2376 temp |= FDI_LINK_TRAIN_PATTERN_1;
2377 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2378
2379 reg = FDI_RX_CTL(pipe);
2380 temp = I915_READ(reg);
2381 temp &= ~FDI_LINK_TRAIN_NONE;
2382 temp |= FDI_LINK_TRAIN_PATTERN_1;
2383 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2384
2385 POSTING_READ(reg);
2386 udelay(150);
2387
2388 /* Ironlake workaround, enable clock pointer after FDI enable*/
2389 if (HAS_PCH_IBX(dev)) {
2390 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2391 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2392 FDI_RX_PHASE_SYNC_POINTER_EN);
2393 }
2394
2395 reg = FDI_RX_IIR(pipe);
2396 for (tries = 0; tries < 5; tries++) {
2397 temp = I915_READ(reg);
2398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400 if ((temp & FDI_RX_BIT_LOCK)) {
2401 DRM_DEBUG_KMS("FDI train 1 done.\n");
2402 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2403 break;
2404 }
2405 }
2406 if (tries == 5)
2407 DRM_ERROR("FDI train 1 fail!\n");
2408
2409 /* Train 2 */
2410 reg = FDI_TX_CTL(pipe);
2411 temp = I915_READ(reg);
2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_PATTERN_2;
2414 I915_WRITE(reg, temp);
2415
2416 reg = FDI_RX_CTL(pipe);
2417 temp = I915_READ(reg);
2418 temp &= ~FDI_LINK_TRAIN_NONE;
2419 temp |= FDI_LINK_TRAIN_PATTERN_2;
2420 I915_WRITE(reg, temp);
2421
2422 POSTING_READ(reg);
2423 udelay(150);
2424
2425 reg = FDI_RX_IIR(pipe);
2426 for (tries = 0; tries < 5; tries++) {
2427 temp = I915_READ(reg);
2428 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2429
2430 if (temp & FDI_RX_SYMBOL_LOCK) {
2431 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2432 DRM_DEBUG_KMS("FDI train 2 done.\n");
2433 break;
2434 }
2435 }
2436 if (tries == 5)
2437 DRM_ERROR("FDI train 2 fail!\n");
2438
2439 DRM_DEBUG_KMS("FDI train done\n");
2440
2441 }
2442
2443 static const int snb_b_fdi_train_param [] = {
2444 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2445 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2446 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2447 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2448 };
2449
2450 /* The FDI link training functions for SNB/Cougarpoint. */
2451 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2452 {
2453 struct drm_device *dev = crtc->dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456 int pipe = intel_crtc->pipe;
2457 u32 reg, temp, i;
2458
2459 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2460 for train result */
2461 reg = FDI_RX_IMR(pipe);
2462 temp = I915_READ(reg);
2463 temp &= ~FDI_RX_SYMBOL_LOCK;
2464 temp &= ~FDI_RX_BIT_LOCK;
2465 I915_WRITE(reg, temp);
2466
2467 POSTING_READ(reg);
2468 udelay(150);
2469
2470 /* enable CPU FDI TX and PCH FDI RX */
2471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~(7 << 19);
2474 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2475 temp &= ~FDI_LINK_TRAIN_NONE;
2476 temp |= FDI_LINK_TRAIN_PATTERN_1;
2477 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2478 /* SNB-B */
2479 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2480 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2481
2482 reg = FDI_RX_CTL(pipe);
2483 temp = I915_READ(reg);
2484 if (HAS_PCH_CPT(dev)) {
2485 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2487 } else {
2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_1;
2490 }
2491 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2492
2493 POSTING_READ(reg);
2494 udelay(150);
2495
2496 if (HAS_PCH_CPT(dev))
2497 cpt_phase_pointer_enable(dev, pipe);
2498
2499 for (i = 0; i < 4; i++ ) {
2500 reg = FDI_TX_CTL(pipe);
2501 temp = I915_READ(reg);
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 temp |= snb_b_fdi_train_param[i];
2504 I915_WRITE(reg, temp);
2505
2506 POSTING_READ(reg);
2507 udelay(500);
2508
2509 reg = FDI_RX_IIR(pipe);
2510 temp = I915_READ(reg);
2511 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2512
2513 if (temp & FDI_RX_BIT_LOCK) {
2514 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2515 DRM_DEBUG_KMS("FDI train 1 done.\n");
2516 break;
2517 }
2518 }
2519 if (i == 4)
2520 DRM_ERROR("FDI train 1 fail!\n");
2521
2522 /* Train 2 */
2523 reg = FDI_TX_CTL(pipe);
2524 temp = I915_READ(reg);
2525 temp &= ~FDI_LINK_TRAIN_NONE;
2526 temp |= FDI_LINK_TRAIN_PATTERN_2;
2527 if (IS_GEN6(dev)) {
2528 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2529 /* SNB-B */
2530 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2531 }
2532 I915_WRITE(reg, temp);
2533
2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2539 } else {
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_2;
2542 }
2543 I915_WRITE(reg, temp);
2544
2545 POSTING_READ(reg);
2546 udelay(150);
2547
2548 for (i = 0; i < 4; i++ ) {
2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552 temp |= snb_b_fdi_train_param[i];
2553 I915_WRITE(reg, temp);
2554
2555 POSTING_READ(reg);
2556 udelay(500);
2557
2558 reg = FDI_RX_IIR(pipe);
2559 temp = I915_READ(reg);
2560 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2561
2562 if (temp & FDI_RX_SYMBOL_LOCK) {
2563 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2564 DRM_DEBUG_KMS("FDI train 2 done.\n");
2565 break;
2566 }
2567 }
2568 if (i == 4)
2569 DRM_ERROR("FDI train 2 fail!\n");
2570
2571 DRM_DEBUG_KMS("FDI train done.\n");
2572 }
2573
2574 /* Manual link training for Ivy Bridge A0 parts */
2575 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2576 {
2577 struct drm_device *dev = crtc->dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2580 int pipe = intel_crtc->pipe;
2581 u32 reg, temp, i;
2582
2583 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2584 for train result */
2585 reg = FDI_RX_IMR(pipe);
2586 temp = I915_READ(reg);
2587 temp &= ~FDI_RX_SYMBOL_LOCK;
2588 temp &= ~FDI_RX_BIT_LOCK;
2589 I915_WRITE(reg, temp);
2590
2591 POSTING_READ(reg);
2592 udelay(150);
2593
2594 /* enable CPU FDI TX and PCH FDI RX */
2595 reg = FDI_TX_CTL(pipe);
2596 temp = I915_READ(reg);
2597 temp &= ~(7 << 19);
2598 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2599 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2600 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2603 temp |= FDI_COMPOSITE_SYNC;
2604 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2605
2606 reg = FDI_RX_CTL(pipe);
2607 temp = I915_READ(reg);
2608 temp &= ~FDI_LINK_TRAIN_AUTO;
2609 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2610 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2611 temp |= FDI_COMPOSITE_SYNC;
2612 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2613
2614 POSTING_READ(reg);
2615 udelay(150);
2616
2617 if (HAS_PCH_CPT(dev))
2618 cpt_phase_pointer_enable(dev, pipe);
2619
2620 for (i = 0; i < 4; i++ ) {
2621 reg = FDI_TX_CTL(pipe);
2622 temp = I915_READ(reg);
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 temp |= snb_b_fdi_train_param[i];
2625 I915_WRITE(reg, temp);
2626
2627 POSTING_READ(reg);
2628 udelay(500);
2629
2630 reg = FDI_RX_IIR(pipe);
2631 temp = I915_READ(reg);
2632 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2633
2634 if (temp & FDI_RX_BIT_LOCK ||
2635 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2636 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2637 DRM_DEBUG_KMS("FDI train 1 done.\n");
2638 break;
2639 }
2640 }
2641 if (i == 4)
2642 DRM_ERROR("FDI train 1 fail!\n");
2643
2644 /* Train 2 */
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2648 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2649 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2650 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2651 I915_WRITE(reg, temp);
2652
2653 reg = FDI_RX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2656 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2657 I915_WRITE(reg, temp);
2658
2659 POSTING_READ(reg);
2660 udelay(150);
2661
2662 for (i = 0; i < 4; i++ ) {
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666 temp |= snb_b_fdi_train_param[i];
2667 I915_WRITE(reg, temp);
2668
2669 POSTING_READ(reg);
2670 udelay(500);
2671
2672 reg = FDI_RX_IIR(pipe);
2673 temp = I915_READ(reg);
2674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2675
2676 if (temp & FDI_RX_SYMBOL_LOCK) {
2677 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2678 DRM_DEBUG_KMS("FDI train 2 done.\n");
2679 break;
2680 }
2681 }
2682 if (i == 4)
2683 DRM_ERROR("FDI train 2 fail!\n");
2684
2685 DRM_DEBUG_KMS("FDI train done.\n");
2686 }
2687
2688 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2689 {
2690 struct drm_device *dev = crtc->dev;
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2693 int pipe = intel_crtc->pipe;
2694 u32 reg, temp;
2695
2696 /* Write the TU size bits so error detection works */
2697 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2698 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2699
2700 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2701 reg = FDI_RX_CTL(pipe);
2702 temp = I915_READ(reg);
2703 temp &= ~((0x7 << 19) | (0x7 << 16));
2704 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2705 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2706 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2707
2708 POSTING_READ(reg);
2709 udelay(200);
2710
2711 /* Switch from Rawclk to PCDclk */
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp | FDI_PCDCLK);
2714
2715 POSTING_READ(reg);
2716 udelay(200);
2717
2718 /* Enable CPU FDI TX PLL, always on for Ironlake */
2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2722 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2723
2724 POSTING_READ(reg);
2725 udelay(100);
2726 }
2727 }
2728
2729 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2730 {
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 u32 flags = I915_READ(SOUTH_CHICKEN1);
2733
2734 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2735 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2736 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2737 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2738 POSTING_READ(SOUTH_CHICKEN1);
2739 }
2740 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2741 {
2742 struct drm_device *dev = crtc->dev;
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2745 int pipe = intel_crtc->pipe;
2746 u32 reg, temp;
2747
2748 /* disable CPU FDI tx and PCH FDI rx */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2752 POSTING_READ(reg);
2753
2754 reg = FDI_RX_CTL(pipe);
2755 temp = I915_READ(reg);
2756 temp &= ~(0x7 << 16);
2757 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2758 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2759
2760 POSTING_READ(reg);
2761 udelay(100);
2762
2763 /* Ironlake workaround, disable clock pointer after downing FDI */
2764 if (HAS_PCH_IBX(dev)) {
2765 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2766 I915_WRITE(FDI_RX_CHICKEN(pipe),
2767 I915_READ(FDI_RX_CHICKEN(pipe) &
2768 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2769 } else if (HAS_PCH_CPT(dev)) {
2770 cpt_phase_pointer_disable(dev, pipe);
2771 }
2772
2773 /* still set train pattern 1 */
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~FDI_LINK_TRAIN_NONE;
2777 temp |= FDI_LINK_TRAIN_PATTERN_1;
2778 I915_WRITE(reg, temp);
2779
2780 reg = FDI_RX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 if (HAS_PCH_CPT(dev)) {
2783 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2784 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2785 } else {
2786 temp &= ~FDI_LINK_TRAIN_NONE;
2787 temp |= FDI_LINK_TRAIN_PATTERN_1;
2788 }
2789 /* BPC in FDI rx is consistent with that in PIPECONF */
2790 temp &= ~(0x07 << 16);
2791 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2792 I915_WRITE(reg, temp);
2793
2794 POSTING_READ(reg);
2795 udelay(100);
2796 }
2797
2798 /*
2799 * When we disable a pipe, we need to clear any pending scanline wait events
2800 * to avoid hanging the ring, which we assume we are waiting on.
2801 */
2802 static void intel_clear_scanline_wait(struct drm_device *dev)
2803 {
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 struct intel_ring_buffer *ring;
2806 u32 tmp;
2807
2808 if (IS_GEN2(dev))
2809 /* Can't break the hang on i8xx */
2810 return;
2811
2812 ring = LP_RING(dev_priv);
2813 tmp = I915_READ_CTL(ring);
2814 if (tmp & RING_WAIT)
2815 I915_WRITE_CTL(ring, tmp);
2816 }
2817
2818 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2819 {
2820 struct drm_i915_gem_object *obj;
2821 struct drm_i915_private *dev_priv;
2822
2823 if (crtc->fb == NULL)
2824 return;
2825
2826 obj = to_intel_framebuffer(crtc->fb)->obj;
2827 dev_priv = crtc->dev->dev_private;
2828 wait_event(dev_priv->pending_flip_queue,
2829 atomic_read(&obj->pending_flip) == 0);
2830 }
2831
2832 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2833 {
2834 struct drm_device *dev = crtc->dev;
2835 struct drm_mode_config *mode_config = &dev->mode_config;
2836 struct intel_encoder *encoder;
2837
2838 /*
2839 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2840 * must be driven by its own crtc; no sharing is possible.
2841 */
2842 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2843 if (encoder->base.crtc != crtc)
2844 continue;
2845
2846 switch (encoder->type) {
2847 case INTEL_OUTPUT_EDP:
2848 if (!intel_encoder_is_pch_edp(&encoder->base))
2849 return false;
2850 continue;
2851 }
2852 }
2853
2854 return true;
2855 }
2856
2857 /*
2858 * Enable PCH resources required for PCH ports:
2859 * - PCH PLLs
2860 * - FDI training & RX/TX
2861 * - update transcoder timings
2862 * - DP transcoding bits
2863 * - transcoder
2864 */
2865 static void ironlake_pch_enable(struct drm_crtc *crtc)
2866 {
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2870 int pipe = intel_crtc->pipe;
2871 u32 reg, temp;
2872
2873 /* For PCH output, training FDI link */
2874 dev_priv->display.fdi_link_train(crtc);
2875
2876 intel_enable_pch_pll(dev_priv, pipe);
2877
2878 if (HAS_PCH_CPT(dev)) {
2879 /* Be sure PCH DPLL SEL is set */
2880 temp = I915_READ(PCH_DPLL_SEL);
2881 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2882 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2883 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2884 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2885 I915_WRITE(PCH_DPLL_SEL, temp);
2886 }
2887
2888 /* set transcoder timing, panel must allow it */
2889 assert_panel_unlocked(dev_priv, pipe);
2890 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2891 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2892 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2893
2894 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2895 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2896 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2897
2898 intel_fdi_normal_train(crtc);
2899
2900 /* For PCH DP, enable TRANS_DP_CTL */
2901 if (HAS_PCH_CPT(dev) &&
2902 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2903 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2904 reg = TRANS_DP_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2907 TRANS_DP_SYNC_MASK |
2908 TRANS_DP_BPC_MASK);
2909 temp |= (TRANS_DP_OUTPUT_ENABLE |
2910 TRANS_DP_ENH_FRAMING);
2911 temp |= bpc << 9; /* same format but at 11:9 */
2912
2913 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2914 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2915 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2916 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2917
2918 switch (intel_trans_dp_port_sel(crtc)) {
2919 case PCH_DP_B:
2920 temp |= TRANS_DP_PORT_SEL_B;
2921 break;
2922 case PCH_DP_C:
2923 temp |= TRANS_DP_PORT_SEL_C;
2924 break;
2925 case PCH_DP_D:
2926 temp |= TRANS_DP_PORT_SEL_D;
2927 break;
2928 default:
2929 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2930 temp |= TRANS_DP_PORT_SEL_B;
2931 break;
2932 }
2933
2934 I915_WRITE(reg, temp);
2935 }
2936
2937 intel_enable_transcoder(dev_priv, pipe);
2938 }
2939
2940 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2941 {
2942 struct drm_device *dev = crtc->dev;
2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2945 int pipe = intel_crtc->pipe;
2946 int plane = intel_crtc->plane;
2947 u32 temp;
2948 bool is_pch_port;
2949
2950 if (intel_crtc->active)
2951 return;
2952
2953 intel_crtc->active = true;
2954 intel_update_watermarks(dev);
2955
2956 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2957 temp = I915_READ(PCH_LVDS);
2958 if ((temp & LVDS_PORT_EN) == 0)
2959 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2960 }
2961
2962 is_pch_port = intel_crtc_driving_pch(crtc);
2963
2964 if (is_pch_port)
2965 ironlake_fdi_pll_enable(crtc);
2966 else
2967 ironlake_fdi_disable(crtc);
2968
2969 /* Enable panel fitting for LVDS */
2970 if (dev_priv->pch_pf_size &&
2971 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2972 /* Force use of hard-coded filter coefficients
2973 * as some pre-programmed values are broken,
2974 * e.g. x201.
2975 */
2976 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2977 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2978 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2979 }
2980
2981 /*
2982 * On ILK+ LUT must be loaded before the pipe is running but with
2983 * clocks enabled
2984 */
2985 intel_crtc_load_lut(crtc);
2986
2987 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2988 intel_enable_plane(dev_priv, plane, pipe);
2989
2990 if (is_pch_port)
2991 ironlake_pch_enable(crtc);
2992
2993 mutex_lock(&dev->struct_mutex);
2994 intel_update_fbc(dev);
2995 mutex_unlock(&dev->struct_mutex);
2996
2997 intel_crtc_update_cursor(crtc, true);
2998 }
2999
3000 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3001 {
3002 struct drm_device *dev = crtc->dev;
3003 struct drm_i915_private *dev_priv = dev->dev_private;
3004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3005 int pipe = intel_crtc->pipe;
3006 int plane = intel_crtc->plane;
3007 u32 reg, temp;
3008
3009 if (!intel_crtc->active)
3010 return;
3011
3012 intel_crtc_wait_for_pending_flips(crtc);
3013 drm_vblank_off(dev, pipe);
3014 intel_crtc_update_cursor(crtc, false);
3015
3016 intel_disable_plane(dev_priv, plane, pipe);
3017
3018 if (dev_priv->cfb_plane == plane)
3019 intel_disable_fbc(dev);
3020
3021 intel_disable_pipe(dev_priv, pipe);
3022
3023 /* Disable PF */
3024 I915_WRITE(PF_CTL(pipe), 0);
3025 I915_WRITE(PF_WIN_SZ(pipe), 0);
3026
3027 ironlake_fdi_disable(crtc);
3028
3029 /* This is a horrible layering violation; we should be doing this in
3030 * the connector/encoder ->prepare instead, but we don't always have
3031 * enough information there about the config to know whether it will
3032 * actually be necessary or just cause undesired flicker.
3033 */
3034 intel_disable_pch_ports(dev_priv, pipe);
3035
3036 intel_disable_transcoder(dev_priv, pipe);
3037
3038 if (HAS_PCH_CPT(dev)) {
3039 /* disable TRANS_DP_CTL */
3040 reg = TRANS_DP_CTL(pipe);
3041 temp = I915_READ(reg);
3042 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3043 temp |= TRANS_DP_PORT_SEL_NONE;
3044 I915_WRITE(reg, temp);
3045
3046 /* disable DPLL_SEL */
3047 temp = I915_READ(PCH_DPLL_SEL);
3048 switch (pipe) {
3049 case 0:
3050 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3051 break;
3052 case 1:
3053 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3054 break;
3055 case 2:
3056 /* FIXME: manage transcoder PLLs? */
3057 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3058 break;
3059 default:
3060 BUG(); /* wtf */
3061 }
3062 I915_WRITE(PCH_DPLL_SEL, temp);
3063 }
3064
3065 /* disable PCH DPLL */
3066 intel_disable_pch_pll(dev_priv, pipe);
3067
3068 /* Switch from PCDclk to Rawclk */
3069 reg = FDI_RX_CTL(pipe);
3070 temp = I915_READ(reg);
3071 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3072
3073 /* Disable CPU FDI TX PLL */
3074 reg = FDI_TX_CTL(pipe);
3075 temp = I915_READ(reg);
3076 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3077
3078 POSTING_READ(reg);
3079 udelay(100);
3080
3081 reg = FDI_RX_CTL(pipe);
3082 temp = I915_READ(reg);
3083 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3084
3085 /* Wait for the clocks to turn off. */
3086 POSTING_READ(reg);
3087 udelay(100);
3088
3089 intel_crtc->active = false;
3090 intel_update_watermarks(dev);
3091
3092 mutex_lock(&dev->struct_mutex);
3093 intel_update_fbc(dev);
3094 intel_clear_scanline_wait(dev);
3095 mutex_unlock(&dev->struct_mutex);
3096 }
3097
3098 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3099 {
3100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101 int pipe = intel_crtc->pipe;
3102 int plane = intel_crtc->plane;
3103
3104 /* XXX: When our outputs are all unaware of DPMS modes other than off
3105 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3106 */
3107 switch (mode) {
3108 case DRM_MODE_DPMS_ON:
3109 case DRM_MODE_DPMS_STANDBY:
3110 case DRM_MODE_DPMS_SUSPEND:
3111 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3112 ironlake_crtc_enable(crtc);
3113 break;
3114
3115 case DRM_MODE_DPMS_OFF:
3116 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3117 ironlake_crtc_disable(crtc);
3118 break;
3119 }
3120 }
3121
3122 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3123 {
3124 if (!enable && intel_crtc->overlay) {
3125 struct drm_device *dev = intel_crtc->base.dev;
3126 struct drm_i915_private *dev_priv = dev->dev_private;
3127
3128 mutex_lock(&dev->struct_mutex);
3129 dev_priv->mm.interruptible = false;
3130 (void) intel_overlay_switch_off(intel_crtc->overlay);
3131 dev_priv->mm.interruptible = true;
3132 mutex_unlock(&dev->struct_mutex);
3133 }
3134
3135 /* Let userspace switch the overlay on again. In most cases userspace
3136 * has to recompute where to put it anyway.
3137 */
3138 }
3139
3140 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3141 {
3142 struct drm_device *dev = crtc->dev;
3143 struct drm_i915_private *dev_priv = dev->dev_private;
3144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3145 int pipe = intel_crtc->pipe;
3146 int plane = intel_crtc->plane;
3147
3148 if (intel_crtc->active)
3149 return;
3150
3151 intel_crtc->active = true;
3152 intel_update_watermarks(dev);
3153
3154 intel_enable_pll(dev_priv, pipe);
3155 intel_enable_pipe(dev_priv, pipe, false);
3156 intel_enable_plane(dev_priv, plane, pipe);
3157
3158 intel_crtc_load_lut(crtc);
3159 intel_update_fbc(dev);
3160
3161 /* Give the overlay scaler a chance to enable if it's on this pipe */
3162 intel_crtc_dpms_overlay(intel_crtc, true);
3163 intel_crtc_update_cursor(crtc, true);
3164 }
3165
3166 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3167 {
3168 struct drm_device *dev = crtc->dev;
3169 struct drm_i915_private *dev_priv = dev->dev_private;
3170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3171 int pipe = intel_crtc->pipe;
3172 int plane = intel_crtc->plane;
3173
3174 if (!intel_crtc->active)
3175 return;
3176
3177 /* Give the overlay scaler a chance to disable if it's on this pipe */
3178 intel_crtc_wait_for_pending_flips(crtc);
3179 drm_vblank_off(dev, pipe);
3180 intel_crtc_dpms_overlay(intel_crtc, false);
3181 intel_crtc_update_cursor(crtc, false);
3182
3183 if (dev_priv->cfb_plane == plane)
3184 intel_disable_fbc(dev);
3185
3186 intel_disable_plane(dev_priv, plane, pipe);
3187 intel_disable_pipe(dev_priv, pipe);
3188 intel_disable_pll(dev_priv, pipe);
3189
3190 intel_crtc->active = false;
3191 intel_update_fbc(dev);
3192 intel_update_watermarks(dev);
3193 intel_clear_scanline_wait(dev);
3194 }
3195
3196 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3197 {
3198 /* XXX: When our outputs are all unaware of DPMS modes other than off
3199 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3200 */
3201 switch (mode) {
3202 case DRM_MODE_DPMS_ON:
3203 case DRM_MODE_DPMS_STANDBY:
3204 case DRM_MODE_DPMS_SUSPEND:
3205 i9xx_crtc_enable(crtc);
3206 break;
3207 case DRM_MODE_DPMS_OFF:
3208 i9xx_crtc_disable(crtc);
3209 break;
3210 }
3211 }
3212
3213 /**
3214 * Sets the power management mode of the pipe and plane.
3215 */
3216 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3217 {
3218 struct drm_device *dev = crtc->dev;
3219 struct drm_i915_private *dev_priv = dev->dev_private;
3220 struct drm_i915_master_private *master_priv;
3221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3222 int pipe = intel_crtc->pipe;
3223 bool enabled;
3224
3225 if (intel_crtc->dpms_mode == mode)
3226 return;
3227
3228 intel_crtc->dpms_mode = mode;
3229
3230 dev_priv->display.dpms(crtc, mode);
3231
3232 if (!dev->primary->master)
3233 return;
3234
3235 master_priv = dev->primary->master->driver_priv;
3236 if (!master_priv->sarea_priv)
3237 return;
3238
3239 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3240
3241 switch (pipe) {
3242 case 0:
3243 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3244 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3245 break;
3246 case 1:
3247 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3248 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3249 break;
3250 default:
3251 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3252 break;
3253 }
3254 }
3255
3256 static void intel_crtc_disable(struct drm_crtc *crtc)
3257 {
3258 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3259 struct drm_device *dev = crtc->dev;
3260
3261 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3262
3263 if (crtc->fb) {
3264 mutex_lock(&dev->struct_mutex);
3265 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3266 mutex_unlock(&dev->struct_mutex);
3267 }
3268 }
3269
3270 /* Prepare for a mode set.
3271 *
3272 * Note we could be a lot smarter here. We need to figure out which outputs
3273 * will be enabled, which disabled (in short, how the config will changes)
3274 * and perform the minimum necessary steps to accomplish that, e.g. updating
3275 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3276 * panel fitting is in the proper state, etc.
3277 */
3278 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3279 {
3280 i9xx_crtc_disable(crtc);
3281 }
3282
3283 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3284 {
3285 i9xx_crtc_enable(crtc);
3286 }
3287
3288 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3289 {
3290 ironlake_crtc_disable(crtc);
3291 }
3292
3293 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3294 {
3295 ironlake_crtc_enable(crtc);
3296 }
3297
3298 void intel_encoder_prepare (struct drm_encoder *encoder)
3299 {
3300 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3301 /* lvds has its own version of prepare see intel_lvds_prepare */
3302 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3303 }
3304
3305 void intel_encoder_commit (struct drm_encoder *encoder)
3306 {
3307 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3308 /* lvds has its own version of commit see intel_lvds_commit */
3309 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3310 }
3311
3312 void intel_encoder_destroy(struct drm_encoder *encoder)
3313 {
3314 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3315
3316 drm_encoder_cleanup(encoder);
3317 kfree(intel_encoder);
3318 }
3319
3320 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3321 struct drm_display_mode *mode,
3322 struct drm_display_mode *adjusted_mode)
3323 {
3324 struct drm_device *dev = crtc->dev;
3325
3326 if (HAS_PCH_SPLIT(dev)) {
3327 /* FDI link clock is fixed at 2.7G */
3328 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3329 return false;
3330 }
3331
3332 /* XXX some encoders set the crtcinfo, others don't.
3333 * Obviously we need some form of conflict resolution here...
3334 */
3335 if (adjusted_mode->crtc_htotal == 0)
3336 drm_mode_set_crtcinfo(adjusted_mode, 0);
3337
3338 return true;
3339 }
3340
3341 static int i945_get_display_clock_speed(struct drm_device *dev)
3342 {
3343 return 400000;
3344 }
3345
3346 static int i915_get_display_clock_speed(struct drm_device *dev)
3347 {
3348 return 333000;
3349 }
3350
3351 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3352 {
3353 return 200000;
3354 }
3355
3356 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3357 {
3358 u16 gcfgc = 0;
3359
3360 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3361
3362 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3363 return 133000;
3364 else {
3365 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3366 case GC_DISPLAY_CLOCK_333_MHZ:
3367 return 333000;
3368 default:
3369 case GC_DISPLAY_CLOCK_190_200_MHZ:
3370 return 190000;
3371 }
3372 }
3373 }
3374
3375 static int i865_get_display_clock_speed(struct drm_device *dev)
3376 {
3377 return 266000;
3378 }
3379
3380 static int i855_get_display_clock_speed(struct drm_device *dev)
3381 {
3382 u16 hpllcc = 0;
3383 /* Assume that the hardware is in the high speed state. This
3384 * should be the default.
3385 */
3386 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3387 case GC_CLOCK_133_200:
3388 case GC_CLOCK_100_200:
3389 return 200000;
3390 case GC_CLOCK_166_250:
3391 return 250000;
3392 case GC_CLOCK_100_133:
3393 return 133000;
3394 }
3395
3396 /* Shouldn't happen */
3397 return 0;
3398 }
3399
3400 static int i830_get_display_clock_speed(struct drm_device *dev)
3401 {
3402 return 133000;
3403 }
3404
3405 struct fdi_m_n {
3406 u32 tu;
3407 u32 gmch_m;
3408 u32 gmch_n;
3409 u32 link_m;
3410 u32 link_n;
3411 };
3412
3413 static void
3414 fdi_reduce_ratio(u32 *num, u32 *den)
3415 {
3416 while (*num > 0xffffff || *den > 0xffffff) {
3417 *num >>= 1;
3418 *den >>= 1;
3419 }
3420 }
3421
3422 static void
3423 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3424 int link_clock, struct fdi_m_n *m_n)
3425 {
3426 m_n->tu = 64; /* default size */
3427
3428 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3429 m_n->gmch_m = bits_per_pixel * pixel_clock;
3430 m_n->gmch_n = link_clock * nlanes * 8;
3431 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3432
3433 m_n->link_m = pixel_clock;
3434 m_n->link_n = link_clock;
3435 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3436 }
3437
3438
3439 struct intel_watermark_params {
3440 unsigned long fifo_size;
3441 unsigned long max_wm;
3442 unsigned long default_wm;
3443 unsigned long guard_size;
3444 unsigned long cacheline_size;
3445 };
3446
3447 /* Pineview has different values for various configs */
3448 static const struct intel_watermark_params pineview_display_wm = {
3449 PINEVIEW_DISPLAY_FIFO,
3450 PINEVIEW_MAX_WM,
3451 PINEVIEW_DFT_WM,
3452 PINEVIEW_GUARD_WM,
3453 PINEVIEW_FIFO_LINE_SIZE
3454 };
3455 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3456 PINEVIEW_DISPLAY_FIFO,
3457 PINEVIEW_MAX_WM,
3458 PINEVIEW_DFT_HPLLOFF_WM,
3459 PINEVIEW_GUARD_WM,
3460 PINEVIEW_FIFO_LINE_SIZE
3461 };
3462 static const struct intel_watermark_params pineview_cursor_wm = {
3463 PINEVIEW_CURSOR_FIFO,
3464 PINEVIEW_CURSOR_MAX_WM,
3465 PINEVIEW_CURSOR_DFT_WM,
3466 PINEVIEW_CURSOR_GUARD_WM,
3467 PINEVIEW_FIFO_LINE_SIZE,
3468 };
3469 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3470 PINEVIEW_CURSOR_FIFO,
3471 PINEVIEW_CURSOR_MAX_WM,
3472 PINEVIEW_CURSOR_DFT_WM,
3473 PINEVIEW_CURSOR_GUARD_WM,
3474 PINEVIEW_FIFO_LINE_SIZE
3475 };
3476 static const struct intel_watermark_params g4x_wm_info = {
3477 G4X_FIFO_SIZE,
3478 G4X_MAX_WM,
3479 G4X_MAX_WM,
3480 2,
3481 G4X_FIFO_LINE_SIZE,
3482 };
3483 static const struct intel_watermark_params g4x_cursor_wm_info = {
3484 I965_CURSOR_FIFO,
3485 I965_CURSOR_MAX_WM,
3486 I965_CURSOR_DFT_WM,
3487 2,
3488 G4X_FIFO_LINE_SIZE,
3489 };
3490 static const struct intel_watermark_params i965_cursor_wm_info = {
3491 I965_CURSOR_FIFO,
3492 I965_CURSOR_MAX_WM,
3493 I965_CURSOR_DFT_WM,
3494 2,
3495 I915_FIFO_LINE_SIZE,
3496 };
3497 static const struct intel_watermark_params i945_wm_info = {
3498 I945_FIFO_SIZE,
3499 I915_MAX_WM,
3500 1,
3501 2,
3502 I915_FIFO_LINE_SIZE
3503 };
3504 static const struct intel_watermark_params i915_wm_info = {
3505 I915_FIFO_SIZE,
3506 I915_MAX_WM,
3507 1,
3508 2,
3509 I915_FIFO_LINE_SIZE
3510 };
3511 static const struct intel_watermark_params i855_wm_info = {
3512 I855GM_FIFO_SIZE,
3513 I915_MAX_WM,
3514 1,
3515 2,
3516 I830_FIFO_LINE_SIZE
3517 };
3518 static const struct intel_watermark_params i830_wm_info = {
3519 I830_FIFO_SIZE,
3520 I915_MAX_WM,
3521 1,
3522 2,
3523 I830_FIFO_LINE_SIZE
3524 };
3525
3526 static const struct intel_watermark_params ironlake_display_wm_info = {
3527 ILK_DISPLAY_FIFO,
3528 ILK_DISPLAY_MAXWM,
3529 ILK_DISPLAY_DFTWM,
3530 2,
3531 ILK_FIFO_LINE_SIZE
3532 };
3533 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3534 ILK_CURSOR_FIFO,
3535 ILK_CURSOR_MAXWM,
3536 ILK_CURSOR_DFTWM,
3537 2,
3538 ILK_FIFO_LINE_SIZE
3539 };
3540 static const struct intel_watermark_params ironlake_display_srwm_info = {
3541 ILK_DISPLAY_SR_FIFO,
3542 ILK_DISPLAY_MAX_SRWM,
3543 ILK_DISPLAY_DFT_SRWM,
3544 2,
3545 ILK_FIFO_LINE_SIZE
3546 };
3547 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3548 ILK_CURSOR_SR_FIFO,
3549 ILK_CURSOR_MAX_SRWM,
3550 ILK_CURSOR_DFT_SRWM,
3551 2,
3552 ILK_FIFO_LINE_SIZE
3553 };
3554
3555 static const struct intel_watermark_params sandybridge_display_wm_info = {
3556 SNB_DISPLAY_FIFO,
3557 SNB_DISPLAY_MAXWM,
3558 SNB_DISPLAY_DFTWM,
3559 2,
3560 SNB_FIFO_LINE_SIZE
3561 };
3562 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3563 SNB_CURSOR_FIFO,
3564 SNB_CURSOR_MAXWM,
3565 SNB_CURSOR_DFTWM,
3566 2,
3567 SNB_FIFO_LINE_SIZE
3568 };
3569 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3570 SNB_DISPLAY_SR_FIFO,
3571 SNB_DISPLAY_MAX_SRWM,
3572 SNB_DISPLAY_DFT_SRWM,
3573 2,
3574 SNB_FIFO_LINE_SIZE
3575 };
3576 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3577 SNB_CURSOR_SR_FIFO,
3578 SNB_CURSOR_MAX_SRWM,
3579 SNB_CURSOR_DFT_SRWM,
3580 2,
3581 SNB_FIFO_LINE_SIZE
3582 };
3583
3584
3585 /**
3586 * intel_calculate_wm - calculate watermark level
3587 * @clock_in_khz: pixel clock
3588 * @wm: chip FIFO params
3589 * @pixel_size: display pixel size
3590 * @latency_ns: memory latency for the platform
3591 *
3592 * Calculate the watermark level (the level at which the display plane will
3593 * start fetching from memory again). Each chip has a different display
3594 * FIFO size and allocation, so the caller needs to figure that out and pass
3595 * in the correct intel_watermark_params structure.
3596 *
3597 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3598 * on the pixel size. When it reaches the watermark level, it'll start
3599 * fetching FIFO line sized based chunks from memory until the FIFO fills
3600 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3601 * will occur, and a display engine hang could result.
3602 */
3603 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3604 const struct intel_watermark_params *wm,
3605 int fifo_size,
3606 int pixel_size,
3607 unsigned long latency_ns)
3608 {
3609 long entries_required, wm_size;
3610
3611 /*
3612 * Note: we need to make sure we don't overflow for various clock &
3613 * latency values.
3614 * clocks go from a few thousand to several hundred thousand.
3615 * latency is usually a few thousand
3616 */
3617 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3618 1000;
3619 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3620
3621 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3622
3623 wm_size = fifo_size - (entries_required + wm->guard_size);
3624
3625 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3626
3627 /* Don't promote wm_size to unsigned... */
3628 if (wm_size > (long)wm->max_wm)
3629 wm_size = wm->max_wm;
3630 if (wm_size <= 0)
3631 wm_size = wm->default_wm;
3632 return wm_size;
3633 }
3634
3635 struct cxsr_latency {
3636 int is_desktop;
3637 int is_ddr3;
3638 unsigned long fsb_freq;
3639 unsigned long mem_freq;
3640 unsigned long display_sr;
3641 unsigned long display_hpll_disable;
3642 unsigned long cursor_sr;
3643 unsigned long cursor_hpll_disable;
3644 };
3645
3646 static const struct cxsr_latency cxsr_latency_table[] = {
3647 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3648 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3649 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3650 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3651 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3652
3653 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3654 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3655 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3656 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3657 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3658
3659 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3660 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3661 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3662 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3663 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3664
3665 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3666 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3667 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3668 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3669 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3670
3671 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3672 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3673 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3674 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3675 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3676
3677 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3678 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3679 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3680 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3681 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3682 };
3683
3684 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3685 int is_ddr3,
3686 int fsb,
3687 int mem)
3688 {
3689 const struct cxsr_latency *latency;
3690 int i;
3691
3692 if (fsb == 0 || mem == 0)
3693 return NULL;
3694
3695 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3696 latency = &cxsr_latency_table[i];
3697 if (is_desktop == latency->is_desktop &&
3698 is_ddr3 == latency->is_ddr3 &&
3699 fsb == latency->fsb_freq && mem == latency->mem_freq)
3700 return latency;
3701 }
3702
3703 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3704
3705 return NULL;
3706 }
3707
3708 static void pineview_disable_cxsr(struct drm_device *dev)
3709 {
3710 struct drm_i915_private *dev_priv = dev->dev_private;
3711
3712 /* deactivate cxsr */
3713 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3714 }
3715
3716 /*
3717 * Latency for FIFO fetches is dependent on several factors:
3718 * - memory configuration (speed, channels)
3719 * - chipset
3720 * - current MCH state
3721 * It can be fairly high in some situations, so here we assume a fairly
3722 * pessimal value. It's a tradeoff between extra memory fetches (if we
3723 * set this value too high, the FIFO will fetch frequently to stay full)
3724 * and power consumption (set it too low to save power and we might see
3725 * FIFO underruns and display "flicker").
3726 *
3727 * A value of 5us seems to be a good balance; safe for very low end
3728 * platforms but not overly aggressive on lower latency configs.
3729 */
3730 static const int latency_ns = 5000;
3731
3732 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3733 {
3734 struct drm_i915_private *dev_priv = dev->dev_private;
3735 uint32_t dsparb = I915_READ(DSPARB);
3736 int size;
3737
3738 size = dsparb & 0x7f;
3739 if (plane)
3740 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3741
3742 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3743 plane ? "B" : "A", size);
3744
3745 return size;
3746 }
3747
3748 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3749 {
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 uint32_t dsparb = I915_READ(DSPARB);
3752 int size;
3753
3754 size = dsparb & 0x1ff;
3755 if (plane)
3756 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3757 size >>= 1; /* Convert to cachelines */
3758
3759 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3760 plane ? "B" : "A", size);
3761
3762 return size;
3763 }
3764
3765 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3766 {
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768 uint32_t dsparb = I915_READ(DSPARB);
3769 int size;
3770
3771 size = dsparb & 0x7f;
3772 size >>= 2; /* Convert to cachelines */
3773
3774 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3775 plane ? "B" : "A",
3776 size);
3777
3778 return size;
3779 }
3780
3781 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3782 {
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3784 uint32_t dsparb = I915_READ(DSPARB);
3785 int size;
3786
3787 size = dsparb & 0x7f;
3788 size >>= 1; /* Convert to cachelines */
3789
3790 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3791 plane ? "B" : "A", size);
3792
3793 return size;
3794 }
3795
3796 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3797 {
3798 struct drm_crtc *crtc, *enabled = NULL;
3799
3800 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3801 if (crtc->enabled && crtc->fb) {
3802 if (enabled)
3803 return NULL;
3804 enabled = crtc;
3805 }
3806 }
3807
3808 return enabled;
3809 }
3810
3811 static void pineview_update_wm(struct drm_device *dev)
3812 {
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 struct drm_crtc *crtc;
3815 const struct cxsr_latency *latency;
3816 u32 reg;
3817 unsigned long wm;
3818
3819 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3820 dev_priv->fsb_freq, dev_priv->mem_freq);
3821 if (!latency) {
3822 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3823 pineview_disable_cxsr(dev);
3824 return;
3825 }
3826
3827 crtc = single_enabled_crtc(dev);
3828 if (crtc) {
3829 int clock = crtc->mode.clock;
3830 int pixel_size = crtc->fb->bits_per_pixel / 8;
3831
3832 /* Display SR */
3833 wm = intel_calculate_wm(clock, &pineview_display_wm,
3834 pineview_display_wm.fifo_size,
3835 pixel_size, latency->display_sr);
3836 reg = I915_READ(DSPFW1);
3837 reg &= ~DSPFW_SR_MASK;
3838 reg |= wm << DSPFW_SR_SHIFT;
3839 I915_WRITE(DSPFW1, reg);
3840 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3841
3842 /* cursor SR */
3843 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3844 pineview_display_wm.fifo_size,
3845 pixel_size, latency->cursor_sr);
3846 reg = I915_READ(DSPFW3);
3847 reg &= ~DSPFW_CURSOR_SR_MASK;
3848 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3849 I915_WRITE(DSPFW3, reg);
3850
3851 /* Display HPLL off SR */
3852 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3853 pineview_display_hplloff_wm.fifo_size,
3854 pixel_size, latency->display_hpll_disable);
3855 reg = I915_READ(DSPFW3);
3856 reg &= ~DSPFW_HPLL_SR_MASK;
3857 reg |= wm & DSPFW_HPLL_SR_MASK;
3858 I915_WRITE(DSPFW3, reg);
3859
3860 /* cursor HPLL off SR */
3861 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3862 pineview_display_hplloff_wm.fifo_size,
3863 pixel_size, latency->cursor_hpll_disable);
3864 reg = I915_READ(DSPFW3);
3865 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3866 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3867 I915_WRITE(DSPFW3, reg);
3868 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3869
3870 /* activate cxsr */
3871 I915_WRITE(DSPFW3,
3872 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3873 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3874 } else {
3875 pineview_disable_cxsr(dev);
3876 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3877 }
3878 }
3879
3880 static bool g4x_compute_wm0(struct drm_device *dev,
3881 int plane,
3882 const struct intel_watermark_params *display,
3883 int display_latency_ns,
3884 const struct intel_watermark_params *cursor,
3885 int cursor_latency_ns,
3886 int *plane_wm,
3887 int *cursor_wm)
3888 {
3889 struct drm_crtc *crtc;
3890 int htotal, hdisplay, clock, pixel_size;
3891 int line_time_us, line_count;
3892 int entries, tlb_miss;
3893
3894 crtc = intel_get_crtc_for_plane(dev, plane);
3895 if (crtc->fb == NULL || !crtc->enabled) {
3896 *cursor_wm = cursor->guard_size;
3897 *plane_wm = display->guard_size;
3898 return false;
3899 }
3900
3901 htotal = crtc->mode.htotal;
3902 hdisplay = crtc->mode.hdisplay;
3903 clock = crtc->mode.clock;
3904 pixel_size = crtc->fb->bits_per_pixel / 8;
3905
3906 /* Use the small buffer method to calculate plane watermark */
3907 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3908 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3909 if (tlb_miss > 0)
3910 entries += tlb_miss;
3911 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3912 *plane_wm = entries + display->guard_size;
3913 if (*plane_wm > (int)display->max_wm)
3914 *plane_wm = display->max_wm;
3915
3916 /* Use the large buffer method to calculate cursor watermark */
3917 line_time_us = ((htotal * 1000) / clock);
3918 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3919 entries = line_count * 64 * pixel_size;
3920 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3921 if (tlb_miss > 0)
3922 entries += tlb_miss;
3923 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3924 *cursor_wm = entries + cursor->guard_size;
3925 if (*cursor_wm > (int)cursor->max_wm)
3926 *cursor_wm = (int)cursor->max_wm;
3927
3928 return true;
3929 }
3930
3931 /*
3932 * Check the wm result.
3933 *
3934 * If any calculated watermark values is larger than the maximum value that
3935 * can be programmed into the associated watermark register, that watermark
3936 * must be disabled.
3937 */
3938 static bool g4x_check_srwm(struct drm_device *dev,
3939 int display_wm, int cursor_wm,
3940 const struct intel_watermark_params *display,
3941 const struct intel_watermark_params *cursor)
3942 {
3943 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3944 display_wm, cursor_wm);
3945
3946 if (display_wm > display->max_wm) {
3947 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3948 display_wm, display->max_wm);
3949 return false;
3950 }
3951
3952 if (cursor_wm > cursor->max_wm) {
3953 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3954 cursor_wm, cursor->max_wm);
3955 return false;
3956 }
3957
3958 if (!(display_wm || cursor_wm)) {
3959 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3960 return false;
3961 }
3962
3963 return true;
3964 }
3965
3966 static bool g4x_compute_srwm(struct drm_device *dev,
3967 int plane,
3968 int latency_ns,
3969 const struct intel_watermark_params *display,
3970 const struct intel_watermark_params *cursor,
3971 int *display_wm, int *cursor_wm)
3972 {
3973 struct drm_crtc *crtc;
3974 int hdisplay, htotal, pixel_size, clock;
3975 unsigned long line_time_us;
3976 int line_count, line_size;
3977 int small, large;
3978 int entries;
3979
3980 if (!latency_ns) {
3981 *display_wm = *cursor_wm = 0;
3982 return false;
3983 }
3984
3985 crtc = intel_get_crtc_for_plane(dev, plane);
3986 hdisplay = crtc->mode.hdisplay;
3987 htotal = crtc->mode.htotal;
3988 clock = crtc->mode.clock;
3989 pixel_size = crtc->fb->bits_per_pixel / 8;
3990
3991 line_time_us = (htotal * 1000) / clock;
3992 line_count = (latency_ns / line_time_us + 1000) / 1000;
3993 line_size = hdisplay * pixel_size;
3994
3995 /* Use the minimum of the small and large buffer method for primary */
3996 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3997 large = line_count * line_size;
3998
3999 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4000 *display_wm = entries + display->guard_size;
4001
4002 /* calculate the self-refresh watermark for display cursor */
4003 entries = line_count * pixel_size * 64;
4004 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4005 *cursor_wm = entries + cursor->guard_size;
4006
4007 return g4x_check_srwm(dev,
4008 *display_wm, *cursor_wm,
4009 display, cursor);
4010 }
4011
4012 #define single_plane_enabled(mask) is_power_of_2(mask)
4013
4014 static void g4x_update_wm(struct drm_device *dev)
4015 {
4016 static const int sr_latency_ns = 12000;
4017 struct drm_i915_private *dev_priv = dev->dev_private;
4018 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4019 int plane_sr, cursor_sr;
4020 unsigned int enabled = 0;
4021
4022 if (g4x_compute_wm0(dev, 0,
4023 &g4x_wm_info, latency_ns,
4024 &g4x_cursor_wm_info, latency_ns,
4025 &planea_wm, &cursora_wm))
4026 enabled |= 1;
4027
4028 if (g4x_compute_wm0(dev, 1,
4029 &g4x_wm_info, latency_ns,
4030 &g4x_cursor_wm_info, latency_ns,
4031 &planeb_wm, &cursorb_wm))
4032 enabled |= 2;
4033
4034 plane_sr = cursor_sr = 0;
4035 if (single_plane_enabled(enabled) &&
4036 g4x_compute_srwm(dev, ffs(enabled) - 1,
4037 sr_latency_ns,
4038 &g4x_wm_info,
4039 &g4x_cursor_wm_info,
4040 &plane_sr, &cursor_sr))
4041 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4042 else
4043 I915_WRITE(FW_BLC_SELF,
4044 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4045
4046 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4047 planea_wm, cursora_wm,
4048 planeb_wm, cursorb_wm,
4049 plane_sr, cursor_sr);
4050
4051 I915_WRITE(DSPFW1,
4052 (plane_sr << DSPFW_SR_SHIFT) |
4053 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4054 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4055 planea_wm);
4056 I915_WRITE(DSPFW2,
4057 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4058 (cursora_wm << DSPFW_CURSORA_SHIFT));
4059 /* HPLL off in SR has some issues on G4x... disable it */
4060 I915_WRITE(DSPFW3,
4061 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4062 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4063 }
4064
4065 static void i965_update_wm(struct drm_device *dev)
4066 {
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4068 struct drm_crtc *crtc;
4069 int srwm = 1;
4070 int cursor_sr = 16;
4071
4072 /* Calc sr entries for one plane configs */
4073 crtc = single_enabled_crtc(dev);
4074 if (crtc) {
4075 /* self-refresh has much higher latency */
4076 static const int sr_latency_ns = 12000;
4077 int clock = crtc->mode.clock;
4078 int htotal = crtc->mode.htotal;
4079 int hdisplay = crtc->mode.hdisplay;
4080 int pixel_size = crtc->fb->bits_per_pixel / 8;
4081 unsigned long line_time_us;
4082 int entries;
4083
4084 line_time_us = ((htotal * 1000) / clock);
4085
4086 /* Use ns/us then divide to preserve precision */
4087 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4088 pixel_size * hdisplay;
4089 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4090 srwm = I965_FIFO_SIZE - entries;
4091 if (srwm < 0)
4092 srwm = 1;
4093 srwm &= 0x1ff;
4094 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4095 entries, srwm);
4096
4097 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4098 pixel_size * 64;
4099 entries = DIV_ROUND_UP(entries,
4100 i965_cursor_wm_info.cacheline_size);
4101 cursor_sr = i965_cursor_wm_info.fifo_size -
4102 (entries + i965_cursor_wm_info.guard_size);
4103
4104 if (cursor_sr > i965_cursor_wm_info.max_wm)
4105 cursor_sr = i965_cursor_wm_info.max_wm;
4106
4107 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4108 "cursor %d\n", srwm, cursor_sr);
4109
4110 if (IS_CRESTLINE(dev))
4111 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4112 } else {
4113 /* Turn off self refresh if both pipes are enabled */
4114 if (IS_CRESTLINE(dev))
4115 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4116 & ~FW_BLC_SELF_EN);
4117 }
4118
4119 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4120 srwm);
4121
4122 /* 965 has limitations... */
4123 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4124 (8 << 16) | (8 << 8) | (8 << 0));
4125 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4126 /* update cursor SR watermark */
4127 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4128 }
4129
4130 static void i9xx_update_wm(struct drm_device *dev)
4131 {
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 const struct intel_watermark_params *wm_info;
4134 uint32_t fwater_lo;
4135 uint32_t fwater_hi;
4136 int cwm, srwm = 1;
4137 int fifo_size;
4138 int planea_wm, planeb_wm;
4139 struct drm_crtc *crtc, *enabled = NULL;
4140
4141 if (IS_I945GM(dev))
4142 wm_info = &i945_wm_info;
4143 else if (!IS_GEN2(dev))
4144 wm_info = &i915_wm_info;
4145 else
4146 wm_info = &i855_wm_info;
4147
4148 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4149 crtc = intel_get_crtc_for_plane(dev, 0);
4150 if (crtc->enabled && crtc->fb) {
4151 planea_wm = intel_calculate_wm(crtc->mode.clock,
4152 wm_info, fifo_size,
4153 crtc->fb->bits_per_pixel / 8,
4154 latency_ns);
4155 enabled = crtc;
4156 } else
4157 planea_wm = fifo_size - wm_info->guard_size;
4158
4159 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4160 crtc = intel_get_crtc_for_plane(dev, 1);
4161 if (crtc->enabled && crtc->fb) {
4162 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4163 wm_info, fifo_size,
4164 crtc->fb->bits_per_pixel / 8,
4165 latency_ns);
4166 if (enabled == NULL)
4167 enabled = crtc;
4168 else
4169 enabled = NULL;
4170 } else
4171 planeb_wm = fifo_size - wm_info->guard_size;
4172
4173 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4174
4175 /*
4176 * Overlay gets an aggressive default since video jitter is bad.
4177 */
4178 cwm = 2;
4179
4180 /* Play safe and disable self-refresh before adjusting watermarks. */
4181 if (IS_I945G(dev) || IS_I945GM(dev))
4182 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4183 else if (IS_I915GM(dev))
4184 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4185
4186 /* Calc sr entries for one plane configs */
4187 if (HAS_FW_BLC(dev) && enabled) {
4188 /* self-refresh has much higher latency */
4189 static const int sr_latency_ns = 6000;
4190 int clock = enabled->mode.clock;
4191 int htotal = enabled->mode.htotal;
4192 int hdisplay = enabled->mode.hdisplay;
4193 int pixel_size = enabled->fb->bits_per_pixel / 8;
4194 unsigned long line_time_us;
4195 int entries;
4196
4197 line_time_us = (htotal * 1000) / clock;
4198
4199 /* Use ns/us then divide to preserve precision */
4200 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4201 pixel_size * hdisplay;
4202 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4203 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4204 srwm = wm_info->fifo_size - entries;
4205 if (srwm < 0)
4206 srwm = 1;
4207
4208 if (IS_I945G(dev) || IS_I945GM(dev))
4209 I915_WRITE(FW_BLC_SELF,
4210 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4211 else if (IS_I915GM(dev))
4212 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4213 }
4214
4215 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4216 planea_wm, planeb_wm, cwm, srwm);
4217
4218 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4219 fwater_hi = (cwm & 0x1f);
4220
4221 /* Set request length to 8 cachelines per fetch */
4222 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4223 fwater_hi = fwater_hi | (1 << 8);
4224
4225 I915_WRITE(FW_BLC, fwater_lo);
4226 I915_WRITE(FW_BLC2, fwater_hi);
4227
4228 if (HAS_FW_BLC(dev)) {
4229 if (enabled) {
4230 if (IS_I945G(dev) || IS_I945GM(dev))
4231 I915_WRITE(FW_BLC_SELF,
4232 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4233 else if (IS_I915GM(dev))
4234 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4235 DRM_DEBUG_KMS("memory self refresh enabled\n");
4236 } else
4237 DRM_DEBUG_KMS("memory self refresh disabled\n");
4238 }
4239 }
4240
4241 static void i830_update_wm(struct drm_device *dev)
4242 {
4243 struct drm_i915_private *dev_priv = dev->dev_private;
4244 struct drm_crtc *crtc;
4245 uint32_t fwater_lo;
4246 int planea_wm;
4247
4248 crtc = single_enabled_crtc(dev);
4249 if (crtc == NULL)
4250 return;
4251
4252 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4253 dev_priv->display.get_fifo_size(dev, 0),
4254 crtc->fb->bits_per_pixel / 8,
4255 latency_ns);
4256 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4257 fwater_lo |= (3<<8) | planea_wm;
4258
4259 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4260
4261 I915_WRITE(FW_BLC, fwater_lo);
4262 }
4263
4264 #define ILK_LP0_PLANE_LATENCY 700
4265 #define ILK_LP0_CURSOR_LATENCY 1300
4266
4267 /*
4268 * Check the wm result.
4269 *
4270 * If any calculated watermark values is larger than the maximum value that
4271 * can be programmed into the associated watermark register, that watermark
4272 * must be disabled.
4273 */
4274 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4275 int fbc_wm, int display_wm, int cursor_wm,
4276 const struct intel_watermark_params *display,
4277 const struct intel_watermark_params *cursor)
4278 {
4279 struct drm_i915_private *dev_priv = dev->dev_private;
4280
4281 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4282 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4283
4284 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4285 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4286 fbc_wm, SNB_FBC_MAX_SRWM, level);
4287
4288 /* fbc has it's own way to disable FBC WM */
4289 I915_WRITE(DISP_ARB_CTL,
4290 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4291 return false;
4292 }
4293
4294 if (display_wm > display->max_wm) {
4295 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4296 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4297 return false;
4298 }
4299
4300 if (cursor_wm > cursor->max_wm) {
4301 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4302 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4303 return false;
4304 }
4305
4306 if (!(fbc_wm || display_wm || cursor_wm)) {
4307 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4308 return false;
4309 }
4310
4311 return true;
4312 }
4313
4314 /*
4315 * Compute watermark values of WM[1-3],
4316 */
4317 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4318 int latency_ns,
4319 const struct intel_watermark_params *display,
4320 const struct intel_watermark_params *cursor,
4321 int *fbc_wm, int *display_wm, int *cursor_wm)
4322 {
4323 struct drm_crtc *crtc;
4324 unsigned long line_time_us;
4325 int hdisplay, htotal, pixel_size, clock;
4326 int line_count, line_size;
4327 int small, large;
4328 int entries;
4329
4330 if (!latency_ns) {
4331 *fbc_wm = *display_wm = *cursor_wm = 0;
4332 return false;
4333 }
4334
4335 crtc = intel_get_crtc_for_plane(dev, plane);
4336 hdisplay = crtc->mode.hdisplay;
4337 htotal = crtc->mode.htotal;
4338 clock = crtc->mode.clock;
4339 pixel_size = crtc->fb->bits_per_pixel / 8;
4340
4341 line_time_us = (htotal * 1000) / clock;
4342 line_count = (latency_ns / line_time_us + 1000) / 1000;
4343 line_size = hdisplay * pixel_size;
4344
4345 /* Use the minimum of the small and large buffer method for primary */
4346 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4347 large = line_count * line_size;
4348
4349 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4350 *display_wm = entries + display->guard_size;
4351
4352 /*
4353 * Spec says:
4354 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4355 */
4356 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4357
4358 /* calculate the self-refresh watermark for display cursor */
4359 entries = line_count * pixel_size * 64;
4360 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4361 *cursor_wm = entries + cursor->guard_size;
4362
4363 return ironlake_check_srwm(dev, level,
4364 *fbc_wm, *display_wm, *cursor_wm,
4365 display, cursor);
4366 }
4367
4368 static void ironlake_update_wm(struct drm_device *dev)
4369 {
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371 int fbc_wm, plane_wm, cursor_wm;
4372 unsigned int enabled;
4373
4374 enabled = 0;
4375 if (g4x_compute_wm0(dev, 0,
4376 &ironlake_display_wm_info,
4377 ILK_LP0_PLANE_LATENCY,
4378 &ironlake_cursor_wm_info,
4379 ILK_LP0_CURSOR_LATENCY,
4380 &plane_wm, &cursor_wm)) {
4381 I915_WRITE(WM0_PIPEA_ILK,
4382 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4383 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4384 " plane %d, " "cursor: %d\n",
4385 plane_wm, cursor_wm);
4386 enabled |= 1;
4387 }
4388
4389 if (g4x_compute_wm0(dev, 1,
4390 &ironlake_display_wm_info,
4391 ILK_LP0_PLANE_LATENCY,
4392 &ironlake_cursor_wm_info,
4393 ILK_LP0_CURSOR_LATENCY,
4394 &plane_wm, &cursor_wm)) {
4395 I915_WRITE(WM0_PIPEB_ILK,
4396 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4397 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4398 " plane %d, cursor: %d\n",
4399 plane_wm, cursor_wm);
4400 enabled |= 2;
4401 }
4402
4403 /*
4404 * Calculate and update the self-refresh watermark only when one
4405 * display plane is used.
4406 */
4407 I915_WRITE(WM3_LP_ILK, 0);
4408 I915_WRITE(WM2_LP_ILK, 0);
4409 I915_WRITE(WM1_LP_ILK, 0);
4410
4411 if (!single_plane_enabled(enabled))
4412 return;
4413 enabled = ffs(enabled) - 1;
4414
4415 /* WM1 */
4416 if (!ironlake_compute_srwm(dev, 1, enabled,
4417 ILK_READ_WM1_LATENCY() * 500,
4418 &ironlake_display_srwm_info,
4419 &ironlake_cursor_srwm_info,
4420 &fbc_wm, &plane_wm, &cursor_wm))
4421 return;
4422
4423 I915_WRITE(WM1_LP_ILK,
4424 WM1_LP_SR_EN |
4425 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4426 (fbc_wm << WM1_LP_FBC_SHIFT) |
4427 (plane_wm << WM1_LP_SR_SHIFT) |
4428 cursor_wm);
4429
4430 /* WM2 */
4431 if (!ironlake_compute_srwm(dev, 2, enabled,
4432 ILK_READ_WM2_LATENCY() * 500,
4433 &ironlake_display_srwm_info,
4434 &ironlake_cursor_srwm_info,
4435 &fbc_wm, &plane_wm, &cursor_wm))
4436 return;
4437
4438 I915_WRITE(WM2_LP_ILK,
4439 WM2_LP_EN |
4440 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4441 (fbc_wm << WM1_LP_FBC_SHIFT) |
4442 (plane_wm << WM1_LP_SR_SHIFT) |
4443 cursor_wm);
4444
4445 /*
4446 * WM3 is unsupported on ILK, probably because we don't have latency
4447 * data for that power state
4448 */
4449 }
4450
4451 static void sandybridge_update_wm(struct drm_device *dev)
4452 {
4453 struct drm_i915_private *dev_priv = dev->dev_private;
4454 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4455 int fbc_wm, plane_wm, cursor_wm;
4456 unsigned int enabled;
4457
4458 enabled = 0;
4459 if (g4x_compute_wm0(dev, 0,
4460 &sandybridge_display_wm_info, latency,
4461 &sandybridge_cursor_wm_info, latency,
4462 &plane_wm, &cursor_wm)) {
4463 I915_WRITE(WM0_PIPEA_ILK,
4464 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4465 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4466 " plane %d, " "cursor: %d\n",
4467 plane_wm, cursor_wm);
4468 enabled |= 1;
4469 }
4470
4471 if (g4x_compute_wm0(dev, 1,
4472 &sandybridge_display_wm_info, latency,
4473 &sandybridge_cursor_wm_info, latency,
4474 &plane_wm, &cursor_wm)) {
4475 I915_WRITE(WM0_PIPEB_ILK,
4476 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4477 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4478 " plane %d, cursor: %d\n",
4479 plane_wm, cursor_wm);
4480 enabled |= 2;
4481 }
4482
4483 /*
4484 * Calculate and update the self-refresh watermark only when one
4485 * display plane is used.
4486 *
4487 * SNB support 3 levels of watermark.
4488 *
4489 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4490 * and disabled in the descending order
4491 *
4492 */
4493 I915_WRITE(WM3_LP_ILK, 0);
4494 I915_WRITE(WM2_LP_ILK, 0);
4495 I915_WRITE(WM1_LP_ILK, 0);
4496
4497 if (!single_plane_enabled(enabled))
4498 return;
4499 enabled = ffs(enabled) - 1;
4500
4501 /* WM1 */
4502 if (!ironlake_compute_srwm(dev, 1, enabled,
4503 SNB_READ_WM1_LATENCY() * 500,
4504 &sandybridge_display_srwm_info,
4505 &sandybridge_cursor_srwm_info,
4506 &fbc_wm, &plane_wm, &cursor_wm))
4507 return;
4508
4509 I915_WRITE(WM1_LP_ILK,
4510 WM1_LP_SR_EN |
4511 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4512 (fbc_wm << WM1_LP_FBC_SHIFT) |
4513 (plane_wm << WM1_LP_SR_SHIFT) |
4514 cursor_wm);
4515
4516 /* WM2 */
4517 if (!ironlake_compute_srwm(dev, 2, enabled,
4518 SNB_READ_WM2_LATENCY() * 500,
4519 &sandybridge_display_srwm_info,
4520 &sandybridge_cursor_srwm_info,
4521 &fbc_wm, &plane_wm, &cursor_wm))
4522 return;
4523
4524 I915_WRITE(WM2_LP_ILK,
4525 WM2_LP_EN |
4526 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4527 (fbc_wm << WM1_LP_FBC_SHIFT) |
4528 (plane_wm << WM1_LP_SR_SHIFT) |
4529 cursor_wm);
4530
4531 /* WM3 */
4532 if (!ironlake_compute_srwm(dev, 3, enabled,
4533 SNB_READ_WM3_LATENCY() * 500,
4534 &sandybridge_display_srwm_info,
4535 &sandybridge_cursor_srwm_info,
4536 &fbc_wm, &plane_wm, &cursor_wm))
4537 return;
4538
4539 I915_WRITE(WM3_LP_ILK,
4540 WM3_LP_EN |
4541 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4542 (fbc_wm << WM1_LP_FBC_SHIFT) |
4543 (plane_wm << WM1_LP_SR_SHIFT) |
4544 cursor_wm);
4545 }
4546
4547 /**
4548 * intel_update_watermarks - update FIFO watermark values based on current modes
4549 *
4550 * Calculate watermark values for the various WM regs based on current mode
4551 * and plane configuration.
4552 *
4553 * There are several cases to deal with here:
4554 * - normal (i.e. non-self-refresh)
4555 * - self-refresh (SR) mode
4556 * - lines are large relative to FIFO size (buffer can hold up to 2)
4557 * - lines are small relative to FIFO size (buffer can hold more than 2
4558 * lines), so need to account for TLB latency
4559 *
4560 * The normal calculation is:
4561 * watermark = dotclock * bytes per pixel * latency
4562 * where latency is platform & configuration dependent (we assume pessimal
4563 * values here).
4564 *
4565 * The SR calculation is:
4566 * watermark = (trunc(latency/line time)+1) * surface width *
4567 * bytes per pixel
4568 * where
4569 * line time = htotal / dotclock
4570 * surface width = hdisplay for normal plane and 64 for cursor
4571 * and latency is assumed to be high, as above.
4572 *
4573 * The final value programmed to the register should always be rounded up,
4574 * and include an extra 2 entries to account for clock crossings.
4575 *
4576 * We don't use the sprite, so we can ignore that. And on Crestline we have
4577 * to set the non-SR watermarks to 8.
4578 */
4579 static void intel_update_watermarks(struct drm_device *dev)
4580 {
4581 struct drm_i915_private *dev_priv = dev->dev_private;
4582
4583 if (dev_priv->display.update_wm)
4584 dev_priv->display.update_wm(dev);
4585 }
4586
4587 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4588 {
4589 return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4590 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4591 }
4592
4593 /**
4594 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4595 * @crtc: CRTC structure
4596 *
4597 * A pipe may be connected to one or more outputs. Based on the depth of the
4598 * attached framebuffer, choose a good color depth to use on the pipe.
4599 *
4600 * If possible, match the pipe depth to the fb depth. In some cases, this
4601 * isn't ideal, because the connected output supports a lesser or restricted
4602 * set of depths. Resolve that here:
4603 * LVDS typically supports only 6bpc, so clamp down in that case
4604 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4605 * Displays may support a restricted set as well, check EDID and clamp as
4606 * appropriate.
4607 *
4608 * RETURNS:
4609 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4610 * true if they don't match).
4611 */
4612 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4613 unsigned int *pipe_bpp)
4614 {
4615 struct drm_device *dev = crtc->dev;
4616 struct drm_i915_private *dev_priv = dev->dev_private;
4617 struct drm_encoder *encoder;
4618 struct drm_connector *connector;
4619 unsigned int display_bpc = UINT_MAX, bpc;
4620
4621 /* Walk the encoders & connectors on this crtc, get min bpc */
4622 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4623 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4624
4625 if (encoder->crtc != crtc)
4626 continue;
4627
4628 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4629 unsigned int lvds_bpc;
4630
4631 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4632 LVDS_A3_POWER_UP)
4633 lvds_bpc = 8;
4634 else
4635 lvds_bpc = 6;
4636
4637 if (lvds_bpc < display_bpc) {
4638 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4639 display_bpc = lvds_bpc;
4640 }
4641 continue;
4642 }
4643
4644 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4645 /* Use VBT settings if we have an eDP panel */
4646 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4647
4648 if (edp_bpc < display_bpc) {
4649 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4650 display_bpc = edp_bpc;
4651 }
4652 continue;
4653 }
4654
4655 /* Not one of the known troublemakers, check the EDID */
4656 list_for_each_entry(connector, &dev->mode_config.connector_list,
4657 head) {
4658 if (connector->encoder != encoder)
4659 continue;
4660
4661 /* Don't use an invalid EDID bpc value */
4662 if (connector->display_info.bpc &&
4663 connector->display_info.bpc < display_bpc) {
4664 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4665 display_bpc = connector->display_info.bpc;
4666 }
4667 }
4668
4669 /*
4670 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4671 * through, clamp it down. (Note: >12bpc will be caught below.)
4672 */
4673 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4674 if (display_bpc > 8 && display_bpc < 12) {
4675 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4676 display_bpc = 12;
4677 } else {
4678 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4679 display_bpc = 8;
4680 }
4681 }
4682 }
4683
4684 /*
4685 * We could just drive the pipe at the highest bpc all the time and
4686 * enable dithering as needed, but that costs bandwidth. So choose
4687 * the minimum value that expresses the full color range of the fb but
4688 * also stays within the max display bpc discovered above.
4689 */
4690
4691 switch (crtc->fb->depth) {
4692 case 8:
4693 bpc = 8; /* since we go through a colormap */
4694 break;
4695 case 15:
4696 case 16:
4697 bpc = 6; /* min is 18bpp */
4698 break;
4699 case 24:
4700 bpc = 8;
4701 break;
4702 case 30:
4703 bpc = 10;
4704 break;
4705 case 48:
4706 bpc = 12;
4707 break;
4708 default:
4709 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4710 bpc = min((unsigned int)8, display_bpc);
4711 break;
4712 }
4713
4714 display_bpc = min(display_bpc, bpc);
4715
4716 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4717 bpc, display_bpc);
4718
4719 *pipe_bpp = display_bpc * 3;
4720
4721 return display_bpc != bpc;
4722 }
4723
4724 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4725 struct drm_display_mode *mode,
4726 struct drm_display_mode *adjusted_mode,
4727 int x, int y,
4728 struct drm_framebuffer *old_fb)
4729 {
4730 struct drm_device *dev = crtc->dev;
4731 struct drm_i915_private *dev_priv = dev->dev_private;
4732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4733 int pipe = intel_crtc->pipe;
4734 int plane = intel_crtc->plane;
4735 int refclk, num_connectors = 0;
4736 intel_clock_t clock, reduced_clock;
4737 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4738 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4739 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4740 struct drm_mode_config *mode_config = &dev->mode_config;
4741 struct intel_encoder *encoder;
4742 const intel_limit_t *limit;
4743 int ret;
4744 u32 temp;
4745 u32 lvds_sync = 0;
4746
4747 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4748 if (encoder->base.crtc != crtc)
4749 continue;
4750
4751 switch (encoder->type) {
4752 case INTEL_OUTPUT_LVDS:
4753 is_lvds = true;
4754 break;
4755 case INTEL_OUTPUT_SDVO:
4756 case INTEL_OUTPUT_HDMI:
4757 is_sdvo = true;
4758 if (encoder->needs_tv_clock)
4759 is_tv = true;
4760 break;
4761 case INTEL_OUTPUT_DVO:
4762 is_dvo = true;
4763 break;
4764 case INTEL_OUTPUT_TVOUT:
4765 is_tv = true;
4766 break;
4767 case INTEL_OUTPUT_ANALOG:
4768 is_crt = true;
4769 break;
4770 case INTEL_OUTPUT_DISPLAYPORT:
4771 is_dp = true;
4772 break;
4773 }
4774
4775 num_connectors++;
4776 }
4777
4778 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4779 refclk = dev_priv->lvds_ssc_freq * 1000;
4780 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4781 refclk / 1000);
4782 } else if (!IS_GEN2(dev)) {
4783 refclk = 96000;
4784 } else {
4785 refclk = 48000;
4786 }
4787
4788 /*
4789 * Returns a set of divisors for the desired target clock with the given
4790 * refclk, or FALSE. The returned values represent the clock equation:
4791 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4792 */
4793 limit = intel_limit(crtc, refclk);
4794 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4795 if (!ok) {
4796 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4797 return -EINVAL;
4798 }
4799
4800 /* Ensure that the cursor is valid for the new mode before changing... */
4801 intel_crtc_update_cursor(crtc, true);
4802
4803 if (is_lvds && dev_priv->lvds_downclock_avail) {
4804 has_reduced_clock = limit->find_pll(limit, crtc,
4805 dev_priv->lvds_downclock,
4806 refclk,
4807 &reduced_clock);
4808 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4809 /*
4810 * If the different P is found, it means that we can't
4811 * switch the display clock by using the FP0/FP1.
4812 * In such case we will disable the LVDS downclock
4813 * feature.
4814 */
4815 DRM_DEBUG_KMS("Different P is found for "
4816 "LVDS clock/downclock\n");
4817 has_reduced_clock = 0;
4818 }
4819 }
4820 /* SDVO TV has fixed PLL values depend on its clock range,
4821 this mirrors vbios setting. */
4822 if (is_sdvo && is_tv) {
4823 if (adjusted_mode->clock >= 100000
4824 && adjusted_mode->clock < 140500) {
4825 clock.p1 = 2;
4826 clock.p2 = 10;
4827 clock.n = 3;
4828 clock.m1 = 16;
4829 clock.m2 = 8;
4830 } else if (adjusted_mode->clock >= 140500
4831 && adjusted_mode->clock <= 200000) {
4832 clock.p1 = 1;
4833 clock.p2 = 10;
4834 clock.n = 6;
4835 clock.m1 = 12;
4836 clock.m2 = 8;
4837 }
4838 }
4839
4840 if (IS_PINEVIEW(dev)) {
4841 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4842 if (has_reduced_clock)
4843 fp2 = (1 << reduced_clock.n) << 16 |
4844 reduced_clock.m1 << 8 | reduced_clock.m2;
4845 } else {
4846 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4847 if (has_reduced_clock)
4848 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4849 reduced_clock.m2;
4850 }
4851
4852 dpll = DPLL_VGA_MODE_DIS;
4853
4854 if (!IS_GEN2(dev)) {
4855 if (is_lvds)
4856 dpll |= DPLLB_MODE_LVDS;
4857 else
4858 dpll |= DPLLB_MODE_DAC_SERIAL;
4859 if (is_sdvo) {
4860 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4861 if (pixel_multiplier > 1) {
4862 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4863 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4864 }
4865 dpll |= DPLL_DVO_HIGH_SPEED;
4866 }
4867 if (is_dp)
4868 dpll |= DPLL_DVO_HIGH_SPEED;
4869
4870 /* compute bitmask from p1 value */
4871 if (IS_PINEVIEW(dev))
4872 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4873 else {
4874 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4875 if (IS_G4X(dev) && has_reduced_clock)
4876 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4877 }
4878 switch (clock.p2) {
4879 case 5:
4880 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4881 break;
4882 case 7:
4883 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4884 break;
4885 case 10:
4886 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4887 break;
4888 case 14:
4889 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4890 break;
4891 }
4892 if (INTEL_INFO(dev)->gen >= 4)
4893 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4894 } else {
4895 if (is_lvds) {
4896 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4897 } else {
4898 if (clock.p1 == 2)
4899 dpll |= PLL_P1_DIVIDE_BY_TWO;
4900 else
4901 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4902 if (clock.p2 == 4)
4903 dpll |= PLL_P2_DIVIDE_BY_4;
4904 }
4905 }
4906
4907 if (is_sdvo && is_tv)
4908 dpll |= PLL_REF_INPUT_TVCLKINBC;
4909 else if (is_tv)
4910 /* XXX: just matching BIOS for now */
4911 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4912 dpll |= 3;
4913 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4914 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4915 else
4916 dpll |= PLL_REF_INPUT_DREFCLK;
4917
4918 /* setup pipeconf */
4919 pipeconf = I915_READ(PIPECONF(pipe));
4920
4921 /* Set up the display plane register */
4922 dspcntr = DISPPLANE_GAMMA_ENABLE;
4923
4924 /* Ironlake's plane is forced to pipe, bit 24 is to
4925 enable color space conversion */
4926 if (pipe == 0)
4927 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4928 else
4929 dspcntr |= DISPPLANE_SEL_PIPE_B;
4930
4931 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4932 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4933 * core speed.
4934 *
4935 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4936 * pipe == 0 check?
4937 */
4938 if (mode->clock >
4939 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4940 pipeconf |= PIPECONF_DOUBLE_WIDE;
4941 else
4942 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4943 }
4944
4945 dpll |= DPLL_VCO_ENABLE;
4946
4947 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4948 drm_mode_debug_printmodeline(mode);
4949
4950 I915_WRITE(FP0(pipe), fp);
4951 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4952
4953 POSTING_READ(DPLL(pipe));
4954 udelay(150);
4955
4956 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4957 * This is an exception to the general rule that mode_set doesn't turn
4958 * things on.
4959 */
4960 if (is_lvds) {
4961 temp = I915_READ(LVDS);
4962 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4963 if (pipe == 1) {
4964 temp |= LVDS_PIPEB_SELECT;
4965 } else {
4966 temp &= ~LVDS_PIPEB_SELECT;
4967 }
4968 /* set the corresponsding LVDS_BORDER bit */
4969 temp |= dev_priv->lvds_border_bits;
4970 /* Set the B0-B3 data pairs corresponding to whether we're going to
4971 * set the DPLLs for dual-channel mode or not.
4972 */
4973 if (clock.p2 == 7)
4974 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4975 else
4976 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4977
4978 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4979 * appropriately here, but we need to look more thoroughly into how
4980 * panels behave in the two modes.
4981 */
4982 /* set the dithering flag on LVDS as needed */
4983 if (INTEL_INFO(dev)->gen >= 4) {
4984 if (dev_priv->lvds_dither)
4985 temp |= LVDS_ENABLE_DITHER;
4986 else
4987 temp &= ~LVDS_ENABLE_DITHER;
4988 }
4989 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4990 lvds_sync |= LVDS_HSYNC_POLARITY;
4991 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4992 lvds_sync |= LVDS_VSYNC_POLARITY;
4993 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4994 != lvds_sync) {
4995 char flags[2] = "-+";
4996 DRM_INFO("Changing LVDS panel from "
4997 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4998 flags[!(temp & LVDS_HSYNC_POLARITY)],
4999 flags[!(temp & LVDS_VSYNC_POLARITY)],
5000 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5001 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5002 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5003 temp |= lvds_sync;
5004 }
5005 I915_WRITE(LVDS, temp);
5006 }
5007
5008 if (is_dp) {
5009 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5010 }
5011
5012 I915_WRITE(DPLL(pipe), dpll);
5013
5014 /* Wait for the clocks to stabilize. */
5015 POSTING_READ(DPLL(pipe));
5016 udelay(150);
5017
5018 if (INTEL_INFO(dev)->gen >= 4) {
5019 temp = 0;
5020 if (is_sdvo) {
5021 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5022 if (temp > 1)
5023 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5024 else
5025 temp = 0;
5026 }
5027 I915_WRITE(DPLL_MD(pipe), temp);
5028 } else {
5029 /* The pixel multiplier can only be updated once the
5030 * DPLL is enabled and the clocks are stable.
5031 *
5032 * So write it again.
5033 */
5034 I915_WRITE(DPLL(pipe), dpll);
5035 }
5036
5037 intel_crtc->lowfreq_avail = false;
5038 if (is_lvds && has_reduced_clock && i915_powersave) {
5039 I915_WRITE(FP1(pipe), fp2);
5040 intel_crtc->lowfreq_avail = true;
5041 if (HAS_PIPE_CXSR(dev)) {
5042 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5043 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5044 }
5045 } else {
5046 I915_WRITE(FP1(pipe), fp);
5047 if (HAS_PIPE_CXSR(dev)) {
5048 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5049 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5050 }
5051 }
5052
5053 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5054 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5055 /* the chip adds 2 halflines automatically */
5056 adjusted_mode->crtc_vdisplay -= 1;
5057 adjusted_mode->crtc_vtotal -= 1;
5058 adjusted_mode->crtc_vblank_start -= 1;
5059 adjusted_mode->crtc_vblank_end -= 1;
5060 adjusted_mode->crtc_vsync_end -= 1;
5061 adjusted_mode->crtc_vsync_start -= 1;
5062 } else
5063 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5064
5065 I915_WRITE(HTOTAL(pipe),
5066 (adjusted_mode->crtc_hdisplay - 1) |
5067 ((adjusted_mode->crtc_htotal - 1) << 16));
5068 I915_WRITE(HBLANK(pipe),
5069 (adjusted_mode->crtc_hblank_start - 1) |
5070 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5071 I915_WRITE(HSYNC(pipe),
5072 (adjusted_mode->crtc_hsync_start - 1) |
5073 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5074
5075 I915_WRITE(VTOTAL(pipe),
5076 (adjusted_mode->crtc_vdisplay - 1) |
5077 ((adjusted_mode->crtc_vtotal - 1) << 16));
5078 I915_WRITE(VBLANK(pipe),
5079 (adjusted_mode->crtc_vblank_start - 1) |
5080 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5081 I915_WRITE(VSYNC(pipe),
5082 (adjusted_mode->crtc_vsync_start - 1) |
5083 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5084
5085 /* pipesrc and dspsize control the size that is scaled from,
5086 * which should always be the user's requested size.
5087 */
5088 I915_WRITE(DSPSIZE(plane),
5089 ((mode->vdisplay - 1) << 16) |
5090 (mode->hdisplay - 1));
5091 I915_WRITE(DSPPOS(plane), 0);
5092 I915_WRITE(PIPESRC(pipe),
5093 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5094
5095 I915_WRITE(PIPECONF(pipe), pipeconf);
5096 POSTING_READ(PIPECONF(pipe));
5097 intel_enable_pipe(dev_priv, pipe, false);
5098
5099 intel_wait_for_vblank(dev, pipe);
5100
5101 I915_WRITE(DSPCNTR(plane), dspcntr);
5102 POSTING_READ(DSPCNTR(plane));
5103 intel_enable_plane(dev_priv, plane, pipe);
5104
5105 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5106
5107 intel_update_watermarks(dev);
5108
5109 return ret;
5110 }
5111
5112 static void ironlake_update_pch_refclk(struct drm_device *dev)
5113 {
5114 struct drm_i915_private *dev_priv = dev->dev_private;
5115 struct drm_mode_config *mode_config = &dev->mode_config;
5116 struct drm_crtc *crtc;
5117 struct intel_encoder *encoder;
5118 struct intel_encoder *has_edp_encoder = NULL;
5119 u32 temp;
5120 bool has_lvds = false;
5121
5122 /* We need to take the global config into account */
5123 list_for_each_entry(crtc, &mode_config->crtc_list, head) {
5124 if (!crtc->enabled)
5125 continue;
5126
5127 list_for_each_entry(encoder, &mode_config->encoder_list,
5128 base.head) {
5129 if (encoder->base.crtc != crtc)
5130 continue;
5131
5132 switch (encoder->type) {
5133 case INTEL_OUTPUT_LVDS:
5134 has_lvds = true;
5135 case INTEL_OUTPUT_EDP:
5136 has_edp_encoder = encoder;
5137 break;
5138 }
5139 }
5140 }
5141
5142 /* Ironlake: try to setup display ref clock before DPLL
5143 * enabling. This is only under driver's control after
5144 * PCH B stepping, previous chipset stepping should be
5145 * ignoring this setting.
5146 */
5147 temp = I915_READ(PCH_DREF_CONTROL);
5148 /* Always enable nonspread source */
5149 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5150 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5151 temp &= ~DREF_SSC_SOURCE_MASK;
5152 temp |= DREF_SSC_SOURCE_ENABLE;
5153 I915_WRITE(PCH_DREF_CONTROL, temp);
5154
5155 POSTING_READ(PCH_DREF_CONTROL);
5156 udelay(200);
5157
5158 if (has_edp_encoder) {
5159 if (intel_panel_use_ssc(dev_priv)) {
5160 temp |= DREF_SSC1_ENABLE;
5161 I915_WRITE(PCH_DREF_CONTROL, temp);
5162
5163 POSTING_READ(PCH_DREF_CONTROL);
5164 udelay(200);
5165 }
5166 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5167
5168 /* Enable CPU source on CPU attached eDP */
5169 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5170 if (intel_panel_use_ssc(dev_priv))
5171 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5172 else
5173 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5174 } else {
5175 /* Enable SSC on PCH eDP if needed */
5176 if (intel_panel_use_ssc(dev_priv)) {
5177 DRM_ERROR("enabling SSC on PCH\n");
5178 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5179 }
5180 }
5181 I915_WRITE(PCH_DREF_CONTROL, temp);
5182 POSTING_READ(PCH_DREF_CONTROL);
5183 udelay(200);
5184 }
5185 }
5186
5187 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5188 struct drm_display_mode *mode,
5189 struct drm_display_mode *adjusted_mode,
5190 int x, int y,
5191 struct drm_framebuffer *old_fb)
5192 {
5193 struct drm_device *dev = crtc->dev;
5194 struct drm_i915_private *dev_priv = dev->dev_private;
5195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5196 int pipe = intel_crtc->pipe;
5197 int plane = intel_crtc->plane;
5198 int refclk, num_connectors = 0;
5199 intel_clock_t clock, reduced_clock;
5200 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5201 bool ok, has_reduced_clock = false, is_sdvo = false;
5202 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5203 struct intel_encoder *has_edp_encoder = NULL;
5204 struct drm_mode_config *mode_config = &dev->mode_config;
5205 struct intel_encoder *encoder;
5206 const intel_limit_t *limit;
5207 int ret;
5208 struct fdi_m_n m_n = {0};
5209 u32 temp;
5210 u32 lvds_sync = 0;
5211 int target_clock, pixel_multiplier, lane, link_bw, factor;
5212 unsigned int pipe_bpp;
5213 bool dither;
5214
5215 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5216 if (encoder->base.crtc != crtc)
5217 continue;
5218
5219 switch (encoder->type) {
5220 case INTEL_OUTPUT_LVDS:
5221 is_lvds = true;
5222 break;
5223 case INTEL_OUTPUT_SDVO:
5224 case INTEL_OUTPUT_HDMI:
5225 is_sdvo = true;
5226 if (encoder->needs_tv_clock)
5227 is_tv = true;
5228 break;
5229 case INTEL_OUTPUT_TVOUT:
5230 is_tv = true;
5231 break;
5232 case INTEL_OUTPUT_ANALOG:
5233 is_crt = true;
5234 break;
5235 case INTEL_OUTPUT_DISPLAYPORT:
5236 is_dp = true;
5237 break;
5238 case INTEL_OUTPUT_EDP:
5239 has_edp_encoder = encoder;
5240 break;
5241 }
5242
5243 num_connectors++;
5244 }
5245
5246 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5247 refclk = dev_priv->lvds_ssc_freq * 1000;
5248 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5249 refclk / 1000);
5250 } else {
5251 refclk = 96000;
5252 if (!has_edp_encoder ||
5253 intel_encoder_is_pch_edp(&has_edp_encoder->base))
5254 refclk = 120000; /* 120Mhz refclk */
5255 }
5256
5257 /*
5258 * Returns a set of divisors for the desired target clock with the given
5259 * refclk, or FALSE. The returned values represent the clock equation:
5260 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5261 */
5262 limit = intel_limit(crtc, refclk);
5263 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5264 if (!ok) {
5265 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5266 return -EINVAL;
5267 }
5268
5269 /* Ensure that the cursor is valid for the new mode before changing... */
5270 intel_crtc_update_cursor(crtc, true);
5271
5272 if (is_lvds && dev_priv->lvds_downclock_avail) {
5273 has_reduced_clock = limit->find_pll(limit, crtc,
5274 dev_priv->lvds_downclock,
5275 refclk,
5276 &reduced_clock);
5277 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5278 /*
5279 * If the different P is found, it means that we can't
5280 * switch the display clock by using the FP0/FP1.
5281 * In such case we will disable the LVDS downclock
5282 * feature.
5283 */
5284 DRM_DEBUG_KMS("Different P is found for "
5285 "LVDS clock/downclock\n");
5286 has_reduced_clock = 0;
5287 }
5288 }
5289 /* SDVO TV has fixed PLL values depend on its clock range,
5290 this mirrors vbios setting. */
5291 if (is_sdvo && is_tv) {
5292 if (adjusted_mode->clock >= 100000
5293 && adjusted_mode->clock < 140500) {
5294 clock.p1 = 2;
5295 clock.p2 = 10;
5296 clock.n = 3;
5297 clock.m1 = 16;
5298 clock.m2 = 8;
5299 } else if (adjusted_mode->clock >= 140500
5300 && adjusted_mode->clock <= 200000) {
5301 clock.p1 = 1;
5302 clock.p2 = 10;
5303 clock.n = 6;
5304 clock.m1 = 12;
5305 clock.m2 = 8;
5306 }
5307 }
5308
5309 /* FDI link */
5310 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5311 lane = 0;
5312 /* CPU eDP doesn't require FDI link, so just set DP M/N
5313 according to current link config */
5314 if (has_edp_encoder &&
5315 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5316 target_clock = mode->clock;
5317 intel_edp_link_config(has_edp_encoder,
5318 &lane, &link_bw);
5319 } else {
5320 /* [e]DP over FDI requires target mode clock
5321 instead of link clock */
5322 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5323 target_clock = mode->clock;
5324 else
5325 target_clock = adjusted_mode->clock;
5326
5327 /* FDI is a binary signal running at ~2.7GHz, encoding
5328 * each output octet as 10 bits. The actual frequency
5329 * is stored as a divider into a 100MHz clock, and the
5330 * mode pixel clock is stored in units of 1KHz.
5331 * Hence the bw of each lane in terms of the mode signal
5332 * is:
5333 */
5334 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5335 }
5336
5337 /* determine panel color depth */
5338 temp = I915_READ(PIPECONF(pipe));
5339 temp &= ~PIPE_BPC_MASK;
5340 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5341 switch (pipe_bpp) {
5342 case 18:
5343 temp |= PIPE_6BPC;
5344 break;
5345 case 24:
5346 temp |= PIPE_8BPC;
5347 break;
5348 case 30:
5349 temp |= PIPE_10BPC;
5350 break;
5351 case 36:
5352 temp |= PIPE_12BPC;
5353 break;
5354 default:
5355 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5356 pipe_bpp);
5357 temp |= PIPE_8BPC;
5358 pipe_bpp = 24;
5359 break;
5360 }
5361
5362 intel_crtc->bpp = pipe_bpp;
5363 I915_WRITE(PIPECONF(pipe), temp);
5364
5365 if (!lane) {
5366 /*
5367 * Account for spread spectrum to avoid
5368 * oversubscribing the link. Max center spread
5369 * is 2.5%; use 5% for safety's sake.
5370 */
5371 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5372 lane = bps / (link_bw * 8) + 1;
5373 }
5374
5375 intel_crtc->fdi_lanes = lane;
5376
5377 if (pixel_multiplier > 1)
5378 link_bw *= pixel_multiplier;
5379 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5380 &m_n);
5381
5382 ironlake_update_pch_refclk(dev);
5383
5384 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5385 if (has_reduced_clock)
5386 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5387 reduced_clock.m2;
5388
5389 /* Enable autotuning of the PLL clock (if permissible) */
5390 factor = 21;
5391 if (is_lvds) {
5392 if ((intel_panel_use_ssc(dev_priv) &&
5393 dev_priv->lvds_ssc_freq == 100) ||
5394 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5395 factor = 25;
5396 } else if (is_sdvo && is_tv)
5397 factor = 20;
5398
5399 if (clock.m < factor * clock.n)
5400 fp |= FP_CB_TUNE;
5401
5402 dpll = 0;
5403
5404 if (is_lvds)
5405 dpll |= DPLLB_MODE_LVDS;
5406 else
5407 dpll |= DPLLB_MODE_DAC_SERIAL;
5408 if (is_sdvo) {
5409 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5410 if (pixel_multiplier > 1) {
5411 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5412 }
5413 dpll |= DPLL_DVO_HIGH_SPEED;
5414 }
5415 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5416 dpll |= DPLL_DVO_HIGH_SPEED;
5417
5418 /* compute bitmask from p1 value */
5419 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5420 /* also FPA1 */
5421 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5422
5423 switch (clock.p2) {
5424 case 5:
5425 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5426 break;
5427 case 7:
5428 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5429 break;
5430 case 10:
5431 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5432 break;
5433 case 14:
5434 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5435 break;
5436 }
5437
5438 if (is_sdvo && is_tv)
5439 dpll |= PLL_REF_INPUT_TVCLKINBC;
5440 else if (is_tv)
5441 /* XXX: just matching BIOS for now */
5442 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5443 dpll |= 3;
5444 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5445 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5446 else
5447 dpll |= PLL_REF_INPUT_DREFCLK;
5448
5449 /* setup pipeconf */
5450 pipeconf = I915_READ(PIPECONF(pipe));
5451
5452 /* Set up the display plane register */
5453 dspcntr = DISPPLANE_GAMMA_ENABLE;
5454
5455 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5456 drm_mode_debug_printmodeline(mode);
5457
5458 /* PCH eDP needs FDI, but CPU eDP does not */
5459 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5460 I915_WRITE(PCH_FP0(pipe), fp);
5461 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5462
5463 POSTING_READ(PCH_DPLL(pipe));
5464 udelay(150);
5465 }
5466
5467 /* enable transcoder DPLL */
5468 if (HAS_PCH_CPT(dev)) {
5469 temp = I915_READ(PCH_DPLL_SEL);
5470 switch (pipe) {
5471 case 0:
5472 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5473 break;
5474 case 1:
5475 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5476 break;
5477 case 2:
5478 /* FIXME: manage transcoder PLLs? */
5479 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5480 break;
5481 default:
5482 BUG();
5483 }
5484 I915_WRITE(PCH_DPLL_SEL, temp);
5485
5486 POSTING_READ(PCH_DPLL_SEL);
5487 udelay(150);
5488 }
5489
5490 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5491 * This is an exception to the general rule that mode_set doesn't turn
5492 * things on.
5493 */
5494 if (is_lvds) {
5495 temp = I915_READ(PCH_LVDS);
5496 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5497 if (pipe == 1) {
5498 if (HAS_PCH_CPT(dev))
5499 temp |= PORT_TRANS_B_SEL_CPT;
5500 else
5501 temp |= LVDS_PIPEB_SELECT;
5502 } else {
5503 if (HAS_PCH_CPT(dev))
5504 temp &= ~PORT_TRANS_SEL_MASK;
5505 else
5506 temp &= ~LVDS_PIPEB_SELECT;
5507 }
5508 /* set the corresponsding LVDS_BORDER bit */
5509 temp |= dev_priv->lvds_border_bits;
5510 /* Set the B0-B3 data pairs corresponding to whether we're going to
5511 * set the DPLLs for dual-channel mode or not.
5512 */
5513 if (clock.p2 == 7)
5514 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5515 else
5516 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5517
5518 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5519 * appropriately here, but we need to look more thoroughly into how
5520 * panels behave in the two modes.
5521 */
5522 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5523 lvds_sync |= LVDS_HSYNC_POLARITY;
5524 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5525 lvds_sync |= LVDS_VSYNC_POLARITY;
5526 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5527 != lvds_sync) {
5528 char flags[2] = "-+";
5529 DRM_INFO("Changing LVDS panel from "
5530 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5531 flags[!(temp & LVDS_HSYNC_POLARITY)],
5532 flags[!(temp & LVDS_VSYNC_POLARITY)],
5533 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5534 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5535 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5536 temp |= lvds_sync;
5537 }
5538 I915_WRITE(PCH_LVDS, temp);
5539 }
5540
5541 pipeconf &= ~PIPECONF_DITHER_EN;
5542 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5543 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5544 pipeconf |= PIPECONF_DITHER_EN;
5545 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5546 }
5547 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5548 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5549 } else {
5550 /* For non-DP output, clear any trans DP clock recovery setting.*/
5551 I915_WRITE(TRANSDATA_M1(pipe), 0);
5552 I915_WRITE(TRANSDATA_N1(pipe), 0);
5553 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5554 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5555 }
5556
5557 if (!has_edp_encoder ||
5558 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5559 I915_WRITE(PCH_DPLL(pipe), dpll);
5560
5561 /* Wait for the clocks to stabilize. */
5562 POSTING_READ(PCH_DPLL(pipe));
5563 udelay(150);
5564
5565 /* The pixel multiplier can only be updated once the
5566 * DPLL is enabled and the clocks are stable.
5567 *
5568 * So write it again.
5569 */
5570 I915_WRITE(PCH_DPLL(pipe), dpll);
5571 }
5572
5573 intel_crtc->lowfreq_avail = false;
5574 if (is_lvds && has_reduced_clock && i915_powersave) {
5575 I915_WRITE(PCH_FP1(pipe), fp2);
5576 intel_crtc->lowfreq_avail = true;
5577 if (HAS_PIPE_CXSR(dev)) {
5578 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5579 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5580 }
5581 } else {
5582 I915_WRITE(PCH_FP1(pipe), fp);
5583 if (HAS_PIPE_CXSR(dev)) {
5584 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5585 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5586 }
5587 }
5588
5589 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5590 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5591 /* the chip adds 2 halflines automatically */
5592 adjusted_mode->crtc_vdisplay -= 1;
5593 adjusted_mode->crtc_vtotal -= 1;
5594 adjusted_mode->crtc_vblank_start -= 1;
5595 adjusted_mode->crtc_vblank_end -= 1;
5596 adjusted_mode->crtc_vsync_end -= 1;
5597 adjusted_mode->crtc_vsync_start -= 1;
5598 } else
5599 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5600
5601 I915_WRITE(HTOTAL(pipe),
5602 (adjusted_mode->crtc_hdisplay - 1) |
5603 ((adjusted_mode->crtc_htotal - 1) << 16));
5604 I915_WRITE(HBLANK(pipe),
5605 (adjusted_mode->crtc_hblank_start - 1) |
5606 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5607 I915_WRITE(HSYNC(pipe),
5608 (adjusted_mode->crtc_hsync_start - 1) |
5609 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5610
5611 I915_WRITE(VTOTAL(pipe),
5612 (adjusted_mode->crtc_vdisplay - 1) |
5613 ((adjusted_mode->crtc_vtotal - 1) << 16));
5614 I915_WRITE(VBLANK(pipe),
5615 (adjusted_mode->crtc_vblank_start - 1) |
5616 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5617 I915_WRITE(VSYNC(pipe),
5618 (adjusted_mode->crtc_vsync_start - 1) |
5619 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5620
5621 /* pipesrc controls the size that is scaled from, which should
5622 * always be the user's requested size.
5623 */
5624 I915_WRITE(PIPESRC(pipe),
5625 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5626
5627 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5628 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5629 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5630 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5631
5632 if (has_edp_encoder &&
5633 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5634 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5635 }
5636
5637 I915_WRITE(PIPECONF(pipe), pipeconf);
5638 POSTING_READ(PIPECONF(pipe));
5639
5640 intel_wait_for_vblank(dev, pipe);
5641
5642 if (IS_GEN5(dev)) {
5643 /* enable address swizzle for tiling buffer */
5644 temp = I915_READ(DISP_ARB_CTL);
5645 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5646 }
5647
5648 I915_WRITE(DSPCNTR(plane), dspcntr);
5649 POSTING_READ(DSPCNTR(plane));
5650
5651 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5652
5653 intel_update_watermarks(dev);
5654
5655 return ret;
5656 }
5657
5658 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5659 struct drm_display_mode *mode,
5660 struct drm_display_mode *adjusted_mode,
5661 int x, int y,
5662 struct drm_framebuffer *old_fb)
5663 {
5664 struct drm_device *dev = crtc->dev;
5665 struct drm_i915_private *dev_priv = dev->dev_private;
5666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5667 int pipe = intel_crtc->pipe;
5668 int ret;
5669
5670 drm_vblank_pre_modeset(dev, pipe);
5671
5672 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5673 x, y, old_fb);
5674
5675 drm_vblank_post_modeset(dev, pipe);
5676
5677 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5678
5679 return ret;
5680 }
5681
5682 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5683 void intel_crtc_load_lut(struct drm_crtc *crtc)
5684 {
5685 struct drm_device *dev = crtc->dev;
5686 struct drm_i915_private *dev_priv = dev->dev_private;
5687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5688 int palreg = PALETTE(intel_crtc->pipe);
5689 int i;
5690
5691 /* The clocks have to be on to load the palette. */
5692 if (!crtc->enabled)
5693 return;
5694
5695 /* use legacy palette for Ironlake */
5696 if (HAS_PCH_SPLIT(dev))
5697 palreg = LGC_PALETTE(intel_crtc->pipe);
5698
5699 for (i = 0; i < 256; i++) {
5700 I915_WRITE(palreg + 4 * i,
5701 (intel_crtc->lut_r[i] << 16) |
5702 (intel_crtc->lut_g[i] << 8) |
5703 intel_crtc->lut_b[i]);
5704 }
5705 }
5706
5707 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5708 {
5709 struct drm_device *dev = crtc->dev;
5710 struct drm_i915_private *dev_priv = dev->dev_private;
5711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5712 bool visible = base != 0;
5713 u32 cntl;
5714
5715 if (intel_crtc->cursor_visible == visible)
5716 return;
5717
5718 cntl = I915_READ(_CURACNTR);
5719 if (visible) {
5720 /* On these chipsets we can only modify the base whilst
5721 * the cursor is disabled.
5722 */
5723 I915_WRITE(_CURABASE, base);
5724
5725 cntl &= ~(CURSOR_FORMAT_MASK);
5726 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5727 cntl |= CURSOR_ENABLE |
5728 CURSOR_GAMMA_ENABLE |
5729 CURSOR_FORMAT_ARGB;
5730 } else
5731 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5732 I915_WRITE(_CURACNTR, cntl);
5733
5734 intel_crtc->cursor_visible = visible;
5735 }
5736
5737 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5738 {
5739 struct drm_device *dev = crtc->dev;
5740 struct drm_i915_private *dev_priv = dev->dev_private;
5741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5742 int pipe = intel_crtc->pipe;
5743 bool visible = base != 0;
5744
5745 if (intel_crtc->cursor_visible != visible) {
5746 uint32_t cntl = I915_READ(CURCNTR(pipe));
5747 if (base) {
5748 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5749 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5750 cntl |= pipe << 28; /* Connect to correct pipe */
5751 } else {
5752 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5753 cntl |= CURSOR_MODE_DISABLE;
5754 }
5755 I915_WRITE(CURCNTR(pipe), cntl);
5756
5757 intel_crtc->cursor_visible = visible;
5758 }
5759 /* and commit changes on next vblank */
5760 I915_WRITE(CURBASE(pipe), base);
5761 }
5762
5763 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5764 {
5765 struct drm_device *dev = crtc->dev;
5766 struct drm_i915_private *dev_priv = dev->dev_private;
5767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5768 int pipe = intel_crtc->pipe;
5769 bool visible = base != 0;
5770
5771 if (intel_crtc->cursor_visible != visible) {
5772 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5773 if (base) {
5774 cntl &= ~CURSOR_MODE;
5775 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5776 } else {
5777 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5778 cntl |= CURSOR_MODE_DISABLE;
5779 }
5780 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5781
5782 intel_crtc->cursor_visible = visible;
5783 }
5784 /* and commit changes on next vblank */
5785 I915_WRITE(CURBASE_IVB(pipe), base);
5786 }
5787
5788 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5789 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5790 bool on)
5791 {
5792 struct drm_device *dev = crtc->dev;
5793 struct drm_i915_private *dev_priv = dev->dev_private;
5794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5795 int pipe = intel_crtc->pipe;
5796 int x = intel_crtc->cursor_x;
5797 int y = intel_crtc->cursor_y;
5798 u32 base, pos;
5799 bool visible;
5800
5801 pos = 0;
5802
5803 if (on && crtc->enabled && crtc->fb) {
5804 base = intel_crtc->cursor_addr;
5805 if (x > (int) crtc->fb->width)
5806 base = 0;
5807
5808 if (y > (int) crtc->fb->height)
5809 base = 0;
5810 } else
5811 base = 0;
5812
5813 if (x < 0) {
5814 if (x + intel_crtc->cursor_width < 0)
5815 base = 0;
5816
5817 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5818 x = -x;
5819 }
5820 pos |= x << CURSOR_X_SHIFT;
5821
5822 if (y < 0) {
5823 if (y + intel_crtc->cursor_height < 0)
5824 base = 0;
5825
5826 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5827 y = -y;
5828 }
5829 pos |= y << CURSOR_Y_SHIFT;
5830
5831 visible = base != 0;
5832 if (!visible && !intel_crtc->cursor_visible)
5833 return;
5834
5835 if (IS_IVYBRIDGE(dev)) {
5836 I915_WRITE(CURPOS_IVB(pipe), pos);
5837 ivb_update_cursor(crtc, base);
5838 } else {
5839 I915_WRITE(CURPOS(pipe), pos);
5840 if (IS_845G(dev) || IS_I865G(dev))
5841 i845_update_cursor(crtc, base);
5842 else
5843 i9xx_update_cursor(crtc, base);
5844 }
5845
5846 if (visible)
5847 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5848 }
5849
5850 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5851 struct drm_file *file,
5852 uint32_t handle,
5853 uint32_t width, uint32_t height)
5854 {
5855 struct drm_device *dev = crtc->dev;
5856 struct drm_i915_private *dev_priv = dev->dev_private;
5857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5858 struct drm_i915_gem_object *obj;
5859 uint32_t addr;
5860 int ret;
5861
5862 DRM_DEBUG_KMS("\n");
5863
5864 /* if we want to turn off the cursor ignore width and height */
5865 if (!handle) {
5866 DRM_DEBUG_KMS("cursor off\n");
5867 addr = 0;
5868 obj = NULL;
5869 mutex_lock(&dev->struct_mutex);
5870 goto finish;
5871 }
5872
5873 /* Currently we only support 64x64 cursors */
5874 if (width != 64 || height != 64) {
5875 DRM_ERROR("we currently only support 64x64 cursors\n");
5876 return -EINVAL;
5877 }
5878
5879 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5880 if (&obj->base == NULL)
5881 return -ENOENT;
5882
5883 if (obj->base.size < width * height * 4) {
5884 DRM_ERROR("buffer is to small\n");
5885 ret = -ENOMEM;
5886 goto fail;
5887 }
5888
5889 /* we only need to pin inside GTT if cursor is non-phy */
5890 mutex_lock(&dev->struct_mutex);
5891 if (!dev_priv->info->cursor_needs_physical) {
5892 if (obj->tiling_mode) {
5893 DRM_ERROR("cursor cannot be tiled\n");
5894 ret = -EINVAL;
5895 goto fail_locked;
5896 }
5897
5898 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5899 if (ret) {
5900 DRM_ERROR("failed to move cursor bo into the GTT\n");
5901 goto fail_locked;
5902 }
5903
5904 ret = i915_gem_object_put_fence(obj);
5905 if (ret) {
5906 DRM_ERROR("failed to release fence for cursor");
5907 goto fail_unpin;
5908 }
5909
5910 addr = obj->gtt_offset;
5911 } else {
5912 int align = IS_I830(dev) ? 16 * 1024 : 256;
5913 ret = i915_gem_attach_phys_object(dev, obj,
5914 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5915 align);
5916 if (ret) {
5917 DRM_ERROR("failed to attach phys object\n");
5918 goto fail_locked;
5919 }
5920 addr = obj->phys_obj->handle->busaddr;
5921 }
5922
5923 if (IS_GEN2(dev))
5924 I915_WRITE(CURSIZE, (height << 12) | width);
5925
5926 finish:
5927 if (intel_crtc->cursor_bo) {
5928 if (dev_priv->info->cursor_needs_physical) {
5929 if (intel_crtc->cursor_bo != obj)
5930 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5931 } else
5932 i915_gem_object_unpin(intel_crtc->cursor_bo);
5933 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5934 }
5935
5936 mutex_unlock(&dev->struct_mutex);
5937
5938 intel_crtc->cursor_addr = addr;
5939 intel_crtc->cursor_bo = obj;
5940 intel_crtc->cursor_width = width;
5941 intel_crtc->cursor_height = height;
5942
5943 intel_crtc_update_cursor(crtc, true);
5944
5945 return 0;
5946 fail_unpin:
5947 i915_gem_object_unpin(obj);
5948 fail_locked:
5949 mutex_unlock(&dev->struct_mutex);
5950 fail:
5951 drm_gem_object_unreference_unlocked(&obj->base);
5952 return ret;
5953 }
5954
5955 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5956 {
5957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5958
5959 intel_crtc->cursor_x = x;
5960 intel_crtc->cursor_y = y;
5961
5962 intel_crtc_update_cursor(crtc, true);
5963
5964 return 0;
5965 }
5966
5967 /** Sets the color ramps on behalf of RandR */
5968 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5969 u16 blue, int regno)
5970 {
5971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5972
5973 intel_crtc->lut_r[regno] = red >> 8;
5974 intel_crtc->lut_g[regno] = green >> 8;
5975 intel_crtc->lut_b[regno] = blue >> 8;
5976 }
5977
5978 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5979 u16 *blue, int regno)
5980 {
5981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5982
5983 *red = intel_crtc->lut_r[regno] << 8;
5984 *green = intel_crtc->lut_g[regno] << 8;
5985 *blue = intel_crtc->lut_b[regno] << 8;
5986 }
5987
5988 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5989 u16 *blue, uint32_t start, uint32_t size)
5990 {
5991 int end = (start + size > 256) ? 256 : start + size, i;
5992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5993
5994 for (i = start; i < end; i++) {
5995 intel_crtc->lut_r[i] = red[i] >> 8;
5996 intel_crtc->lut_g[i] = green[i] >> 8;
5997 intel_crtc->lut_b[i] = blue[i] >> 8;
5998 }
5999
6000 intel_crtc_load_lut(crtc);
6001 }
6002
6003 /**
6004 * Get a pipe with a simple mode set on it for doing load-based monitor
6005 * detection.
6006 *
6007 * It will be up to the load-detect code to adjust the pipe as appropriate for
6008 * its requirements. The pipe will be connected to no other encoders.
6009 *
6010 * Currently this code will only succeed if there is a pipe with no encoders
6011 * configured for it. In the future, it could choose to temporarily disable
6012 * some outputs to free up a pipe for its use.
6013 *
6014 * \return crtc, or NULL if no pipes are available.
6015 */
6016
6017 /* VESA 640x480x72Hz mode to set on the pipe */
6018 static struct drm_display_mode load_detect_mode = {
6019 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6020 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6021 };
6022
6023 static struct drm_framebuffer *
6024 intel_framebuffer_create(struct drm_device *dev,
6025 struct drm_mode_fb_cmd *mode_cmd,
6026 struct drm_i915_gem_object *obj)
6027 {
6028 struct intel_framebuffer *intel_fb;
6029 int ret;
6030
6031 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6032 if (!intel_fb) {
6033 drm_gem_object_unreference_unlocked(&obj->base);
6034 return ERR_PTR(-ENOMEM);
6035 }
6036
6037 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6038 if (ret) {
6039 drm_gem_object_unreference_unlocked(&obj->base);
6040 kfree(intel_fb);
6041 return ERR_PTR(ret);
6042 }
6043
6044 return &intel_fb->base;
6045 }
6046
6047 static u32
6048 intel_framebuffer_pitch_for_width(int width, int bpp)
6049 {
6050 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6051 return ALIGN(pitch, 64);
6052 }
6053
6054 static u32
6055 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6056 {
6057 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6058 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6059 }
6060
6061 static struct drm_framebuffer *
6062 intel_framebuffer_create_for_mode(struct drm_device *dev,
6063 struct drm_display_mode *mode,
6064 int depth, int bpp)
6065 {
6066 struct drm_i915_gem_object *obj;
6067 struct drm_mode_fb_cmd mode_cmd;
6068
6069 obj = i915_gem_alloc_object(dev,
6070 intel_framebuffer_size_for_mode(mode, bpp));
6071 if (obj == NULL)
6072 return ERR_PTR(-ENOMEM);
6073
6074 mode_cmd.width = mode->hdisplay;
6075 mode_cmd.height = mode->vdisplay;
6076 mode_cmd.depth = depth;
6077 mode_cmd.bpp = bpp;
6078 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6079
6080 return intel_framebuffer_create(dev, &mode_cmd, obj);
6081 }
6082
6083 static struct drm_framebuffer *
6084 mode_fits_in_fbdev(struct drm_device *dev,
6085 struct drm_display_mode *mode)
6086 {
6087 struct drm_i915_private *dev_priv = dev->dev_private;
6088 struct drm_i915_gem_object *obj;
6089 struct drm_framebuffer *fb;
6090
6091 if (dev_priv->fbdev == NULL)
6092 return NULL;
6093
6094 obj = dev_priv->fbdev->ifb.obj;
6095 if (obj == NULL)
6096 return NULL;
6097
6098 fb = &dev_priv->fbdev->ifb.base;
6099 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6100 fb->bits_per_pixel))
6101 return NULL;
6102
6103 if (obj->base.size < mode->vdisplay * fb->pitch)
6104 return NULL;
6105
6106 return fb;
6107 }
6108
6109 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6110 struct drm_connector *connector,
6111 struct drm_display_mode *mode,
6112 struct intel_load_detect_pipe *old)
6113 {
6114 struct intel_crtc *intel_crtc;
6115 struct drm_crtc *possible_crtc;
6116 struct drm_encoder *encoder = &intel_encoder->base;
6117 struct drm_crtc *crtc = NULL;
6118 struct drm_device *dev = encoder->dev;
6119 struct drm_framebuffer *old_fb;
6120 int i = -1;
6121
6122 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6123 connector->base.id, drm_get_connector_name(connector),
6124 encoder->base.id, drm_get_encoder_name(encoder));
6125
6126 /*
6127 * Algorithm gets a little messy:
6128 *
6129 * - if the connector already has an assigned crtc, use it (but make
6130 * sure it's on first)
6131 *
6132 * - try to find the first unused crtc that can drive this connector,
6133 * and use that if we find one
6134 */
6135
6136 /* See if we already have a CRTC for this connector */
6137 if (encoder->crtc) {
6138 crtc = encoder->crtc;
6139
6140 intel_crtc = to_intel_crtc(crtc);
6141 old->dpms_mode = intel_crtc->dpms_mode;
6142 old->load_detect_temp = false;
6143
6144 /* Make sure the crtc and connector are running */
6145 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6146 struct drm_encoder_helper_funcs *encoder_funcs;
6147 struct drm_crtc_helper_funcs *crtc_funcs;
6148
6149 crtc_funcs = crtc->helper_private;
6150 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6151
6152 encoder_funcs = encoder->helper_private;
6153 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6154 }
6155
6156 return true;
6157 }
6158
6159 /* Find an unused one (if possible) */
6160 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6161 i++;
6162 if (!(encoder->possible_crtcs & (1 << i)))
6163 continue;
6164 if (!possible_crtc->enabled) {
6165 crtc = possible_crtc;
6166 break;
6167 }
6168 }
6169
6170 /*
6171 * If we didn't find an unused CRTC, don't use any.
6172 */
6173 if (!crtc) {
6174 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6175 return false;
6176 }
6177
6178 encoder->crtc = crtc;
6179 connector->encoder = encoder;
6180
6181 intel_crtc = to_intel_crtc(crtc);
6182 old->dpms_mode = intel_crtc->dpms_mode;
6183 old->load_detect_temp = true;
6184 old->release_fb = NULL;
6185
6186 if (!mode)
6187 mode = &load_detect_mode;
6188
6189 old_fb = crtc->fb;
6190
6191 /* We need a framebuffer large enough to accommodate all accesses
6192 * that the plane may generate whilst we perform load detection.
6193 * We can not rely on the fbcon either being present (we get called
6194 * during its initialisation to detect all boot displays, or it may
6195 * not even exist) or that it is large enough to satisfy the
6196 * requested mode.
6197 */
6198 crtc->fb = mode_fits_in_fbdev(dev, mode);
6199 if (crtc->fb == NULL) {
6200 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6201 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6202 old->release_fb = crtc->fb;
6203 } else
6204 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6205 if (IS_ERR(crtc->fb)) {
6206 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6207 crtc->fb = old_fb;
6208 return false;
6209 }
6210
6211 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6212 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6213 if (old->release_fb)
6214 old->release_fb->funcs->destroy(old->release_fb);
6215 crtc->fb = old_fb;
6216 return false;
6217 }
6218
6219 /* let the connector get through one full cycle before testing */
6220 intel_wait_for_vblank(dev, intel_crtc->pipe);
6221
6222 return true;
6223 }
6224
6225 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6226 struct drm_connector *connector,
6227 struct intel_load_detect_pipe *old)
6228 {
6229 struct drm_encoder *encoder = &intel_encoder->base;
6230 struct drm_device *dev = encoder->dev;
6231 struct drm_crtc *crtc = encoder->crtc;
6232 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6233 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6234
6235 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6236 connector->base.id, drm_get_connector_name(connector),
6237 encoder->base.id, drm_get_encoder_name(encoder));
6238
6239 if (old->load_detect_temp) {
6240 connector->encoder = NULL;
6241 drm_helper_disable_unused_functions(dev);
6242
6243 if (old->release_fb)
6244 old->release_fb->funcs->destroy(old->release_fb);
6245
6246 return;
6247 }
6248
6249 /* Switch crtc and encoder back off if necessary */
6250 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6251 encoder_funcs->dpms(encoder, old->dpms_mode);
6252 crtc_funcs->dpms(crtc, old->dpms_mode);
6253 }
6254 }
6255
6256 /* Returns the clock of the currently programmed mode of the given pipe. */
6257 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6258 {
6259 struct drm_i915_private *dev_priv = dev->dev_private;
6260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6261 int pipe = intel_crtc->pipe;
6262 u32 dpll = I915_READ(DPLL(pipe));
6263 u32 fp;
6264 intel_clock_t clock;
6265
6266 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6267 fp = I915_READ(FP0(pipe));
6268 else
6269 fp = I915_READ(FP1(pipe));
6270
6271 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6272 if (IS_PINEVIEW(dev)) {
6273 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6274 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6275 } else {
6276 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6277 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6278 }
6279
6280 if (!IS_GEN2(dev)) {
6281 if (IS_PINEVIEW(dev))
6282 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6283 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6284 else
6285 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6286 DPLL_FPA01_P1_POST_DIV_SHIFT);
6287
6288 switch (dpll & DPLL_MODE_MASK) {
6289 case DPLLB_MODE_DAC_SERIAL:
6290 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6291 5 : 10;
6292 break;
6293 case DPLLB_MODE_LVDS:
6294 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6295 7 : 14;
6296 break;
6297 default:
6298 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6299 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6300 return 0;
6301 }
6302
6303 /* XXX: Handle the 100Mhz refclk */
6304 intel_clock(dev, 96000, &clock);
6305 } else {
6306 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6307
6308 if (is_lvds) {
6309 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6310 DPLL_FPA01_P1_POST_DIV_SHIFT);
6311 clock.p2 = 14;
6312
6313 if ((dpll & PLL_REF_INPUT_MASK) ==
6314 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6315 /* XXX: might not be 66MHz */
6316 intel_clock(dev, 66000, &clock);
6317 } else
6318 intel_clock(dev, 48000, &clock);
6319 } else {
6320 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6321 clock.p1 = 2;
6322 else {
6323 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6324 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6325 }
6326 if (dpll & PLL_P2_DIVIDE_BY_4)
6327 clock.p2 = 4;
6328 else
6329 clock.p2 = 2;
6330
6331 intel_clock(dev, 48000, &clock);
6332 }
6333 }
6334
6335 /* XXX: It would be nice to validate the clocks, but we can't reuse
6336 * i830PllIsValid() because it relies on the xf86_config connector
6337 * configuration being accurate, which it isn't necessarily.
6338 */
6339
6340 return clock.dot;
6341 }
6342
6343 /** Returns the currently programmed mode of the given pipe. */
6344 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6345 struct drm_crtc *crtc)
6346 {
6347 struct drm_i915_private *dev_priv = dev->dev_private;
6348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6349 int pipe = intel_crtc->pipe;
6350 struct drm_display_mode *mode;
6351 int htot = I915_READ(HTOTAL(pipe));
6352 int hsync = I915_READ(HSYNC(pipe));
6353 int vtot = I915_READ(VTOTAL(pipe));
6354 int vsync = I915_READ(VSYNC(pipe));
6355
6356 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6357 if (!mode)
6358 return NULL;
6359
6360 mode->clock = intel_crtc_clock_get(dev, crtc);
6361 mode->hdisplay = (htot & 0xffff) + 1;
6362 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6363 mode->hsync_start = (hsync & 0xffff) + 1;
6364 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6365 mode->vdisplay = (vtot & 0xffff) + 1;
6366 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6367 mode->vsync_start = (vsync & 0xffff) + 1;
6368 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6369
6370 drm_mode_set_name(mode);
6371 drm_mode_set_crtcinfo(mode, 0);
6372
6373 return mode;
6374 }
6375
6376 #define GPU_IDLE_TIMEOUT 500 /* ms */
6377
6378 /* When this timer fires, we've been idle for awhile */
6379 static void intel_gpu_idle_timer(unsigned long arg)
6380 {
6381 struct drm_device *dev = (struct drm_device *)arg;
6382 drm_i915_private_t *dev_priv = dev->dev_private;
6383
6384 if (!list_empty(&dev_priv->mm.active_list)) {
6385 /* Still processing requests, so just re-arm the timer. */
6386 mod_timer(&dev_priv->idle_timer, jiffies +
6387 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6388 return;
6389 }
6390
6391 dev_priv->busy = false;
6392 queue_work(dev_priv->wq, &dev_priv->idle_work);
6393 }
6394
6395 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6396
6397 static void intel_crtc_idle_timer(unsigned long arg)
6398 {
6399 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6400 struct drm_crtc *crtc = &intel_crtc->base;
6401 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6402 struct intel_framebuffer *intel_fb;
6403
6404 intel_fb = to_intel_framebuffer(crtc->fb);
6405 if (intel_fb && intel_fb->obj->active) {
6406 /* The framebuffer is still being accessed by the GPU. */
6407 mod_timer(&intel_crtc->idle_timer, jiffies +
6408 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6409 return;
6410 }
6411
6412 intel_crtc->busy = false;
6413 queue_work(dev_priv->wq, &dev_priv->idle_work);
6414 }
6415
6416 static void intel_increase_pllclock(struct drm_crtc *crtc)
6417 {
6418 struct drm_device *dev = crtc->dev;
6419 drm_i915_private_t *dev_priv = dev->dev_private;
6420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6421 int pipe = intel_crtc->pipe;
6422 int dpll_reg = DPLL(pipe);
6423 int dpll;
6424
6425 if (HAS_PCH_SPLIT(dev))
6426 return;
6427
6428 if (!dev_priv->lvds_downclock_avail)
6429 return;
6430
6431 dpll = I915_READ(dpll_reg);
6432 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6433 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6434
6435 /* Unlock panel regs */
6436 I915_WRITE(PP_CONTROL,
6437 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6438
6439 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6440 I915_WRITE(dpll_reg, dpll);
6441 intel_wait_for_vblank(dev, pipe);
6442
6443 dpll = I915_READ(dpll_reg);
6444 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6445 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6446
6447 /* ...and lock them again */
6448 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6449 }
6450
6451 /* Schedule downclock */
6452 mod_timer(&intel_crtc->idle_timer, jiffies +
6453 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6454 }
6455
6456 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6457 {
6458 struct drm_device *dev = crtc->dev;
6459 drm_i915_private_t *dev_priv = dev->dev_private;
6460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6461 int pipe = intel_crtc->pipe;
6462 int dpll_reg = DPLL(pipe);
6463 int dpll = I915_READ(dpll_reg);
6464
6465 if (HAS_PCH_SPLIT(dev))
6466 return;
6467
6468 if (!dev_priv->lvds_downclock_avail)
6469 return;
6470
6471 /*
6472 * Since this is called by a timer, we should never get here in
6473 * the manual case.
6474 */
6475 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6476 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6477
6478 /* Unlock panel regs */
6479 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6480 PANEL_UNLOCK_REGS);
6481
6482 dpll |= DISPLAY_RATE_SELECT_FPA1;
6483 I915_WRITE(dpll_reg, dpll);
6484 intel_wait_for_vblank(dev, pipe);
6485 dpll = I915_READ(dpll_reg);
6486 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6487 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6488
6489 /* ...and lock them again */
6490 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6491 }
6492
6493 }
6494
6495 /**
6496 * intel_idle_update - adjust clocks for idleness
6497 * @work: work struct
6498 *
6499 * Either the GPU or display (or both) went idle. Check the busy status
6500 * here and adjust the CRTC and GPU clocks as necessary.
6501 */
6502 static void intel_idle_update(struct work_struct *work)
6503 {
6504 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6505 idle_work);
6506 struct drm_device *dev = dev_priv->dev;
6507 struct drm_crtc *crtc;
6508 struct intel_crtc *intel_crtc;
6509
6510 if (!i915_powersave)
6511 return;
6512
6513 mutex_lock(&dev->struct_mutex);
6514
6515 i915_update_gfx_val(dev_priv);
6516
6517 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6518 /* Skip inactive CRTCs */
6519 if (!crtc->fb)
6520 continue;
6521
6522 intel_crtc = to_intel_crtc(crtc);
6523 if (!intel_crtc->busy)
6524 intel_decrease_pllclock(crtc);
6525 }
6526
6527
6528 mutex_unlock(&dev->struct_mutex);
6529 }
6530
6531 /**
6532 * intel_mark_busy - mark the GPU and possibly the display busy
6533 * @dev: drm device
6534 * @obj: object we're operating on
6535 *
6536 * Callers can use this function to indicate that the GPU is busy processing
6537 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6538 * buffer), we'll also mark the display as busy, so we know to increase its
6539 * clock frequency.
6540 */
6541 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6542 {
6543 drm_i915_private_t *dev_priv = dev->dev_private;
6544 struct drm_crtc *crtc = NULL;
6545 struct intel_framebuffer *intel_fb;
6546 struct intel_crtc *intel_crtc;
6547
6548 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6549 return;
6550
6551 if (!dev_priv->busy)
6552 dev_priv->busy = true;
6553 else
6554 mod_timer(&dev_priv->idle_timer, jiffies +
6555 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6556
6557 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6558 if (!crtc->fb)
6559 continue;
6560
6561 intel_crtc = to_intel_crtc(crtc);
6562 intel_fb = to_intel_framebuffer(crtc->fb);
6563 if (intel_fb->obj == obj) {
6564 if (!intel_crtc->busy) {
6565 /* Non-busy -> busy, upclock */
6566 intel_increase_pllclock(crtc);
6567 intel_crtc->busy = true;
6568 } else {
6569 /* Busy -> busy, put off timer */
6570 mod_timer(&intel_crtc->idle_timer, jiffies +
6571 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6572 }
6573 }
6574 }
6575 }
6576
6577 static void intel_crtc_destroy(struct drm_crtc *crtc)
6578 {
6579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6580 struct drm_device *dev = crtc->dev;
6581 struct intel_unpin_work *work;
6582 unsigned long flags;
6583
6584 spin_lock_irqsave(&dev->event_lock, flags);
6585 work = intel_crtc->unpin_work;
6586 intel_crtc->unpin_work = NULL;
6587 spin_unlock_irqrestore(&dev->event_lock, flags);
6588
6589 if (work) {
6590 cancel_work_sync(&work->work);
6591 kfree(work);
6592 }
6593
6594 drm_crtc_cleanup(crtc);
6595
6596 kfree(intel_crtc);
6597 }
6598
6599 static void intel_unpin_work_fn(struct work_struct *__work)
6600 {
6601 struct intel_unpin_work *work =
6602 container_of(__work, struct intel_unpin_work, work);
6603
6604 mutex_lock(&work->dev->struct_mutex);
6605 i915_gem_object_unpin(work->old_fb_obj);
6606 drm_gem_object_unreference(&work->pending_flip_obj->base);
6607 drm_gem_object_unreference(&work->old_fb_obj->base);
6608
6609 intel_update_fbc(work->dev);
6610 mutex_unlock(&work->dev->struct_mutex);
6611 kfree(work);
6612 }
6613
6614 static void do_intel_finish_page_flip(struct drm_device *dev,
6615 struct drm_crtc *crtc)
6616 {
6617 drm_i915_private_t *dev_priv = dev->dev_private;
6618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6619 struct intel_unpin_work *work;
6620 struct drm_i915_gem_object *obj;
6621 struct drm_pending_vblank_event *e;
6622 struct timeval tnow, tvbl;
6623 unsigned long flags;
6624
6625 /* Ignore early vblank irqs */
6626 if (intel_crtc == NULL)
6627 return;
6628
6629 do_gettimeofday(&tnow);
6630
6631 spin_lock_irqsave(&dev->event_lock, flags);
6632 work = intel_crtc->unpin_work;
6633 if (work == NULL || !work->pending) {
6634 spin_unlock_irqrestore(&dev->event_lock, flags);
6635 return;
6636 }
6637
6638 intel_crtc->unpin_work = NULL;
6639
6640 if (work->event) {
6641 e = work->event;
6642 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6643
6644 /* Called before vblank count and timestamps have
6645 * been updated for the vblank interval of flip
6646 * completion? Need to increment vblank count and
6647 * add one videorefresh duration to returned timestamp
6648 * to account for this. We assume this happened if we
6649 * get called over 0.9 frame durations after the last
6650 * timestamped vblank.
6651 *
6652 * This calculation can not be used with vrefresh rates
6653 * below 5Hz (10Hz to be on the safe side) without
6654 * promoting to 64 integers.
6655 */
6656 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6657 9 * crtc->framedur_ns) {
6658 e->event.sequence++;
6659 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6660 crtc->framedur_ns);
6661 }
6662
6663 e->event.tv_sec = tvbl.tv_sec;
6664 e->event.tv_usec = tvbl.tv_usec;
6665
6666 list_add_tail(&e->base.link,
6667 &e->base.file_priv->event_list);
6668 wake_up_interruptible(&e->base.file_priv->event_wait);
6669 }
6670
6671 drm_vblank_put(dev, intel_crtc->pipe);
6672
6673 spin_unlock_irqrestore(&dev->event_lock, flags);
6674
6675 obj = work->old_fb_obj;
6676
6677 atomic_clear_mask(1 << intel_crtc->plane,
6678 &obj->pending_flip.counter);
6679 if (atomic_read(&obj->pending_flip) == 0)
6680 wake_up(&dev_priv->pending_flip_queue);
6681
6682 schedule_work(&work->work);
6683
6684 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6685 }
6686
6687 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6688 {
6689 drm_i915_private_t *dev_priv = dev->dev_private;
6690 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6691
6692 do_intel_finish_page_flip(dev, crtc);
6693 }
6694
6695 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6696 {
6697 drm_i915_private_t *dev_priv = dev->dev_private;
6698 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6699
6700 do_intel_finish_page_flip(dev, crtc);
6701 }
6702
6703 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6704 {
6705 drm_i915_private_t *dev_priv = dev->dev_private;
6706 struct intel_crtc *intel_crtc =
6707 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6708 unsigned long flags;
6709
6710 spin_lock_irqsave(&dev->event_lock, flags);
6711 if (intel_crtc->unpin_work) {
6712 if ((++intel_crtc->unpin_work->pending) > 1)
6713 DRM_ERROR("Prepared flip multiple times\n");
6714 } else {
6715 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6716 }
6717 spin_unlock_irqrestore(&dev->event_lock, flags);
6718 }
6719
6720 static int intel_gen2_queue_flip(struct drm_device *dev,
6721 struct drm_crtc *crtc,
6722 struct drm_framebuffer *fb,
6723 struct drm_i915_gem_object *obj)
6724 {
6725 struct drm_i915_private *dev_priv = dev->dev_private;
6726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6727 unsigned long offset;
6728 u32 flip_mask;
6729 int ret;
6730
6731 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6732 if (ret)
6733 goto out;
6734
6735 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6736 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6737
6738 ret = BEGIN_LP_RING(6);
6739 if (ret)
6740 goto out;
6741
6742 /* Can't queue multiple flips, so wait for the previous
6743 * one to finish before executing the next.
6744 */
6745 if (intel_crtc->plane)
6746 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6747 else
6748 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6749 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6750 OUT_RING(MI_NOOP);
6751 OUT_RING(MI_DISPLAY_FLIP |
6752 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6753 OUT_RING(fb->pitch);
6754 OUT_RING(obj->gtt_offset + offset);
6755 OUT_RING(MI_NOOP);
6756 ADVANCE_LP_RING();
6757 out:
6758 return ret;
6759 }
6760
6761 static int intel_gen3_queue_flip(struct drm_device *dev,
6762 struct drm_crtc *crtc,
6763 struct drm_framebuffer *fb,
6764 struct drm_i915_gem_object *obj)
6765 {
6766 struct drm_i915_private *dev_priv = dev->dev_private;
6767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6768 unsigned long offset;
6769 u32 flip_mask;
6770 int ret;
6771
6772 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6773 if (ret)
6774 goto out;
6775
6776 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6777 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6778
6779 ret = BEGIN_LP_RING(6);
6780 if (ret)
6781 goto out;
6782
6783 if (intel_crtc->plane)
6784 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6785 else
6786 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6787 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6788 OUT_RING(MI_NOOP);
6789 OUT_RING(MI_DISPLAY_FLIP_I915 |
6790 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6791 OUT_RING(fb->pitch);
6792 OUT_RING(obj->gtt_offset + offset);
6793 OUT_RING(MI_NOOP);
6794
6795 ADVANCE_LP_RING();
6796 out:
6797 return ret;
6798 }
6799
6800 static int intel_gen4_queue_flip(struct drm_device *dev,
6801 struct drm_crtc *crtc,
6802 struct drm_framebuffer *fb,
6803 struct drm_i915_gem_object *obj)
6804 {
6805 struct drm_i915_private *dev_priv = dev->dev_private;
6806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6807 uint32_t pf, pipesrc;
6808 int ret;
6809
6810 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6811 if (ret)
6812 goto out;
6813
6814 ret = BEGIN_LP_RING(4);
6815 if (ret)
6816 goto out;
6817
6818 /* i965+ uses the linear or tiled offsets from the
6819 * Display Registers (which do not change across a page-flip)
6820 * so we need only reprogram the base address.
6821 */
6822 OUT_RING(MI_DISPLAY_FLIP |
6823 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6824 OUT_RING(fb->pitch);
6825 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6826
6827 /* XXX Enabling the panel-fitter across page-flip is so far
6828 * untested on non-native modes, so ignore it for now.
6829 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6830 */
6831 pf = 0;
6832 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6833 OUT_RING(pf | pipesrc);
6834 ADVANCE_LP_RING();
6835 out:
6836 return ret;
6837 }
6838
6839 static int intel_gen6_queue_flip(struct drm_device *dev,
6840 struct drm_crtc *crtc,
6841 struct drm_framebuffer *fb,
6842 struct drm_i915_gem_object *obj)
6843 {
6844 struct drm_i915_private *dev_priv = dev->dev_private;
6845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6846 uint32_t pf, pipesrc;
6847 int ret;
6848
6849 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6850 if (ret)
6851 goto out;
6852
6853 ret = BEGIN_LP_RING(4);
6854 if (ret)
6855 goto out;
6856
6857 OUT_RING(MI_DISPLAY_FLIP |
6858 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6859 OUT_RING(fb->pitch | obj->tiling_mode);
6860 OUT_RING(obj->gtt_offset);
6861
6862 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6863 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6864 OUT_RING(pf | pipesrc);
6865 ADVANCE_LP_RING();
6866 out:
6867 return ret;
6868 }
6869
6870 /*
6871 * On gen7 we currently use the blit ring because (in early silicon at least)
6872 * the render ring doesn't give us interrpts for page flip completion, which
6873 * means clients will hang after the first flip is queued. Fortunately the
6874 * blit ring generates interrupts properly, so use it instead.
6875 */
6876 static int intel_gen7_queue_flip(struct drm_device *dev,
6877 struct drm_crtc *crtc,
6878 struct drm_framebuffer *fb,
6879 struct drm_i915_gem_object *obj)
6880 {
6881 struct drm_i915_private *dev_priv = dev->dev_private;
6882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6883 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6884 int ret;
6885
6886 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6887 if (ret)
6888 goto out;
6889
6890 ret = intel_ring_begin(ring, 4);
6891 if (ret)
6892 goto out;
6893
6894 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6895 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6896 intel_ring_emit(ring, (obj->gtt_offset));
6897 intel_ring_emit(ring, (MI_NOOP));
6898 intel_ring_advance(ring);
6899 out:
6900 return ret;
6901 }
6902
6903 static int intel_default_queue_flip(struct drm_device *dev,
6904 struct drm_crtc *crtc,
6905 struct drm_framebuffer *fb,
6906 struct drm_i915_gem_object *obj)
6907 {
6908 return -ENODEV;
6909 }
6910
6911 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6912 struct drm_framebuffer *fb,
6913 struct drm_pending_vblank_event *event)
6914 {
6915 struct drm_device *dev = crtc->dev;
6916 struct drm_i915_private *dev_priv = dev->dev_private;
6917 struct intel_framebuffer *intel_fb;
6918 struct drm_i915_gem_object *obj;
6919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6920 struct intel_unpin_work *work;
6921 unsigned long flags;
6922 int ret;
6923
6924 work = kzalloc(sizeof *work, GFP_KERNEL);
6925 if (work == NULL)
6926 return -ENOMEM;
6927
6928 work->event = event;
6929 work->dev = crtc->dev;
6930 intel_fb = to_intel_framebuffer(crtc->fb);
6931 work->old_fb_obj = intel_fb->obj;
6932 INIT_WORK(&work->work, intel_unpin_work_fn);
6933
6934 /* We borrow the event spin lock for protecting unpin_work */
6935 spin_lock_irqsave(&dev->event_lock, flags);
6936 if (intel_crtc->unpin_work) {
6937 spin_unlock_irqrestore(&dev->event_lock, flags);
6938 kfree(work);
6939
6940 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6941 return -EBUSY;
6942 }
6943 intel_crtc->unpin_work = work;
6944 spin_unlock_irqrestore(&dev->event_lock, flags);
6945
6946 intel_fb = to_intel_framebuffer(fb);
6947 obj = intel_fb->obj;
6948
6949 mutex_lock(&dev->struct_mutex);
6950
6951 /* Reference the objects for the scheduled work. */
6952 drm_gem_object_reference(&work->old_fb_obj->base);
6953 drm_gem_object_reference(&obj->base);
6954
6955 crtc->fb = fb;
6956
6957 ret = drm_vblank_get(dev, intel_crtc->pipe);
6958 if (ret)
6959 goto cleanup_objs;
6960
6961 work->pending_flip_obj = obj;
6962
6963 work->enable_stall_check = true;
6964
6965 /* Block clients from rendering to the new back buffer until
6966 * the flip occurs and the object is no longer visible.
6967 */
6968 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6969
6970 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6971 if (ret)
6972 goto cleanup_pending;
6973
6974 intel_disable_fbc(dev);
6975 mutex_unlock(&dev->struct_mutex);
6976
6977 trace_i915_flip_request(intel_crtc->plane, obj);
6978
6979 return 0;
6980
6981 cleanup_pending:
6982 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6983 cleanup_objs:
6984 drm_gem_object_unreference(&work->old_fb_obj->base);
6985 drm_gem_object_unreference(&obj->base);
6986 mutex_unlock(&dev->struct_mutex);
6987
6988 spin_lock_irqsave(&dev->event_lock, flags);
6989 intel_crtc->unpin_work = NULL;
6990 spin_unlock_irqrestore(&dev->event_lock, flags);
6991
6992 kfree(work);
6993
6994 return ret;
6995 }
6996
6997 static void intel_sanitize_modesetting(struct drm_device *dev,
6998 int pipe, int plane)
6999 {
7000 struct drm_i915_private *dev_priv = dev->dev_private;
7001 u32 reg, val;
7002
7003 if (HAS_PCH_SPLIT(dev))
7004 return;
7005
7006 /* Who knows what state these registers were left in by the BIOS or
7007 * grub?
7008 *
7009 * If we leave the registers in a conflicting state (e.g. with the
7010 * display plane reading from the other pipe than the one we intend
7011 * to use) then when we attempt to teardown the active mode, we will
7012 * not disable the pipes and planes in the correct order -- leaving
7013 * a plane reading from a disabled pipe and possibly leading to
7014 * undefined behaviour.
7015 */
7016
7017 reg = DSPCNTR(plane);
7018 val = I915_READ(reg);
7019
7020 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7021 return;
7022 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7023 return;
7024
7025 /* This display plane is active and attached to the other CPU pipe. */
7026 pipe = !pipe;
7027
7028 /* Disable the plane and wait for it to stop reading from the pipe. */
7029 intel_disable_plane(dev_priv, plane, pipe);
7030 intel_disable_pipe(dev_priv, pipe);
7031 }
7032
7033 static void intel_crtc_reset(struct drm_crtc *crtc)
7034 {
7035 struct drm_device *dev = crtc->dev;
7036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7037
7038 /* Reset flags back to the 'unknown' status so that they
7039 * will be correctly set on the initial modeset.
7040 */
7041 intel_crtc->dpms_mode = -1;
7042
7043 /* We need to fix up any BIOS configuration that conflicts with
7044 * our expectations.
7045 */
7046 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7047 }
7048
7049 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7050 .dpms = intel_crtc_dpms,
7051 .mode_fixup = intel_crtc_mode_fixup,
7052 .mode_set = intel_crtc_mode_set,
7053 .mode_set_base = intel_pipe_set_base,
7054 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7055 .load_lut = intel_crtc_load_lut,
7056 .disable = intel_crtc_disable,
7057 };
7058
7059 static const struct drm_crtc_funcs intel_crtc_funcs = {
7060 .reset = intel_crtc_reset,
7061 .cursor_set = intel_crtc_cursor_set,
7062 .cursor_move = intel_crtc_cursor_move,
7063 .gamma_set = intel_crtc_gamma_set,
7064 .set_config = drm_crtc_helper_set_config,
7065 .destroy = intel_crtc_destroy,
7066 .page_flip = intel_crtc_page_flip,
7067 };
7068
7069 static void intel_crtc_init(struct drm_device *dev, int pipe)
7070 {
7071 drm_i915_private_t *dev_priv = dev->dev_private;
7072 struct intel_crtc *intel_crtc;
7073 int i;
7074
7075 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7076 if (intel_crtc == NULL)
7077 return;
7078
7079 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7080
7081 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7082 for (i = 0; i < 256; i++) {
7083 intel_crtc->lut_r[i] = i;
7084 intel_crtc->lut_g[i] = i;
7085 intel_crtc->lut_b[i] = i;
7086 }
7087
7088 /* Swap pipes & planes for FBC on pre-965 */
7089 intel_crtc->pipe = pipe;
7090 intel_crtc->plane = pipe;
7091 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7092 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7093 intel_crtc->plane = !pipe;
7094 }
7095
7096 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7097 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7098 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7099 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7100
7101 intel_crtc_reset(&intel_crtc->base);
7102 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7103 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7104
7105 if (HAS_PCH_SPLIT(dev)) {
7106 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7107 intel_helper_funcs.commit = ironlake_crtc_commit;
7108 } else {
7109 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7110 intel_helper_funcs.commit = i9xx_crtc_commit;
7111 }
7112
7113 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7114
7115 intel_crtc->busy = false;
7116
7117 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7118 (unsigned long)intel_crtc);
7119 }
7120
7121 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7122 struct drm_file *file)
7123 {
7124 drm_i915_private_t *dev_priv = dev->dev_private;
7125 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7126 struct drm_mode_object *drmmode_obj;
7127 struct intel_crtc *crtc;
7128
7129 if (!dev_priv) {
7130 DRM_ERROR("called with no initialization\n");
7131 return -EINVAL;
7132 }
7133
7134 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7135 DRM_MODE_OBJECT_CRTC);
7136
7137 if (!drmmode_obj) {
7138 DRM_ERROR("no such CRTC id\n");
7139 return -EINVAL;
7140 }
7141
7142 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7143 pipe_from_crtc_id->pipe = crtc->pipe;
7144
7145 return 0;
7146 }
7147
7148 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7149 {
7150 struct intel_encoder *encoder;
7151 int index_mask = 0;
7152 int entry = 0;
7153
7154 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7155 if (type_mask & encoder->clone_mask)
7156 index_mask |= (1 << entry);
7157 entry++;
7158 }
7159
7160 return index_mask;
7161 }
7162
7163 static bool has_edp_a(struct drm_device *dev)
7164 {
7165 struct drm_i915_private *dev_priv = dev->dev_private;
7166
7167 if (!IS_MOBILE(dev))
7168 return false;
7169
7170 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7171 return false;
7172
7173 if (IS_GEN5(dev) &&
7174 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7175 return false;
7176
7177 return true;
7178 }
7179
7180 static void intel_setup_outputs(struct drm_device *dev)
7181 {
7182 struct drm_i915_private *dev_priv = dev->dev_private;
7183 struct intel_encoder *encoder;
7184 bool dpd_is_edp = false;
7185 bool has_lvds = false;
7186
7187 if (IS_MOBILE(dev) && !IS_I830(dev))
7188 has_lvds = intel_lvds_init(dev);
7189 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7190 /* disable the panel fitter on everything but LVDS */
7191 I915_WRITE(PFIT_CONTROL, 0);
7192 }
7193
7194 if (HAS_PCH_SPLIT(dev)) {
7195 dpd_is_edp = intel_dpd_is_edp(dev);
7196
7197 if (has_edp_a(dev))
7198 intel_dp_init(dev, DP_A);
7199
7200 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7201 intel_dp_init(dev, PCH_DP_D);
7202 }
7203
7204 intel_crt_init(dev);
7205
7206 if (HAS_PCH_SPLIT(dev)) {
7207 int found;
7208
7209 if (I915_READ(HDMIB) & PORT_DETECTED) {
7210 /* PCH SDVOB multiplex with HDMIB */
7211 found = intel_sdvo_init(dev, PCH_SDVOB);
7212 if (!found)
7213 intel_hdmi_init(dev, HDMIB);
7214 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7215 intel_dp_init(dev, PCH_DP_B);
7216 }
7217
7218 if (I915_READ(HDMIC) & PORT_DETECTED)
7219 intel_hdmi_init(dev, HDMIC);
7220
7221 if (I915_READ(HDMID) & PORT_DETECTED)
7222 intel_hdmi_init(dev, HDMID);
7223
7224 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7225 intel_dp_init(dev, PCH_DP_C);
7226
7227 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7228 intel_dp_init(dev, PCH_DP_D);
7229
7230 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7231 bool found = false;
7232
7233 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7234 DRM_DEBUG_KMS("probing SDVOB\n");
7235 found = intel_sdvo_init(dev, SDVOB);
7236 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7237 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7238 intel_hdmi_init(dev, SDVOB);
7239 }
7240
7241 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7242 DRM_DEBUG_KMS("probing DP_B\n");
7243 intel_dp_init(dev, DP_B);
7244 }
7245 }
7246
7247 /* Before G4X SDVOC doesn't have its own detect register */
7248
7249 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7250 DRM_DEBUG_KMS("probing SDVOC\n");
7251 found = intel_sdvo_init(dev, SDVOC);
7252 }
7253
7254 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7255
7256 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7257 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7258 intel_hdmi_init(dev, SDVOC);
7259 }
7260 if (SUPPORTS_INTEGRATED_DP(dev)) {
7261 DRM_DEBUG_KMS("probing DP_C\n");
7262 intel_dp_init(dev, DP_C);
7263 }
7264 }
7265
7266 if (SUPPORTS_INTEGRATED_DP(dev) &&
7267 (I915_READ(DP_D) & DP_DETECTED)) {
7268 DRM_DEBUG_KMS("probing DP_D\n");
7269 intel_dp_init(dev, DP_D);
7270 }
7271 } else if (IS_GEN2(dev))
7272 intel_dvo_init(dev);
7273
7274 if (SUPPORTS_TV(dev))
7275 intel_tv_init(dev);
7276
7277 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7278 encoder->base.possible_crtcs = encoder->crtc_mask;
7279 encoder->base.possible_clones =
7280 intel_encoder_clones(dev, encoder->clone_mask);
7281 }
7282
7283 /* disable all the possible outputs/crtcs before entering KMS mode */
7284 drm_helper_disable_unused_functions(dev);
7285 }
7286
7287 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7288 {
7289 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7290
7291 drm_framebuffer_cleanup(fb);
7292 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7293
7294 kfree(intel_fb);
7295 }
7296
7297 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7298 struct drm_file *file,
7299 unsigned int *handle)
7300 {
7301 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7302 struct drm_i915_gem_object *obj = intel_fb->obj;
7303
7304 return drm_gem_handle_create(file, &obj->base, handle);
7305 }
7306
7307 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7308 .destroy = intel_user_framebuffer_destroy,
7309 .create_handle = intel_user_framebuffer_create_handle,
7310 };
7311
7312 int intel_framebuffer_init(struct drm_device *dev,
7313 struct intel_framebuffer *intel_fb,
7314 struct drm_mode_fb_cmd *mode_cmd,
7315 struct drm_i915_gem_object *obj)
7316 {
7317 int ret;
7318
7319 if (obj->tiling_mode == I915_TILING_Y)
7320 return -EINVAL;
7321
7322 if (mode_cmd->pitch & 63)
7323 return -EINVAL;
7324
7325 switch (mode_cmd->bpp) {
7326 case 8:
7327 case 16:
7328 /* Only pre-ILK can handle 5:5:5 */
7329 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7330 return -EINVAL;
7331 break;
7332
7333 case 24:
7334 case 32:
7335 break;
7336 default:
7337 return -EINVAL;
7338 }
7339
7340 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7341 if (ret) {
7342 DRM_ERROR("framebuffer init failed %d\n", ret);
7343 return ret;
7344 }
7345
7346 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7347 intel_fb->obj = obj;
7348 return 0;
7349 }
7350
7351 static struct drm_framebuffer *
7352 intel_user_framebuffer_create(struct drm_device *dev,
7353 struct drm_file *filp,
7354 struct drm_mode_fb_cmd *mode_cmd)
7355 {
7356 struct drm_i915_gem_object *obj;
7357
7358 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7359 if (&obj->base == NULL)
7360 return ERR_PTR(-ENOENT);
7361
7362 return intel_framebuffer_create(dev, mode_cmd, obj);
7363 }
7364
7365 static const struct drm_mode_config_funcs intel_mode_funcs = {
7366 .fb_create = intel_user_framebuffer_create,
7367 .output_poll_changed = intel_fb_output_poll_changed,
7368 };
7369
7370 static struct drm_i915_gem_object *
7371 intel_alloc_context_page(struct drm_device *dev)
7372 {
7373 struct drm_i915_gem_object *ctx;
7374 int ret;
7375
7376 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7377
7378 ctx = i915_gem_alloc_object(dev, 4096);
7379 if (!ctx) {
7380 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7381 return NULL;
7382 }
7383
7384 ret = i915_gem_object_pin(ctx, 4096, true);
7385 if (ret) {
7386 DRM_ERROR("failed to pin power context: %d\n", ret);
7387 goto err_unref;
7388 }
7389
7390 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7391 if (ret) {
7392 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7393 goto err_unpin;
7394 }
7395
7396 return ctx;
7397
7398 err_unpin:
7399 i915_gem_object_unpin(ctx);
7400 err_unref:
7401 drm_gem_object_unreference(&ctx->base);
7402 mutex_unlock(&dev->struct_mutex);
7403 return NULL;
7404 }
7405
7406 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7407 {
7408 struct drm_i915_private *dev_priv = dev->dev_private;
7409 u16 rgvswctl;
7410
7411 rgvswctl = I915_READ16(MEMSWCTL);
7412 if (rgvswctl & MEMCTL_CMD_STS) {
7413 DRM_DEBUG("gpu busy, RCS change rejected\n");
7414 return false; /* still busy with another command */
7415 }
7416
7417 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7418 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7419 I915_WRITE16(MEMSWCTL, rgvswctl);
7420 POSTING_READ16(MEMSWCTL);
7421
7422 rgvswctl |= MEMCTL_CMD_STS;
7423 I915_WRITE16(MEMSWCTL, rgvswctl);
7424
7425 return true;
7426 }
7427
7428 void ironlake_enable_drps(struct drm_device *dev)
7429 {
7430 struct drm_i915_private *dev_priv = dev->dev_private;
7431 u32 rgvmodectl = I915_READ(MEMMODECTL);
7432 u8 fmax, fmin, fstart, vstart;
7433
7434 /* Enable temp reporting */
7435 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7436 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7437
7438 /* 100ms RC evaluation intervals */
7439 I915_WRITE(RCUPEI, 100000);
7440 I915_WRITE(RCDNEI, 100000);
7441
7442 /* Set max/min thresholds to 90ms and 80ms respectively */
7443 I915_WRITE(RCBMAXAVG, 90000);
7444 I915_WRITE(RCBMINAVG, 80000);
7445
7446 I915_WRITE(MEMIHYST, 1);
7447
7448 /* Set up min, max, and cur for interrupt handling */
7449 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7450 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7451 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7452 MEMMODE_FSTART_SHIFT;
7453
7454 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7455 PXVFREQ_PX_SHIFT;
7456
7457 dev_priv->fmax = fmax; /* IPS callback will increase this */
7458 dev_priv->fstart = fstart;
7459
7460 dev_priv->max_delay = fstart;
7461 dev_priv->min_delay = fmin;
7462 dev_priv->cur_delay = fstart;
7463
7464 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7465 fmax, fmin, fstart);
7466
7467 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7468
7469 /*
7470 * Interrupts will be enabled in ironlake_irq_postinstall
7471 */
7472
7473 I915_WRITE(VIDSTART, vstart);
7474 POSTING_READ(VIDSTART);
7475
7476 rgvmodectl |= MEMMODE_SWMODE_EN;
7477 I915_WRITE(MEMMODECTL, rgvmodectl);
7478
7479 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7480 DRM_ERROR("stuck trying to change perf mode\n");
7481 msleep(1);
7482
7483 ironlake_set_drps(dev, fstart);
7484
7485 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7486 I915_READ(0x112e0);
7487 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7488 dev_priv->last_count2 = I915_READ(0x112f4);
7489 getrawmonotonic(&dev_priv->last_time2);
7490 }
7491
7492 void ironlake_disable_drps(struct drm_device *dev)
7493 {
7494 struct drm_i915_private *dev_priv = dev->dev_private;
7495 u16 rgvswctl = I915_READ16(MEMSWCTL);
7496
7497 /* Ack interrupts, disable EFC interrupt */
7498 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7499 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7500 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7501 I915_WRITE(DEIIR, DE_PCU_EVENT);
7502 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7503
7504 /* Go back to the starting frequency */
7505 ironlake_set_drps(dev, dev_priv->fstart);
7506 msleep(1);
7507 rgvswctl |= MEMCTL_CMD_STS;
7508 I915_WRITE(MEMSWCTL, rgvswctl);
7509 msleep(1);
7510
7511 }
7512
7513 void gen6_set_rps(struct drm_device *dev, u8 val)
7514 {
7515 struct drm_i915_private *dev_priv = dev->dev_private;
7516 u32 swreq;
7517
7518 swreq = (val & 0x3ff) << 25;
7519 I915_WRITE(GEN6_RPNSWREQ, swreq);
7520 }
7521
7522 void gen6_disable_rps(struct drm_device *dev)
7523 {
7524 struct drm_i915_private *dev_priv = dev->dev_private;
7525
7526 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7527 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7528 I915_WRITE(GEN6_PMIER, 0);
7529
7530 spin_lock_irq(&dev_priv->rps_lock);
7531 dev_priv->pm_iir = 0;
7532 spin_unlock_irq(&dev_priv->rps_lock);
7533
7534 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7535 }
7536
7537 static unsigned long intel_pxfreq(u32 vidfreq)
7538 {
7539 unsigned long freq;
7540 int div = (vidfreq & 0x3f0000) >> 16;
7541 int post = (vidfreq & 0x3000) >> 12;
7542 int pre = (vidfreq & 0x7);
7543
7544 if (!pre)
7545 return 0;
7546
7547 freq = ((div * 133333) / ((1<<post) * pre));
7548
7549 return freq;
7550 }
7551
7552 void intel_init_emon(struct drm_device *dev)
7553 {
7554 struct drm_i915_private *dev_priv = dev->dev_private;
7555 u32 lcfuse;
7556 u8 pxw[16];
7557 int i;
7558
7559 /* Disable to program */
7560 I915_WRITE(ECR, 0);
7561 POSTING_READ(ECR);
7562
7563 /* Program energy weights for various events */
7564 I915_WRITE(SDEW, 0x15040d00);
7565 I915_WRITE(CSIEW0, 0x007f0000);
7566 I915_WRITE(CSIEW1, 0x1e220004);
7567 I915_WRITE(CSIEW2, 0x04000004);
7568
7569 for (i = 0; i < 5; i++)
7570 I915_WRITE(PEW + (i * 4), 0);
7571 for (i = 0; i < 3; i++)
7572 I915_WRITE(DEW + (i * 4), 0);
7573
7574 /* Program P-state weights to account for frequency power adjustment */
7575 for (i = 0; i < 16; i++) {
7576 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7577 unsigned long freq = intel_pxfreq(pxvidfreq);
7578 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7579 PXVFREQ_PX_SHIFT;
7580 unsigned long val;
7581
7582 val = vid * vid;
7583 val *= (freq / 1000);
7584 val *= 255;
7585 val /= (127*127*900);
7586 if (val > 0xff)
7587 DRM_ERROR("bad pxval: %ld\n", val);
7588 pxw[i] = val;
7589 }
7590 /* Render standby states get 0 weight */
7591 pxw[14] = 0;
7592 pxw[15] = 0;
7593
7594 for (i = 0; i < 4; i++) {
7595 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7596 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7597 I915_WRITE(PXW + (i * 4), val);
7598 }
7599
7600 /* Adjust magic regs to magic values (more experimental results) */
7601 I915_WRITE(OGW0, 0);
7602 I915_WRITE(OGW1, 0);
7603 I915_WRITE(EG0, 0x00007f00);
7604 I915_WRITE(EG1, 0x0000000e);
7605 I915_WRITE(EG2, 0x000e0000);
7606 I915_WRITE(EG3, 0x68000300);
7607 I915_WRITE(EG4, 0x42000000);
7608 I915_WRITE(EG5, 0x00140031);
7609 I915_WRITE(EG6, 0);
7610 I915_WRITE(EG7, 0);
7611
7612 for (i = 0; i < 8; i++)
7613 I915_WRITE(PXWL + (i * 4), 0);
7614
7615 /* Enable PMON + select events */
7616 I915_WRITE(ECR, 0x80000019);
7617
7618 lcfuse = I915_READ(LCFUSE02);
7619
7620 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7621 }
7622
7623 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7624 {
7625 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7626 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7627 u32 pcu_mbox, rc6_mask = 0;
7628 int cur_freq, min_freq, max_freq;
7629 int i;
7630
7631 /* Here begins a magic sequence of register writes to enable
7632 * auto-downclocking.
7633 *
7634 * Perhaps there might be some value in exposing these to
7635 * userspace...
7636 */
7637 I915_WRITE(GEN6_RC_STATE, 0);
7638 mutex_lock(&dev_priv->dev->struct_mutex);
7639 gen6_gt_force_wake_get(dev_priv);
7640
7641 /* disable the counters and set deterministic thresholds */
7642 I915_WRITE(GEN6_RC_CONTROL, 0);
7643
7644 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7645 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7646 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7647 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7648 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7649
7650 for (i = 0; i < I915_NUM_RINGS; i++)
7651 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7652
7653 I915_WRITE(GEN6_RC_SLEEP, 0);
7654 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7655 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7656 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7657 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7658
7659 if (i915_enable_rc6)
7660 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7661 GEN6_RC_CTL_RC6_ENABLE;
7662
7663 I915_WRITE(GEN6_RC_CONTROL,
7664 rc6_mask |
7665 GEN6_RC_CTL_EI_MODE(1) |
7666 GEN6_RC_CTL_HW_ENABLE);
7667
7668 I915_WRITE(GEN6_RPNSWREQ,
7669 GEN6_FREQUENCY(10) |
7670 GEN6_OFFSET(0) |
7671 GEN6_AGGRESSIVE_TURBO);
7672 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7673 GEN6_FREQUENCY(12));
7674
7675 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7676 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7677 18 << 24 |
7678 6 << 16);
7679 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7680 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7681 I915_WRITE(GEN6_RP_UP_EI, 100000);
7682 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7683 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7684 I915_WRITE(GEN6_RP_CONTROL,
7685 GEN6_RP_MEDIA_TURBO |
7686 GEN6_RP_USE_NORMAL_FREQ |
7687 GEN6_RP_MEDIA_IS_GFX |
7688 GEN6_RP_ENABLE |
7689 GEN6_RP_UP_BUSY_AVG |
7690 GEN6_RP_DOWN_IDLE_CONT);
7691
7692 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7693 500))
7694 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7695
7696 I915_WRITE(GEN6_PCODE_DATA, 0);
7697 I915_WRITE(GEN6_PCODE_MAILBOX,
7698 GEN6_PCODE_READY |
7699 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7700 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7701 500))
7702 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7703
7704 min_freq = (rp_state_cap & 0xff0000) >> 16;
7705 max_freq = rp_state_cap & 0xff;
7706 cur_freq = (gt_perf_status & 0xff00) >> 8;
7707
7708 /* Check for overclock support */
7709 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7710 500))
7711 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7712 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7713 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7714 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7715 500))
7716 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7717 if (pcu_mbox & (1<<31)) { /* OC supported */
7718 max_freq = pcu_mbox & 0xff;
7719 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7720 }
7721
7722 /* In units of 100MHz */
7723 dev_priv->max_delay = max_freq;
7724 dev_priv->min_delay = min_freq;
7725 dev_priv->cur_delay = cur_freq;
7726
7727 /* requires MSI enabled */
7728 I915_WRITE(GEN6_PMIER,
7729 GEN6_PM_MBOX_EVENT |
7730 GEN6_PM_THERMAL_EVENT |
7731 GEN6_PM_RP_DOWN_TIMEOUT |
7732 GEN6_PM_RP_UP_THRESHOLD |
7733 GEN6_PM_RP_DOWN_THRESHOLD |
7734 GEN6_PM_RP_UP_EI_EXPIRED |
7735 GEN6_PM_RP_DOWN_EI_EXPIRED);
7736 spin_lock_irq(&dev_priv->rps_lock);
7737 WARN_ON(dev_priv->pm_iir != 0);
7738 I915_WRITE(GEN6_PMIMR, 0);
7739 spin_unlock_irq(&dev_priv->rps_lock);
7740 /* enable all PM interrupts */
7741 I915_WRITE(GEN6_PMINTRMSK, 0);
7742
7743 gen6_gt_force_wake_put(dev_priv);
7744 mutex_unlock(&dev_priv->dev->struct_mutex);
7745 }
7746
7747 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7748 {
7749 int min_freq = 15;
7750 int gpu_freq, ia_freq, max_ia_freq;
7751 int scaling_factor = 180;
7752
7753 max_ia_freq = cpufreq_quick_get_max(0);
7754 /*
7755 * Default to measured freq if none found, PCU will ensure we don't go
7756 * over
7757 */
7758 if (!max_ia_freq)
7759 max_ia_freq = tsc_khz;
7760
7761 /* Convert from kHz to MHz */
7762 max_ia_freq /= 1000;
7763
7764 mutex_lock(&dev_priv->dev->struct_mutex);
7765
7766 /*
7767 * For each potential GPU frequency, load a ring frequency we'd like
7768 * to use for memory access. We do this by specifying the IA frequency
7769 * the PCU should use as a reference to determine the ring frequency.
7770 */
7771 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7772 gpu_freq--) {
7773 int diff = dev_priv->max_delay - gpu_freq;
7774
7775 /*
7776 * For GPU frequencies less than 750MHz, just use the lowest
7777 * ring freq.
7778 */
7779 if (gpu_freq < min_freq)
7780 ia_freq = 800;
7781 else
7782 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7783 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7784
7785 I915_WRITE(GEN6_PCODE_DATA,
7786 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7787 gpu_freq);
7788 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7789 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7790 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7791 GEN6_PCODE_READY) == 0, 10)) {
7792 DRM_ERROR("pcode write of freq table timed out\n");
7793 continue;
7794 }
7795 }
7796
7797 mutex_unlock(&dev_priv->dev->struct_mutex);
7798 }
7799
7800 static void ironlake_init_clock_gating(struct drm_device *dev)
7801 {
7802 struct drm_i915_private *dev_priv = dev->dev_private;
7803 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7804
7805 /* Required for FBC */
7806 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7807 DPFCRUNIT_CLOCK_GATE_DISABLE |
7808 DPFDUNIT_CLOCK_GATE_DISABLE;
7809 /* Required for CxSR */
7810 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7811
7812 I915_WRITE(PCH_3DCGDIS0,
7813 MARIUNIT_CLOCK_GATE_DISABLE |
7814 SVSMUNIT_CLOCK_GATE_DISABLE);
7815 I915_WRITE(PCH_3DCGDIS1,
7816 VFMUNIT_CLOCK_GATE_DISABLE);
7817
7818 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7819
7820 /*
7821 * According to the spec the following bits should be set in
7822 * order to enable memory self-refresh
7823 * The bit 22/21 of 0x42004
7824 * The bit 5 of 0x42020
7825 * The bit 15 of 0x45000
7826 */
7827 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7828 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7829 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7830 I915_WRITE(ILK_DSPCLK_GATE,
7831 (I915_READ(ILK_DSPCLK_GATE) |
7832 ILK_DPARB_CLK_GATE));
7833 I915_WRITE(DISP_ARB_CTL,
7834 (I915_READ(DISP_ARB_CTL) |
7835 DISP_FBC_WM_DIS));
7836 I915_WRITE(WM3_LP_ILK, 0);
7837 I915_WRITE(WM2_LP_ILK, 0);
7838 I915_WRITE(WM1_LP_ILK, 0);
7839
7840 /*
7841 * Based on the document from hardware guys the following bits
7842 * should be set unconditionally in order to enable FBC.
7843 * The bit 22 of 0x42000
7844 * The bit 22 of 0x42004
7845 * The bit 7,8,9 of 0x42020.
7846 */
7847 if (IS_IRONLAKE_M(dev)) {
7848 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7849 I915_READ(ILK_DISPLAY_CHICKEN1) |
7850 ILK_FBCQ_DIS);
7851 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7852 I915_READ(ILK_DISPLAY_CHICKEN2) |
7853 ILK_DPARB_GATE);
7854 I915_WRITE(ILK_DSPCLK_GATE,
7855 I915_READ(ILK_DSPCLK_GATE) |
7856 ILK_DPFC_DIS1 |
7857 ILK_DPFC_DIS2 |
7858 ILK_CLK_FBC);
7859 }
7860
7861 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7862 I915_READ(ILK_DISPLAY_CHICKEN2) |
7863 ILK_ELPIN_409_SELECT);
7864 I915_WRITE(_3D_CHICKEN2,
7865 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7866 _3D_CHICKEN2_WM_READ_PIPELINED);
7867 }
7868
7869 static void gen6_init_clock_gating(struct drm_device *dev)
7870 {
7871 struct drm_i915_private *dev_priv = dev->dev_private;
7872 int pipe;
7873 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7874
7875 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7876
7877 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7878 I915_READ(ILK_DISPLAY_CHICKEN2) |
7879 ILK_ELPIN_409_SELECT);
7880
7881 I915_WRITE(WM3_LP_ILK, 0);
7882 I915_WRITE(WM2_LP_ILK, 0);
7883 I915_WRITE(WM1_LP_ILK, 0);
7884
7885 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7886 * gating disable must be set. Failure to set it results in
7887 * flickering pixels due to Z write ordering failures after
7888 * some amount of runtime in the Mesa "fire" demo, and Unigine
7889 * Sanctuary and Tropics, and apparently anything else with
7890 * alpha test or pixel discard.
7891 */
7892 I915_WRITE(GEN6_UCGCTL2, GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);
7893
7894 /*
7895 * According to the spec the following bits should be
7896 * set in order to enable memory self-refresh and fbc:
7897 * The bit21 and bit22 of 0x42000
7898 * The bit21 and bit22 of 0x42004
7899 * The bit5 and bit7 of 0x42020
7900 * The bit14 of 0x70180
7901 * The bit14 of 0x71180
7902 */
7903 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7904 I915_READ(ILK_DISPLAY_CHICKEN1) |
7905 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7906 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7907 I915_READ(ILK_DISPLAY_CHICKEN2) |
7908 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7909 I915_WRITE(ILK_DSPCLK_GATE,
7910 I915_READ(ILK_DSPCLK_GATE) |
7911 ILK_DPARB_CLK_GATE |
7912 ILK_DPFD_CLK_GATE);
7913
7914 for_each_pipe(pipe) {
7915 I915_WRITE(DSPCNTR(pipe),
7916 I915_READ(DSPCNTR(pipe)) |
7917 DISPPLANE_TRICKLE_FEED_DISABLE);
7918 intel_flush_display_plane(dev_priv, pipe);
7919 }
7920 }
7921
7922 static void ivybridge_init_clock_gating(struct drm_device *dev)
7923 {
7924 struct drm_i915_private *dev_priv = dev->dev_private;
7925 int pipe;
7926 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7927
7928 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7929
7930 I915_WRITE(WM3_LP_ILK, 0);
7931 I915_WRITE(WM2_LP_ILK, 0);
7932 I915_WRITE(WM1_LP_ILK, 0);
7933
7934 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7935
7936 for_each_pipe(pipe) {
7937 I915_WRITE(DSPCNTR(pipe),
7938 I915_READ(DSPCNTR(pipe)) |
7939 DISPPLANE_TRICKLE_FEED_DISABLE);
7940 intel_flush_display_plane(dev_priv, pipe);
7941 }
7942 }
7943
7944 static void g4x_init_clock_gating(struct drm_device *dev)
7945 {
7946 struct drm_i915_private *dev_priv = dev->dev_private;
7947 uint32_t dspclk_gate;
7948
7949 I915_WRITE(RENCLK_GATE_D1, 0);
7950 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7951 GS_UNIT_CLOCK_GATE_DISABLE |
7952 CL_UNIT_CLOCK_GATE_DISABLE);
7953 I915_WRITE(RAMCLK_GATE_D, 0);
7954 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7955 OVRUNIT_CLOCK_GATE_DISABLE |
7956 OVCUNIT_CLOCK_GATE_DISABLE;
7957 if (IS_GM45(dev))
7958 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7959 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7960 }
7961
7962 static void crestline_init_clock_gating(struct drm_device *dev)
7963 {
7964 struct drm_i915_private *dev_priv = dev->dev_private;
7965
7966 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7967 I915_WRITE(RENCLK_GATE_D2, 0);
7968 I915_WRITE(DSPCLK_GATE_D, 0);
7969 I915_WRITE(RAMCLK_GATE_D, 0);
7970 I915_WRITE16(DEUC, 0);
7971 }
7972
7973 static void broadwater_init_clock_gating(struct drm_device *dev)
7974 {
7975 struct drm_i915_private *dev_priv = dev->dev_private;
7976
7977 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7978 I965_RCC_CLOCK_GATE_DISABLE |
7979 I965_RCPB_CLOCK_GATE_DISABLE |
7980 I965_ISC_CLOCK_GATE_DISABLE |
7981 I965_FBC_CLOCK_GATE_DISABLE);
7982 I915_WRITE(RENCLK_GATE_D2, 0);
7983 }
7984
7985 static void gen3_init_clock_gating(struct drm_device *dev)
7986 {
7987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 u32 dstate = I915_READ(D_STATE);
7989
7990 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7991 DSTATE_DOT_CLOCK_GATING;
7992 I915_WRITE(D_STATE, dstate);
7993 }
7994
7995 static void i85x_init_clock_gating(struct drm_device *dev)
7996 {
7997 struct drm_i915_private *dev_priv = dev->dev_private;
7998
7999 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8000 }
8001
8002 static void i830_init_clock_gating(struct drm_device *dev)
8003 {
8004 struct drm_i915_private *dev_priv = dev->dev_private;
8005
8006 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8007 }
8008
8009 static void ibx_init_clock_gating(struct drm_device *dev)
8010 {
8011 struct drm_i915_private *dev_priv = dev->dev_private;
8012
8013 /*
8014 * On Ibex Peak and Cougar Point, we need to disable clock
8015 * gating for the panel power sequencer or it will fail to
8016 * start up when no ports are active.
8017 */
8018 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8019 }
8020
8021 static void cpt_init_clock_gating(struct drm_device *dev)
8022 {
8023 struct drm_i915_private *dev_priv = dev->dev_private;
8024 int pipe;
8025
8026 /*
8027 * On Ibex Peak and Cougar Point, we need to disable clock
8028 * gating for the panel power sequencer or it will fail to
8029 * start up when no ports are active.
8030 */
8031 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8032 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8033 DPLS_EDP_PPS_FIX_DIS);
8034 /* Without this, mode sets may fail silently on FDI */
8035 for_each_pipe(pipe)
8036 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8037 }
8038
8039 static void ironlake_teardown_rc6(struct drm_device *dev)
8040 {
8041 struct drm_i915_private *dev_priv = dev->dev_private;
8042
8043 if (dev_priv->renderctx) {
8044 i915_gem_object_unpin(dev_priv->renderctx);
8045 drm_gem_object_unreference(&dev_priv->renderctx->base);
8046 dev_priv->renderctx = NULL;
8047 }
8048
8049 if (dev_priv->pwrctx) {
8050 i915_gem_object_unpin(dev_priv->pwrctx);
8051 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8052 dev_priv->pwrctx = NULL;
8053 }
8054 }
8055
8056 static void ironlake_disable_rc6(struct drm_device *dev)
8057 {
8058 struct drm_i915_private *dev_priv = dev->dev_private;
8059
8060 if (I915_READ(PWRCTXA)) {
8061 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8062 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8063 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8064 50);
8065
8066 I915_WRITE(PWRCTXA, 0);
8067 POSTING_READ(PWRCTXA);
8068
8069 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8070 POSTING_READ(RSTDBYCTL);
8071 }
8072
8073 ironlake_teardown_rc6(dev);
8074 }
8075
8076 static int ironlake_setup_rc6(struct drm_device *dev)
8077 {
8078 struct drm_i915_private *dev_priv = dev->dev_private;
8079
8080 if (dev_priv->renderctx == NULL)
8081 dev_priv->renderctx = intel_alloc_context_page(dev);
8082 if (!dev_priv->renderctx)
8083 return -ENOMEM;
8084
8085 if (dev_priv->pwrctx == NULL)
8086 dev_priv->pwrctx = intel_alloc_context_page(dev);
8087 if (!dev_priv->pwrctx) {
8088 ironlake_teardown_rc6(dev);
8089 return -ENOMEM;
8090 }
8091
8092 return 0;
8093 }
8094
8095 void ironlake_enable_rc6(struct drm_device *dev)
8096 {
8097 struct drm_i915_private *dev_priv = dev->dev_private;
8098 int ret;
8099
8100 /* rc6 disabled by default due to repeated reports of hanging during
8101 * boot and resume.
8102 */
8103 if (!i915_enable_rc6)
8104 return;
8105
8106 mutex_lock(&dev->struct_mutex);
8107 ret = ironlake_setup_rc6(dev);
8108 if (ret) {
8109 mutex_unlock(&dev->struct_mutex);
8110 return;
8111 }
8112
8113 /*
8114 * GPU can automatically power down the render unit if given a page
8115 * to save state.
8116 */
8117 ret = BEGIN_LP_RING(6);
8118 if (ret) {
8119 ironlake_teardown_rc6(dev);
8120 mutex_unlock(&dev->struct_mutex);
8121 return;
8122 }
8123
8124 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8125 OUT_RING(MI_SET_CONTEXT);
8126 OUT_RING(dev_priv->renderctx->gtt_offset |
8127 MI_MM_SPACE_GTT |
8128 MI_SAVE_EXT_STATE_EN |
8129 MI_RESTORE_EXT_STATE_EN |
8130 MI_RESTORE_INHIBIT);
8131 OUT_RING(MI_SUSPEND_FLUSH);
8132 OUT_RING(MI_NOOP);
8133 OUT_RING(MI_FLUSH);
8134 ADVANCE_LP_RING();
8135
8136 /*
8137 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8138 * does an implicit flush, combined with MI_FLUSH above, it should be
8139 * safe to assume that renderctx is valid
8140 */
8141 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8142 if (ret) {
8143 DRM_ERROR("failed to enable ironlake power power savings\n");
8144 ironlake_teardown_rc6(dev);
8145 mutex_unlock(&dev->struct_mutex);
8146 return;
8147 }
8148
8149 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8150 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8151 mutex_unlock(&dev->struct_mutex);
8152 }
8153
8154 void intel_init_clock_gating(struct drm_device *dev)
8155 {
8156 struct drm_i915_private *dev_priv = dev->dev_private;
8157
8158 dev_priv->display.init_clock_gating(dev);
8159
8160 if (dev_priv->display.init_pch_clock_gating)
8161 dev_priv->display.init_pch_clock_gating(dev);
8162 }
8163
8164 /* Set up chip specific display functions */
8165 static void intel_init_display(struct drm_device *dev)
8166 {
8167 struct drm_i915_private *dev_priv = dev->dev_private;
8168
8169 /* We always want a DPMS function */
8170 if (HAS_PCH_SPLIT(dev)) {
8171 dev_priv->display.dpms = ironlake_crtc_dpms;
8172 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8173 dev_priv->display.update_plane = ironlake_update_plane;
8174 } else {
8175 dev_priv->display.dpms = i9xx_crtc_dpms;
8176 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8177 dev_priv->display.update_plane = i9xx_update_plane;
8178 }
8179
8180 if (I915_HAS_FBC(dev)) {
8181 if (HAS_PCH_SPLIT(dev)) {
8182 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8183 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8184 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8185 } else if (IS_GM45(dev)) {
8186 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8187 dev_priv->display.enable_fbc = g4x_enable_fbc;
8188 dev_priv->display.disable_fbc = g4x_disable_fbc;
8189 } else if (IS_CRESTLINE(dev)) {
8190 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8191 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8192 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8193 }
8194 /* 855GM needs testing */
8195 }
8196
8197 /* Returns the core display clock speed */
8198 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
8199 dev_priv->display.get_display_clock_speed =
8200 i945_get_display_clock_speed;
8201 else if (IS_I915G(dev))
8202 dev_priv->display.get_display_clock_speed =
8203 i915_get_display_clock_speed;
8204 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8205 dev_priv->display.get_display_clock_speed =
8206 i9xx_misc_get_display_clock_speed;
8207 else if (IS_I915GM(dev))
8208 dev_priv->display.get_display_clock_speed =
8209 i915gm_get_display_clock_speed;
8210 else if (IS_I865G(dev))
8211 dev_priv->display.get_display_clock_speed =
8212 i865_get_display_clock_speed;
8213 else if (IS_I85X(dev))
8214 dev_priv->display.get_display_clock_speed =
8215 i855_get_display_clock_speed;
8216 else /* 852, 830 */
8217 dev_priv->display.get_display_clock_speed =
8218 i830_get_display_clock_speed;
8219
8220 /* For FIFO watermark updates */
8221 if (HAS_PCH_SPLIT(dev)) {
8222 if (HAS_PCH_IBX(dev))
8223 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8224 else if (HAS_PCH_CPT(dev))
8225 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8226
8227 if (IS_GEN5(dev)) {
8228 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8229 dev_priv->display.update_wm = ironlake_update_wm;
8230 else {
8231 DRM_DEBUG_KMS("Failed to get proper latency. "
8232 "Disable CxSR\n");
8233 dev_priv->display.update_wm = NULL;
8234 }
8235 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8236 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8237 } else if (IS_GEN6(dev)) {
8238 if (SNB_READ_WM0_LATENCY()) {
8239 dev_priv->display.update_wm = sandybridge_update_wm;
8240 } else {
8241 DRM_DEBUG_KMS("Failed to read display plane latency. "
8242 "Disable CxSR\n");
8243 dev_priv->display.update_wm = NULL;
8244 }
8245 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8246 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8247 } else if (IS_IVYBRIDGE(dev)) {
8248 /* FIXME: detect B0+ stepping and use auto training */
8249 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8250 if (SNB_READ_WM0_LATENCY()) {
8251 dev_priv->display.update_wm = sandybridge_update_wm;
8252 } else {
8253 DRM_DEBUG_KMS("Failed to read display plane latency. "
8254 "Disable CxSR\n");
8255 dev_priv->display.update_wm = NULL;
8256 }
8257 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8258
8259 } else
8260 dev_priv->display.update_wm = NULL;
8261 } else if (IS_PINEVIEW(dev)) {
8262 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8263 dev_priv->is_ddr3,
8264 dev_priv->fsb_freq,
8265 dev_priv->mem_freq)) {
8266 DRM_INFO("failed to find known CxSR latency "
8267 "(found ddr%s fsb freq %d, mem freq %d), "
8268 "disabling CxSR\n",
8269 (dev_priv->is_ddr3 == 1) ? "3": "2",
8270 dev_priv->fsb_freq, dev_priv->mem_freq);
8271 /* Disable CxSR and never update its watermark again */
8272 pineview_disable_cxsr(dev);
8273 dev_priv->display.update_wm = NULL;
8274 } else
8275 dev_priv->display.update_wm = pineview_update_wm;
8276 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8277 } else if (IS_G4X(dev)) {
8278 dev_priv->display.update_wm = g4x_update_wm;
8279 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8280 } else if (IS_GEN4(dev)) {
8281 dev_priv->display.update_wm = i965_update_wm;
8282 if (IS_CRESTLINE(dev))
8283 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8284 else if (IS_BROADWATER(dev))
8285 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8286 } else if (IS_GEN3(dev)) {
8287 dev_priv->display.update_wm = i9xx_update_wm;
8288 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8289 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8290 } else if (IS_I865G(dev)) {
8291 dev_priv->display.update_wm = i830_update_wm;
8292 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8293 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8294 } else if (IS_I85X(dev)) {
8295 dev_priv->display.update_wm = i9xx_update_wm;
8296 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8297 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8298 } else {
8299 dev_priv->display.update_wm = i830_update_wm;
8300 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8301 if (IS_845G(dev))
8302 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8303 else
8304 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8305 }
8306
8307 /* Default just returns -ENODEV to indicate unsupported */
8308 dev_priv->display.queue_flip = intel_default_queue_flip;
8309
8310 switch (INTEL_INFO(dev)->gen) {
8311 case 2:
8312 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8313 break;
8314
8315 case 3:
8316 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8317 break;
8318
8319 case 4:
8320 case 5:
8321 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8322 break;
8323
8324 case 6:
8325 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8326 break;
8327 case 7:
8328 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8329 break;
8330 }
8331 }
8332
8333 /*
8334 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8335 * resume, or other times. This quirk makes sure that's the case for
8336 * affected systems.
8337 */
8338 static void quirk_pipea_force (struct drm_device *dev)
8339 {
8340 struct drm_i915_private *dev_priv = dev->dev_private;
8341
8342 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8343 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8344 }
8345
8346 /*
8347 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8348 */
8349 static void quirk_ssc_force_disable(struct drm_device *dev)
8350 {
8351 struct drm_i915_private *dev_priv = dev->dev_private;
8352 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8353 }
8354
8355 struct intel_quirk {
8356 int device;
8357 int subsystem_vendor;
8358 int subsystem_device;
8359 void (*hook)(struct drm_device *dev);
8360 };
8361
8362 struct intel_quirk intel_quirks[] = {
8363 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8364 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8365 /* HP Mini needs pipe A force quirk (LP: #322104) */
8366 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8367
8368 /* Thinkpad R31 needs pipe A force quirk */
8369 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8370 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8371 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8372
8373 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8374 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8375 /* ThinkPad X40 needs pipe A force quirk */
8376
8377 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8378 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8379
8380 /* 855 & before need to leave pipe A & dpll A up */
8381 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8382 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8383
8384 /* Lenovo U160 cannot use SSC on LVDS */
8385 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8386
8387 /* Sony Vaio Y cannot use SSC on LVDS */
8388 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8389 };
8390
8391 static void intel_init_quirks(struct drm_device *dev)
8392 {
8393 struct pci_dev *d = dev->pdev;
8394 int i;
8395
8396 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8397 struct intel_quirk *q = &intel_quirks[i];
8398
8399 if (d->device == q->device &&
8400 (d->subsystem_vendor == q->subsystem_vendor ||
8401 q->subsystem_vendor == PCI_ANY_ID) &&
8402 (d->subsystem_device == q->subsystem_device ||
8403 q->subsystem_device == PCI_ANY_ID))
8404 q->hook(dev);
8405 }
8406 }
8407
8408 /* Disable the VGA plane that we never use */
8409 static void i915_disable_vga(struct drm_device *dev)
8410 {
8411 struct drm_i915_private *dev_priv = dev->dev_private;
8412 u8 sr1;
8413 u32 vga_reg;
8414
8415 if (HAS_PCH_SPLIT(dev))
8416 vga_reg = CPU_VGACNTRL;
8417 else
8418 vga_reg = VGACNTRL;
8419
8420 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8421 outb(1, VGA_SR_INDEX);
8422 sr1 = inb(VGA_SR_DATA);
8423 outb(sr1 | 1<<5, VGA_SR_DATA);
8424 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8425 udelay(300);
8426
8427 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8428 POSTING_READ(vga_reg);
8429 }
8430
8431 void intel_modeset_init(struct drm_device *dev)
8432 {
8433 struct drm_i915_private *dev_priv = dev->dev_private;
8434 int i;
8435
8436 drm_mode_config_init(dev);
8437
8438 dev->mode_config.min_width = 0;
8439 dev->mode_config.min_height = 0;
8440
8441 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8442
8443 intel_init_quirks(dev);
8444
8445 intel_init_display(dev);
8446
8447 if (IS_GEN2(dev)) {
8448 dev->mode_config.max_width = 2048;
8449 dev->mode_config.max_height = 2048;
8450 } else if (IS_GEN3(dev)) {
8451 dev->mode_config.max_width = 4096;
8452 dev->mode_config.max_height = 4096;
8453 } else {
8454 dev->mode_config.max_width = 8192;
8455 dev->mode_config.max_height = 8192;
8456 }
8457 dev->mode_config.fb_base = dev->agp->base;
8458
8459 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8460 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8461
8462 for (i = 0; i < dev_priv->num_pipe; i++) {
8463 intel_crtc_init(dev, i);
8464 }
8465
8466 /* Just disable it once at startup */
8467 i915_disable_vga(dev);
8468 intel_setup_outputs(dev);
8469
8470 intel_init_clock_gating(dev);
8471
8472 if (IS_IRONLAKE_M(dev)) {
8473 ironlake_enable_drps(dev);
8474 intel_init_emon(dev);
8475 }
8476
8477 if (IS_GEN6(dev) || IS_GEN7(dev)) {
8478 gen6_enable_rps(dev_priv);
8479 gen6_update_ring_freq(dev_priv);
8480 }
8481
8482 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8483 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8484 (unsigned long)dev);
8485 }
8486
8487 void intel_modeset_gem_init(struct drm_device *dev)
8488 {
8489 if (IS_IRONLAKE_M(dev))
8490 ironlake_enable_rc6(dev);
8491
8492 intel_setup_overlay(dev);
8493 }
8494
8495 void intel_modeset_cleanup(struct drm_device *dev)
8496 {
8497 struct drm_i915_private *dev_priv = dev->dev_private;
8498 struct drm_crtc *crtc;
8499 struct intel_crtc *intel_crtc;
8500
8501 drm_kms_helper_poll_fini(dev);
8502 mutex_lock(&dev->struct_mutex);
8503
8504 intel_unregister_dsm_handler();
8505
8506
8507 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8508 /* Skip inactive CRTCs */
8509 if (!crtc->fb)
8510 continue;
8511
8512 intel_crtc = to_intel_crtc(crtc);
8513 intel_increase_pllclock(crtc);
8514 }
8515
8516 intel_disable_fbc(dev);
8517
8518 if (IS_IRONLAKE_M(dev))
8519 ironlake_disable_drps(dev);
8520 if (IS_GEN6(dev) || IS_GEN7(dev))
8521 gen6_disable_rps(dev);
8522
8523 if (IS_IRONLAKE_M(dev))
8524 ironlake_disable_rc6(dev);
8525
8526 mutex_unlock(&dev->struct_mutex);
8527
8528 /* Disable the irq before mode object teardown, for the irq might
8529 * enqueue unpin/hotplug work. */
8530 drm_irq_uninstall(dev);
8531 cancel_work_sync(&dev_priv->hotplug_work);
8532
8533 /* flush any delayed tasks or pending work */
8534 flush_scheduled_work();
8535
8536 /* Shut off idle work before the crtcs get freed. */
8537 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8538 intel_crtc = to_intel_crtc(crtc);
8539 del_timer_sync(&intel_crtc->idle_timer);
8540 }
8541 del_timer_sync(&dev_priv->idle_timer);
8542 cancel_work_sync(&dev_priv->idle_work);
8543
8544 drm_mode_config_cleanup(dev);
8545 }
8546
8547 /*
8548 * Return which encoder is currently attached for connector.
8549 */
8550 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8551 {
8552 return &intel_attached_encoder(connector)->base;
8553 }
8554
8555 void intel_connector_attach_encoder(struct intel_connector *connector,
8556 struct intel_encoder *encoder)
8557 {
8558 connector->encoder = encoder;
8559 drm_mode_connector_attach_encoder(&connector->base,
8560 &encoder->base);
8561 }
8562
8563 /*
8564 * set vga decode state - true == enable VGA decode
8565 */
8566 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8567 {
8568 struct drm_i915_private *dev_priv = dev->dev_private;
8569 u16 gmch_ctrl;
8570
8571 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8572 if (state)
8573 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8574 else
8575 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8576 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8577 return 0;
8578 }
8579
8580 #ifdef CONFIG_DEBUG_FS
8581 #include <linux/seq_file.h>
8582
8583 struct intel_display_error_state {
8584 struct intel_cursor_error_state {
8585 u32 control;
8586 u32 position;
8587 u32 base;
8588 u32 size;
8589 } cursor[2];
8590
8591 struct intel_pipe_error_state {
8592 u32 conf;
8593 u32 source;
8594
8595 u32 htotal;
8596 u32 hblank;
8597 u32 hsync;
8598 u32 vtotal;
8599 u32 vblank;
8600 u32 vsync;
8601 } pipe[2];
8602
8603 struct intel_plane_error_state {
8604 u32 control;
8605 u32 stride;
8606 u32 size;
8607 u32 pos;
8608 u32 addr;
8609 u32 surface;
8610 u32 tile_offset;
8611 } plane[2];
8612 };
8613
8614 struct intel_display_error_state *
8615 intel_display_capture_error_state(struct drm_device *dev)
8616 {
8617 drm_i915_private_t *dev_priv = dev->dev_private;
8618 struct intel_display_error_state *error;
8619 int i;
8620
8621 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8622 if (error == NULL)
8623 return NULL;
8624
8625 for (i = 0; i < 2; i++) {
8626 error->cursor[i].control = I915_READ(CURCNTR(i));
8627 error->cursor[i].position = I915_READ(CURPOS(i));
8628 error->cursor[i].base = I915_READ(CURBASE(i));
8629
8630 error->plane[i].control = I915_READ(DSPCNTR(i));
8631 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8632 error->plane[i].size = I915_READ(DSPSIZE(i));
8633 error->plane[i].pos= I915_READ(DSPPOS(i));
8634 error->plane[i].addr = I915_READ(DSPADDR(i));
8635 if (INTEL_INFO(dev)->gen >= 4) {
8636 error->plane[i].surface = I915_READ(DSPSURF(i));
8637 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8638 }
8639
8640 error->pipe[i].conf = I915_READ(PIPECONF(i));
8641 error->pipe[i].source = I915_READ(PIPESRC(i));
8642 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8643 error->pipe[i].hblank = I915_READ(HBLANK(i));
8644 error->pipe[i].hsync = I915_READ(HSYNC(i));
8645 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8646 error->pipe[i].vblank = I915_READ(VBLANK(i));
8647 error->pipe[i].vsync = I915_READ(VSYNC(i));
8648 }
8649
8650 return error;
8651 }
8652
8653 void
8654 intel_display_print_error_state(struct seq_file *m,
8655 struct drm_device *dev,
8656 struct intel_display_error_state *error)
8657 {
8658 int i;
8659
8660 for (i = 0; i < 2; i++) {
8661 seq_printf(m, "Pipe [%d]:\n", i);
8662 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8663 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8664 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8665 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8666 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8667 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8668 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8669 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8670
8671 seq_printf(m, "Plane [%d]:\n", i);
8672 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8673 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8674 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8675 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8676 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8677 if (INTEL_INFO(dev)->gen >= 4) {
8678 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8679 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8680 }
8681
8682 seq_printf(m, "Cursor [%d]:\n", i);
8683 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8684 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8685 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8686 }
8687 }
8688 #endif
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree