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lis3: add support for HP ProBook 432x/442x/452x/522x
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / r6040.c
blob0298d8c1dcb6fa002cb2f58bb50a61fd79d748a6
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/interrupt.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/mii.h>
40 #include <linux/ethtool.h>
41 #include <linux/crc32.h>
42 #include <linux/spinlock.h>
43 #include <linux/bitops.h>
44 #include <linux/io.h>
45 #include <linux/irq.h>
46 #include <linux/uaccess.h>
47
48 #include <asm/processor.h>
49
50 #define DRV_NAME "r6040"
51 #define DRV_VERSION "0.25"
52 #define DRV_RELDATE "20Aug2009"
53
54 /* PHY CHIP Address */
55 #define PHY1_ADDR 1 /* For MAC1 */
56 #define PHY2_ADDR 3 /* For MAC2 */
57 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
58 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
59
60 /* Time in jiffies before concluding the transmitter is hung. */
61 #define TX_TIMEOUT (6000 * HZ / 1000)
62
63 /* RDC MAC I/O Size */
64 #define R6040_IO_SIZE 256
65
66 /* MAX RDC MAC */
67 #define MAX_MAC 2
68
69 /* MAC registers */
70 #define MCR0 0x00 /* Control register 0 */
71 #define MCR1 0x04 /* Control register 1 */
72 #define MAC_RST 0x0001 /* Reset the MAC */
73 #define MBCR 0x08 /* Bus control */
74 #define MT_ICR 0x0C /* TX interrupt control */
75 #define MR_ICR 0x10 /* RX interrupt control */
76 #define MTPR 0x14 /* TX poll command register */
77 #define MR_BSR 0x18 /* RX buffer size */
78 #define MR_DCR 0x1A /* RX descriptor control */
79 #define MLSR 0x1C /* Last status */
80 #define MMDIO 0x20 /* MDIO control register */
81 #define MDIO_WRITE 0x4000 /* MDIO write */
82 #define MDIO_READ 0x2000 /* MDIO read */
83 #define MMRD 0x24 /* MDIO read data register */
84 #define MMWD 0x28 /* MDIO write data register */
85 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
86 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
87 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
88 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
89 #define MISR 0x3C /* Status register */
90 #define MIER 0x40 /* INT enable register */
91 #define MSK_INT 0x0000 /* Mask off interrupts */
92 #define RX_FINISH 0x0001 /* RX finished */
93 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
94 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
95 #define RX_EARLY 0x0008 /* RX early */
96 #define TX_FINISH 0x0010 /* TX finished */
97 #define TX_EARLY 0x0080 /* TX early */
98 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
99 #define LINK_CHANGED 0x0200 /* PHY link changed */
100 #define ME_CISR 0x44 /* Event counter INT status */
101 #define ME_CIER 0x48 /* Event counter INT enable */
102 #define MR_CNT 0x50 /* Successfully received packet counter */
103 #define ME_CNT0 0x52 /* Event counter 0 */
104 #define ME_CNT1 0x54 /* Event counter 1 */
105 #define ME_CNT2 0x56 /* Event counter 2 */
106 #define ME_CNT3 0x58 /* Event counter 3 */
107 #define MT_CNT 0x5A /* Successfully transmit packet counter */
108 #define ME_CNT4 0x5C /* Event counter 4 */
109 #define MP_CNT 0x5E /* Pause frame counter register */
110 #define MAR0 0x60 /* Hash table 0 */
111 #define MAR1 0x62 /* Hash table 1 */
112 #define MAR2 0x64 /* Hash table 2 */
113 #define MAR3 0x66 /* Hash table 3 */
114 #define MID_0L 0x68 /* Multicast address MID0 Low */
115 #define MID_0M 0x6A /* Multicast address MID0 Medium */
116 #define MID_0H 0x6C /* Multicast address MID0 High */
117 #define MID_1L 0x70 /* MID1 Low */
118 #define MID_1M 0x72 /* MID1 Medium */
119 #define MID_1H 0x74 /* MID1 High */
120 #define MID_2L 0x78 /* MID2 Low */
121 #define MID_2M 0x7A /* MID2 Medium */
122 #define MID_2H 0x7C /* MID2 High */
123 #define MID_3L 0x80 /* MID3 Low */
124 #define MID_3M 0x82 /* MID3 Medium */
125 #define MID_3H 0x84 /* MID3 High */
126 #define PHY_CC 0x88 /* PHY status change configuration register */
127 #define PHY_ST 0x8A /* PHY status register */
128 #define MAC_SM 0xAC /* MAC status machine */
129 #define MAC_ID 0xBE /* Identifier register */
130
131 #define TX_DCNT 0x80 /* TX descriptor count */
132 #define RX_DCNT 0x80 /* RX descriptor count */
133 #define MAX_BUF_SIZE 0x600
134 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
135 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
136 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
137 #define MCAST_MAX 3 /* Max number multicast addresses to filter */
138
139 /* Descriptor status */
140 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
141 #define DSC_RX_OK 0x4000 /* RX was successful */
142 #define DSC_RX_ERR 0x0800 /* RX PHY error */
143 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
144 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
145 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
146 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
147 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
148 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
149 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
150 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
151 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
152 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
153
154 /* PHY settings */
155 #define ICPLUS_PHY_ID 0x0243
156
157 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
158 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
159 "Florian Fainelli <florian@openwrt.org>");
160 MODULE_LICENSE("GPL");
161 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
162 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
163
164 /* RX and TX interrupts that we handle */
165 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
166 #define TX_INTS (TX_FINISH)
167 #define INT_MASK (RX_INTS | TX_INTS)
168
169 struct r6040_descriptor {
170 u16 status, len; /* 0-3 */
171 __le32 buf; /* 4-7 */
172 __le32 ndesc; /* 8-B */
173 u32 rev1; /* C-F */
174 char *vbufp; /* 10-13 */
175 struct r6040_descriptor *vndescp; /* 14-17 */
176 struct sk_buff *skb_ptr; /* 18-1B */
177 u32 rev2; /* 1C-1F */
178 } __attribute__((aligned(32)));
179
180 struct r6040_private {
181 spinlock_t lock; /* driver lock */
182 struct timer_list timer;
183 struct pci_dev *pdev;
184 struct r6040_descriptor *rx_insert_ptr;
185 struct r6040_descriptor *rx_remove_ptr;
186 struct r6040_descriptor *tx_insert_ptr;
187 struct r6040_descriptor *tx_remove_ptr;
188 struct r6040_descriptor *rx_ring;
189 struct r6040_descriptor *tx_ring;
190 dma_addr_t rx_ring_dma;
191 dma_addr_t tx_ring_dma;
192 u16 tx_free_desc, phy_addr, phy_mode;
193 u16 mcr0, mcr1;
194 u16 switch_sig;
195 struct net_device *dev;
196 struct mii_if_info mii_if;
197 struct napi_struct napi;
198 void __iomem *base;
199 };
200
201 static char version[] __devinitdata = KERN_INFO DRV_NAME
202 ": RDC R6040 NAPI net driver,"
203 "version "DRV_VERSION " (" DRV_RELDATE ")";
204
205 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
206
207 /* Read a word data from PHY Chip */
208 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
209 {
210 int limit = 2048;
211 u16 cmd;
212
213 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
214 /* Wait for the read bit to be cleared */
215 while (limit--) {
216 cmd = ioread16(ioaddr + MMDIO);
217 if (!(cmd & MDIO_READ))
218 break;
219 }
220
221 return ioread16(ioaddr + MMRD);
222 }
223
224 /* Write a word data from PHY Chip */
225 static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
226 {
227 int limit = 2048;
228 u16 cmd;
229
230 iowrite16(val, ioaddr + MMWD);
231 /* Write the command to the MDIO bus */
232 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
233 /* Wait for the write bit to be cleared */
234 while (limit--) {
235 cmd = ioread16(ioaddr + MMDIO);
236 if (!(cmd & MDIO_WRITE))
237 break;
238 }
239 }
240
241 static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg)
242 {
243 struct r6040_private *lp = netdev_priv(dev);
244 void __iomem *ioaddr = lp->base;
245
246 return (r6040_phy_read(ioaddr, lp->phy_addr, reg));
247 }
248
249 static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val)
250 {
251 struct r6040_private *lp = netdev_priv(dev);
252 void __iomem *ioaddr = lp->base;
253
254 r6040_phy_write(ioaddr, lp->phy_addr, reg, val);
255 }
256
257 static void r6040_free_txbufs(struct net_device *dev)
258 {
259 struct r6040_private *lp = netdev_priv(dev);
260 int i;
261
262 for (i = 0; i < TX_DCNT; i++) {
263 if (lp->tx_insert_ptr->skb_ptr) {
264 pci_unmap_single(lp->pdev,
265 le32_to_cpu(lp->tx_insert_ptr->buf),
266 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
267 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
268 lp->tx_insert_ptr->skb_ptr = NULL;
269 }
270 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
271 }
272 }
273
274 static void r6040_free_rxbufs(struct net_device *dev)
275 {
276 struct r6040_private *lp = netdev_priv(dev);
277 int i;
278
279 for (i = 0; i < RX_DCNT; i++) {
280 if (lp->rx_insert_ptr->skb_ptr) {
281 pci_unmap_single(lp->pdev,
282 le32_to_cpu(lp->rx_insert_ptr->buf),
283 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
284 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
285 lp->rx_insert_ptr->skb_ptr = NULL;
286 }
287 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
288 }
289 }
290
291 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
292 dma_addr_t desc_dma, int size)
293 {
294 struct r6040_descriptor *desc = desc_ring;
295 dma_addr_t mapping = desc_dma;
296
297 while (size-- > 0) {
298 mapping += sizeof(*desc);
299 desc->ndesc = cpu_to_le32(mapping);
300 desc->vndescp = desc + 1;
301 desc++;
302 }
303 desc--;
304 desc->ndesc = cpu_to_le32(desc_dma);
305 desc->vndescp = desc_ring;
306 }
307
308 static void r6040_init_txbufs(struct net_device *dev)
309 {
310 struct r6040_private *lp = netdev_priv(dev);
311
312 lp->tx_free_desc = TX_DCNT;
313
314 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
315 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
316 }
317
318 static int r6040_alloc_rxbufs(struct net_device *dev)
319 {
320 struct r6040_private *lp = netdev_priv(dev);
321 struct r6040_descriptor *desc;
322 struct sk_buff *skb;
323 int rc;
324
325 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
326 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
327
328 /* Allocate skbs for the rx descriptors */
329 desc = lp->rx_ring;
330 do {
331 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
332 if (!skb) {
333 printk(KERN_ERR DRV_NAME "%s: failed to alloc skb for rx\n", dev->name);
334 rc = -ENOMEM;
335 goto err_exit;
336 }
337 desc->skb_ptr = skb;
338 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
339 desc->skb_ptr->data,
340 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
341 desc->status = DSC_OWNER_MAC;
342 desc = desc->vndescp;
343 } while (desc != lp->rx_ring);
344
345 return 0;
346
347 err_exit:
348 /* Deallocate all previously allocated skbs */
349 r6040_free_rxbufs(dev);
350 return rc;
351 }
352
353 static void r6040_init_mac_regs(struct net_device *dev)
354 {
355 struct r6040_private *lp = netdev_priv(dev);
356 void __iomem *ioaddr = lp->base;
357 int limit = 2048;
358 u16 cmd;
359
360 /* Mask Off Interrupt */
361 iowrite16(MSK_INT, ioaddr + MIER);
362
363 /* Reset RDC MAC */
364 iowrite16(MAC_RST, ioaddr + MCR1);
365 while (limit--) {
366 cmd = ioread16(ioaddr + MCR1);
367 if (cmd & 0x1)
368 break;
369 }
370 /* Reset internal state machine */
371 iowrite16(2, ioaddr + MAC_SM);
372 iowrite16(0, ioaddr + MAC_SM);
373 mdelay(5);
374
375 /* MAC Bus Control Register */
376 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
377
378 /* Buffer Size Register */
379 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
380
381 /* Write TX ring start address */
382 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
383 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
384
385 /* Write RX ring start address */
386 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
387 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
388
389 /* Set interrupt waiting time and packet numbers */
390 iowrite16(0, ioaddr + MT_ICR);
391 iowrite16(0, ioaddr + MR_ICR);
392
393 /* Enable interrupts */
394 iowrite16(INT_MASK, ioaddr + MIER);
395
396 /* Enable TX and RX */
397 iowrite16(lp->mcr0 | 0x0002, ioaddr);
398
399 /* Let TX poll the descriptors
400 * we may got called by r6040_tx_timeout which has left
401 * some unsent tx buffers */
402 iowrite16(0x01, ioaddr + MTPR);
403
404 /* Check media */
405 mii_check_media(&lp->mii_if, 1, 1);
406 }
407
408 static void r6040_tx_timeout(struct net_device *dev)
409 {
410 struct r6040_private *priv = netdev_priv(dev);
411 void __iomem *ioaddr = priv->base;
412
413 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
414 "status %4.4x, PHY status %4.4x\n",
415 dev->name, ioread16(ioaddr + MIER),
416 ioread16(ioaddr + MISR),
417 r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
418
419 dev->stats.tx_errors++;
420
421 /* Reset MAC and re-init all registers */
422 r6040_init_mac_regs(dev);
423 }
424
425 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
426 {
427 struct r6040_private *priv = netdev_priv(dev);
428 void __iomem *ioaddr = priv->base;
429 unsigned long flags;
430
431 spin_lock_irqsave(&priv->lock, flags);
432 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
433 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
434 spin_unlock_irqrestore(&priv->lock, flags);
435
436 return &dev->stats;
437 }
438
439 /* Stop RDC MAC and Free the allocated resource */
440 static void r6040_down(struct net_device *dev)
441 {
442 struct r6040_private *lp = netdev_priv(dev);
443 void __iomem *ioaddr = lp->base;
444 int limit = 2048;
445 u16 *adrp;
446 u16 cmd;
447
448 /* Stop MAC */
449 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
450 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
451 while (limit--) {
452 cmd = ioread16(ioaddr + MCR1);
453 if (cmd & 0x1)
454 break;
455 }
456
457 /* Restore MAC Address to MIDx */
458 adrp = (u16 *) dev->dev_addr;
459 iowrite16(adrp[0], ioaddr + MID_0L);
460 iowrite16(adrp[1], ioaddr + MID_0M);
461 iowrite16(adrp[2], ioaddr + MID_0H);
462 }
463
464 static int r6040_close(struct net_device *dev)
465 {
466 struct r6040_private *lp = netdev_priv(dev);
467 struct pci_dev *pdev = lp->pdev;
468
469 /* deleted timer */
470 del_timer_sync(&lp->timer);
471
472 spin_lock_irq(&lp->lock);
473 napi_disable(&lp->napi);
474 netif_stop_queue(dev);
475 r6040_down(dev);
476
477 free_irq(dev->irq, dev);
478
479 /* Free RX buffer */
480 r6040_free_rxbufs(dev);
481
482 /* Free TX buffer */
483 r6040_free_txbufs(dev);
484
485 spin_unlock_irq(&lp->lock);
486
487 /* Free Descriptor memory */
488 if (lp->rx_ring) {
489 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
490 lp->rx_ring = NULL;
491 }
492
493 if (lp->tx_ring) {
494 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
495 lp->tx_ring = NULL;
496 }
497
498 return 0;
499 }
500
501 /* Status of PHY CHIP */
502 static int r6040_phy_mode_chk(struct net_device *dev)
503 {
504 struct r6040_private *lp = netdev_priv(dev);
505 void __iomem *ioaddr = lp->base;
506 int phy_dat;
507
508 /* PHY Link Status Check */
509 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
510 if (!(phy_dat & 0x4))
511 phy_dat = 0x8000; /* Link Failed, full duplex */
512
513 /* PHY Chip Auto-Negotiation Status */
514 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
515 if (phy_dat & 0x0020) {
516 /* Auto Negotiation Mode */
517 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5);
518 phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4);
519 if (phy_dat & 0x140)
520 /* Force full duplex */
521 phy_dat = 0x8000;
522 else
523 phy_dat = 0;
524 } else {
525 /* Force Mode */
526 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0);
527 if (phy_dat & 0x100)
528 phy_dat = 0x8000;
529 else
530 phy_dat = 0x0000;
531 }
532
533 mii_check_media(&lp->mii_if, 0, 1);
534
535 return phy_dat;
536 };
537
538 static void r6040_set_carrier(struct mii_if_info *mii)
539 {
540 if (r6040_phy_mode_chk(mii->dev)) {
541 /* autoneg is off: Link is always assumed to be up */
542 if (!netif_carrier_ok(mii->dev))
543 netif_carrier_on(mii->dev);
544 } else
545 r6040_phy_mode_chk(mii->dev);
546 }
547
548 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
549 {
550 struct r6040_private *lp = netdev_priv(dev);
551 struct mii_ioctl_data *data = if_mii(rq);
552 int rc;
553
554 if (!netif_running(dev))
555 return -EINVAL;
556 spin_lock_irq(&lp->lock);
557 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
558 spin_unlock_irq(&lp->lock);
559 r6040_set_carrier(&lp->mii_if);
560 return rc;
561 }
562
563 static int r6040_rx(struct net_device *dev, int limit)
564 {
565 struct r6040_private *priv = netdev_priv(dev);
566 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
567 struct sk_buff *skb_ptr, *new_skb;
568 int count = 0;
569 u16 err;
570
571 /* Limit not reached and the descriptor belongs to the CPU */
572 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
573 /* Read the descriptor status */
574 err = descptr->status;
575 /* Global error status set */
576 if (err & DSC_RX_ERR) {
577 /* RX dribble */
578 if (err & DSC_RX_ERR_DRI)
579 dev->stats.rx_frame_errors++;
580 /* Buffer lenght exceeded */
581 if (err & DSC_RX_ERR_BUF)
582 dev->stats.rx_length_errors++;
583 /* Packet too long */
584 if (err & DSC_RX_ERR_LONG)
585 dev->stats.rx_length_errors++;
586 /* Packet < 64 bytes */
587 if (err & DSC_RX_ERR_RUNT)
588 dev->stats.rx_length_errors++;
589 /* CRC error */
590 if (err & DSC_RX_ERR_CRC) {
591 spin_lock(&priv->lock);
592 dev->stats.rx_crc_errors++;
593 spin_unlock(&priv->lock);
594 }
595 goto next_descr;
596 }
597
598 /* Packet successfully received */
599 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
600 if (!new_skb) {
601 dev->stats.rx_dropped++;
602 goto next_descr;
603 }
604 skb_ptr = descptr->skb_ptr;
605 skb_ptr->dev = priv->dev;
606
607 /* Do not count the CRC */
608 skb_put(skb_ptr, descptr->len - 4);
609 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
610 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
611 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
612
613 /* Send to upper layer */
614 netif_receive_skb(skb_ptr);
615 dev->stats.rx_packets++;
616 dev->stats.rx_bytes += descptr->len - 4;
617
618 /* put new skb into descriptor */
619 descptr->skb_ptr = new_skb;
620 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
621 descptr->skb_ptr->data,
622 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
623
624 next_descr:
625 /* put the descriptor back to the MAC */
626 descptr->status = DSC_OWNER_MAC;
627 descptr = descptr->vndescp;
628 count++;
629 }
630 priv->rx_remove_ptr = descptr;
631
632 return count;
633 }
634
635 static void r6040_tx(struct net_device *dev)
636 {
637 struct r6040_private *priv = netdev_priv(dev);
638 struct r6040_descriptor *descptr;
639 void __iomem *ioaddr = priv->base;
640 struct sk_buff *skb_ptr;
641 u16 err;
642
643 spin_lock(&priv->lock);
644 descptr = priv->tx_remove_ptr;
645 while (priv->tx_free_desc < TX_DCNT) {
646 /* Check for errors */
647 err = ioread16(ioaddr + MLSR);
648
649 if (err & 0x0200)
650 dev->stats.rx_fifo_errors++;
651 if (err & (0x2000 | 0x4000))
652 dev->stats.tx_carrier_errors++;
653
654 if (descptr->status & DSC_OWNER_MAC)
655 break; /* Not complete */
656 skb_ptr = descptr->skb_ptr;
657 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
658 skb_ptr->len, PCI_DMA_TODEVICE);
659 /* Free buffer */
660 dev_kfree_skb_irq(skb_ptr);
661 descptr->skb_ptr = NULL;
662 /* To next descriptor */
663 descptr = descptr->vndescp;
664 priv->tx_free_desc++;
665 }
666 priv->tx_remove_ptr = descptr;
667
668 if (priv->tx_free_desc)
669 netif_wake_queue(dev);
670 spin_unlock(&priv->lock);
671 }
672
673 static int r6040_poll(struct napi_struct *napi, int budget)
674 {
675 struct r6040_private *priv =
676 container_of(napi, struct r6040_private, napi);
677 struct net_device *dev = priv->dev;
678 void __iomem *ioaddr = priv->base;
679 int work_done;
680
681 work_done = r6040_rx(dev, budget);
682
683 if (work_done < budget) {
684 napi_complete(napi);
685 /* Enable RX interrupt */
686 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
687 }
688 return work_done;
689 }
690
691 /* The RDC interrupt handler. */
692 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
693 {
694 struct net_device *dev = dev_id;
695 struct r6040_private *lp = netdev_priv(dev);
696 void __iomem *ioaddr = lp->base;
697 u16 misr, status;
698
699 /* Save MIER */
700 misr = ioread16(ioaddr + MIER);
701 /* Mask off RDC MAC interrupt */
702 iowrite16(MSK_INT, ioaddr + MIER);
703 /* Read MISR status and clear */
704 status = ioread16(ioaddr + MISR);
705
706 if (status == 0x0000 || status == 0xffff) {
707 /* Restore RDC MAC interrupt */
708 iowrite16(misr, ioaddr + MIER);
709 return IRQ_NONE;
710 }
711
712 /* RX interrupt request */
713 if (status & RX_INTS) {
714 if (status & RX_NO_DESC) {
715 /* RX descriptor unavailable */
716 dev->stats.rx_dropped++;
717 dev->stats.rx_missed_errors++;
718 }
719 if (status & RX_FIFO_FULL)
720 dev->stats.rx_fifo_errors++;
721
722 /* Mask off RX interrupt */
723 misr &= ~RX_INTS;
724 napi_schedule(&lp->napi);
725 }
726
727 /* TX interrupt request */
728 if (status & TX_INTS)
729 r6040_tx(dev);
730
731 /* Restore RDC MAC interrupt */
732 iowrite16(misr, ioaddr + MIER);
733
734 return IRQ_HANDLED;
735 }
736
737 #ifdef CONFIG_NET_POLL_CONTROLLER
738 static void r6040_poll_controller(struct net_device *dev)
739 {
740 disable_irq(dev->irq);
741 r6040_interrupt(dev->irq, dev);
742 enable_irq(dev->irq);
743 }
744 #endif
745
746 /* Init RDC MAC */
747 static int r6040_up(struct net_device *dev)
748 {
749 struct r6040_private *lp = netdev_priv(dev);
750 void __iomem *ioaddr = lp->base;
751 int ret;
752
753 /* Initialise and alloc RX/TX buffers */
754 r6040_init_txbufs(dev);
755 ret = r6040_alloc_rxbufs(dev);
756 if (ret)
757 return ret;
758
759 /* Read the PHY ID */
760 lp->switch_sig = r6040_phy_read(ioaddr, 0, 2);
761
762 if (lp->switch_sig == ICPLUS_PHY_ID) {
763 r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
764 lp->phy_mode = 0x8000;
765 } else {
766 /* PHY Mode Check */
767 r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
768 r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
769
770 if (PHY_MODE == 0x3100)
771 lp->phy_mode = r6040_phy_mode_chk(dev);
772 else
773 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
774 }
775
776 /* Set duplex mode */
777 lp->mcr0 |= lp->phy_mode;
778
779 /* improve performance (by RDC guys) */
780 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
781 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
782 r6040_phy_write(ioaddr, 0, 19, 0x0000);
783 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
784
785 /* Initialize all MAC registers */
786 r6040_init_mac_regs(dev);
787
788 return 0;
789 }
790
791 /*
792 A periodic timer routine
793 Polling PHY Chip Link Status
794 */
795 static void r6040_timer(unsigned long data)
796 {
797 struct net_device *dev = (struct net_device *)data;
798 struct r6040_private *lp = netdev_priv(dev);
799 void __iomem *ioaddr = lp->base;
800 u16 phy_mode;
801
802 /* Polling PHY Chip Status */
803 if (PHY_MODE == 0x3100)
804 phy_mode = r6040_phy_mode_chk(dev);
805 else
806 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
807
808 if (phy_mode != lp->phy_mode) {
809 lp->phy_mode = phy_mode;
810 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
811 iowrite16(lp->mcr0, ioaddr);
812 }
813
814 /* Timer active again */
815 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
816 }
817
818 /* Read/set MAC address routines */
819 static void r6040_mac_address(struct net_device *dev)
820 {
821 struct r6040_private *lp = netdev_priv(dev);
822 void __iomem *ioaddr = lp->base;
823 u16 *adrp;
824
825 /* MAC operation register */
826 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
827 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
828 iowrite16(0, ioaddr + MAC_SM);
829 mdelay(5);
830
831 /* Restore MAC Address */
832 adrp = (u16 *) dev->dev_addr;
833 iowrite16(adrp[0], ioaddr + MID_0L);
834 iowrite16(adrp[1], ioaddr + MID_0M);
835 iowrite16(adrp[2], ioaddr + MID_0H);
836 }
837
838 static int r6040_open(struct net_device *dev)
839 {
840 struct r6040_private *lp = netdev_priv(dev);
841 int ret;
842
843 /* Request IRQ and Register interrupt handler */
844 ret = request_irq(dev->irq, r6040_interrupt,
845 IRQF_SHARED, dev->name, dev);
846 if (ret)
847 return ret;
848
849 /* Set MAC address */
850 r6040_mac_address(dev);
851
852 /* Allocate Descriptor memory */
853 lp->rx_ring =
854 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
855 if (!lp->rx_ring)
856 return -ENOMEM;
857
858 lp->tx_ring =
859 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
860 if (!lp->tx_ring) {
861 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
862 lp->rx_ring_dma);
863 return -ENOMEM;
864 }
865
866 ret = r6040_up(dev);
867 if (ret) {
868 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
869 lp->tx_ring_dma);
870 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
871 lp->rx_ring_dma);
872 return ret;
873 }
874
875 napi_enable(&lp->napi);
876 netif_start_queue(dev);
877
878 /* set and active a timer process */
879 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
880 if (lp->switch_sig != ICPLUS_PHY_ID)
881 mod_timer(&lp->timer, jiffies + HZ);
882 return 0;
883 }
884
885 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
886 struct net_device *dev)
887 {
888 struct r6040_private *lp = netdev_priv(dev);
889 struct r6040_descriptor *descptr;
890 void __iomem *ioaddr = lp->base;
891 unsigned long flags;
892
893 /* Critical Section */
894 spin_lock_irqsave(&lp->lock, flags);
895
896 /* TX resource check */
897 if (!lp->tx_free_desc) {
898 spin_unlock_irqrestore(&lp->lock, flags);
899 netif_stop_queue(dev);
900 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
901 return NETDEV_TX_BUSY;
902 }
903
904 /* Statistic Counter */
905 dev->stats.tx_packets++;
906 dev->stats.tx_bytes += skb->len;
907 /* Set TX descriptor & Transmit it */
908 lp->tx_free_desc--;
909 descptr = lp->tx_insert_ptr;
910 if (skb->len < MISR)
911 descptr->len = MISR;
912 else
913 descptr->len = skb->len;
914
915 descptr->skb_ptr = skb;
916 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
917 skb->data, skb->len, PCI_DMA_TODEVICE));
918 descptr->status = DSC_OWNER_MAC;
919 /* Trigger the MAC to check the TX descriptor */
920 iowrite16(0x01, ioaddr + MTPR);
921 lp->tx_insert_ptr = descptr->vndescp;
922
923 /* If no tx resource, stop */
924 if (!lp->tx_free_desc)
925 netif_stop_queue(dev);
926
927 dev->trans_start = jiffies;
928 spin_unlock_irqrestore(&lp->lock, flags);
929
930 return NETDEV_TX_OK;
931 }
932
933 static void r6040_multicast_list(struct net_device *dev)
934 {
935 struct r6040_private *lp = netdev_priv(dev);
936 void __iomem *ioaddr = lp->base;
937 u16 *adrp;
938 u16 reg;
939 unsigned long flags;
940 struct dev_mc_list *dmi;
941 int i;
942
943 /* MAC Address */
944 adrp = (u16 *)dev->dev_addr;
945 iowrite16(adrp[0], ioaddr + MID_0L);
946 iowrite16(adrp[1], ioaddr + MID_0M);
947 iowrite16(adrp[2], ioaddr + MID_0H);
948
949 /* Promiscous Mode */
950 spin_lock_irqsave(&lp->lock, flags);
951
952 /* Clear AMCP & PROM bits */
953 reg = ioread16(ioaddr) & ~0x0120;
954 if (dev->flags & IFF_PROMISC) {
955 reg |= 0x0020;
956 lp->mcr0 |= 0x0020;
957 }
958 /* Too many multicast addresses
959 * accept all traffic */
960 else if ((netdev_mc_count(dev) > MCAST_MAX) ||
961 (dev->flags & IFF_ALLMULTI))
962 reg |= 0x0020;
963
964 iowrite16(reg, ioaddr);
965 spin_unlock_irqrestore(&lp->lock, flags);
966
967 /* Build the hash table */
968 if (netdev_mc_count(dev) > MCAST_MAX) {
969 u16 hash_table[4];
970 u32 crc;
971
972 for (i = 0; i < 4; i++)
973 hash_table[i] = 0;
974
975 netdev_for_each_mc_addr(dmi, dev) {
976 char *addrs = dmi->dmi_addr;
977
978 if (!(*addrs & 1))
979 continue;
980
981 crc = ether_crc_le(6, addrs);
982 crc >>= 26;
983 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
984 }
985 /* Fill the MAC hash tables with their values */
986 iowrite16(hash_table[0], ioaddr + MAR0);
987 iowrite16(hash_table[1], ioaddr + MAR1);
988 iowrite16(hash_table[2], ioaddr + MAR2);
989 iowrite16(hash_table[3], ioaddr + MAR3);
990 }
991 /* Multicast Address 1~4 case */
992 i = 0;
993 netdev_for_each_mc_addr(dmi, dev) {
994 if (i < MCAST_MAX) {
995 adrp = (u16 *) dmi->dmi_addr;
996 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
997 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
998 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
999 } else {
1000 iowrite16(0xffff, ioaddr + MID_1L + 8 * i);
1001 iowrite16(0xffff, ioaddr + MID_1M + 8 * i);
1002 iowrite16(0xffff, ioaddr + MID_1H + 8 * i);
1003 }
1004 i++;
1005 }
1006 }
1007
1008 static void netdev_get_drvinfo(struct net_device *dev,
1009 struct ethtool_drvinfo *info)
1010 {
1011 struct r6040_private *rp = netdev_priv(dev);
1012
1013 strcpy(info->driver, DRV_NAME);
1014 strcpy(info->version, DRV_VERSION);
1015 strcpy(info->bus_info, pci_name(rp->pdev));
1016 }
1017
1018 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1019 {
1020 struct r6040_private *rp = netdev_priv(dev);
1021 int rc;
1022
1023 spin_lock_irq(&rp->lock);
1024 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1025 spin_unlock_irq(&rp->lock);
1026
1027 return rc;
1028 }
1029
1030 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1031 {
1032 struct r6040_private *rp = netdev_priv(dev);
1033 int rc;
1034
1035 spin_lock_irq(&rp->lock);
1036 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1037 spin_unlock_irq(&rp->lock);
1038 r6040_set_carrier(&rp->mii_if);
1039
1040 return rc;
1041 }
1042
1043 static u32 netdev_get_link(struct net_device *dev)
1044 {
1045 struct r6040_private *rp = netdev_priv(dev);
1046
1047 return mii_link_ok(&rp->mii_if);
1048 }
1049
1050 static const struct ethtool_ops netdev_ethtool_ops = {
1051 .get_drvinfo = netdev_get_drvinfo,
1052 .get_settings = netdev_get_settings,
1053 .set_settings = netdev_set_settings,
1054 .get_link = netdev_get_link,
1055 };
1056
1057 static const struct net_device_ops r6040_netdev_ops = {
1058 .ndo_open = r6040_open,
1059 .ndo_stop = r6040_close,
1060 .ndo_start_xmit = r6040_start_xmit,
1061 .ndo_get_stats = r6040_get_stats,
1062 .ndo_set_multicast_list = r6040_multicast_list,
1063 .ndo_change_mtu = eth_change_mtu,
1064 .ndo_validate_addr = eth_validate_addr,
1065 .ndo_set_mac_address = eth_mac_addr,
1066 .ndo_do_ioctl = r6040_ioctl,
1067 .ndo_tx_timeout = r6040_tx_timeout,
1068 #ifdef CONFIG_NET_POLL_CONTROLLER
1069 .ndo_poll_controller = r6040_poll_controller,
1070 #endif
1071 };
1072
1073 static int __devinit r6040_init_one(struct pci_dev *pdev,
1074 const struct pci_device_id *ent)
1075 {
1076 struct net_device *dev;
1077 struct r6040_private *lp;
1078 void __iomem *ioaddr;
1079 int err, io_size = R6040_IO_SIZE;
1080 static int card_idx = -1;
1081 int bar = 0;
1082 u16 *adrp;
1083
1084 printk("%s\n", version);
1085
1086 err = pci_enable_device(pdev);
1087 if (err)
1088 goto err_out;
1089
1090 /* this should always be supported */
1091 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1092 if (err) {
1093 printk(KERN_ERR DRV_NAME ": 32-bit PCI DMA addresses"
1094 "not supported by the card\n");
1095 goto err_out;
1096 }
1097 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1098 if (err) {
1099 printk(KERN_ERR DRV_NAME ": 32-bit PCI DMA addresses"
1100 "not supported by the card\n");
1101 goto err_out;
1102 }
1103
1104 /* IO Size check */
1105 if (pci_resource_len(pdev, bar) < io_size) {
1106 printk(KERN_ERR DRV_NAME ": Insufficient PCI resources, aborting\n");
1107 err = -EIO;
1108 goto err_out;
1109 }
1110
1111 pci_set_master(pdev);
1112
1113 dev = alloc_etherdev(sizeof(struct r6040_private));
1114 if (!dev) {
1115 printk(KERN_ERR DRV_NAME ": Failed to allocate etherdev\n");
1116 err = -ENOMEM;
1117 goto err_out;
1118 }
1119 SET_NETDEV_DEV(dev, &pdev->dev);
1120 lp = netdev_priv(dev);
1121
1122 err = pci_request_regions(pdev, DRV_NAME);
1123
1124 if (err) {
1125 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1126 goto err_out_free_dev;
1127 }
1128
1129 ioaddr = pci_iomap(pdev, bar, io_size);
1130 if (!ioaddr) {
1131 printk(KERN_ERR DRV_NAME ": ioremap failed for device %s\n",
1132 pci_name(pdev));
1133 err = -EIO;
1134 goto err_out_free_res;
1135 }
1136 /* If PHY status change register is still set to zero it means the
1137 * bootloader didn't initialize it */
1138 if (ioread16(ioaddr + PHY_CC) == 0)
1139 iowrite16(0x9f07, ioaddr + PHY_CC);
1140
1141 /* Init system & device */
1142 lp->base = ioaddr;
1143 dev->irq = pdev->irq;
1144
1145 spin_lock_init(&lp->lock);
1146 pci_set_drvdata(pdev, dev);
1147
1148 /* Set MAC address */
1149 card_idx++;
1150
1151 adrp = (u16 *)dev->dev_addr;
1152 adrp[0] = ioread16(ioaddr + MID_0L);
1153 adrp[1] = ioread16(ioaddr + MID_0M);
1154 adrp[2] = ioread16(ioaddr + MID_0H);
1155
1156 /* Some bootloader/BIOSes do not initialize
1157 * MAC address, warn about that */
1158 if (!(adrp[0] || adrp[1] || adrp[2])) {
1159 printk(KERN_WARNING DRV_NAME ": MAC address not initialized, generating random\n");
1160 random_ether_addr(dev->dev_addr);
1161 }
1162
1163 /* Link new device into r6040_root_dev */
1164 lp->pdev = pdev;
1165 lp->dev = dev;
1166
1167 /* Init RDC private data */
1168 lp->mcr0 = 0x1002;
1169 lp->phy_addr = phy_table[card_idx];
1170 lp->switch_sig = 0;
1171
1172 /* The RDC-specific entries in the device structure. */
1173 dev->netdev_ops = &r6040_netdev_ops;
1174 dev->ethtool_ops = &netdev_ethtool_ops;
1175 dev->watchdog_timeo = TX_TIMEOUT;
1176
1177 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1178 lp->mii_if.dev = dev;
1179 lp->mii_if.mdio_read = r6040_mdio_read;
1180 lp->mii_if.mdio_write = r6040_mdio_write;
1181 lp->mii_if.phy_id = lp->phy_addr;
1182 lp->mii_if.phy_id_mask = 0x1f;
1183 lp->mii_if.reg_num_mask = 0x1f;
1184
1185 /* Check the vendor ID on the PHY, if 0xffff assume none attached */
1186 if (r6040_phy_read(ioaddr, lp->phy_addr, 2) == 0xffff) {
1187 printk(KERN_ERR DRV_NAME ": Failed to detect an attached PHY\n");
1188 err = -ENODEV;
1189 goto err_out_unmap;
1190 }
1191
1192 /* Register net device. After this dev->name assign */
1193 err = register_netdev(dev);
1194 if (err) {
1195 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1196 goto err_out_unmap;
1197 }
1198 return 0;
1199
1200 err_out_unmap:
1201 pci_iounmap(pdev, ioaddr);
1202 err_out_free_res:
1203 pci_release_regions(pdev);
1204 err_out_free_dev:
1205 free_netdev(dev);
1206 err_out:
1207 return err;
1208 }
1209
1210 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1211 {
1212 struct net_device *dev = pci_get_drvdata(pdev);
1213
1214 unregister_netdev(dev);
1215 pci_release_regions(pdev);
1216 free_netdev(dev);
1217 pci_disable_device(pdev);
1218 pci_set_drvdata(pdev, NULL);
1219 }
1220
1221
1222 static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
1223 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1224 { 0 }
1225 };
1226 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1227
1228 static struct pci_driver r6040_driver = {
1229 .name = DRV_NAME,
1230 .id_table = r6040_pci_tbl,
1231 .probe = r6040_init_one,
1232 .remove = __devexit_p(r6040_remove_one),
1233 };
1234
1235
1236 static int __init r6040_init(void)
1237 {
1238 return pci_register_driver(&r6040_driver);
1239 }
1240
1241
1242 static void __exit r6040_cleanup(void)
1243 {
1244 pci_unregister_driver(&r6040_driver);
1245 }
1246
1247 module_init(r6040_init);
1248 module_exit(r6040_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree