arch/mips/kernel/irq_cpu.c

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   4  *
   5  * Copyright (C) 2001 Ralf Baechle
   6  * Copyright (C) 2005  MIPS Technologies, Inc.  All rights reserved.
   7  *      Author: Maciej W. Rozycki <macro@mips.com>
   8  *
   9  * This file define the irq handler for MIPS CPU interrupts.
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 /*
  18  * Almost all MIPS CPUs define 8 interrupt sources.  They are typically
  19  * level triggered (i.e., cannot be cleared from CPU; must be cleared from
  20  * device).  The first two are software interrupts which we don't really
  21  * use or support.  The last one is usually the CPU timer interrupt if
  22  * counter register is present or, for CPUs with an external FPU, by
  23  * convention it's the FPU exception interrupt.
  24  *
  25  * Don't even think about using this on SMP.  You have been warned.
  26  *
  27  * This file exports one global function:
  28  *      void mips_cpu_irq_init(void);
  29  */
  30 #include <linux/init.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/kernel.h>
  33 #include <linux/irq.h>
  34
  35 #include <asm/irq_cpu.h>
  36 #include <asm/mipsregs.h>
  37 #include <asm/mipsmtregs.h>
  38 #include <asm/system.h>
  39
  40 static inline void unmask_mips_irq(unsigned int irq)
  41 {
  42         set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
  43         irq_enable_hazard();
  44 }
  45
  46 static inline void mask_mips_irq(unsigned int irq)
  47 {
  48         clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
  49         irq_disable_hazard();
  50 }
  51
  52 static struct irq_chip mips_cpu_irq_controller = {
  53         .name           = "MIPS",
  54         .ack            = mask_mips_irq,
  55         .mask           = mask_mips_irq,
  56         .mask_ack       = mask_mips_irq,
  57         .unmask         = unmask_mips_irq,
  58         .eoi            = unmask_mips_irq,
  59 };
  60
  61 /*
  62  * Basically the same as above but taking care of all the MT stuff
  63  */
  64
  65 #define unmask_mips_mt_irq      unmask_mips_irq
  66 #define mask_mips_mt_irq        mask_mips_irq
  67
  68 static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
  69 {
  70         unsigned int vpflags = dvpe();
  71
  72         clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
  73         evpe(vpflags);
  74         unmask_mips_mt_irq(irq);
  75
  76         return 0;
  77 }
  78
  79 /*
  80  * While we ack the interrupt interrupts are disabled and thus we don't need
  81  * to deal with concurrency issues.  Same for mips_cpu_irq_end.
  82  */
  83 static void mips_mt_cpu_irq_ack(unsigned int irq)
  84 {
  85         unsigned int vpflags = dvpe();
  86         clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
  87         evpe(vpflags);
  88         mask_mips_mt_irq(irq);
  89 }
  90
  91 static struct irq_chip mips_mt_cpu_irq_controller = {
  92         .name           = "MIPS",
  93         .startup        = mips_mt_cpu_irq_startup,
  94         .ack            = mips_mt_cpu_irq_ack,
  95         .mask           = mask_mips_mt_irq,
  96         .mask_ack       = mips_mt_cpu_irq_ack,
  97         .unmask         = unmask_mips_mt_irq,
  98         .eoi            = unmask_mips_mt_irq,
  99 };
 100
 101 void __init mips_cpu_irq_init(void)
 102 {
 103         int irq_base = MIPS_CPU_IRQ_BASE;
 104         int i;
 105
 106         /* Mask interrupts. */
 107         clear_c0_status(ST0_IM);
 108         clear_c0_cause(CAUSEF_IP);
 109
 110         /*
 111          * Only MT is using the software interrupts currently, so we just
 112          * leave them uninitialized for other processors.
 113          */
 114         if (cpu_has_mipsmt)
 115                 for (i = irq_base; i < irq_base + 2; i++)
 116                         set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
 117                                                  handle_percpu_irq);
 118
 119         for (i = irq_base + 2; i < irq_base + 8; i++)
 120                 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
 121                                          handle_percpu_irq);
 122 }