4 * Copyright (C) 2008 Renesas Solutions
6 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/platform_device.h>
13 #include <linux/init.h>
14 #include <linux/serial.h>
15 #include <linux/serial_sci.h>
16 #include <linux/uio_driver.h>
17 #include <linux/sh_timer.h>
18 #include <linux/usb/r8a66597.h>
19 #include <asm/clock.h>
21 static struct plat_sci_port scif0_platform_data
= {
22 .mapbase
= 0xffe00000,
23 .flags
= UPF_BOOT_AUTOCONF
,
25 .irqs
= { 80, 80, 80, 80 },
28 static struct platform_device scif0_device
= {
32 .platform_data
= &scif0_platform_data
,
36 static struct resource iic_resources
[] = {
41 .flags
= IORESOURCE_MEM
,
46 .flags
= IORESOURCE_IRQ
,
50 static struct platform_device iic_device
= {
51 .name
= "i2c-sh_mobile",
52 .id
= 0, /* "i2c0" clock */
53 .num_resources
= ARRAY_SIZE(iic_resources
),
54 .resource
= iic_resources
,
57 static struct r8a66597_platdata r8a66597_data
= {
61 static struct resource usb_host_resources
[] = {
65 .flags
= IORESOURCE_MEM
,
70 .flags
= IORESOURCE_IRQ
| IRQF_TRIGGER_LOW
,
74 static struct platform_device usb_host_device
= {
75 .name
= "r8a66597_hcd",
79 .coherent_dma_mask
= 0xffffffff,
80 .platform_data
= &r8a66597_data
,
82 .num_resources
= ARRAY_SIZE(usb_host_resources
),
83 .resource
= usb_host_resources
,
86 static struct uio_info vpu_platform_data
= {
92 static struct resource vpu_resources
[] = {
97 .flags
= IORESOURCE_MEM
,
100 /* place holder for contiguous memory */
104 static struct platform_device vpu_device
= {
105 .name
= "uio_pdrv_genirq",
108 .platform_data
= &vpu_platform_data
,
110 .resource
= vpu_resources
,
111 .num_resources
= ARRAY_SIZE(vpu_resources
),
114 static struct uio_info veu0_platform_data
= {
120 static struct resource veu0_resources
[] = {
125 .flags
= IORESOURCE_MEM
,
128 /* place holder for contiguous memory */
132 static struct platform_device veu0_device
= {
133 .name
= "uio_pdrv_genirq",
136 .platform_data
= &veu0_platform_data
,
138 .resource
= veu0_resources
,
139 .num_resources
= ARRAY_SIZE(veu0_resources
),
142 static struct uio_info veu1_platform_data
= {
148 static struct resource veu1_resources
[] = {
153 .flags
= IORESOURCE_MEM
,
156 /* place holder for contiguous memory */
160 static struct platform_device veu1_device
= {
161 .name
= "uio_pdrv_genirq",
164 .platform_data
= &veu1_platform_data
,
166 .resource
= veu1_resources
,
167 .num_resources
= ARRAY_SIZE(veu1_resources
),
170 static struct sh_timer_config cmt_platform_data
= {
171 .channel_offset
= 0x60,
173 .clockevent_rating
= 125,
174 .clocksource_rating
= 200,
177 static struct resource cmt_resources
[] = {
181 .flags
= IORESOURCE_MEM
,
185 .flags
= IORESOURCE_IRQ
,
189 static struct platform_device cmt_device
= {
193 .platform_data
= &cmt_platform_data
,
195 .resource
= cmt_resources
,
196 .num_resources
= ARRAY_SIZE(cmt_resources
),
199 static struct sh_timer_config tmu0_platform_data
= {
200 .channel_offset
= 0x04,
202 .clockevent_rating
= 200,
205 static struct resource tmu0_resources
[] = {
209 .flags
= IORESOURCE_MEM
,
213 .flags
= IORESOURCE_IRQ
,
217 static struct platform_device tmu0_device
= {
221 .platform_data
= &tmu0_platform_data
,
223 .resource
= tmu0_resources
,
224 .num_resources
= ARRAY_SIZE(tmu0_resources
),
227 static struct sh_timer_config tmu1_platform_data
= {
228 .channel_offset
= 0x10,
230 .clocksource_rating
= 200,
233 static struct resource tmu1_resources
[] = {
237 .flags
= IORESOURCE_MEM
,
241 .flags
= IORESOURCE_IRQ
,
245 static struct platform_device tmu1_device
= {
249 .platform_data
= &tmu1_platform_data
,
251 .resource
= tmu1_resources
,
252 .num_resources
= ARRAY_SIZE(tmu1_resources
),
255 static struct sh_timer_config tmu2_platform_data
= {
256 .channel_offset
= 0x1c,
260 static struct resource tmu2_resources
[] = {
264 .flags
= IORESOURCE_MEM
,
268 .flags
= IORESOURCE_IRQ
,
272 static struct platform_device tmu2_device
= {
276 .platform_data
= &tmu2_platform_data
,
278 .resource
= tmu2_resources
,
279 .num_resources
= ARRAY_SIZE(tmu2_resources
),
282 static struct platform_device
*sh7366_devices
[] __initdata
= {
295 static int __init
sh7366_devices_setup(void)
297 platform_resource_setup_memory(&vpu_device
, "vpu", 2 << 20);
298 platform_resource_setup_memory(&veu0_device
, "veu0", 2 << 20);
299 platform_resource_setup_memory(&veu1_device
, "veu1", 2 << 20);
301 return platform_add_devices(sh7366_devices
,
302 ARRAY_SIZE(sh7366_devices
));
304 arch_initcall(sh7366_devices_setup
);
306 static struct platform_device
*sh7366_early_devices
[] __initdata
= {
314 void __init
plat_early_device_setup(void)
316 early_platform_add_devices(sh7366_early_devices
,
317 ARRAY_SIZE(sh7366_early_devices
));
325 /* interrupt sources */
326 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
328 DMAC0
, DMAC1
, DMAC2
, DMAC3
,
329 VIO_CEUI
, VIO_BEUI
, VIO_VEUI
, VOU
,
331 MMC_MMC1I
, MMC_MMC2I
, MMC_MMC3I
,
332 DMAC4
, DMAC5
, DMAC_DADERR
,
333 SCIF
, SCIFA1
, SCIFA2
,
335 FLCTL_FLSTEI
, FLCTL_FLENDI
, FLCTL_FLTREQ0I
, FLCTL_FLTREQ1I
,
336 I2C_ALI
, I2C_TACKI
, I2C_WAITI
, I2C_DTEI
,
337 SDHI
, CMT
, TSIF
, SIU
,
341 /* interrupt groups */
343 DMAC0123
, VIOVOU
, MMC
, DMAC45
, FLCTL
, I2C
,
346 static struct intc_vect vectors
[] __initdata
= {
347 INTC_VECT(IRQ0
, 0x600), INTC_VECT(IRQ1
, 0x620),
348 INTC_VECT(IRQ2
, 0x640), INTC_VECT(IRQ3
, 0x660),
349 INTC_VECT(IRQ4
, 0x680), INTC_VECT(IRQ5
, 0x6a0),
350 INTC_VECT(IRQ6
, 0x6c0), INTC_VECT(IRQ7
, 0x6e0),
351 INTC_VECT(ICB
, 0x700),
352 INTC_VECT(DMAC0
, 0x800), INTC_VECT(DMAC1
, 0x820),
353 INTC_VECT(DMAC2
, 0x840), INTC_VECT(DMAC3
, 0x860),
354 INTC_VECT(VIO_CEUI
, 0x880), INTC_VECT(VIO_BEUI
, 0x8a0),
355 INTC_VECT(VIO_VEUI
, 0x8c0), INTC_VECT(VOU
, 0x8e0),
356 INTC_VECT(MFI
, 0x900), INTC_VECT(VPU
, 0x980), INTC_VECT(USB
, 0xa20),
357 INTC_VECT(MMC_MMC1I
, 0xb00), INTC_VECT(MMC_MMC2I
, 0xb20),
358 INTC_VECT(MMC_MMC3I
, 0xb40),
359 INTC_VECT(DMAC4
, 0xb80), INTC_VECT(DMAC5
, 0xba0),
360 INTC_VECT(DMAC_DADERR
, 0xbc0),
361 INTC_VECT(SCIF
, 0xc00), INTC_VECT(SCIFA1
, 0xc20),
362 INTC_VECT(SCIFA2
, 0xc40),
363 INTC_VECT(DENC
, 0xc60), INTC_VECT(MSIOF
, 0xc80),
364 INTC_VECT(FLCTL_FLSTEI
, 0xd80), INTC_VECT(FLCTL_FLENDI
, 0xda0),
365 INTC_VECT(FLCTL_FLTREQ0I
, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I
, 0xde0),
366 INTC_VECT(I2C_ALI
, 0xe00), INTC_VECT(I2C_TACKI
, 0xe20),
367 INTC_VECT(I2C_WAITI
, 0xe40), INTC_VECT(I2C_DTEI
, 0xe60),
368 INTC_VECT(SDHI
, 0xe80), INTC_VECT(SDHI
, 0xea0),
369 INTC_VECT(SDHI
, 0xec0), INTC_VECT(SDHI
, 0xee0),
370 INTC_VECT(CMT
, 0xf00), INTC_VECT(TSIF
, 0xf20),
371 INTC_VECT(SIU
, 0xf80),
372 INTC_VECT(TMU0
, 0x400), INTC_VECT(TMU1
, 0x420),
373 INTC_VECT(TMU2
, 0x440),
374 INTC_VECT(VEU2
, 0x560), INTC_VECT(LCDC
, 0x580),
377 static struct intc_group groups
[] __initdata
= {
378 INTC_GROUP(DMAC0123
, DMAC0
, DMAC1
, DMAC2
, DMAC3
),
379 INTC_GROUP(VIOVOU
, VIO_CEUI
, VIO_BEUI
, VIO_VEUI
, VOU
),
380 INTC_GROUP(MMC
, MMC_MMC1I
, MMC_MMC2I
, MMC_MMC3I
),
381 INTC_GROUP(DMAC45
, DMAC4
, DMAC5
, DMAC_DADERR
),
382 INTC_GROUP(FLCTL
, FLCTL_FLSTEI
, FLCTL_FLENDI
,
383 FLCTL_FLTREQ0I
, FLCTL_FLTREQ1I
),
384 INTC_GROUP(I2C
, I2C_ALI
, I2C_TACKI
, I2C_WAITI
, I2C_DTEI
),
387 static struct intc_mask_reg mask_registers
[] __initdata
= {
388 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
390 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
391 { VOU
, VIO_VEUI
, VIO_BEUI
, VIO_CEUI
, DMAC3
, DMAC2
, DMAC1
, DMAC0
} },
392 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
393 { 0, 0, 0, VPU
, 0, 0, 0, MFI
} },
394 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
396 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
397 { 0, TMU2
, TMU1
, TMU0
, VEU2
, 0, 0, LCDC
} },
398 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
399 { 0, DMAC_DADERR
, DMAC5
, DMAC4
, DENC
, SCIFA2
, SCIFA1
, SCIF
} },
400 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
401 { 0, 0, 0, 0, 0, 0, 0, MSIOF
} },
402 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
403 { I2C_DTEI
, I2C_WAITI
, I2C_TACKI
, I2C_ALI
,
404 FLCTL_FLTREQ1I
, FLCTL_FLTREQ0I
, FLCTL_FLENDI
, FLCTL_FLSTEI
} },
405 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
406 { DISABLED
, ENABLED
, ENABLED
, ENABLED
, 0, 0, 0, SIU
} },
407 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
408 { 0, 0, 0, CMT
, 0, USB
, } },
409 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
410 { 0, MMC_MMC3I
, MMC_MMC2I
, MMC_MMC1I
} },
411 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
412 { 0, 0, 0, 0, 0, 0, 0, TSIF
} },
413 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
414 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
417 static struct intc_prio_reg prio_registers
[] __initdata
= {
418 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0
, TMU1
, TMU2
} },
419 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2
, LCDC
, ICB
} },
420 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
421 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
422 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123
, VIOVOU
, MFI
, VPU
} },
423 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45
, USB
, CMT
} },
424 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF
, SCIFA1
, SCIFA2
, DENC
} },
425 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF
, 0, FLCTL
, I2C
} },
426 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF
, } },
427 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU
} },
428 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC
, 0, SDHI
} },
429 { 0xa408002c, 0, 16, 4, /* IPRL */ { } },
430 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
431 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
434 static struct intc_sense_reg sense_registers
[] __initdata
= {
435 { 0xa414001c, 16, 2, /* ICR1 */
436 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
439 static struct intc_mask_reg ack_registers
[] __initdata
= {
440 { 0xa4140024, 0, 8, /* INTREQ00 */
441 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
444 static struct intc_desc intc_desc __initdata
= {
446 .force_enable
= ENABLED
,
447 .force_disable
= DISABLED
,
448 .hw
= INTC_HW_DESC(vectors
, groups
, mask_registers
,
449 prio_registers
, sense_registers
, ack_registers
),
452 void __init
plat_irq_setup(void)
454 register_intc_controller(&intc_desc
);
457 void __init
plat_mem_setup(void)
459 /* TODO: Register Node 1 */