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drm/radeon/kms: rework texture cache flush in r6xx+ blit code
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / evergreen_blit_kms.c
blob879f7335029e088b47437cc8be952d64100af720
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Alex Deucher <alexander.deucher@amd.com>
25 */
26
27 #include "drmP.h"
28 #include "drm.h"
29 #include "radeon_drm.h"
30 #include "radeon.h"
31
32 #include "evergreend.h"
33 #include "evergreen_blit_shaders.h"
34 #include "cayman_blit_shaders.h"
35
36 #define DI_PT_RECTLIST 0x11
37 #define DI_INDEX_SIZE_16_BIT 0x0
38 #define DI_SRC_SEL_AUTO_INDEX 0x2
39
40 #define FMT_8 0x1
41 #define FMT_5_6_5 0x8
42 #define FMT_8_8_8_8 0x1a
43 #define COLOR_8 0x1
44 #define COLOR_5_6_5 0x8
45 #define COLOR_8_8_8_8 0x1a
46
47 /* emits 17 */
48 static void
49 set_render_target(struct radeon_device *rdev, int format,
50 int w, int h, u64 gpu_addr)
51 {
52 u32 cb_color_info;
53 int pitch, slice;
54
55 h = ALIGN(h, 8);
56 if (h < 8)
57 h = 8;
58
59 cb_color_info = CB_FORMAT(format) |
60 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
61 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
62 pitch = (w / 8) - 1;
63 slice = ((w * h) / 64) - 1;
64
65 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
66 radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
67 radeon_ring_write(rdev, gpu_addr >> 8);
68 radeon_ring_write(rdev, pitch);
69 radeon_ring_write(rdev, slice);
70 radeon_ring_write(rdev, 0);
71 radeon_ring_write(rdev, cb_color_info);
72 radeon_ring_write(rdev, 0);
73 radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16));
74 radeon_ring_write(rdev, 0);
75 radeon_ring_write(rdev, 0);
76 radeon_ring_write(rdev, 0);
77 radeon_ring_write(rdev, 0);
78 radeon_ring_write(rdev, 0);
79 radeon_ring_write(rdev, 0);
80 radeon_ring_write(rdev, 0);
81 radeon_ring_write(rdev, 0);
82 }
83
84 /* emits 5dw */
85 static void
86 cp_set_surface_sync(struct radeon_device *rdev,
87 u32 sync_type, u32 size,
88 u64 mc_addr)
89 {
90 u32 cp_coher_size;
91
92 if (size == 0xffffffff)
93 cp_coher_size = 0xffffffff;
94 else
95 cp_coher_size = ((size + 255) >> 8);
96
97 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
98 radeon_ring_write(rdev, sync_type);
99 radeon_ring_write(rdev, cp_coher_size);
100 radeon_ring_write(rdev, mc_addr >> 8);
101 radeon_ring_write(rdev, 10); /* poll interval */
102 }
103
104 /* emits 11dw + 1 surface sync = 16dw */
105 static void
106 set_shaders(struct radeon_device *rdev)
107 {
108 u64 gpu_addr;
109
110 /* VS */
111 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
112 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
113 radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
114 radeon_ring_write(rdev, gpu_addr >> 8);
115 radeon_ring_write(rdev, 2);
116 radeon_ring_write(rdev, 0);
117
118 /* PS */
119 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
120 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
121 radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
122 radeon_ring_write(rdev, gpu_addr >> 8);
123 radeon_ring_write(rdev, 1);
124 radeon_ring_write(rdev, 0);
125 radeon_ring_write(rdev, 2);
126
127 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
128 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
129 }
130
131 /* emits 10 + 1 sync (5) = 15 */
132 static void
133 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
134 {
135 u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
136
137 /* high addr, stride */
138 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
139 SQ_VTXC_STRIDE(16);
140 #ifdef __BIG_ENDIAN
141 sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
142 #endif
143 /* xyzw swizzles */
144 sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) |
145 SQ_VTCX_SEL_Y(SQ_SEL_Y) |
146 SQ_VTCX_SEL_Z(SQ_SEL_Z) |
147 SQ_VTCX_SEL_W(SQ_SEL_W);
148
149 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
150 radeon_ring_write(rdev, 0x580);
151 radeon_ring_write(rdev, gpu_addr & 0xffffffff);
152 radeon_ring_write(rdev, 48 - 1); /* size */
153 radeon_ring_write(rdev, sq_vtx_constant_word2);
154 radeon_ring_write(rdev, sq_vtx_constant_word3);
155 radeon_ring_write(rdev, 0);
156 radeon_ring_write(rdev, 0);
157 radeon_ring_write(rdev, 0);
158 radeon_ring_write(rdev, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
159
160 if ((rdev->family == CHIP_CEDAR) ||
161 (rdev->family == CHIP_PALM) ||
162 (rdev->family == CHIP_SUMO) ||
163 (rdev->family == CHIP_SUMO2) ||
164 (rdev->family == CHIP_CAICOS))
165 cp_set_surface_sync(rdev,
166 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
167 else
168 cp_set_surface_sync(rdev,
169 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
170
171 }
172
173 /* emits 10 */
174 static void
175 set_tex_resource(struct radeon_device *rdev,
176 int format, int w, int h, int pitch,
177 u64 gpu_addr, u32 size)
178 {
179 u32 sq_tex_resource_word0, sq_tex_resource_word1;
180 u32 sq_tex_resource_word4, sq_tex_resource_word7;
181
182 if (h < 1)
183 h = 1;
184
185 sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D);
186 sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
187 ((w - 1) << 18));
188 sq_tex_resource_word1 = ((h - 1) << 0) |
189 TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
190 /* xyzw swizzles */
191 sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) |
192 TEX_DST_SEL_Y(SQ_SEL_Y) |
193 TEX_DST_SEL_Z(SQ_SEL_Z) |
194 TEX_DST_SEL_W(SQ_SEL_W);
195
196 sq_tex_resource_word7 = format |
197 S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE);
198
199 cp_set_surface_sync(rdev,
200 PACKET3_TC_ACTION_ENA, size, gpu_addr);
201
202 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
203 radeon_ring_write(rdev, 0);
204 radeon_ring_write(rdev, sq_tex_resource_word0);
205 radeon_ring_write(rdev, sq_tex_resource_word1);
206 radeon_ring_write(rdev, gpu_addr >> 8);
207 radeon_ring_write(rdev, gpu_addr >> 8);
208 radeon_ring_write(rdev, sq_tex_resource_word4);
209 radeon_ring_write(rdev, 0);
210 radeon_ring_write(rdev, 0);
211 radeon_ring_write(rdev, sq_tex_resource_word7);
212 }
213
214 /* emits 12 */
215 static void
216 set_scissors(struct radeon_device *rdev, int x1, int y1,
217 int x2, int y2)
218 {
219 /* workaround some hw bugs */
220 if (x2 == 0)
221 x1 = 1;
222 if (y2 == 0)
223 y1 = 1;
224 if (rdev->family == CHIP_CAYMAN) {
225 if ((x2 == 1) && (y2 == 1))
226 x2 = 2;
227 }
228
229 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
230 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
231 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
232 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
233
234 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
235 radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
236 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
237 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
238
239 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
240 radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
241 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
242 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
243 }
244
245 /* emits 10 */
246 static void
247 draw_auto(struct radeon_device *rdev)
248 {
249 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
250 radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
251 radeon_ring_write(rdev, DI_PT_RECTLIST);
252
253 radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
254 radeon_ring_write(rdev,
255 #ifdef __BIG_ENDIAN
256 (2 << 2) |
257 #endif
258 DI_INDEX_SIZE_16_BIT);
259
260 radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
261 radeon_ring_write(rdev, 1);
262
263 radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
264 radeon_ring_write(rdev, 3);
265 radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
266
267 }
268
269 /* emits 39 */
270 static void
271 set_default_state(struct radeon_device *rdev)
272 {
273 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
274 u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
275 u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
276 int num_ps_gprs, num_vs_gprs, num_temp_gprs;
277 int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
278 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
279 int num_hs_threads, num_ls_threads;
280 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
281 int num_hs_stack_entries, num_ls_stack_entries;
282 u64 gpu_addr;
283 int dwords;
284
285 /* set clear context state */
286 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
287 radeon_ring_write(rdev, 0);
288
289 if (rdev->family < CHIP_CAYMAN) {
290 switch (rdev->family) {
291 case CHIP_CEDAR:
292 default:
293 num_ps_gprs = 93;
294 num_vs_gprs = 46;
295 num_temp_gprs = 4;
296 num_gs_gprs = 31;
297 num_es_gprs = 31;
298 num_hs_gprs = 23;
299 num_ls_gprs = 23;
300 num_ps_threads = 96;
301 num_vs_threads = 16;
302 num_gs_threads = 16;
303 num_es_threads = 16;
304 num_hs_threads = 16;
305 num_ls_threads = 16;
306 num_ps_stack_entries = 42;
307 num_vs_stack_entries = 42;
308 num_gs_stack_entries = 42;
309 num_es_stack_entries = 42;
310 num_hs_stack_entries = 42;
311 num_ls_stack_entries = 42;
312 break;
313 case CHIP_REDWOOD:
314 num_ps_gprs = 93;
315 num_vs_gprs = 46;
316 num_temp_gprs = 4;
317 num_gs_gprs = 31;
318 num_es_gprs = 31;
319 num_hs_gprs = 23;
320 num_ls_gprs = 23;
321 num_ps_threads = 128;
322 num_vs_threads = 20;
323 num_gs_threads = 20;
324 num_es_threads = 20;
325 num_hs_threads = 20;
326 num_ls_threads = 20;
327 num_ps_stack_entries = 42;
328 num_vs_stack_entries = 42;
329 num_gs_stack_entries = 42;
330 num_es_stack_entries = 42;
331 num_hs_stack_entries = 42;
332 num_ls_stack_entries = 42;
333 break;
334 case CHIP_JUNIPER:
335 num_ps_gprs = 93;
336 num_vs_gprs = 46;
337 num_temp_gprs = 4;
338 num_gs_gprs = 31;
339 num_es_gprs = 31;
340 num_hs_gprs = 23;
341 num_ls_gprs = 23;
342 num_ps_threads = 128;
343 num_vs_threads = 20;
344 num_gs_threads = 20;
345 num_es_threads = 20;
346 num_hs_threads = 20;
347 num_ls_threads = 20;
348 num_ps_stack_entries = 85;
349 num_vs_stack_entries = 85;
350 num_gs_stack_entries = 85;
351 num_es_stack_entries = 85;
352 num_hs_stack_entries = 85;
353 num_ls_stack_entries = 85;
354 break;
355 case CHIP_CYPRESS:
356 case CHIP_HEMLOCK:
357 num_ps_gprs = 93;
358 num_vs_gprs = 46;
359 num_temp_gprs = 4;
360 num_gs_gprs = 31;
361 num_es_gprs = 31;
362 num_hs_gprs = 23;
363 num_ls_gprs = 23;
364 num_ps_threads = 128;
365 num_vs_threads = 20;
366 num_gs_threads = 20;
367 num_es_threads = 20;
368 num_hs_threads = 20;
369 num_ls_threads = 20;
370 num_ps_stack_entries = 85;
371 num_vs_stack_entries = 85;
372 num_gs_stack_entries = 85;
373 num_es_stack_entries = 85;
374 num_hs_stack_entries = 85;
375 num_ls_stack_entries = 85;
376 break;
377 case CHIP_PALM:
378 num_ps_gprs = 93;
379 num_vs_gprs = 46;
380 num_temp_gprs = 4;
381 num_gs_gprs = 31;
382 num_es_gprs = 31;
383 num_hs_gprs = 23;
384 num_ls_gprs = 23;
385 num_ps_threads = 96;
386 num_vs_threads = 16;
387 num_gs_threads = 16;
388 num_es_threads = 16;
389 num_hs_threads = 16;
390 num_ls_threads = 16;
391 num_ps_stack_entries = 42;
392 num_vs_stack_entries = 42;
393 num_gs_stack_entries = 42;
394 num_es_stack_entries = 42;
395 num_hs_stack_entries = 42;
396 num_ls_stack_entries = 42;
397 break;
398 case CHIP_SUMO:
399 num_ps_gprs = 93;
400 num_vs_gprs = 46;
401 num_temp_gprs = 4;
402 num_gs_gprs = 31;
403 num_es_gprs = 31;
404 num_hs_gprs = 23;
405 num_ls_gprs = 23;
406 num_ps_threads = 96;
407 num_vs_threads = 25;
408 num_gs_threads = 25;
409 num_es_threads = 25;
410 num_hs_threads = 25;
411 num_ls_threads = 25;
412 num_ps_stack_entries = 42;
413 num_vs_stack_entries = 42;
414 num_gs_stack_entries = 42;
415 num_es_stack_entries = 42;
416 num_hs_stack_entries = 42;
417 num_ls_stack_entries = 42;
418 break;
419 case CHIP_SUMO2:
420 num_ps_gprs = 93;
421 num_vs_gprs = 46;
422 num_temp_gprs = 4;
423 num_gs_gprs = 31;
424 num_es_gprs = 31;
425 num_hs_gprs = 23;
426 num_ls_gprs = 23;
427 num_ps_threads = 96;
428 num_vs_threads = 25;
429 num_gs_threads = 25;
430 num_es_threads = 25;
431 num_hs_threads = 25;
432 num_ls_threads = 25;
433 num_ps_stack_entries = 85;
434 num_vs_stack_entries = 85;
435 num_gs_stack_entries = 85;
436 num_es_stack_entries = 85;
437 num_hs_stack_entries = 85;
438 num_ls_stack_entries = 85;
439 break;
440 case CHIP_BARTS:
441 num_ps_gprs = 93;
442 num_vs_gprs = 46;
443 num_temp_gprs = 4;
444 num_gs_gprs = 31;
445 num_es_gprs = 31;
446 num_hs_gprs = 23;
447 num_ls_gprs = 23;
448 num_ps_threads = 128;
449 num_vs_threads = 20;
450 num_gs_threads = 20;
451 num_es_threads = 20;
452 num_hs_threads = 20;
453 num_ls_threads = 20;
454 num_ps_stack_entries = 85;
455 num_vs_stack_entries = 85;
456 num_gs_stack_entries = 85;
457 num_es_stack_entries = 85;
458 num_hs_stack_entries = 85;
459 num_ls_stack_entries = 85;
460 break;
461 case CHIP_TURKS:
462 num_ps_gprs = 93;
463 num_vs_gprs = 46;
464 num_temp_gprs = 4;
465 num_gs_gprs = 31;
466 num_es_gprs = 31;
467 num_hs_gprs = 23;
468 num_ls_gprs = 23;
469 num_ps_threads = 128;
470 num_vs_threads = 20;
471 num_gs_threads = 20;
472 num_es_threads = 20;
473 num_hs_threads = 20;
474 num_ls_threads = 20;
475 num_ps_stack_entries = 42;
476 num_vs_stack_entries = 42;
477 num_gs_stack_entries = 42;
478 num_es_stack_entries = 42;
479 num_hs_stack_entries = 42;
480 num_ls_stack_entries = 42;
481 break;
482 case CHIP_CAICOS:
483 num_ps_gprs = 93;
484 num_vs_gprs = 46;
485 num_temp_gprs = 4;
486 num_gs_gprs = 31;
487 num_es_gprs = 31;
488 num_hs_gprs = 23;
489 num_ls_gprs = 23;
490 num_ps_threads = 128;
491 num_vs_threads = 10;
492 num_gs_threads = 10;
493 num_es_threads = 10;
494 num_hs_threads = 10;
495 num_ls_threads = 10;
496 num_ps_stack_entries = 42;
497 num_vs_stack_entries = 42;
498 num_gs_stack_entries = 42;
499 num_es_stack_entries = 42;
500 num_hs_stack_entries = 42;
501 num_ls_stack_entries = 42;
502 break;
503 }
504
505 if ((rdev->family == CHIP_CEDAR) ||
506 (rdev->family == CHIP_PALM) ||
507 (rdev->family == CHIP_SUMO) ||
508 (rdev->family == CHIP_SUMO2) ||
509 (rdev->family == CHIP_CAICOS))
510 sq_config = 0;
511 else
512 sq_config = VC_ENABLE;
513
514 sq_config |= (EXPORT_SRC_C |
515 CS_PRIO(0) |
516 LS_PRIO(0) |
517 HS_PRIO(0) |
518 PS_PRIO(0) |
519 VS_PRIO(1) |
520 GS_PRIO(2) |
521 ES_PRIO(3));
522
523 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
524 NUM_VS_GPRS(num_vs_gprs) |
525 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
526 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
527 NUM_ES_GPRS(num_es_gprs));
528 sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
529 NUM_LS_GPRS(num_ls_gprs));
530 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
531 NUM_VS_THREADS(num_vs_threads) |
532 NUM_GS_THREADS(num_gs_threads) |
533 NUM_ES_THREADS(num_es_threads));
534 sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
535 NUM_LS_THREADS(num_ls_threads));
536 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
537 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
538 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
539 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
540 sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
541 NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
542
543 /* disable dyn gprs */
544 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
545 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
546 radeon_ring_write(rdev, 0);
547
548 /* setup LDS */
549 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
550 radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
551 radeon_ring_write(rdev, 0x10001000);
552
553 /* SQ config */
554 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
555 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
556 radeon_ring_write(rdev, sq_config);
557 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
558 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
559 radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
560 radeon_ring_write(rdev, 0);
561 radeon_ring_write(rdev, 0);
562 radeon_ring_write(rdev, sq_thread_resource_mgmt);
563 radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
564 radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
565 radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
566 radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
567 }
568
569 /* CONTEXT_CONTROL */
570 radeon_ring_write(rdev, 0xc0012800);
571 radeon_ring_write(rdev, 0x80000000);
572 radeon_ring_write(rdev, 0x80000000);
573
574 /* SQ_VTX_BASE_VTX_LOC */
575 radeon_ring_write(rdev, 0xc0026f00);
576 radeon_ring_write(rdev, 0x00000000);
577 radeon_ring_write(rdev, 0x00000000);
578 radeon_ring_write(rdev, 0x00000000);
579
580 /* SET_SAMPLER */
581 radeon_ring_write(rdev, 0xc0036e00);
582 radeon_ring_write(rdev, 0x00000000);
583 radeon_ring_write(rdev, 0x00000012);
584 radeon_ring_write(rdev, 0x00000000);
585 radeon_ring_write(rdev, 0x00000000);
586
587 /* set to DX10/11 mode */
588 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
589 radeon_ring_write(rdev, 1);
590
591 /* emit an IB pointing at default state */
592 dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
593 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
594 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
595 radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
596 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
597 radeon_ring_write(rdev, dwords);
598
599 }
600
601 int evergreen_blit_init(struct radeon_device *rdev)
602 {
603 u32 obj_size;
604 int i, r, dwords;
605 void *ptr;
606 u32 packet2s[16];
607 int num_packet2s = 0;
608
609 rdev->r600_blit.primitives.set_render_target = set_render_target;
610 rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
611 rdev->r600_blit.primitives.set_shaders = set_shaders;
612 rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
613 rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
614 rdev->r600_blit.primitives.set_scissors = set_scissors;
615 rdev->r600_blit.primitives.draw_auto = draw_auto;
616 rdev->r600_blit.primitives.set_default_state = set_default_state;
617
618 rdev->r600_blit.ring_size_common = 55; /* shaders + def state */
619 rdev->r600_blit.ring_size_common += 10; /* fence emit for VB IB */
620 rdev->r600_blit.ring_size_common += 5; /* done copy */
621 rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */
622
623 rdev->r600_blit.ring_size_per_loop = 74;
624
625 rdev->r600_blit.max_dim = 16384;
626
627 /* pin copy shader into vram if already initialized */
628 if (rdev->r600_blit.shader_obj)
629 goto done;
630
631 mutex_init(&rdev->r600_blit.mutex);
632 rdev->r600_blit.state_offset = 0;
633
634 if (rdev->family < CHIP_CAYMAN)
635 rdev->r600_blit.state_len = evergreen_default_size;
636 else
637 rdev->r600_blit.state_len = cayman_default_size;
638
639 dwords = rdev->r600_blit.state_len;
640 while (dwords & 0xf) {
641 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
642 dwords++;
643 }
644
645 obj_size = dwords * 4;
646 obj_size = ALIGN(obj_size, 256);
647
648 rdev->r600_blit.vs_offset = obj_size;
649 if (rdev->family < CHIP_CAYMAN)
650 obj_size += evergreen_vs_size * 4;
651 else
652 obj_size += cayman_vs_size * 4;
653 obj_size = ALIGN(obj_size, 256);
654
655 rdev->r600_blit.ps_offset = obj_size;
656 if (rdev->family < CHIP_CAYMAN)
657 obj_size += evergreen_ps_size * 4;
658 else
659 obj_size += cayman_ps_size * 4;
660 obj_size = ALIGN(obj_size, 256);
661
662 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
663 &rdev->r600_blit.shader_obj);
664 if (r) {
665 DRM_ERROR("evergreen failed to allocate shader\n");
666 return r;
667 }
668
669 DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
670 obj_size,
671 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
672
673 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
674 if (unlikely(r != 0))
675 return r;
676 r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
677 if (r) {
678 DRM_ERROR("failed to map blit object %d\n", r);
679 return r;
680 }
681
682 if (rdev->family < CHIP_CAYMAN) {
683 memcpy_toio(ptr + rdev->r600_blit.state_offset,
684 evergreen_default_state, rdev->r600_blit.state_len * 4);
685
686 if (num_packet2s)
687 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
688 packet2s, num_packet2s * 4);
689 for (i = 0; i < evergreen_vs_size; i++)
690 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
691 for (i = 0; i < evergreen_ps_size; i++)
692 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
693 } else {
694 memcpy_toio(ptr + rdev->r600_blit.state_offset,
695 cayman_default_state, rdev->r600_blit.state_len * 4);
696
697 if (num_packet2s)
698 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
699 packet2s, num_packet2s * 4);
700 for (i = 0; i < cayman_vs_size; i++)
701 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]);
702 for (i = 0; i < cayman_ps_size; i++)
703 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]);
704 }
705 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
706 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
707
708 done:
709 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
710 if (unlikely(r != 0))
711 return r;
712 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
713 &rdev->r600_blit.shader_gpu_addr);
714 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
715 if (r) {
716 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
717 return r;
718 }
719 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
720 return 0;
721 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree