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drm/i915/overlay: Explicitly pass regs from map to unmap
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_overlay.c
blob88c2d1f8d05cc271bbe921c5dd97228f92e7c0a6
1 /*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
28
29 #include <linux/seq_file.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drm.h"
33 #include "i915_drv.h"
34 #include "i915_reg.h"
35 #include "intel_drv.h"
36
37 /* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41 #define IMAGE_MAX_WIDTH 2048
42 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43 /* on 830 and 845 these large limits result in the card hanging */
44 #define IMAGE_MAX_WIDTH_LEGACY 1024
45 #define IMAGE_MAX_HEIGHT_LEGACY 1088
46
47 /* overlay register definitions */
48 /* OCMD register */
49 #define OCMD_TILED_SURFACE (0x1<<19)
50 #define OCMD_MIRROR_MASK (0x3<<17)
51 #define OCMD_MIRROR_MODE (0x3<<17)
52 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53 #define OCMD_MIRROR_VERTICAL (0x2<<17)
54 #define OCMD_MIRROR_BOTH (0x3<<17)
55 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_422_PACKED (0x8<<10)
64 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65 #define OCMD_YUV_420_PLANAR (0xc<<10)
66 #define OCMD_YUV_422_PLANAR (0xd<<10)
67 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
70 #define OCMD_BUF_TYPE_MASK (0x1<<5)
71 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
72 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
73 #define OCMD_TEST_MODE (0x1<<4)
74 #define OCMD_BUFFER_SELECT (0x3<<2)
75 #define OCMD_BUFFER0 (0x0<<2)
76 #define OCMD_BUFFER1 (0x1<<2)
77 #define OCMD_FIELD_SELECT (0x1<<2)
78 #define OCMD_FIELD0 (0x0<<1)
79 #define OCMD_FIELD1 (0x1<<1)
80 #define OCMD_ENABLE (0x1<<0)
81
82 /* OCONFIG register */
83 #define OCONF_PIPE_MASK (0x1<<18)
84 #define OCONF_PIPE_A (0x0<<18)
85 #define OCONF_PIPE_B (0x1<<18)
86 #define OCONF_GAMMA2_ENABLE (0x1<<16)
87 #define OCONF_CSC_MODE_BT601 (0x0<<5)
88 #define OCONF_CSC_MODE_BT709 (0x1<<5)
89 #define OCONF_CSC_BYPASS (0x1<<4)
90 #define OCONF_CC_OUT_8BIT (0x1<<3)
91 #define OCONF_TEST_MODE (0x1<<2)
92 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
93 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
94
95 /* DCLRKM (dst-key) register */
96 #define DST_KEY_ENABLE (0x1<<31)
97 #define CLK_RGB24_MASK 0x0
98 #define CLK_RGB16_MASK 0x070307
99 #define CLK_RGB15_MASK 0x070707
100 #define CLK_RGB8I_MASK 0xffffff
101
102 #define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104 #define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
106
107 /* overlay flip addr flag */
108 #define OFC_UPDATE 0x1
109
110 /* polyphase filter coefficients */
111 #define N_HORIZ_Y_TAPS 5
112 #define N_VERT_Y_TAPS 3
113 #define N_HORIZ_UV_TAPS 3
114 #define N_VERT_UV_TAPS 3
115 #define N_PHASES 17
116 #define MAX_TAPS 5
117
118 /* memory bufferd overlay registers */
119 struct overlay_registers {
120 u32 OBUF_0Y;
121 u32 OBUF_1Y;
122 u32 OBUF_0U;
123 u32 OBUF_0V;
124 u32 OBUF_1U;
125 u32 OBUF_1V;
126 u32 OSTRIDE;
127 u32 YRGB_VPH;
128 u32 UV_VPH;
129 u32 HORZ_PH;
130 u32 INIT_PHS;
131 u32 DWINPOS;
132 u32 DWINSZ;
133 u32 SWIDTH;
134 u32 SWIDTHSW;
135 u32 SHEIGHT;
136 u32 YRGBSCALE;
137 u32 UVSCALE;
138 u32 OCLRC0;
139 u32 OCLRC1;
140 u32 DCLRKV;
141 u32 DCLRKM;
142 u32 SCLRKVH;
143 u32 SCLRKVL;
144 u32 SCLRKEN;
145 u32 OCONFIG;
146 u32 OCMD;
147 u32 RESERVED1; /* 0x6C */
148 u32 OSTART_0Y;
149 u32 OSTART_1Y;
150 u32 OSTART_0U;
151 u32 OSTART_0V;
152 u32 OSTART_1U;
153 u32 OSTART_1V;
154 u32 OTILEOFF_0Y;
155 u32 OTILEOFF_1Y;
156 u32 OTILEOFF_0U;
157 u32 OTILEOFF_0V;
158 u32 OTILEOFF_1U;
159 u32 OTILEOFF_1V;
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171 };
172
173 static struct overlay_registers *
174 intel_overlay_map_regs_atomic(struct intel_overlay *overlay,
175 int slot)
176 {
177 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
178 struct overlay_registers *regs;
179
180 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
181 regs = overlay->reg_bo->phys_obj->handle->vaddr;
182 else
183 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
184 overlay->reg_bo->gtt_offset,
185 slot);
186
187 return regs;
188 }
189
190 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
191 int slot,
192 struct overlay_registers *regs)
193 {
194 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
195 io_mapping_unmap_atomic(regs, slot);
196 }
197
198 static struct overlay_registers *
199 intel_overlay_map_regs(struct intel_overlay *overlay)
200 {
201 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
202 struct overlay_registers *regs;
203
204 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
205 regs = overlay->reg_bo->phys_obj->handle->vaddr;
206 else
207 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
208 overlay->reg_bo->gtt_offset);
209
210 return regs;
211 }
212
213 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
214 struct overlay_registers *regs)
215 {
216 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
217 io_mapping_unmap(regs);
218 }
219
220 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
221 bool interruptible,
222 int stage)
223 {
224 struct drm_device *dev = overlay->dev;
225 drm_i915_private_t *dev_priv = dev->dev_private;
226 int ret;
227
228 overlay->last_flip_req =
229 i915_add_request(dev, NULL, &dev_priv->render_ring);
230 if (overlay->last_flip_req == 0)
231 return -ENOMEM;
232
233 overlay->hw_wedged = stage;
234 ret = i915_do_wait_request(dev,
235 overlay->last_flip_req, true,
236 &dev_priv->render_ring);
237 if (ret)
238 return ret;
239
240 overlay->hw_wedged = 0;
241 overlay->last_flip_req = 0;
242 return 0;
243 }
244
245 /* overlay needs to be disable in OCMD reg */
246 static int intel_overlay_on(struct intel_overlay *overlay)
247 {
248 struct drm_device *dev = overlay->dev;
249
250 BUG_ON(overlay->active);
251
252 overlay->active = 1;
253
254 BEGIN_LP_RING(4);
255 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
256 OUT_RING(overlay->flip_addr | OFC_UPDATE);
257 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
258 OUT_RING(MI_NOOP);
259 ADVANCE_LP_RING();
260
261 return intel_overlay_do_wait_request(overlay, true,
262 NEEDS_WAIT_FOR_FLIP);
263 }
264
265 /* overlay needs to be enabled in OCMD reg */
266 static void intel_overlay_continue(struct intel_overlay *overlay,
267 bool load_polyphase_filter)
268 {
269 struct drm_device *dev = overlay->dev;
270 drm_i915_private_t *dev_priv = dev->dev_private;
271 u32 flip_addr = overlay->flip_addr;
272 u32 tmp;
273
274 BUG_ON(!overlay->active);
275
276 if (load_polyphase_filter)
277 flip_addr |= OFC_UPDATE;
278
279 /* check for underruns */
280 tmp = I915_READ(DOVSTA);
281 if (tmp & (1 << 17))
282 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
283
284 BEGIN_LP_RING(2);
285 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
286 OUT_RING(flip_addr);
287 ADVANCE_LP_RING();
288
289 overlay->last_flip_req =
290 i915_add_request(dev, NULL, &dev_priv->render_ring);
291 }
292
293 static int intel_overlay_wait_flip(struct intel_overlay *overlay)
294 {
295 struct drm_device *dev = overlay->dev;
296 drm_i915_private_t *dev_priv = dev->dev_private;
297 int ret;
298 u32 tmp;
299
300 if (overlay->last_flip_req != 0) {
301 ret = i915_do_wait_request(dev,
302 overlay->last_flip_req, true,
303 &dev_priv->render_ring);
304 if (ret == 0) {
305 overlay->last_flip_req = 0;
306
307 tmp = I915_READ(ISR);
308
309 if (!(tmp & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT))
310 return 0;
311 }
312 }
313
314 /* synchronous slowpath */
315 BEGIN_LP_RING(2);
316 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
317 OUT_RING(MI_NOOP);
318 ADVANCE_LP_RING();
319
320 return intel_overlay_do_wait_request(overlay, true, RELEASE_OLD_VID);
321 }
322
323 /* overlay needs to be disabled in OCMD reg */
324 static int intel_overlay_off(struct intel_overlay *overlay)
325 {
326 u32 flip_addr = overlay->flip_addr;
327 struct drm_device *dev = overlay->dev;
328 int ret;
329
330 BUG_ON(!overlay->active);
331
332 /* According to intel docs the overlay hw may hang (when switching
333 * off) without loading the filter coeffs. It is however unclear whether
334 * this applies to the disabling of the overlay or to the switching off
335 * of the hw. Do it in both cases */
336 flip_addr |= OFC_UPDATE;
337
338 /* wait for overlay to go idle */
339 BEGIN_LP_RING(4);
340 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
341 OUT_RING(flip_addr);
342 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
343 OUT_RING(MI_NOOP);
344 ADVANCE_LP_RING();
345
346 ret = intel_overlay_do_wait_request(overlay, true,
347 SWITCH_OFF_STAGE_1);
348 if (ret)
349 return ret;
350
351 /* turn overlay off */
352 BEGIN_LP_RING(4);
353 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
354 OUT_RING(flip_addr);
355 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
356 OUT_RING(MI_NOOP);
357 ADVANCE_LP_RING();
358
359 return intel_overlay_do_wait_request(overlay, true,
360 SWITCH_OFF_STAGE_2);
361 }
362
363 static void intel_overlay_off_tail(struct intel_overlay *overlay)
364 {
365 struct drm_gem_object *obj;
366
367 /* never have the overlay hw on without showing a frame */
368 BUG_ON(!overlay->vid_bo);
369 obj = &overlay->vid_bo->base;
370
371 i915_gem_object_unpin(obj);
372 drm_gem_object_unreference(obj);
373 overlay->vid_bo = NULL;
374
375 overlay->crtc->overlay = NULL;
376 overlay->crtc = NULL;
377 overlay->active = 0;
378 }
379
380 /* recover from an interruption due to a signal
381 * We have to be careful not to repeat work forever an make forward progess. */
382 int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
383 bool interruptible)
384 {
385 struct drm_device *dev = overlay->dev;
386 struct drm_gem_object *obj;
387 drm_i915_private_t *dev_priv = dev->dev_private;
388 u32 flip_addr;
389 int ret;
390
391 if (overlay->hw_wedged == HW_WEDGED)
392 return -EIO;
393
394 ret = i915_do_wait_request(dev, overlay->last_flip_req,
395 interruptible, &dev_priv->render_ring);
396 if (ret)
397 return ret;
398
399 switch (overlay->hw_wedged) {
400 case RELEASE_OLD_VID:
401 obj = &overlay->old_vid_bo->base;
402 i915_gem_object_unpin(obj);
403 drm_gem_object_unreference(obj);
404 overlay->old_vid_bo = NULL;
405 break;
406
407 case SWITCH_OFF_STAGE_1:
408 flip_addr = overlay->flip_addr;
409 flip_addr |= OFC_UPDATE;
410
411 BEGIN_LP_RING(4);
412 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
413 OUT_RING(flip_addr);
414 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
415 OUT_RING(MI_NOOP);
416 ADVANCE_LP_RING();
417
418 ret = intel_overlay_do_wait_request(overlay, interruptible,
419 SWITCH_OFF_STAGE_2);
420 if (ret)
421 return ret;
422
423 case SWITCH_OFF_STAGE_2:
424 intel_overlay_off_tail(overlay);
425 break;
426 default:
427 BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
428 }
429
430 overlay->hw_wedged = 0;
431 overlay->last_flip_req = 0;
432 return 0;
433 }
434
435 /* Wait for pending overlay flip and release old frame.
436 * Needs to be called before the overlay register are changed
437 * via intel_overlay_(un)map_regs
438 */
439 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
440 {
441 int ret;
442 struct drm_gem_object *obj;
443
444 /* only wait if there is actually an old frame to release to
445 * guarantee forward progress */
446 if (!overlay->old_vid_bo)
447 return 0;
448
449 ret = intel_overlay_wait_flip(overlay);
450 if (ret != 0)
451 return ret;
452
453 obj = &overlay->old_vid_bo->base;
454 i915_gem_object_unpin(obj);
455 drm_gem_object_unreference(obj);
456 overlay->old_vid_bo = NULL;
457
458 return 0;
459 }
460
461 struct put_image_params {
462 int format;
463 short dst_x;
464 short dst_y;
465 short dst_w;
466 short dst_h;
467 short src_w;
468 short src_scan_h;
469 short src_scan_w;
470 short src_h;
471 short stride_Y;
472 short stride_UV;
473 int offset_Y;
474 int offset_U;
475 int offset_V;
476 };
477
478 static int packed_depth_bytes(u32 format)
479 {
480 switch (format & I915_OVERLAY_DEPTH_MASK) {
481 case I915_OVERLAY_YUV422:
482 return 4;
483 case I915_OVERLAY_YUV411:
484 /* return 6; not implemented */
485 default:
486 return -EINVAL;
487 }
488 }
489
490 static int packed_width_bytes(u32 format, short width)
491 {
492 switch (format & I915_OVERLAY_DEPTH_MASK) {
493 case I915_OVERLAY_YUV422:
494 return width << 1;
495 default:
496 return -EINVAL;
497 }
498 }
499
500 static int uv_hsubsampling(u32 format)
501 {
502 switch (format & I915_OVERLAY_DEPTH_MASK) {
503 case I915_OVERLAY_YUV422:
504 case I915_OVERLAY_YUV420:
505 return 2;
506 case I915_OVERLAY_YUV411:
507 case I915_OVERLAY_YUV410:
508 return 4;
509 default:
510 return -EINVAL;
511 }
512 }
513
514 static int uv_vsubsampling(u32 format)
515 {
516 switch (format & I915_OVERLAY_DEPTH_MASK) {
517 case I915_OVERLAY_YUV420:
518 case I915_OVERLAY_YUV410:
519 return 2;
520 case I915_OVERLAY_YUV422:
521 case I915_OVERLAY_YUV411:
522 return 1;
523 default:
524 return -EINVAL;
525 }
526 }
527
528 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
529 {
530 u32 mask, shift, ret;
531 if (IS_I9XX(dev)) {
532 mask = 0x3f;
533 shift = 6;
534 } else {
535 mask = 0x1f;
536 shift = 5;
537 }
538 ret = ((offset + width + mask) >> shift) - (offset >> shift);
539 if (IS_I9XX(dev))
540 ret <<= 1;
541 ret -=1;
542 return ret << 2;
543 }
544
545 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
546 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
547 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
548 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
549 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
550 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
551 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
552 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
553 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
554 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
555 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
556 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
557 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
558 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
559 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
560 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
561 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
562 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
563 };
564
565 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
566 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
567 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
568 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
569 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
570 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
571 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
572 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
573 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
574 0x3000, 0x0800, 0x3000
575 };
576
577 static void update_polyphase_filter(struct overlay_registers *regs)
578 {
579 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
580 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
581 }
582
583 static bool update_scaling_factors(struct intel_overlay *overlay,
584 struct overlay_registers *regs,
585 struct put_image_params *params)
586 {
587 /* fixed point with a 12 bit shift */
588 u32 xscale, yscale, xscale_UV, yscale_UV;
589 #define FP_SHIFT 12
590 #define FRACT_MASK 0xfff
591 bool scale_changed = false;
592 int uv_hscale = uv_hsubsampling(params->format);
593 int uv_vscale = uv_vsubsampling(params->format);
594
595 if (params->dst_w > 1)
596 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
597 /(params->dst_w);
598 else
599 xscale = 1 << FP_SHIFT;
600
601 if (params->dst_h > 1)
602 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
603 /(params->dst_h);
604 else
605 yscale = 1 << FP_SHIFT;
606
607 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
608 xscale_UV = xscale/uv_hscale;
609 yscale_UV = yscale/uv_vscale;
610 /* make the Y scale to UV scale ratio an exact multiply */
611 xscale = xscale_UV * uv_hscale;
612 yscale = yscale_UV * uv_vscale;
613 /*} else {
614 xscale_UV = 0;
615 yscale_UV = 0;
616 }*/
617
618 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
619 scale_changed = true;
620 overlay->old_xscale = xscale;
621 overlay->old_yscale = yscale;
622
623 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
624 ((xscale >> FP_SHIFT) << 16) |
625 ((xscale & FRACT_MASK) << 3));
626
627 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
628 ((xscale_UV >> FP_SHIFT) << 16) |
629 ((xscale_UV & FRACT_MASK) << 3));
630
631 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
632 ((yscale_UV >> FP_SHIFT) << 0)));
633
634 if (scale_changed)
635 update_polyphase_filter(regs);
636
637 return scale_changed;
638 }
639
640 static void update_colorkey(struct intel_overlay *overlay,
641 struct overlay_registers *regs)
642 {
643 u32 key = overlay->color_key;
644
645 switch (overlay->crtc->base.fb->bits_per_pixel) {
646 case 8:
647 regs->DCLRKV = 0;
648 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
649 break;
650
651 case 16:
652 if (overlay->crtc->base.fb->depth == 15) {
653 regs->DCLRKV = RGB15_TO_COLORKEY(key);
654 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
655 } else {
656 regs->DCLRKV = RGB16_TO_COLORKEY(key);
657 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
658 }
659 break;
660
661 case 24:
662 case 32:
663 regs->DCLRKV = key;
664 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
665 break;
666 }
667 }
668
669 static u32 overlay_cmd_reg(struct put_image_params *params)
670 {
671 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
672
673 if (params->format & I915_OVERLAY_YUV_PLANAR) {
674 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
675 case I915_OVERLAY_YUV422:
676 cmd |= OCMD_YUV_422_PLANAR;
677 break;
678 case I915_OVERLAY_YUV420:
679 cmd |= OCMD_YUV_420_PLANAR;
680 break;
681 case I915_OVERLAY_YUV411:
682 case I915_OVERLAY_YUV410:
683 cmd |= OCMD_YUV_410_PLANAR;
684 break;
685 }
686 } else { /* YUV packed */
687 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
688 case I915_OVERLAY_YUV422:
689 cmd |= OCMD_YUV_422_PACKED;
690 break;
691 case I915_OVERLAY_YUV411:
692 cmd |= OCMD_YUV_411_PACKED;
693 break;
694 }
695
696 switch (params->format & I915_OVERLAY_SWAP_MASK) {
697 case I915_OVERLAY_NO_SWAP:
698 break;
699 case I915_OVERLAY_UV_SWAP:
700 cmd |= OCMD_UV_SWAP;
701 break;
702 case I915_OVERLAY_Y_SWAP:
703 cmd |= OCMD_Y_SWAP;
704 break;
705 case I915_OVERLAY_Y_AND_UV_SWAP:
706 cmd |= OCMD_Y_AND_UV_SWAP;
707 break;
708 }
709 }
710
711 return cmd;
712 }
713
714 int intel_overlay_do_put_image(struct intel_overlay *overlay,
715 struct drm_gem_object *new_bo,
716 struct put_image_params *params)
717 {
718 int ret, tmp_width;
719 struct overlay_registers *regs;
720 bool scale_changed = false;
721 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
722 struct drm_device *dev = overlay->dev;
723
724 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
725 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
726 BUG_ON(!overlay);
727
728 ret = intel_overlay_release_old_vid(overlay);
729 if (ret != 0)
730 return ret;
731
732 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
733 if (ret != 0)
734 return ret;
735
736 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
737 if (ret != 0)
738 goto out_unpin;
739
740 if (!overlay->active) {
741 regs = intel_overlay_map_regs(overlay);
742 if (!regs) {
743 ret = -ENOMEM;
744 goto out_unpin;
745 }
746 regs->OCONFIG = OCONF_CC_OUT_8BIT;
747 if (IS_I965GM(overlay->dev))
748 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
749 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
750 OCONF_PIPE_A : OCONF_PIPE_B;
751 intel_overlay_unmap_regs(overlay, regs);
752
753 ret = intel_overlay_on(overlay);
754 if (ret != 0)
755 goto out_unpin;
756 }
757
758 regs = intel_overlay_map_regs(overlay);
759 if (!regs) {
760 ret = -ENOMEM;
761 goto out_unpin;
762 }
763
764 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
765 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
766
767 if (params->format & I915_OVERLAY_YUV_PACKED)
768 tmp_width = packed_width_bytes(params->format, params->src_w);
769 else
770 tmp_width = params->src_w;
771
772 regs->SWIDTH = params->src_w;
773 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
774 params->offset_Y, tmp_width);
775 regs->SHEIGHT = params->src_h;
776 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
777 regs->OSTRIDE = params->stride_Y;
778
779 if (params->format & I915_OVERLAY_YUV_PLANAR) {
780 int uv_hscale = uv_hsubsampling(params->format);
781 int uv_vscale = uv_vsubsampling(params->format);
782 u32 tmp_U, tmp_V;
783 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
784 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
785 params->src_w/uv_hscale);
786 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
787 params->src_w/uv_hscale);
788 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
789 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
790 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
791 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
792 regs->OSTRIDE |= params->stride_UV << 16;
793 }
794
795 scale_changed = update_scaling_factors(overlay, regs, params);
796
797 update_colorkey(overlay, regs);
798
799 regs->OCMD = overlay_cmd_reg(params);
800
801 intel_overlay_unmap_regs(overlay, regs);
802
803 intel_overlay_continue(overlay, scale_changed);
804
805 overlay->old_vid_bo = overlay->vid_bo;
806 overlay->vid_bo = to_intel_bo(new_bo);
807
808 return 0;
809
810 out_unpin:
811 i915_gem_object_unpin(new_bo);
812 return ret;
813 }
814
815 int intel_overlay_switch_off(struct intel_overlay *overlay)
816 {
817 int ret;
818 struct overlay_registers *regs;
819 struct drm_device *dev = overlay->dev;
820
821 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
822 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
823
824 if (overlay->hw_wedged) {
825 ret = intel_overlay_recover_from_interrupt(overlay, 1);
826 if (ret != 0)
827 return ret;
828 }
829
830 if (!overlay->active)
831 return 0;
832
833 ret = intel_overlay_release_old_vid(overlay);
834 if (ret != 0)
835 return ret;
836
837 regs = intel_overlay_map_regs(overlay);
838 regs->OCMD = 0;
839 intel_overlay_unmap_regs(overlay, regs);
840
841 ret = intel_overlay_off(overlay);
842 if (ret != 0)
843 return ret;
844
845 intel_overlay_off_tail(overlay);
846
847 return 0;
848 }
849
850 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
851 struct intel_crtc *crtc)
852 {
853 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
854 u32 pipeconf;
855 int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
856
857 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
858 return -EINVAL;
859
860 pipeconf = I915_READ(pipeconf_reg);
861
862 /* can't use the overlay with double wide pipe */
863 if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
864 return -EINVAL;
865
866 return 0;
867 }
868
869 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
870 {
871 struct drm_device *dev = overlay->dev;
872 drm_i915_private_t *dev_priv = dev->dev_private;
873 u32 pfit_control = I915_READ(PFIT_CONTROL);
874 u32 ratio;
875
876 /* XXX: This is not the same logic as in the xorg driver, but more in
877 * line with the intel documentation for the i965
878 */
879 if (!IS_I965G(dev)) {
880 if (pfit_control & VERT_AUTO_SCALE)
881 ratio = I915_READ(PFIT_AUTO_RATIOS);
882 else
883 ratio = I915_READ(PFIT_PGM_RATIOS);
884 ratio >>= PFIT_VERT_SCALE_SHIFT;
885 } else { /* on i965 use the PGM reg to read out the autoscaler values */
886 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
887 }
888
889 overlay->pfit_vscale_ratio = ratio;
890 }
891
892 static int check_overlay_dst(struct intel_overlay *overlay,
893 struct drm_intel_overlay_put_image *rec)
894 {
895 struct drm_display_mode *mode = &overlay->crtc->base.mode;
896
897 if (rec->dst_x < mode->crtc_hdisplay &&
898 rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
899 rec->dst_y < mode->crtc_vdisplay &&
900 rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
901 return 0;
902 else
903 return -EINVAL;
904 }
905
906 static int check_overlay_scaling(struct put_image_params *rec)
907 {
908 u32 tmp;
909
910 /* downscaling limit is 8.0 */
911 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
912 if (tmp > 7)
913 return -EINVAL;
914 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
915 if (tmp > 7)
916 return -EINVAL;
917
918 return 0;
919 }
920
921 static int check_overlay_src(struct drm_device *dev,
922 struct drm_intel_overlay_put_image *rec,
923 struct drm_gem_object *new_bo)
924 {
925 int uv_hscale = uv_hsubsampling(rec->flags);
926 int uv_vscale = uv_vsubsampling(rec->flags);
927 u32 stride_mask, depth, tmp;
928
929 /* check src dimensions */
930 if (IS_845G(dev) || IS_I830(dev)) {
931 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
932 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
933 return -EINVAL;
934 } else {
935 if (rec->src_height > IMAGE_MAX_HEIGHT ||
936 rec->src_width > IMAGE_MAX_WIDTH)
937 return -EINVAL;
938 }
939
940 /* better safe than sorry, use 4 as the maximal subsampling ratio */
941 if (rec->src_height < N_VERT_Y_TAPS*4 ||
942 rec->src_width < N_HORIZ_Y_TAPS*4)
943 return -EINVAL;
944
945 /* check alignment constraints */
946 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
947 case I915_OVERLAY_RGB:
948 /* not implemented */
949 return -EINVAL;
950
951 case I915_OVERLAY_YUV_PACKED:
952 if (uv_vscale != 1)
953 return -EINVAL;
954
955 depth = packed_depth_bytes(rec->flags);
956 if (depth < 0)
957 return depth;
958
959 /* ignore UV planes */
960 rec->stride_UV = 0;
961 rec->offset_U = 0;
962 rec->offset_V = 0;
963 /* check pixel alignment */
964 if (rec->offset_Y % depth)
965 return -EINVAL;
966 break;
967
968 case I915_OVERLAY_YUV_PLANAR:
969 if (uv_vscale < 0 || uv_hscale < 0)
970 return -EINVAL;
971 /* no offset restrictions for planar formats */
972 break;
973
974 default:
975 return -EINVAL;
976 }
977
978 if (rec->src_width % uv_hscale)
979 return -EINVAL;
980
981 /* stride checking */
982 if (IS_I830(dev) || IS_845G(dev))
983 stride_mask = 255;
984 else
985 stride_mask = 63;
986
987 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
988 return -EINVAL;
989 if (IS_I965G(dev) && rec->stride_Y < 512)
990 return -EINVAL;
991
992 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
993 4096 : 8192;
994 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
995 return -EINVAL;
996
997 /* check buffer dimensions */
998 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
999 case I915_OVERLAY_RGB:
1000 case I915_OVERLAY_YUV_PACKED:
1001 /* always 4 Y values per depth pixels */
1002 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1003 return -EINVAL;
1004
1005 tmp = rec->stride_Y*rec->src_height;
1006 if (rec->offset_Y + tmp > new_bo->size)
1007 return -EINVAL;
1008 break;
1009
1010 case I915_OVERLAY_YUV_PLANAR:
1011 if (rec->src_width > rec->stride_Y)
1012 return -EINVAL;
1013 if (rec->src_width/uv_hscale > rec->stride_UV)
1014 return -EINVAL;
1015
1016 tmp = rec->stride_Y * rec->src_height;
1017 if (rec->offset_Y + tmp > new_bo->size)
1018 return -EINVAL;
1019
1020 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1021 if (rec->offset_U + tmp > new_bo->size ||
1022 rec->offset_V + tmp > new_bo->size)
1023 return -EINVAL;
1024 break;
1025 }
1026
1027 return 0;
1028 }
1029
1030 int intel_overlay_put_image(struct drm_device *dev, void *data,
1031 struct drm_file *file_priv)
1032 {
1033 struct drm_intel_overlay_put_image *put_image_rec = data;
1034 drm_i915_private_t *dev_priv = dev->dev_private;
1035 struct intel_overlay *overlay;
1036 struct drm_mode_object *drmmode_obj;
1037 struct intel_crtc *crtc;
1038 struct drm_gem_object *new_bo;
1039 struct put_image_params *params;
1040 int ret;
1041
1042 if (!dev_priv) {
1043 DRM_ERROR("called with no initialization\n");
1044 return -EINVAL;
1045 }
1046
1047 overlay = dev_priv->overlay;
1048 if (!overlay) {
1049 DRM_DEBUG("userspace bug: no overlay\n");
1050 return -ENODEV;
1051 }
1052
1053 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1054 mutex_lock(&dev->mode_config.mutex);
1055 mutex_lock(&dev->struct_mutex);
1056
1057 ret = intel_overlay_switch_off(overlay);
1058
1059 mutex_unlock(&dev->struct_mutex);
1060 mutex_unlock(&dev->mode_config.mutex);
1061
1062 return ret;
1063 }
1064
1065 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1066 if (!params)
1067 return -ENOMEM;
1068
1069 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1070 DRM_MODE_OBJECT_CRTC);
1071 if (!drmmode_obj) {
1072 ret = -ENOENT;
1073 goto out_free;
1074 }
1075 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1076
1077 new_bo = drm_gem_object_lookup(dev, file_priv,
1078 put_image_rec->bo_handle);
1079 if (!new_bo) {
1080 ret = -ENOENT;
1081 goto out_free;
1082 }
1083
1084 mutex_lock(&dev->mode_config.mutex);
1085 mutex_lock(&dev->struct_mutex);
1086
1087 if (overlay->hw_wedged) {
1088 ret = intel_overlay_recover_from_interrupt(overlay, 1);
1089 if (ret != 0)
1090 goto out_unlock;
1091 }
1092
1093 if (overlay->crtc != crtc) {
1094 struct drm_display_mode *mode = &crtc->base.mode;
1095 ret = intel_overlay_switch_off(overlay);
1096 if (ret != 0)
1097 goto out_unlock;
1098
1099 ret = check_overlay_possible_on_crtc(overlay, crtc);
1100 if (ret != 0)
1101 goto out_unlock;
1102
1103 overlay->crtc = crtc;
1104 crtc->overlay = overlay;
1105
1106 if (intel_panel_fitter_pipe(dev) == crtc->pipe
1107 /* and line to wide, i.e. one-line-mode */
1108 && mode->hdisplay > 1024) {
1109 overlay->pfit_active = 1;
1110 update_pfit_vscale_ratio(overlay);
1111 } else
1112 overlay->pfit_active = 0;
1113 }
1114
1115 ret = check_overlay_dst(overlay, put_image_rec);
1116 if (ret != 0)
1117 goto out_unlock;
1118
1119 if (overlay->pfit_active) {
1120 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1121 overlay->pfit_vscale_ratio);
1122 /* shifting right rounds downwards, so add 1 */
1123 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1124 overlay->pfit_vscale_ratio) + 1;
1125 } else {
1126 params->dst_y = put_image_rec->dst_y;
1127 params->dst_h = put_image_rec->dst_height;
1128 }
1129 params->dst_x = put_image_rec->dst_x;
1130 params->dst_w = put_image_rec->dst_width;
1131
1132 params->src_w = put_image_rec->src_width;
1133 params->src_h = put_image_rec->src_height;
1134 params->src_scan_w = put_image_rec->src_scan_width;
1135 params->src_scan_h = put_image_rec->src_scan_height;
1136 if (params->src_scan_h > params->src_h ||
1137 params->src_scan_w > params->src_w) {
1138 ret = -EINVAL;
1139 goto out_unlock;
1140 }
1141
1142 ret = check_overlay_src(dev, put_image_rec, new_bo);
1143 if (ret != 0)
1144 goto out_unlock;
1145 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1146 params->stride_Y = put_image_rec->stride_Y;
1147 params->stride_UV = put_image_rec->stride_UV;
1148 params->offset_Y = put_image_rec->offset_Y;
1149 params->offset_U = put_image_rec->offset_U;
1150 params->offset_V = put_image_rec->offset_V;
1151
1152 /* Check scaling after src size to prevent a divide-by-zero. */
1153 ret = check_overlay_scaling(params);
1154 if (ret != 0)
1155 goto out_unlock;
1156
1157 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1158 if (ret != 0)
1159 goto out_unlock;
1160
1161 mutex_unlock(&dev->struct_mutex);
1162 mutex_unlock(&dev->mode_config.mutex);
1163
1164 kfree(params);
1165
1166 return 0;
1167
1168 out_unlock:
1169 mutex_unlock(&dev->struct_mutex);
1170 mutex_unlock(&dev->mode_config.mutex);
1171 drm_gem_object_unreference_unlocked(new_bo);
1172 out_free:
1173 kfree(params);
1174
1175 return ret;
1176 }
1177
1178 static void update_reg_attrs(struct intel_overlay *overlay,
1179 struct overlay_registers *regs)
1180 {
1181 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1182 regs->OCLRC1 = overlay->saturation;
1183 }
1184
1185 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1186 {
1187 int i;
1188
1189 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1190 return false;
1191
1192 for (i = 0; i < 3; i++) {
1193 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1194 return false;
1195 }
1196
1197 return true;
1198 }
1199
1200 static bool check_gamma5_errata(u32 gamma5)
1201 {
1202 int i;
1203
1204 for (i = 0; i < 3; i++) {
1205 if (((gamma5 >> i*8) & 0xff) == 0x80)
1206 return false;
1207 }
1208
1209 return true;
1210 }
1211
1212 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1213 {
1214 if (!check_gamma_bounds(0, attrs->gamma0) ||
1215 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1216 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1217 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1218 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1219 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1220 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1221 return -EINVAL;
1222
1223 if (!check_gamma5_errata(attrs->gamma5))
1224 return -EINVAL;
1225
1226 return 0;
1227 }
1228
1229 int intel_overlay_attrs(struct drm_device *dev, void *data,
1230 struct drm_file *file_priv)
1231 {
1232 struct drm_intel_overlay_attrs *attrs = data;
1233 drm_i915_private_t *dev_priv = dev->dev_private;
1234 struct intel_overlay *overlay;
1235 struct overlay_registers *regs;
1236 int ret;
1237
1238 if (!dev_priv) {
1239 DRM_ERROR("called with no initialization\n");
1240 return -EINVAL;
1241 }
1242
1243 overlay = dev_priv->overlay;
1244 if (!overlay) {
1245 DRM_DEBUG("userspace bug: no overlay\n");
1246 return -ENODEV;
1247 }
1248
1249 mutex_lock(&dev->mode_config.mutex);
1250 mutex_lock(&dev->struct_mutex);
1251
1252 ret = -EINVAL;
1253 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1254 attrs->color_key = overlay->color_key;
1255 attrs->brightness = overlay->brightness;
1256 attrs->contrast = overlay->contrast;
1257 attrs->saturation = overlay->saturation;
1258
1259 if (IS_I9XX(dev)) {
1260 attrs->gamma0 = I915_READ(OGAMC0);
1261 attrs->gamma1 = I915_READ(OGAMC1);
1262 attrs->gamma2 = I915_READ(OGAMC2);
1263 attrs->gamma3 = I915_READ(OGAMC3);
1264 attrs->gamma4 = I915_READ(OGAMC4);
1265 attrs->gamma5 = I915_READ(OGAMC5);
1266 }
1267 } else {
1268 if (attrs->brightness < -128 || attrs->brightness > 127)
1269 goto out_unlock;
1270 if (attrs->contrast > 255)
1271 goto out_unlock;
1272 if (attrs->saturation > 1023)
1273 goto out_unlock;
1274
1275 overlay->color_key = attrs->color_key;
1276 overlay->brightness = attrs->brightness;
1277 overlay->contrast = attrs->contrast;
1278 overlay->saturation = attrs->saturation;
1279
1280 regs = intel_overlay_map_regs(overlay);
1281 if (!regs) {
1282 ret = -ENOMEM;
1283 goto out_unlock;
1284 }
1285
1286 update_reg_attrs(overlay, regs);
1287
1288 intel_overlay_unmap_regs(overlay, regs);
1289
1290 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1291 if (!IS_I9XX(dev))
1292 goto out_unlock;
1293
1294 if (overlay->active) {
1295 ret = -EBUSY;
1296 goto out_unlock;
1297 }
1298
1299 ret = check_gamma(attrs);
1300 if (ret)
1301 goto out_unlock;
1302
1303 I915_WRITE(OGAMC0, attrs->gamma0);
1304 I915_WRITE(OGAMC1, attrs->gamma1);
1305 I915_WRITE(OGAMC2, attrs->gamma2);
1306 I915_WRITE(OGAMC3, attrs->gamma3);
1307 I915_WRITE(OGAMC4, attrs->gamma4);
1308 I915_WRITE(OGAMC5, attrs->gamma5);
1309 }
1310 }
1311
1312 ret = 0;
1313 out_unlock:
1314 mutex_unlock(&dev->struct_mutex);
1315 mutex_unlock(&dev->mode_config.mutex);
1316
1317 return ret;
1318 }
1319
1320 void intel_setup_overlay(struct drm_device *dev)
1321 {
1322 drm_i915_private_t *dev_priv = dev->dev_private;
1323 struct intel_overlay *overlay;
1324 struct drm_gem_object *reg_bo;
1325 struct overlay_registers *regs;
1326 int ret;
1327
1328 if (!HAS_OVERLAY(dev))
1329 return;
1330
1331 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1332 if (!overlay)
1333 return;
1334 overlay->dev = dev;
1335
1336 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1337 if (!reg_bo)
1338 goto out_free;
1339 overlay->reg_bo = to_intel_bo(reg_bo);
1340
1341 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1342 ret = i915_gem_attach_phys_object(dev, reg_bo,
1343 I915_GEM_PHYS_OVERLAY_REGS,
1344 PAGE_SIZE);
1345 if (ret) {
1346 DRM_ERROR("failed to attach phys overlay regs\n");
1347 goto out_free_bo;
1348 }
1349 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1350 } else {
1351 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1352 if (ret) {
1353 DRM_ERROR("failed to pin overlay register bo\n");
1354 goto out_free_bo;
1355 }
1356 overlay->flip_addr = overlay->reg_bo->gtt_offset;
1357
1358 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1359 if (ret) {
1360 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1361 goto out_unpin_bo;
1362 }
1363 }
1364
1365 /* init all values */
1366 overlay->color_key = 0x0101fe;
1367 overlay->brightness = -19;
1368 overlay->contrast = 75;
1369 overlay->saturation = 146;
1370
1371 regs = intel_overlay_map_regs(overlay);
1372 if (!regs)
1373 goto out_free_bo;
1374
1375 memset(regs, 0, sizeof(struct overlay_registers));
1376 update_polyphase_filter(regs);
1377 update_reg_attrs(overlay, regs);
1378
1379 intel_overlay_unmap_regs(overlay, regs);
1380
1381 dev_priv->overlay = overlay;
1382 DRM_INFO("initialized overlay support\n");
1383 return;
1384
1385 out_unpin_bo:
1386 i915_gem_object_unpin(reg_bo);
1387 out_free_bo:
1388 drm_gem_object_unreference(reg_bo);
1389 out_free:
1390 kfree(overlay);
1391 return;
1392 }
1393
1394 void intel_cleanup_overlay(struct drm_device *dev)
1395 {
1396 drm_i915_private_t *dev_priv = dev->dev_private;
1397
1398 if (!dev_priv->overlay)
1399 return;
1400
1401 /* The bo's should be free'd by the generic code already.
1402 * Furthermore modesetting teardown happens beforehand so the
1403 * hardware should be off already */
1404 BUG_ON(dev_priv->overlay->active);
1405
1406 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1407 kfree(dev_priv->overlay);
1408 }
1409
1410 struct intel_overlay_error_state {
1411 struct overlay_registers regs;
1412 unsigned long base;
1413 u32 dovsta;
1414 u32 isr;
1415 };
1416
1417 struct intel_overlay_error_state *
1418 intel_overlay_capture_error_state(struct drm_device *dev)
1419 {
1420 drm_i915_private_t *dev_priv = dev->dev_private;
1421 struct intel_overlay *overlay = dev_priv->overlay;
1422 struct intel_overlay_error_state *error;
1423 struct overlay_registers __iomem *regs;
1424
1425 if (!overlay || !overlay->active)
1426 return NULL;
1427
1428 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1429 if (error == NULL)
1430 return NULL;
1431
1432 error->dovsta = I915_READ(DOVSTA);
1433 error->isr = I915_READ(ISR);
1434 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1435 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
1436 else
1437 error->base = (long) overlay->reg_bo->gtt_offset;
1438
1439 regs = intel_overlay_map_regs_atomic(overlay, KM_IRQ0);
1440 if (!regs)
1441 goto err;
1442
1443 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1444 intel_overlay_unmap_regs_atomic(overlay, KM_IRQ0, regs);
1445
1446 return error;
1447
1448 err:
1449 kfree(error);
1450 return NULL;
1451 }
1452
1453 void
1454 intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1455 {
1456 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1457 error->dovsta, error->isr);
1458 seq_printf(m, " Register file at 0x%08lx:\n",
1459 error->base);
1460
1461 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1462 P(OBUF_0Y);
1463 P(OBUF_1Y);
1464 P(OBUF_0U);
1465 P(OBUF_0V);
1466 P(OBUF_1U);
1467 P(OBUF_1V);
1468 P(OSTRIDE);
1469 P(YRGB_VPH);
1470 P(UV_VPH);
1471 P(HORZ_PH);
1472 P(INIT_PHS);
1473 P(DWINPOS);
1474 P(DWINSZ);
1475 P(SWIDTH);
1476 P(SWIDTHSW);
1477 P(SHEIGHT);
1478 P(YRGBSCALE);
1479 P(UVSCALE);
1480 P(OCLRC0);
1481 P(OCLRC1);
1482 P(DCLRKV);
1483 P(DCLRKM);
1484 P(SCLRKVH);
1485 P(SCLRKVL);
1486 P(SCLRKEN);
1487 P(OCONFIG);
1488 P(OCMD);
1489 P(OSTART_0Y);
1490 P(OSTART_1Y);
1491 P(OSTART_0U);
1492 P(OSTART_0V);
1493 P(OSTART_1U);
1494 P(OSTART_1V);
1495 P(OTILEOFF_0Y);
1496 P(OTILEOFF_1Y);
1497 P(OTILEOFF_0U);
1498 P(OTILEOFF_0V);
1499 P(OTILEOFF_1U);
1500 P(OTILEOFF_1V);
1501 P(FASTHSCALE);
1502 P(UVSCALEV);
1503 #undef P
1504 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree