arch/x86/kernel/suspend_64.c

   1 /*
   2  * Suspend support specific for i386.
   3  *
   4  * Distribute under GPLv2
   5  *
   6  * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
   7  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
   8  */
   9
  10 #include <linux/smp.h>
  11 #include <linux/suspend.h>
  12 #include <asm/proto.h>
  13 #include <asm/page.h>
  14 #include <asm/pgtable.h>
  15 #include <asm/mtrr.h>
  16
  17 /* References to section boundaries */
  18 extern const void __nosave_begin, __nosave_end;
  19
  20 static void fix_processor_context(void);
  21
  22 struct saved_context saved_context;
  23
  24 /**
  25  *      __save_processor_state - save CPU registers before creating a
  26  *              hibernation image and before restoring the memory state from it
  27  *      @ctxt - structure to store the registers contents in
  28  *
  29  *      NOTE: If there is a CPU register the modification of which by the
  30  *      boot kernel (ie. the kernel used for loading the hibernation image)
  31  *      might affect the operations of the restored target kernel (ie. the one
  32  *      saved in the hibernation image), then its contents must be saved by this
  33  *      function.  In other words, if kernel A is hibernated and different
  34  *      kernel B is used for loading the hibernation image into memory, the
  35  *      kernel A's __save_processor_state() function must save all registers
  36  *      needed by kernel A, so that it can operate correctly after the resume
  37  *      regardless of what kernel B does in the meantime.
  38  */
  39 static void __save_processor_state(struct saved_context *ctxt)
  40 {
  41         kernel_fpu_begin();
  42
  43         /*
  44          * descriptor tables
  45          */
  46         store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
  47         store_idt((struct desc_ptr *)&ctxt->idt_limit);
  48         store_tr(ctxt->tr);
  49
  50         /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
  51         /*
  52          * segment registers
  53          */
  54         asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
  55         asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
  56         asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
  57         asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
  58         asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
  59
  60         rdmsrl(MSR_FS_BASE, ctxt->fs_base);
  61         rdmsrl(MSR_GS_BASE, ctxt->gs_base);
  62         rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
  63         mtrr_save_fixed_ranges(NULL);
  64
  65         /*
  66          * control registers
  67          */
  68         rdmsrl(MSR_EFER, ctxt->efer);
  69         ctxt->cr0 = read_cr0();
  70         ctxt->cr2 = read_cr2();
  71         ctxt->cr3 = read_cr3();
  72         ctxt->cr4 = read_cr4();
  73         ctxt->cr8 = read_cr8();
  74 }
  75
  76 void save_processor_state(void)
  77 {
  78         __save_processor_state(&saved_context);
  79 }
  80
  81 static void do_fpu_end(void)
  82 {
  83         /*
  84          * Restore FPU regs if necessary
  85          */
  86         kernel_fpu_end();
  87 }
  88
  89 /**
  90  *      __restore_processor_state - restore the contents of CPU registers saved
  91  *              by __save_processor_state()
  92  *      @ctxt - structure to load the registers contents from
  93  */
  94 static void __restore_processor_state(struct saved_context *ctxt)
  95 {
  96         /*
  97          * control registers
  98          */
  99         wrmsrl(MSR_EFER, ctxt->efer);
 100         write_cr8(ctxt->cr8);
 101         write_cr4(ctxt->cr4);
 102         write_cr3(ctxt->cr3);
 103         write_cr2(ctxt->cr2);
 104         write_cr0(ctxt->cr0);
 105
 106         /*
 107          * now restore the descriptor tables to their proper values
 108          * ltr is done i fix_processor_context().
 109          */
 110         load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
 111         load_idt((const struct desc_ptr *)&ctxt->idt_limit);
 112
 113
 114         /*
 115          * segment registers
 116          */
 117         asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
 118         asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
 119         asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
 120         load_gs_index(ctxt->gs);
 121         asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
 122
 123         wrmsrl(MSR_FS_BASE, ctxt->fs_base);
 124         wrmsrl(MSR_GS_BASE, ctxt->gs_base);
 125         wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
 126
 127         fix_processor_context();
 128
 129         do_fpu_end();
 130         mtrr_ap_init();
 131 }
 132
 133 void restore_processor_state(void)
 134 {
 135         __restore_processor_state(&saved_context);
 136 }
 137
 138 static void fix_processor_context(void)
 139 {
 140         int cpu = smp_processor_id();
 141         struct tss_struct *t = &per_cpu(init_tss, cpu);
 142
 143         /*
 144          * This just modifies memory; should not be necessary. But... This
 145          * is necessary, because 386 hardware has concept of busy TSS or some
 146          * similar stupidity.
 147          */
 148         set_tss_desc(cpu, t);
 149
 150         get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
 151
 152         syscall_init();                         /* This sets MSR_*STAR and related */
 153         load_TR_desc();                         /* This does ltr */
 154         load_LDT(&current->active_mm->context); /* This does lldt */
 155
 156         /*
 157          * Now maybe reload the debug registers
 158          */
 159         if (current->thread.debugreg7){
 160                 loaddebug(&current->thread, 0);
 161                 loaddebug(&current->thread, 1);
 162                 loaddebug(&current->thread, 2);
 163                 loaddebug(&current->thread, 3);
 164                 /* no 4 and 5 */
 165                 loaddebug(&current->thread, 6);
 166                 loaddebug(&current->thread, 7);
 167         }
 168 }
 169
 170 #ifdef CONFIG_HIBERNATION
 171 /* Defined in arch/x86_64/kernel/suspend_asm.S */
 172 extern int restore_image(void);
 173
 174 /*
 175  * Address to jump to in the last phase of restore in order to get to the image
 176  * kernel's text (this value is passed in the image header).
 177  */
 178 unsigned long restore_jump_address;
 179
 180 /*
 181  * Value of the cr3 register from before the hibernation (this value is passed
 182  * in the image header).
 183  */
 184 unsigned long restore_cr3;
 185
 186 pgd_t *temp_level4_pgt;
 187
 188 void *relocated_restore_code;
 189
 190 static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
 191 {
 192         long i, j;
 193
 194         i = pud_index(address);
 195         pud = pud + i;
 196         for (; i < PTRS_PER_PUD; pud++, i++) {
 197                 unsigned long paddr;
 198                 pmd_t *pmd;
 199
 200                 paddr = address + i*PUD_SIZE;
 201                 if (paddr >= end)
 202                         break;
 203
 204                 pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
 205                 if (!pmd)
 206                         return -ENOMEM;
 207                 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
 208                 for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
 209                         unsigned long pe;
 210
 211                         if (paddr >= end)
 212                                 break;
 213                         pe = __PAGE_KERNEL_LARGE_EXEC | paddr;
 214                         pe &= __supported_pte_mask;
 215                         set_pmd(pmd, __pmd(pe));
 216                 }
 217         }
 218         return 0;
 219 }
 220
 221 static int set_up_temporary_mappings(void)
 222 {
 223         unsigned long start, end, next;
 224         int error;
 225
 226         temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
 227         if (!temp_level4_pgt)
 228                 return -ENOMEM;
 229
 230         /* It is safe to reuse the original kernel mapping */
 231         set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
 232                 init_level4_pgt[pgd_index(__START_KERNEL_map)]);
 233
 234         /* Set up the direct mapping from scratch */
 235         start = (unsigned long)pfn_to_kaddr(0);
 236         end = (unsigned long)pfn_to_kaddr(end_pfn);
 237
 238         for (; start < end; start = next) {
 239                 pud_t *pud = (pud_t *)get_safe_page(GFP_ATOMIC);
 240                 if (!pud)
 241                         return -ENOMEM;
 242                 next = start + PGDIR_SIZE;
 243                 if (next > end)
 244                         next = end;
 245                 if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
 246                         return error;
 247                 set_pgd(temp_level4_pgt + pgd_index(start),
 248                         mk_kernel_pgd(__pa(pud)));
 249         }
 250         return 0;
 251 }
 252
 253 int swsusp_arch_resume(void)
 254 {
 255         int error;
 256
 257         /* We have got enough memory and from now on we cannot recover */
 258         if ((error = set_up_temporary_mappings()))
 259                 return error;
 260
 261         relocated_restore_code = (void *)get_safe_page(GFP_ATOMIC);
 262         if (!relocated_restore_code)
 263                 return -ENOMEM;
 264         memcpy(relocated_restore_code, &core_restore_code,
 265                &restore_registers - &core_restore_code);
 266
 267         restore_image();
 268         return 0;
 269 }
 270
 271 /*
 272  *      pfn_is_nosave - check if given pfn is in the 'nosave' section
 273  */
 274
 275 int pfn_is_nosave(unsigned long pfn)
 276 {
 277         unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
 278         unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
 279         return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
 280 }
 281
 282 struct restore_data_record {
 283         unsigned long jump_address;
 284         unsigned long cr3;
 285         unsigned long magic;
 286 };
 287
 288 #define RESTORE_MAGIC   0x0123456789ABCDEFUL
 289
 290 /**
 291  *      arch_hibernation_header_save - populate the architecture specific part
 292  *              of a hibernation image header
 293  *      @addr: address to save the data at
 294  */
 295 int arch_hibernation_header_save(void *addr, unsigned int max_size)
 296 {
 297         struct restore_data_record *rdr = addr;
 298
 299         if (max_size < sizeof(struct restore_data_record))
 300                 return -EOVERFLOW;
 301         rdr->jump_address = restore_jump_address;
 302         rdr->cr3 = restore_cr3;
 303         rdr->magic = RESTORE_MAGIC;
 304         return 0;
 305 }
 306
 307 /**
 308  *      arch_hibernation_header_restore - read the architecture specific data
 309  *              from the hibernation image header
 310  *      @addr: address to read the data from
 311  */
 312 int arch_hibernation_header_restore(void *addr)
 313 {
 314         struct restore_data_record *rdr = addr;
 315
 316         restore_jump_address = rdr->jump_address;
 317         restore_cr3 = rdr->cr3;
 318         return (rdr->magic == RESTORE_MAGIC) ? 0 : -EINVAL;
 319 }
 320 #endif /* CONFIG_HIBERNATION */