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viafb: remove the remaining VIA_RES_* uses
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / video / via / lcd.c
blob3a83e5bc25d9818db388cae43e7c151b9d1e13ee
1 /*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 #include "global.h"
23 #include "lcdtbl.h"
24
25 #define viafb_compact_res(x, y) (((x)<<16)|(y))
26
27 static struct iga2_shadow_crtc_timing iga2_shadow_crtc_reg = {
28 /* IGA2 Shadow Horizontal Total */
29 {IGA2_SHADOW_HOR_TOTAL_REG_NUM, {{CR6D, 0, 7}, {CR71, 3, 3} } },
30 /* IGA2 Shadow Horizontal Blank End */
31 {IGA2_SHADOW_HOR_BLANK_END_REG_NUM, {{CR6E, 0, 7} } },
32 /* IGA2 Shadow Vertical Total */
33 {IGA2_SHADOW_VER_TOTAL_REG_NUM, {{CR6F, 0, 7}, {CR71, 0, 2} } },
34 /* IGA2 Shadow Vertical Addressable Video */
35 {IGA2_SHADOW_VER_ADDR_REG_NUM, {{CR70, 0, 7}, {CR71, 4, 6} } },
36 /* IGA2 Shadow Vertical Blank Start */
37 {IGA2_SHADOW_VER_BLANK_START_REG_NUM,
38 {{CR72, 0, 7}, {CR74, 4, 6} } },
39 /* IGA2 Shadow Vertical Blank End */
40 {IGA2_SHADOW_VER_BLANK_END_REG_NUM, {{CR73, 0, 7}, {CR74, 0, 2} } },
41 /* IGA2 Shadow Vertical Sync Start */
42 {IGA2_SHADOW_VER_SYNC_START_REG_NUM, {{CR75, 0, 7}, {CR76, 4, 6} } },
43 /* IGA2 Shadow Vertical Sync End */
44 {IGA2_SHADOW_VER_SYNC_END_REG_NUM, {{CR76, 0, 3} } }
45 };
46
47 static struct _lcd_scaling_factor lcd_scaling_factor = {
48 /* LCD Horizontal Scaling Factor Register */
49 {LCD_HOR_SCALING_FACTOR_REG_NUM,
50 {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
51 /* LCD Vertical Scaling Factor Register */
52 {LCD_VER_SCALING_FACTOR_REG_NUM,
53 {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
54 };
55 static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
56 /* LCD Horizontal Scaling Factor Register */
57 {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
58 /* LCD Vertical Scaling Factor Register */
59 {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
60 };
61
62 static int check_lvds_chip(int device_id_subaddr, int device_id);
63 static bool lvds_identify_integratedlvds(void);
64 static void fp_id_to_vindex(int panel_id);
65 static int lvds_register_read(int index);
66 static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
67 int panel_vres);
68 static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
69 int panel_id);
70 static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
71 int panel_id);
72 static void load_lcd_patch_regs(int set_hres, int set_vres,
73 int panel_id, int set_iga);
74 static void via_pitch_alignment_patch_lcd(
75 struct lvds_setting_information *plvds_setting_info,
76 struct lvds_chip_information
77 *plvds_chip_info);
78 static void lcd_patch_skew_dvp0(struct lvds_setting_information
79 *plvds_setting_info,
80 struct lvds_chip_information *plvds_chip_info);
81 static void lcd_patch_skew_dvp1(struct lvds_setting_information
82 *plvds_setting_info,
83 struct lvds_chip_information *plvds_chip_info);
84 static void lcd_patch_skew(struct lvds_setting_information
85 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
86
87 static void integrated_lvds_disable(struct lvds_setting_information
88 *plvds_setting_info,
89 struct lvds_chip_information *plvds_chip_info);
90 static void integrated_lvds_enable(struct lvds_setting_information
91 *plvds_setting_info,
92 struct lvds_chip_information *plvds_chip_info);
93 static void lcd_powersequence_off(void);
94 static void lcd_powersequence_on(void);
95 static void fill_lcd_format(void);
96 static void check_diport_of_integrated_lvds(
97 struct lvds_chip_information *plvds_chip_info,
98 struct lvds_setting_information
99 *plvds_setting_info);
100 static struct display_timing lcd_centering_timging(struct display_timing
101 mode_crt_reg,
102 struct display_timing panel_crt_reg);
103 static void load_crtc_shadow_timing(struct display_timing mode_timing,
104 struct display_timing panel_timing);
105 static void viafb_load_scaling_factor_for_p4m900(int set_hres,
106 int set_vres, int panel_hres, int panel_vres);
107
108 static int check_lvds_chip(int device_id_subaddr, int device_id)
109 {
110 if (lvds_register_read(device_id_subaddr) == device_id)
111 return OK;
112 else
113 return FAIL;
114 }
115
116 void viafb_init_lcd_size(void)
117 {
118 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
119 DEBUG_MSG(KERN_INFO
120 "viaparinfo->lvds_setting_info->get_lcd_size_method %d\n",
121 viaparinfo->lvds_setting_info->get_lcd_size_method);
122
123 switch (viaparinfo->lvds_setting_info->get_lcd_size_method) {
124 case GET_LCD_SIZE_BY_SYSTEM_BIOS:
125 break;
126 case GET_LCD_SZIE_BY_HW_STRAPPING:
127 break;
128 case GET_LCD_SIZE_BY_VGA_BIOS:
129 DEBUG_MSG(KERN_INFO "Get LCD Size method by VGA BIOS !!\n");
130 fp_id_to_vindex(viafb_lcd_panel_id);
131 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
132 viaparinfo->lvds_setting_info->lcd_panel_id);
133 break;
134 case GET_LCD_SIZE_BY_USER_SETTING:
135 DEBUG_MSG(KERN_INFO "Get LCD Size method by user setting !!\n");
136 fp_id_to_vindex(viafb_lcd_panel_id);
137 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
138 viaparinfo->lvds_setting_info->lcd_panel_id);
139 break;
140 default:
141 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size fail\n");
142 viaparinfo->lvds_setting_info->lcd_panel_id =
143 LCD_PANEL_ID1_800X600;
144 fp_id_to_vindex(LCD_PANEL_ID1_800X600);
145 }
146 viaparinfo->lvds_setting_info2->lcd_panel_id =
147 viaparinfo->lvds_setting_info->lcd_panel_id;
148 viaparinfo->lvds_setting_info2->lcd_panel_hres =
149 viaparinfo->lvds_setting_info->lcd_panel_hres;
150 viaparinfo->lvds_setting_info2->lcd_panel_vres =
151 viaparinfo->lvds_setting_info->lcd_panel_vres;
152 viaparinfo->lvds_setting_info2->device_lcd_dualedge =
153 viaparinfo->lvds_setting_info->device_lcd_dualedge;
154 viaparinfo->lvds_setting_info2->LCDDithering =
155 viaparinfo->lvds_setting_info->LCDDithering;
156 }
157
158 static bool lvds_identify_integratedlvds(void)
159 {
160 if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
161 /* Two dual channel LCD (Internal LVDS + External LVDS): */
162 /* If we have an external LVDS, such as VT1636, we should
163 have its chip ID already. */
164 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
165 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
166 INTEGRATED_LVDS;
167 DEBUG_MSG(KERN_INFO "Support two dual channel LVDS!\
168 (Internal LVDS + External LVDS)\n");
169 } else {
170 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
171 INTEGRATED_LVDS;
172 DEBUG_MSG(KERN_INFO "Not found external LVDS,\
173 so can't support two dual channel LVDS!\n");
174 }
175 } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
176 /* Two single channel LCD (Internal LVDS + Internal LVDS): */
177 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
178 INTEGRATED_LVDS;
179 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
180 INTEGRATED_LVDS;
181 DEBUG_MSG(KERN_INFO "Support two single channel LVDS!\
182 (Internal LVDS + Internal LVDS)\n");
183 } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
184 /* If we have found external LVDS, just use it,
185 otherwise, we will use internal LVDS as default. */
186 if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
187 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
188 INTEGRATED_LVDS;
189 DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
190 }
191 } else {
192 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
193 NON_LVDS_TRANSMITTER;
194 DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
195 return false;
196 }
197
198 return true;
199 }
200
201 int viafb_lvds_trasmitter_identify(void)
202 {
203 viaparinfo->shared->i2c_stuff.i2c_port = I2CPORTINDEX;
204 if (viafb_lvds_identify_vt1636()) {
205 viaparinfo->chip_info->lvds_chip_info.i2c_port = I2CPORTINDEX;
206 DEBUG_MSG(KERN_INFO
207 "Found VIA VT1636 LVDS on port i2c 0x31 \n");
208 } else {
209 viaparinfo->shared->i2c_stuff.i2c_port = GPIOPORTINDEX;
210 if (viafb_lvds_identify_vt1636()) {
211 viaparinfo->chip_info->lvds_chip_info.i2c_port =
212 GPIOPORTINDEX;
213 DEBUG_MSG(KERN_INFO
214 "Found VIA VT1636 LVDS on port gpio 0x2c \n");
215 }
216 }
217
218 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
219 lvds_identify_integratedlvds();
220
221 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
222 return true;
223 /* Check for VT1631: */
224 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
225 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
226 VT1631_LVDS_I2C_ADDR;
227
228 if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
229 DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
230 DEBUG_MSG(KERN_INFO "\n %2d",
231 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
232 DEBUG_MSG(KERN_INFO "\n %2d",
233 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
234 return OK;
235 }
236
237 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
238 NON_LVDS_TRANSMITTER;
239 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
240 VT1631_LVDS_I2C_ADDR;
241 return FAIL;
242 }
243
244 static void fp_id_to_vindex(int panel_id)
245 {
246 DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
247
248 if (panel_id > LCD_PANEL_ID_MAXIMUM)
249 viafb_lcd_panel_id = panel_id =
250 viafb_read_reg(VIACR, CR3F) & 0x0F;
251
252 switch (panel_id) {
253 case 0x0:
254 viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
255 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
256 viaparinfo->lvds_setting_info->lcd_panel_id =
257 LCD_PANEL_ID0_640X480;
258 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
259 viaparinfo->lvds_setting_info->LCDDithering = 1;
260 break;
261 case 0x1:
262 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
263 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
264 viaparinfo->lvds_setting_info->lcd_panel_id =
265 LCD_PANEL_ID1_800X600;
266 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
267 viaparinfo->lvds_setting_info->LCDDithering = 1;
268 break;
269 case 0x2:
270 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
271 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
272 viaparinfo->lvds_setting_info->lcd_panel_id =
273 LCD_PANEL_ID2_1024X768;
274 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
275 viaparinfo->lvds_setting_info->LCDDithering = 1;
276 break;
277 case 0x3:
278 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
279 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
280 viaparinfo->lvds_setting_info->lcd_panel_id =
281 LCD_PANEL_ID3_1280X768;
282 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
283 viaparinfo->lvds_setting_info->LCDDithering = 1;
284 break;
285 case 0x4:
286 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
287 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
288 viaparinfo->lvds_setting_info->lcd_panel_id =
289 LCD_PANEL_ID4_1280X1024;
290 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
291 viaparinfo->lvds_setting_info->LCDDithering = 1;
292 break;
293 case 0x5:
294 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
295 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
296 viaparinfo->lvds_setting_info->lcd_panel_id =
297 LCD_PANEL_ID5_1400X1050;
298 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
299 viaparinfo->lvds_setting_info->LCDDithering = 1;
300 break;
301 case 0x6:
302 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
303 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
304 viaparinfo->lvds_setting_info->lcd_panel_id =
305 LCD_PANEL_ID6_1600X1200;
306 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
307 viaparinfo->lvds_setting_info->LCDDithering = 1;
308 break;
309 case 0x8:
310 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
311 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
312 viaparinfo->lvds_setting_info->lcd_panel_id =
313 LCD_PANEL_IDA_800X480;
314 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
315 viaparinfo->lvds_setting_info->LCDDithering = 1;
316 break;
317 case 0x9:
318 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
319 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
320 viaparinfo->lvds_setting_info->lcd_panel_id =
321 LCD_PANEL_ID2_1024X768;
322 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
323 viaparinfo->lvds_setting_info->LCDDithering = 1;
324 break;
325 case 0xA:
326 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
327 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
328 viaparinfo->lvds_setting_info->lcd_panel_id =
329 LCD_PANEL_ID2_1024X768;
330 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
331 viaparinfo->lvds_setting_info->LCDDithering = 0;
332 break;
333 case 0xB:
334 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
335 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
336 viaparinfo->lvds_setting_info->lcd_panel_id =
337 LCD_PANEL_ID2_1024X768;
338 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
339 viaparinfo->lvds_setting_info->LCDDithering = 0;
340 break;
341 case 0xC:
342 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
343 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
344 viaparinfo->lvds_setting_info->lcd_panel_id =
345 LCD_PANEL_ID3_1280X768;
346 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
347 viaparinfo->lvds_setting_info->LCDDithering = 0;
348 break;
349 case 0xD:
350 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
351 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
352 viaparinfo->lvds_setting_info->lcd_panel_id =
353 LCD_PANEL_ID4_1280X1024;
354 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
355 viaparinfo->lvds_setting_info->LCDDithering = 0;
356 break;
357 case 0xE:
358 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
359 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
360 viaparinfo->lvds_setting_info->lcd_panel_id =
361 LCD_PANEL_ID5_1400X1050;
362 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
363 viaparinfo->lvds_setting_info->LCDDithering = 0;
364 break;
365 case 0xF:
366 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
367 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
368 viaparinfo->lvds_setting_info->lcd_panel_id =
369 LCD_PANEL_ID6_1600X1200;
370 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
371 viaparinfo->lvds_setting_info->LCDDithering = 0;
372 break;
373 case 0x10:
374 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
375 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
376 viaparinfo->lvds_setting_info->lcd_panel_id =
377 LCD_PANEL_ID7_1366X768;
378 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
379 viaparinfo->lvds_setting_info->LCDDithering = 0;
380 break;
381 case 0x11:
382 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
383 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
384 viaparinfo->lvds_setting_info->lcd_panel_id =
385 LCD_PANEL_ID8_1024X600;
386 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
387 viaparinfo->lvds_setting_info->LCDDithering = 1;
388 break;
389 case 0x12:
390 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
391 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
392 viaparinfo->lvds_setting_info->lcd_panel_id =
393 LCD_PANEL_ID3_1280X768;
394 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
395 viaparinfo->lvds_setting_info->LCDDithering = 1;
396 break;
397 case 0x13:
398 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
399 viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
400 viaparinfo->lvds_setting_info->lcd_panel_id =
401 LCD_PANEL_ID9_1280X800;
402 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
403 viaparinfo->lvds_setting_info->LCDDithering = 1;
404 break;
405 case 0x14:
406 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
407 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
408 viaparinfo->lvds_setting_info->lcd_panel_id =
409 LCD_PANEL_IDB_1360X768;
410 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
411 viaparinfo->lvds_setting_info->LCDDithering = 0;
412 break;
413 case 0x15:
414 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
415 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
416 viaparinfo->lvds_setting_info->lcd_panel_id =
417 LCD_PANEL_ID3_1280X768;
418 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
419 viaparinfo->lvds_setting_info->LCDDithering = 0;
420 break;
421 case 0x16:
422 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
423 viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
424 viaparinfo->lvds_setting_info->lcd_panel_id =
425 LCD_PANEL_IDC_480X640;
426 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
427 viaparinfo->lvds_setting_info->LCDDithering = 1;
428 break;
429 default:
430 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
431 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
432 viaparinfo->lvds_setting_info->lcd_panel_id =
433 LCD_PANEL_ID1_800X600;
434 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
435 viaparinfo->lvds_setting_info->LCDDithering = 1;
436 }
437 }
438
439 static int lvds_register_read(int index)
440 {
441 u8 data;
442
443 viaparinfo->shared->i2c_stuff.i2c_port = GPIOPORTINDEX;
444 viafb_i2c_readbyte((u8) viaparinfo->chip_info->
445 lvds_chip_info.lvds_chip_slave_addr,
446 (u8) index, &data);
447 return data;
448 }
449
450 static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
451 int panel_vres)
452 {
453 int reg_value = 0;
454 int viafb_load_reg_num;
455 struct io_register *reg = NULL;
456
457 DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
458
459 /* LCD Scaling Enable */
460 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
461 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
462 viafb_load_scaling_factor_for_p4m900(set_hres, set_vres,
463 panel_hres, panel_vres);
464 return;
465 }
466
467 /* Check if expansion for horizontal */
468 if (set_hres != panel_hres) {
469 /* Load Horizontal Scaling Factor */
470 switch (viaparinfo->chip_info->gfx_chip_name) {
471 case UNICHROME_CLE266:
472 case UNICHROME_K400:
473 reg_value =
474 CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
475 viafb_load_reg_num =
476 lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
477 reg_num;
478 reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
479 viafb_load_reg(reg_value,
480 viafb_load_reg_num, reg, VIACR);
481 break;
482 case UNICHROME_K800:
483 case UNICHROME_PM800:
484 case UNICHROME_CN700:
485 case UNICHROME_CX700:
486 case UNICHROME_K8M890:
487 case UNICHROME_P4M890:
488 reg_value =
489 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
490 /* Horizontal scaling enabled */
491 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
492 viafb_load_reg_num =
493 lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
494 reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
495 viafb_load_reg(reg_value,
496 viafb_load_reg_num, reg, VIACR);
497 break;
498 }
499
500 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
501 } else {
502 /* Horizontal scaling disabled */
503 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
504 }
505
506 /* Check if expansion for vertical */
507 if (set_vres != panel_vres) {
508 /* Load Vertical Scaling Factor */
509 switch (viaparinfo->chip_info->gfx_chip_name) {
510 case UNICHROME_CLE266:
511 case UNICHROME_K400:
512 reg_value =
513 CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
514 viafb_load_reg_num =
515 lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
516 reg_num;
517 reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
518 viafb_load_reg(reg_value,
519 viafb_load_reg_num, reg, VIACR);
520 break;
521 case UNICHROME_K800:
522 case UNICHROME_PM800:
523 case UNICHROME_CN700:
524 case UNICHROME_CX700:
525 case UNICHROME_K8M890:
526 case UNICHROME_P4M890:
527 reg_value =
528 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
529 /* Vertical scaling enabled */
530 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
531 viafb_load_reg_num =
532 lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
533 reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
534 viafb_load_reg(reg_value,
535 viafb_load_reg_num, reg, VIACR);
536 break;
537 }
538
539 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
540 } else {
541 /* Vertical scaling disabled */
542 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
543 }
544 }
545
546 static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
547 int panel_id)
548 {
549 u32 compact_mode = viafb_compact_res(set_hres, set_vres);
550 int reg_num = 0;
551 struct io_reg *lcd_patch_reg = NULL;
552
553 switch (panel_id) {
554 /* LCD 800x600 */
555 case LCD_PANEL_ID1_800X600:
556 switch (compact_mode) {
557 case viafb_compact_res(640, 400):
558 case viafb_compact_res(640, 480):
559 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_8X6;
560 lcd_patch_reg = K400_LCD_RES_6X4_8X6;
561 break;
562 case viafb_compact_res(720, 480):
563 case viafb_compact_res(720, 576):
564 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_8X6;
565 lcd_patch_reg = K400_LCD_RES_7X4_8X6;
566 break;
567 }
568 break;
569
570 /* LCD 1024x768 */
571 case LCD_PANEL_ID2_1024X768:
572 switch (compact_mode) {
573 case viafb_compact_res(640, 400):
574 case viafb_compact_res(640, 480):
575 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_10X7;
576 lcd_patch_reg = K400_LCD_RES_6X4_10X7;
577 break;
578 case viafb_compact_res(720, 480):
579 case viafb_compact_res(720, 576):
580 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_10X7;
581 lcd_patch_reg = K400_LCD_RES_7X4_10X7;
582 break;
583 case viafb_compact_res(800, 600):
584 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_10X7;
585 lcd_patch_reg = K400_LCD_RES_8X6_10X7;
586 break;
587 }
588 break;
589
590 /* LCD 1280x1024 */
591 case LCD_PANEL_ID4_1280X1024:
592 switch (compact_mode) {
593 case viafb_compact_res(640, 400):
594 case viafb_compact_res(640, 480):
595 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_12X10;
596 lcd_patch_reg = K400_LCD_RES_6X4_12X10;
597 break;
598 case viafb_compact_res(720, 480):
599 case viafb_compact_res(720, 576):
600 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_12X10;
601 lcd_patch_reg = K400_LCD_RES_7X4_12X10;
602 break;
603 case viafb_compact_res(800, 600):
604 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_12X10;
605 lcd_patch_reg = K400_LCD_RES_8X6_12X10;
606 break;
607 case viafb_compact_res(1024, 768):
608 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_12X10;
609 lcd_patch_reg = K400_LCD_RES_10X7_12X10;
610 break;
611
612 }
613 break;
614
615 /* LCD 1400x1050 */
616 case LCD_PANEL_ID5_1400X1050:
617 switch (compact_mode) {
618 case viafb_compact_res(640, 480):
619 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_14X10;
620 lcd_patch_reg = K400_LCD_RES_6X4_14X10;
621 break;
622 case viafb_compact_res(800, 600):
623 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_14X10;
624 lcd_patch_reg = K400_LCD_RES_8X6_14X10;
625 break;
626 case viafb_compact_res(1024, 768):
627 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_14X10;
628 lcd_patch_reg = K400_LCD_RES_10X7_14X10;
629 break;
630 case viafb_compact_res(1280, 768):
631 case viafb_compact_res(1280, 800):
632 case viafb_compact_res(1280, 960):
633 case viafb_compact_res(1280, 1024):
634 reg_num = NUM_TOTAL_K400_LCD_RES_12X10_14X10;
635 lcd_patch_reg = K400_LCD_RES_12X10_14X10;
636 break;
637 }
638 break;
639
640 /* LCD 1600x1200 */
641 case LCD_PANEL_ID6_1600X1200:
642 switch (compact_mode) {
643 case viafb_compact_res(640, 400):
644 case viafb_compact_res(640, 480):
645 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_16X12;
646 lcd_patch_reg = K400_LCD_RES_6X4_16X12;
647 break;
648 case viafb_compact_res(720, 480):
649 case viafb_compact_res(720, 576):
650 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_16X12;
651 lcd_patch_reg = K400_LCD_RES_7X4_16X12;
652 break;
653 case viafb_compact_res(800, 600):
654 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_16X12;
655 lcd_patch_reg = K400_LCD_RES_8X6_16X12;
656 break;
657 case viafb_compact_res(1024, 768):
658 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_16X12;
659 lcd_patch_reg = K400_LCD_RES_10X7_16X12;
660 break;
661 case viafb_compact_res(1280, 768):
662 case viafb_compact_res(1280, 800):
663 case viafb_compact_res(1280, 960):
664 case viafb_compact_res(1280, 1024):
665 reg_num = NUM_TOTAL_K400_LCD_RES_12X10_16X12;
666 lcd_patch_reg = K400_LCD_RES_12X10_16X12;
667 break;
668 }
669 break;
670
671 /* LCD 1366x768 */
672 case LCD_PANEL_ID7_1366X768:
673 switch (compact_mode) {
674 case viafb_compact_res(640, 480):
675 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_1366X7;
676 lcd_patch_reg = K400_LCD_RES_6X4_1366X7;
677 break;
678 case viafb_compact_res(720, 480):
679 case viafb_compact_res(720, 576):
680 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_1366X7;
681 lcd_patch_reg = K400_LCD_RES_7X4_1366X7;
682 break;
683 case viafb_compact_res(800, 600):
684 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_1366X7;
685 lcd_patch_reg = K400_LCD_RES_8X6_1366X7;
686 break;
687 case viafb_compact_res(1024, 768):
688 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_1366X7;
689 lcd_patch_reg = K400_LCD_RES_10X7_1366X7;
690 break;
691 case viafb_compact_res(1280, 768):
692 case viafb_compact_res(1280, 800):
693 case viafb_compact_res(1280, 960):
694 case viafb_compact_res(1280, 1024):
695 reg_num = NUM_TOTAL_K400_LCD_RES_12X10_1366X7;
696 lcd_patch_reg = K400_LCD_RES_12X10_1366X7;
697 break;
698 }
699 break;
700
701 /* LCD 1360x768 */
702 case LCD_PANEL_IDB_1360X768:
703 break;
704 }
705 if (reg_num != 0) {
706 /* H.W. Reset : ON */
707 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
708
709 viafb_write_regx(lcd_patch_reg, reg_num);
710
711 /* H.W. Reset : OFF */
712 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
713
714 /* Reset PLL */
715 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
716 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
717
718 /* Fire! */
719 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
720 }
721 }
722
723 static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
724 int panel_id)
725 {
726 u32 compact_mode = viafb_compact_res(set_hres, set_vres);
727 int reg_num = 0;
728 struct io_reg *lcd_patch_reg = NULL;
729
730 switch (panel_id) {
731 case LCD_PANEL_ID5_1400X1050:
732 switch (compact_mode) {
733 case viafb_compact_res(640, 480):
734 reg_num = NUM_TOTAL_P880_LCD_RES_6X4_14X10;
735 lcd_patch_reg = P880_LCD_RES_6X4_14X10;
736 break;
737 case viafb_compact_res(800, 600):
738 reg_num = NUM_TOTAL_P880_LCD_RES_8X6_14X10;
739 lcd_patch_reg = P880_LCD_RES_8X6_14X10;
740 break;
741 }
742 break;
743 case LCD_PANEL_ID6_1600X1200:
744 switch (compact_mode) {
745 case viafb_compact_res(640, 400):
746 case viafb_compact_res(640, 480):
747 reg_num = NUM_TOTAL_P880_LCD_RES_6X4_16X12;
748 lcd_patch_reg = P880_LCD_RES_6X4_16X12;
749 break;
750 case viafb_compact_res(720, 480):
751 case viafb_compact_res(720, 576):
752 reg_num = NUM_TOTAL_P880_LCD_RES_7X4_16X12;
753 lcd_patch_reg = P880_LCD_RES_7X4_16X12;
754 break;
755 case viafb_compact_res(800, 600):
756 reg_num = NUM_TOTAL_P880_LCD_RES_8X6_16X12;
757 lcd_patch_reg = P880_LCD_RES_8X6_16X12;
758 break;
759 case viafb_compact_res(1024, 768):
760 reg_num = NUM_TOTAL_P880_LCD_RES_10X7_16X12;
761 lcd_patch_reg = P880_LCD_RES_10X7_16X12;
762 break;
763 case viafb_compact_res(1280, 768):
764 case viafb_compact_res(1280, 960):
765 case viafb_compact_res(1280, 1024):
766 reg_num = NUM_TOTAL_P880_LCD_RES_12X10_16X12;
767 lcd_patch_reg = P880_LCD_RES_12X10_16X12;
768 break;
769 }
770 break;
771
772 }
773 if (reg_num != 0) {
774 /* H.W. Reset : ON */
775 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
776
777 viafb_write_regx(lcd_patch_reg, reg_num);
778
779 /* H.W. Reset : OFF */
780 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
781
782 /* Reset PLL */
783 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
784 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
785
786 /* Fire! */
787 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
788 }
789 }
790
791 static void load_lcd_patch_regs(int set_hres, int set_vres,
792 int panel_id, int set_iga)
793 {
794 viafb_unlock_crt();
795
796 /* Patch for simultaneous & Expansion */
797 if ((set_iga == IGA1_IGA2) &&
798 (viaparinfo->lvds_setting_info->display_method ==
799 LCD_EXPANDSION)) {
800 switch (viaparinfo->chip_info->gfx_chip_name) {
801 case UNICHROME_CLE266:
802 case UNICHROME_K400:
803 load_lcd_k400_patch_tbl(set_hres, set_vres, panel_id);
804 break;
805 case UNICHROME_K800:
806 break;
807 case UNICHROME_PM800:
808 case UNICHROME_CN700:
809 case UNICHROME_CX700:
810 load_lcd_p880_patch_tbl(set_hres, set_vres, panel_id);
811 }
812 }
813
814 viafb_lock_crt();
815 }
816
817 static void via_pitch_alignment_patch_lcd(
818 struct lvds_setting_information *plvds_setting_info,
819 struct lvds_chip_information
820 *plvds_chip_info)
821 {
822 unsigned char cr13, cr35, cr65, cr66, cr67;
823 unsigned long dwScreenPitch = 0;
824 unsigned long dwPitch;
825
826 dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
827 if (dwPitch & 0x1F) {
828 dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
829 if (plvds_setting_info->iga_path == IGA2) {
830 if (plvds_setting_info->bpp > 8) {
831 cr66 = (unsigned char)(dwScreenPitch & 0xFF);
832 viafb_write_reg(CR66, VIACR, cr66);
833 cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
834 cr67 |=
835 (unsigned
836 char)((dwScreenPitch & 0x300) >> 8);
837 viafb_write_reg(CR67, VIACR, cr67);
838 }
839
840 /* Fetch Count */
841 cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
842 cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
843 viafb_write_reg(CR67, VIACR, cr67);
844 cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
845 cr65 += 2;
846 viafb_write_reg(CR65, VIACR, cr65);
847 } else {
848 if (plvds_setting_info->bpp > 8) {
849 cr13 = (unsigned char)(dwScreenPitch & 0xFF);
850 viafb_write_reg(CR13, VIACR, cr13);
851 cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
852 cr35 |=
853 (unsigned
854 char)((dwScreenPitch & 0x700) >> 3);
855 viafb_write_reg(CR35, VIACR, cr35);
856 }
857 }
858 }
859 }
860 static void lcd_patch_skew_dvp0(struct lvds_setting_information
861 *plvds_setting_info,
862 struct lvds_chip_information *plvds_chip_info)
863 {
864 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
865 switch (viaparinfo->chip_info->gfx_chip_name) {
866 case UNICHROME_P4M900:
867 viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
868 plvds_chip_info);
869 break;
870 case UNICHROME_P4M890:
871 viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
872 plvds_chip_info);
873 break;
874 }
875 }
876 }
877 static void lcd_patch_skew_dvp1(struct lvds_setting_information
878 *plvds_setting_info,
879 struct lvds_chip_information *plvds_chip_info)
880 {
881 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
882 switch (viaparinfo->chip_info->gfx_chip_name) {
883 case UNICHROME_CX700:
884 viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
885 plvds_chip_info);
886 break;
887 }
888 }
889 }
890 static void lcd_patch_skew(struct lvds_setting_information
891 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
892 {
893 DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
894 switch (plvds_chip_info->output_interface) {
895 case INTERFACE_DVP0:
896 lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
897 break;
898 case INTERFACE_DVP1:
899 lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
900 break;
901 case INTERFACE_DFP_LOW:
902 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
903 viafb_write_reg_mask(CR99, VIACR, 0x08,
904 BIT0 + BIT1 + BIT2 + BIT3);
905 }
906 break;
907 }
908 }
909
910 /* LCD Set Mode */
911 void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
912 struct lvds_setting_information *plvds_setting_info,
913 struct lvds_chip_information *plvds_chip_info)
914 {
915 int set_iga = plvds_setting_info->iga_path;
916 int mode_bpp = plvds_setting_info->bpp;
917 int set_hres = plvds_setting_info->h_active;
918 int set_vres = plvds_setting_info->v_active;
919 int panel_hres = plvds_setting_info->lcd_panel_hres;
920 int panel_vres = plvds_setting_info->lcd_panel_vres;
921 u32 pll_D_N;
922 int offset;
923 struct display_timing mode_crt_reg, panel_crt_reg;
924 struct crt_mode_table *panel_crt_table = NULL;
925 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
926 panel_vres);
927
928 DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
929 /* Get mode table */
930 mode_crt_reg = mode_crt_table->crtc;
931 /* Get panel table Pointer */
932 panel_crt_table = vmode_tbl->crtc;
933 panel_crt_reg = panel_crt_table->crtc;
934 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
935 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
936 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
937 plvds_setting_info->vclk = panel_crt_table->clk;
938 if (set_iga == IGA1) {
939 /* IGA1 doesn't have LCD scaling, so set it as centering. */
940 viafb_load_crtc_timing(lcd_centering_timging
941 (mode_crt_reg, panel_crt_reg), IGA1);
942 } else {
943 /* Expansion */
944 if ((plvds_setting_info->display_method ==
945 LCD_EXPANDSION) & ((set_hres != panel_hres)
946 || (set_vres != panel_vres))) {
947 /* expansion timing IGA2 loaded panel set timing*/
948 viafb_load_crtc_timing(panel_crt_reg, IGA2);
949 DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
950 load_lcd_scaling(set_hres, set_vres, panel_hres,
951 panel_vres);
952 DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
953 } else { /* Centering */
954 /* centering timing IGA2 always loaded panel
955 and mode releative timing */
956 viafb_load_crtc_timing(lcd_centering_timging
957 (mode_crt_reg, panel_crt_reg), IGA2);
958 viafb_write_reg_mask(CR79, VIACR, 0x00,
959 BIT0 + BIT1 + BIT2);
960 /* LCD scaling disabled */
961 }
962 }
963
964 if (set_iga == IGA1_IGA2) {
965 load_crtc_shadow_timing(mode_crt_reg, panel_crt_reg);
966 /* Fill shadow registers */
967
968 switch (plvds_setting_info->lcd_panel_id) {
969 case LCD_PANEL_ID0_640X480:
970 offset = 80;
971 break;
972 case LCD_PANEL_ID1_800X600:
973 case LCD_PANEL_IDA_800X480:
974 offset = 110;
975 break;
976 case LCD_PANEL_ID2_1024X768:
977 offset = 150;
978 break;
979 case LCD_PANEL_ID3_1280X768:
980 case LCD_PANEL_ID4_1280X1024:
981 case LCD_PANEL_ID5_1400X1050:
982 case LCD_PANEL_ID9_1280X800:
983 offset = 190;
984 break;
985 case LCD_PANEL_ID6_1600X1200:
986 offset = 250;
987 break;
988 case LCD_PANEL_ID7_1366X768:
989 case LCD_PANEL_IDB_1360X768:
990 offset = 212;
991 break;
992 default:
993 offset = 140;
994 break;
995 }
996
997 /* Offset for simultaneous */
998 viafb_set_secondary_pitch(offset << 3);
999 DEBUG_MSG(KERN_INFO "viafb_load_reg!!\n");
1000 viafb_load_fetch_count_reg(set_hres, 4, IGA2);
1001 /* Fetch count for simultaneous */
1002 } else { /* SAMM */
1003 /* Fetch count for IGA2 only */
1004 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
1005
1006 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1007 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1008 viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
1009
1010 viafb_set_color_depth(mode_bpp / 8, set_iga);
1011 }
1012
1013 fill_lcd_format();
1014
1015 pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
1016 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
1017 viafb_set_vclock(pll_D_N, set_iga);
1018
1019 viafb_set_output_path(DEVICE_LCD, set_iga,
1020 plvds_chip_info->output_interface);
1021 lcd_patch_skew(plvds_setting_info, plvds_chip_info);
1022
1023 /* If K8M800, enable LCD Prefetch Mode. */
1024 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1025 || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
1026 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
1027
1028 load_lcd_patch_regs(set_hres, set_vres,
1029 plvds_setting_info->lcd_panel_id, set_iga);
1030
1031 DEBUG_MSG(KERN_INFO "load_lcd_patch_regs!!\n");
1032
1033 /* Patch for non 32bit alignment mode */
1034 via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
1035 }
1036
1037 static void integrated_lvds_disable(struct lvds_setting_information
1038 *plvds_setting_info,
1039 struct lvds_chip_information *plvds_chip_info)
1040 {
1041 bool turn_off_first_powersequence = false;
1042 bool turn_off_second_powersequence = false;
1043 if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
1044 turn_off_first_powersequence = true;
1045 if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
1046 turn_off_first_powersequence = true;
1047 if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
1048 turn_off_second_powersequence = true;
1049 if (turn_off_second_powersequence) {
1050 /* Use second power sequence control: */
1051
1052 /* Turn off power sequence. */
1053 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
1054
1055 /* Turn off back light. */
1056 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
1057 }
1058 if (turn_off_first_powersequence) {
1059 /* Use first power sequence control: */
1060
1061 /* Turn off power sequence. */
1062 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
1063
1064 /* Turn off back light. */
1065 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
1066 }
1067
1068 /* Turn DFP High/Low Pad off. */
1069 viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
1070
1071 /* Power off LVDS channel. */
1072 switch (plvds_chip_info->output_interface) {
1073 case INTERFACE_LVDS0:
1074 {
1075 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
1076 break;
1077 }
1078
1079 case INTERFACE_LVDS1:
1080 {
1081 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
1082 break;
1083 }
1084
1085 case INTERFACE_LVDS0LVDS1:
1086 {
1087 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
1088 break;
1089 }
1090 }
1091 }
1092
1093 static void integrated_lvds_enable(struct lvds_setting_information
1094 *plvds_setting_info,
1095 struct lvds_chip_information *plvds_chip_info)
1096 {
1097 DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
1098 plvds_chip_info->output_interface);
1099 if (plvds_setting_info->lcd_mode == LCD_SPWG)
1100 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
1101 else
1102 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
1103
1104 switch (plvds_chip_info->output_interface) {
1105 case INTERFACE_LVDS0LVDS1:
1106 case INTERFACE_LVDS0:
1107 /* Use first power sequence control: */
1108 /* Use hardware control power sequence. */
1109 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
1110 /* Turn on back light. */
1111 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
1112 /* Turn on hardware power sequence. */
1113 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1114 break;
1115 case INTERFACE_LVDS1:
1116 /* Use second power sequence control: */
1117 /* Use hardware control power sequence. */
1118 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
1119 /* Turn on back light. */
1120 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
1121 /* Turn on hardware power sequence. */
1122 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
1123 break;
1124 }
1125
1126 /* Turn DFP High/Low pad on. */
1127 viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
1128
1129 /* Power on LVDS channel. */
1130 switch (plvds_chip_info->output_interface) {
1131 case INTERFACE_LVDS0:
1132 {
1133 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
1134 break;
1135 }
1136
1137 case INTERFACE_LVDS1:
1138 {
1139 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
1140 break;
1141 }
1142
1143 case INTERFACE_LVDS0LVDS1:
1144 {
1145 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
1146 break;
1147 }
1148 }
1149 }
1150
1151 void viafb_lcd_disable(void)
1152 {
1153
1154 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1155 lcd_powersequence_off();
1156 /* DI1 pad off */
1157 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
1158 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1159 if (viafb_LCD2_ON
1160 && (INTEGRATED_LVDS ==
1161 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
1162 integrated_lvds_disable(viaparinfo->lvds_setting_info,
1163 &viaparinfo->chip_info->lvds_chip_info2);
1164 if (INTEGRATED_LVDS ==
1165 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
1166 integrated_lvds_disable(viaparinfo->lvds_setting_info,
1167 &viaparinfo->chip_info->lvds_chip_info);
1168 if (VT1636_LVDS == viaparinfo->chip_info->
1169 lvds_chip_info.lvds_chip_name)
1170 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
1171 &viaparinfo->chip_info->lvds_chip_info);
1172 } else if (VT1636_LVDS ==
1173 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
1174 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
1175 &viaparinfo->chip_info->lvds_chip_info);
1176 } else {
1177 /* DFP-HL pad off */
1178 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
1179 /* Backlight off */
1180 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
1181 /* 24 bit DI data paht off */
1182 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
1183 /* Simultaneout disabled */
1184 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
1185 }
1186
1187 /* Disable expansion bit */
1188 viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
1189 /* CRT path set to IGA1 */
1190 viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
1191 /* Simultaneout disabled */
1192 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
1193 /* IGA2 path disabled */
1194 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
1195
1196 }
1197
1198 void viafb_lcd_enable(void)
1199 {
1200 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1201 /* DI1 pad on */
1202 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
1203 lcd_powersequence_on();
1204 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1205 if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
1206 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
1207 integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
1208 &viaparinfo->chip_info->lvds_chip_info2);
1209 if (INTEGRATED_LVDS ==
1210 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
1211 integrated_lvds_enable(viaparinfo->lvds_setting_info,
1212 &viaparinfo->chip_info->lvds_chip_info);
1213 if (VT1636_LVDS == viaparinfo->chip_info->
1214 lvds_chip_info.lvds_chip_name)
1215 viafb_enable_lvds_vt1636(viaparinfo->
1216 lvds_setting_info, &viaparinfo->chip_info->
1217 lvds_chip_info);
1218 } else if (VT1636_LVDS ==
1219 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
1220 viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
1221 &viaparinfo->chip_info->lvds_chip_info);
1222 } else {
1223 /* DFP-HL pad on */
1224 viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
1225 /* Backlight on */
1226 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
1227 /* 24 bit DI data paht on */
1228 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
1229
1230 /* Set data source selection bit by iga path */
1231 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
1232 /* DFP-H set to IGA1 */
1233 viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
1234 /* DFP-L set to IGA1 */
1235 viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
1236 } else {
1237 /* DFP-H set to IGA2 */
1238 viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
1239 /* DFP-L set to IGA2 */
1240 viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
1241 }
1242 /* LCD enabled */
1243 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
1244 }
1245
1246 if ((viaparinfo->lvds_setting_info->iga_path == IGA1)
1247 || (viaparinfo->lvds_setting_info->iga_path == IGA1_IGA2)) {
1248 /* CRT path set to IGA2 */
1249 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
1250 /* IGA2 path disabled */
1251 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
1252 /* IGA2 path enabled */
1253 } else { /* IGA2 */
1254 viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
1255 }
1256
1257 }
1258
1259 static void lcd_powersequence_off(void)
1260 {
1261 int i, mask, data;
1262
1263 /* Software control power sequence */
1264 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
1265
1266 for (i = 0; i < 3; i++) {
1267 mask = PowerSequenceOff[0][i];
1268 data = PowerSequenceOff[1][i] & mask;
1269 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
1270 udelay(PowerSequenceOff[2][i]);
1271 }
1272
1273 /* Disable LCD */
1274 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
1275 }
1276
1277 static void lcd_powersequence_on(void)
1278 {
1279 int i, mask, data;
1280
1281 /* Software control power sequence */
1282 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
1283
1284 /* Enable LCD */
1285 viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
1286
1287 for (i = 0; i < 3; i++) {
1288 mask = PowerSequenceOn[0][i];
1289 data = PowerSequenceOn[1][i] & mask;
1290 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
1291 udelay(PowerSequenceOn[2][i]);
1292 }
1293
1294 udelay(1);
1295 }
1296
1297 static void fill_lcd_format(void)
1298 {
1299 u8 bdithering = 0, bdual = 0;
1300
1301 if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
1302 bdual = BIT4;
1303 if (viaparinfo->lvds_setting_info->LCDDithering)
1304 bdithering = BIT0;
1305 /* Dual & Dithering */
1306 viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
1307 }
1308
1309 static void check_diport_of_integrated_lvds(
1310 struct lvds_chip_information *plvds_chip_info,
1311 struct lvds_setting_information
1312 *plvds_setting_info)
1313 {
1314 /* Determine LCD DI Port by hardware layout. */
1315 switch (viafb_display_hardware_layout) {
1316 case HW_LAYOUT_LCD_ONLY:
1317 {
1318 if (plvds_setting_info->device_lcd_dualedge) {
1319 plvds_chip_info->output_interface =
1320 INTERFACE_LVDS0LVDS1;
1321 } else {
1322 plvds_chip_info->output_interface =
1323 INTERFACE_LVDS0;
1324 }
1325
1326 break;
1327 }
1328
1329 case HW_LAYOUT_DVI_ONLY:
1330 {
1331 plvds_chip_info->output_interface = INTERFACE_NONE;
1332 break;
1333 }
1334
1335 case HW_LAYOUT_LCD1_LCD2:
1336 case HW_LAYOUT_LCD_EXTERNAL_LCD2:
1337 {
1338 plvds_chip_info->output_interface =
1339 INTERFACE_LVDS0LVDS1;
1340 break;
1341 }
1342
1343 case HW_LAYOUT_LCD_DVI:
1344 {
1345 plvds_chip_info->output_interface = INTERFACE_LVDS1;
1346 break;
1347 }
1348
1349 default:
1350 {
1351 plvds_chip_info->output_interface = INTERFACE_LVDS1;
1352 break;
1353 }
1354 }
1355
1356 DEBUG_MSG(KERN_INFO
1357 "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
1358 viafb_display_hardware_layout,
1359 plvds_chip_info->output_interface);
1360 }
1361
1362 void viafb_init_lvds_output_interface(struct lvds_chip_information
1363 *plvds_chip_info,
1364 struct lvds_setting_information
1365 *plvds_setting_info)
1366 {
1367 if (INTERFACE_NONE != plvds_chip_info->output_interface) {
1368 /*Do nothing, lcd port is specified by module parameter */
1369 return;
1370 }
1371
1372 switch (plvds_chip_info->lvds_chip_name) {
1373
1374 case VT1636_LVDS:
1375 switch (viaparinfo->chip_info->gfx_chip_name) {
1376 case UNICHROME_CX700:
1377 plvds_chip_info->output_interface = INTERFACE_DVP1;
1378 break;
1379 case UNICHROME_CN700:
1380 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1381 break;
1382 default:
1383 plvds_chip_info->output_interface = INTERFACE_DVP0;
1384 break;
1385 }
1386 break;
1387
1388 case INTEGRATED_LVDS:
1389 check_diport_of_integrated_lvds(plvds_chip_info,
1390 plvds_setting_info);
1391 break;
1392
1393 default:
1394 switch (viaparinfo->chip_info->gfx_chip_name) {
1395 case UNICHROME_K8M890:
1396 case UNICHROME_P4M900:
1397 case UNICHROME_P4M890:
1398 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1399 break;
1400 default:
1401 plvds_chip_info->output_interface = INTERFACE_DFP;
1402 break;
1403 }
1404 break;
1405 }
1406 }
1407
1408 static struct display_timing lcd_centering_timging(struct display_timing
1409 mode_crt_reg,
1410 struct display_timing panel_crt_reg)
1411 {
1412 struct display_timing crt_reg;
1413
1414 crt_reg.hor_total = panel_crt_reg.hor_total;
1415 crt_reg.hor_addr = mode_crt_reg.hor_addr;
1416 crt_reg.hor_blank_start =
1417 (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
1418 crt_reg.hor_addr;
1419 crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
1420 crt_reg.hor_sync_start =
1421 (panel_crt_reg.hor_sync_start -
1422 panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
1423 crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
1424
1425 crt_reg.ver_total = panel_crt_reg.ver_total;
1426 crt_reg.ver_addr = mode_crt_reg.ver_addr;
1427 crt_reg.ver_blank_start =
1428 (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
1429 crt_reg.ver_addr;
1430 crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
1431 crt_reg.ver_sync_start =
1432 (panel_crt_reg.ver_sync_start -
1433 panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
1434 crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
1435
1436 return crt_reg;
1437 }
1438
1439 static void load_crtc_shadow_timing(struct display_timing mode_timing,
1440 struct display_timing panel_timing)
1441 {
1442 struct io_register *reg = NULL;
1443 int i;
1444 int viafb_load_reg_Num = 0;
1445 int reg_value = 0;
1446
1447 if (viaparinfo->lvds_setting_info->display_method == LCD_EXPANDSION) {
1448 /* Expansion */
1449 for (i = 12; i < 20; i++) {
1450 switch (i) {
1451 case H_TOTAL_SHADOW_INDEX:
1452 reg_value =
1453 IGA2_HOR_TOTAL_SHADOW_FORMULA
1454 (panel_timing.hor_total);
1455 viafb_load_reg_Num =
1456 iga2_shadow_crtc_reg.hor_total_shadow.
1457 reg_num;
1458 reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
1459 break;
1460 case H_BLANK_END_SHADOW_INDEX:
1461 reg_value =
1462 IGA2_HOR_BLANK_END_SHADOW_FORMULA
1463 (panel_timing.hor_blank_start,
1464 panel_timing.hor_blank_end);
1465 viafb_load_reg_Num =
1466 iga2_shadow_crtc_reg.
1467 hor_blank_end_shadow.reg_num;
1468 reg =
1469 iga2_shadow_crtc_reg.
1470 hor_blank_end_shadow.reg;
1471 break;
1472 case V_TOTAL_SHADOW_INDEX:
1473 reg_value =
1474 IGA2_VER_TOTAL_SHADOW_FORMULA
1475 (panel_timing.ver_total);
1476 viafb_load_reg_Num =
1477 iga2_shadow_crtc_reg.ver_total_shadow.
1478 reg_num;
1479 reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
1480 break;
1481 case V_ADDR_SHADOW_INDEX:
1482 reg_value =
1483 IGA2_VER_ADDR_SHADOW_FORMULA
1484 (panel_timing.ver_addr);
1485 viafb_load_reg_Num =
1486 iga2_shadow_crtc_reg.ver_addr_shadow.
1487 reg_num;
1488 reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
1489 break;
1490 case V_BLANK_SATRT_SHADOW_INDEX:
1491 reg_value =
1492 IGA2_VER_BLANK_START_SHADOW_FORMULA
1493 (panel_timing.ver_blank_start);
1494 viafb_load_reg_Num =
1495 iga2_shadow_crtc_reg.
1496 ver_blank_start_shadow.reg_num;
1497 reg =
1498 iga2_shadow_crtc_reg.
1499 ver_blank_start_shadow.reg;
1500 break;
1501 case V_BLANK_END_SHADOW_INDEX:
1502 reg_value =
1503 IGA2_VER_BLANK_END_SHADOW_FORMULA
1504 (panel_timing.ver_blank_start,
1505 panel_timing.ver_blank_end);
1506 viafb_load_reg_Num =
1507 iga2_shadow_crtc_reg.
1508 ver_blank_end_shadow.reg_num;
1509 reg =
1510 iga2_shadow_crtc_reg.
1511 ver_blank_end_shadow.reg;
1512 break;
1513 case V_SYNC_SATRT_SHADOW_INDEX:
1514 reg_value =
1515 IGA2_VER_SYNC_START_SHADOW_FORMULA
1516 (panel_timing.ver_sync_start);
1517 viafb_load_reg_Num =
1518 iga2_shadow_crtc_reg.
1519 ver_sync_start_shadow.reg_num;
1520 reg =
1521 iga2_shadow_crtc_reg.
1522 ver_sync_start_shadow.reg;
1523 break;
1524 case V_SYNC_END_SHADOW_INDEX:
1525 reg_value =
1526 IGA2_VER_SYNC_END_SHADOW_FORMULA
1527 (panel_timing.ver_sync_start,
1528 panel_timing.ver_sync_end);
1529 viafb_load_reg_Num =
1530 iga2_shadow_crtc_reg.
1531 ver_sync_end_shadow.reg_num;
1532 reg =
1533 iga2_shadow_crtc_reg.
1534 ver_sync_end_shadow.reg;
1535 break;
1536 }
1537 viafb_load_reg(reg_value,
1538 viafb_load_reg_Num, reg, VIACR);
1539 }
1540 } else { /* Centering */
1541 for (i = 12; i < 20; i++) {
1542 switch (i) {
1543 case H_TOTAL_SHADOW_INDEX:
1544 reg_value =
1545 IGA2_HOR_TOTAL_SHADOW_FORMULA
1546 (panel_timing.hor_total);
1547 viafb_load_reg_Num =
1548 iga2_shadow_crtc_reg.hor_total_shadow.
1549 reg_num;
1550 reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
1551 break;
1552 case H_BLANK_END_SHADOW_INDEX:
1553 reg_value =
1554 IGA2_HOR_BLANK_END_SHADOW_FORMULA
1555 (panel_timing.hor_blank_start,
1556 panel_timing.hor_blank_end);
1557 viafb_load_reg_Num =
1558 iga2_shadow_crtc_reg.
1559 hor_blank_end_shadow.reg_num;
1560 reg =
1561 iga2_shadow_crtc_reg.
1562 hor_blank_end_shadow.reg;
1563 break;
1564 case V_TOTAL_SHADOW_INDEX:
1565 reg_value =
1566 IGA2_VER_TOTAL_SHADOW_FORMULA
1567 (panel_timing.ver_total);
1568 viafb_load_reg_Num =
1569 iga2_shadow_crtc_reg.ver_total_shadow.
1570 reg_num;
1571 reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
1572 break;
1573 case V_ADDR_SHADOW_INDEX:
1574 reg_value =
1575 IGA2_VER_ADDR_SHADOW_FORMULA
1576 (mode_timing.ver_addr);
1577 viafb_load_reg_Num =
1578 iga2_shadow_crtc_reg.ver_addr_shadow.
1579 reg_num;
1580 reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
1581 break;
1582 case V_BLANK_SATRT_SHADOW_INDEX:
1583 reg_value =
1584 IGA2_VER_BLANK_START_SHADOW_FORMULA
1585 (mode_timing.ver_blank_start);
1586 viafb_load_reg_Num =
1587 iga2_shadow_crtc_reg.
1588 ver_blank_start_shadow.reg_num;
1589 reg =
1590 iga2_shadow_crtc_reg.
1591 ver_blank_start_shadow.reg;
1592 break;
1593 case V_BLANK_END_SHADOW_INDEX:
1594 reg_value =
1595 IGA2_VER_BLANK_END_SHADOW_FORMULA
1596 (panel_timing.ver_blank_start,
1597 panel_timing.ver_blank_end);
1598 viafb_load_reg_Num =
1599 iga2_shadow_crtc_reg.
1600 ver_blank_end_shadow.reg_num;
1601 reg =
1602 iga2_shadow_crtc_reg.
1603 ver_blank_end_shadow.reg;
1604 break;
1605 case V_SYNC_SATRT_SHADOW_INDEX:
1606 reg_value =
1607 IGA2_VER_SYNC_START_SHADOW_FORMULA(
1608 (panel_timing.ver_sync_start -
1609 panel_timing.ver_blank_start) +
1610 (panel_timing.ver_addr -
1611 mode_timing.ver_addr) / 2 +
1612 mode_timing.ver_addr);
1613 viafb_load_reg_Num =
1614 iga2_shadow_crtc_reg.ver_sync_start_shadow.
1615 reg_num;
1616 reg =
1617 iga2_shadow_crtc_reg.ver_sync_start_shadow.
1618 reg;
1619 break;
1620 case V_SYNC_END_SHADOW_INDEX:
1621 reg_value =
1622 IGA2_VER_SYNC_END_SHADOW_FORMULA(
1623 (panel_timing.ver_sync_start -
1624 panel_timing.ver_blank_start) +
1625 (panel_timing.ver_addr -
1626 mode_timing.ver_addr) / 2 +
1627 mode_timing.ver_addr,
1628 panel_timing.ver_sync_end);
1629 viafb_load_reg_Num =
1630 iga2_shadow_crtc_reg.ver_sync_end_shadow.
1631 reg_num;
1632 reg =
1633 iga2_shadow_crtc_reg.ver_sync_end_shadow.
1634 reg;
1635 break;
1636 }
1637 viafb_load_reg(reg_value,
1638 viafb_load_reg_Num, reg, VIACR);
1639 }
1640 }
1641 }
1642
1643 bool viafb_lcd_get_mobile_state(bool *mobile)
1644 {
1645 unsigned char *romptr, *tableptr;
1646 u8 core_base;
1647 unsigned char *biosptr;
1648 /* Rom address */
1649 u32 romaddr = 0x000C0000;
1650 u16 start_pattern = 0;
1651
1652 biosptr = ioremap(romaddr, 0x10000);
1653
1654 memcpy(&start_pattern, biosptr, 2);
1655 /* Compare pattern */
1656 if (start_pattern == 0xAA55) {
1657 /* Get the start of Table */
1658 /* 0x1B means BIOS offset position */
1659 romptr = biosptr + 0x1B;
1660 tableptr = biosptr + *((u16 *) romptr);
1661
1662 /* Get the start of biosver structure */
1663 /* 18 means BIOS version position. */
1664 romptr = tableptr + 18;
1665 romptr = biosptr + *((u16 *) romptr);
1666
1667 /* The offset should be 44, but the
1668 actual image is less three char. */
1669 /* pRom += 44; */
1670 romptr += 41;
1671
1672 core_base = *romptr++;
1673
1674 if (core_base & 0x8)
1675 *mobile = false;
1676 else
1677 *mobile = true;
1678 /* release memory */
1679 iounmap(biosptr);
1680
1681 return true;
1682 } else {
1683 iounmap(biosptr);
1684 return false;
1685 }
1686 }
1687
1688 static void viafb_load_scaling_factor_for_p4m900(int set_hres,
1689 int set_vres, int panel_hres, int panel_vres)
1690 {
1691 int h_scaling_factor;
1692 int v_scaling_factor;
1693 u8 cra2 = 0;
1694 u8 cr77 = 0;
1695 u8 cr78 = 0;
1696 u8 cr79 = 0;
1697 u8 cr9f = 0;
1698 /* Check if expansion for horizontal */
1699 if (set_hres < panel_hres) {
1700 /* Load Horizontal Scaling Factor */
1701
1702 /* For VIA_K8M800 or later chipsets. */
1703 h_scaling_factor =
1704 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
1705 /* HSCaleFactor[1:0] at CR9F[1:0] */
1706 cr9f = h_scaling_factor & 0x0003;
1707 /* HSCaleFactor[9:2] at CR77[7:0] */
1708 cr77 = (h_scaling_factor & 0x03FC) >> 2;
1709 /* HSCaleFactor[11:10] at CR79[5:4] */
1710 cr79 = (h_scaling_factor & 0x0C00) >> 10;
1711 cr79 <<= 4;
1712
1713 /* Horizontal scaling enabled */
1714 cra2 = 0xC0;
1715
1716 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d\n",
1717 h_scaling_factor);
1718 } else {
1719 /* Horizontal scaling disabled */
1720 cra2 = 0x00;
1721 }
1722
1723 /* Check if expansion for vertical */
1724 if (set_vres < panel_vres) {
1725 /* Load Vertical Scaling Factor */
1726
1727 /* For VIA_K8M800 or later chipsets. */
1728 v_scaling_factor =
1729 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
1730
1731 /* Vertical scaling enabled */
1732 cra2 |= 0x08;
1733 /* VSCaleFactor[0] at CR79[3] */
1734 cr79 |= ((v_scaling_factor & 0x0001) << 3);
1735 /* VSCaleFactor[8:1] at CR78[7:0] */
1736 cr78 |= (v_scaling_factor & 0x01FE) >> 1;
1737 /* VSCaleFactor[10:9] at CR79[7:6] */
1738 cr79 |= ((v_scaling_factor & 0x0600) >> 9) << 6;
1739
1740 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d\n",
1741 v_scaling_factor);
1742 } else {
1743 /* Vertical scaling disabled */
1744 cra2 |= 0x00;
1745 }
1746
1747 viafb_write_reg_mask(CRA2, VIACR, cra2, BIT3 + BIT6 + BIT7);
1748 viafb_write_reg_mask(CR77, VIACR, cr77, 0xFF);
1749 viafb_write_reg_mask(CR78, VIACR, cr78, 0xFF);
1750 viafb_write_reg_mask(CR79, VIACR, cr79, 0xF8);
1751 viafb_write_reg_mask(CR9F, VIACR, cr9f, BIT0 + BIT1);
1752 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree