2 * Copyright (C) 2001,2002,2005 Broadcom Corporation
3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 * BCM1480/1455-specific HT support (looking like PCI)
23 * This module provides the glue between Linux's PCI subsystem
24 * and the hardware. We basically provide glue for accessing
25 * configuration space, and set up the translation for I/O
28 * To access configuration space, we use ioremap. In the 32-bit
29 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
30 * kernel mapped memory. Hopefully neither of these should be a huge
34 #include <linux/types.h>
35 #include <linux/pci.h>
36 #include <linux/kernel.h>
37 #include <linux/init.h>
39 #include <linux/console.h>
40 #include <linux/tty.h>
42 #include <asm/sibyte/bcm1480_regs.h>
43 #include <asm/sibyte/bcm1480_scd.h>
44 #include <asm/sibyte/board.h>
48 * Macros for calculating offsets into config space given a device
49 * structure or dev/fun/reg
51 #define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
52 #define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
54 static void *ht_cfg_space
;
56 #define PCI_BUS_ENABLED 1
57 #define PCI_DEVICE_MODE 2
59 static int bcm1480ht_bus_status
;
61 #define PCI_BRIDGE_DEVICE 0
62 #define HT_BRIDGE_DEVICE 1
65 * HT's level-sensitive interrupts require EOI, which is generated
66 * through a 4MB memory-mapped region
68 unsigned long ht_eoi_space
;
71 * Read/write 32-bit values in config space.
73 static inline u32
READCFG32(u32 addr
)
75 return *(u32
*)(ht_cfg_space
+ (addr
&~3));
78 static inline void WRITECFG32(u32 addr
, u32 data
)
80 *(u32
*)(ht_cfg_space
+ (addr
& ~3)) = data
;
84 * Some checks before doing config cycles:
85 * In PCI Device Mode, hide everything on bus 0 except the LDT host
86 * bridge. Otherwise, access is controlled by bridge MasterEn bits.
88 static int bcm1480ht_can_access(struct pci_bus
*bus
, int devfn
)
92 if (!(bcm1480ht_bus_status
& (PCI_BUS_ENABLED
| PCI_DEVICE_MODE
)))
95 if (bus
->number
== 0) {
96 devno
= PCI_SLOT(devfn
);
97 if (bcm1480ht_bus_status
& PCI_DEVICE_MODE
)
104 * Read/write access functions for various sizes of values
105 * in config space. Return all 1's for disallowed accesses
106 * for a kludgy but adequate simulation of master aborts.
109 static int bcm1480ht_pcibios_read(struct pci_bus
*bus
, unsigned int devfn
,
110 int where
, int size
, u32
* val
)
114 if ((size
== 2) && (where
& 1))
115 return PCIBIOS_BAD_REGISTER_NUMBER
;
116 else if ((size
== 4) && (where
& 3))
117 return PCIBIOS_BAD_REGISTER_NUMBER
;
119 if (bcm1480ht_can_access(bus
, devfn
))
120 data
= READCFG32(CFGADDR(bus
, devfn
, where
));
125 *val
= (data
>> ((where
& 3) << 3)) & 0xff;
127 *val
= (data
>> ((where
& 3) << 3)) & 0xffff;
131 return PCIBIOS_SUCCESSFUL
;
134 static int bcm1480ht_pcibios_write(struct pci_bus
*bus
, unsigned int devfn
,
135 int where
, int size
, u32 val
)
137 u32 cfgaddr
= CFGADDR(bus
, devfn
, where
);
140 if ((size
== 2) && (where
& 1))
141 return PCIBIOS_BAD_REGISTER_NUMBER
;
142 else if ((size
== 4) && (where
& 3))
143 return PCIBIOS_BAD_REGISTER_NUMBER
;
145 if (!bcm1480ht_can_access(bus
, devfn
))
146 return PCIBIOS_BAD_REGISTER_NUMBER
;
148 data
= READCFG32(cfgaddr
);
151 data
= (data
& ~(0xff << ((where
& 3) << 3))) |
152 (val
<< ((where
& 3) << 3));
154 data
= (data
& ~(0xffff << ((where
& 3) << 3))) |
155 (val
<< ((where
& 3) << 3));
159 WRITECFG32(cfgaddr
, data
);
161 return PCIBIOS_SUCCESSFUL
;
164 static int bcm1480ht_pcibios_get_busno(void)
169 struct pci_ops bcm1480ht_pci_ops
= {
170 .read
= bcm1480ht_pcibios_read
,
171 .write
= bcm1480ht_pcibios_write
,
174 static struct resource bcm1480ht_mem_resource
= {
175 .name
= "BCM1480 HT MEM",
176 .start
= A_BCM1480_PHYS_HT_MEM_MATCH_BYTES
,
177 .end
= A_BCM1480_PHYS_HT_MEM_MATCH_BYTES
+ 0x1fffffffUL
,
178 .flags
= IORESOURCE_MEM
,
181 static struct resource bcm1480ht_io_resource
= {
182 .name
= "BCM1480 HT I/O",
183 .start
= A_BCM1480_PHYS_HT_IO_MATCH_BYTES
,
184 .end
= A_BCM1480_PHYS_HT_IO_MATCH_BYTES
+ 0x01ffffffUL
,
185 .flags
= IORESOURCE_IO
,
188 struct pci_controller bcm1480ht_controller
= {
189 .pci_ops
= &bcm1480ht_pci_ops
,
190 .mem_resource
= &bcm1480ht_mem_resource
,
191 .io_resource
= &bcm1480ht_io_resource
,
193 .get_busno
= bcm1480ht_pcibios_get_busno
,
194 .io_offset
= A_BCM1480_PHYS_HT_IO_MATCH_BYTES
,
197 static int __init
bcm1480ht_pcibios_init(void)
199 ht_cfg_space
= ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS
, 16*1024*1024);
201 /* CFE doesn't always init all HT paths, so we always scan */
202 bcm1480ht_bus_status
|= PCI_BUS_ENABLED
;
204 ht_eoi_space
= (unsigned long)
205 ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES
,
207 bcm1480ht_controller
.io_map_base
= (unsigned long)
208 ioremap(A_BCM1480_PHYS_HT_IO_MATCH_BYTES
, 65536);
209 bcm1480ht_controller
.io_map_base
-= bcm1480ht_controller
.io_offset
;
211 register_pci_controller(&bcm1480ht_controller
);
216 arch_initcall(bcm1480ht_pcibios_init
);